src/arm/nxp/imx/imx6dl-alti6p.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright (c) 2016 Protonic Holland
   4  * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/leds/common.h>
  10 #include <dt-bindings/sound/fsl-imx-audmux.h>
  11 #include "imx6dl.dtsi"
  12
  13 / {
  14         model = "Altesco I6P Board";
  15         compatible = "alt,alti6p", "fsl,imx6dl";
  16
  17         chosen {
  18                 stdout-path = &uart4;
  19         };
  20
  21         clock_ksz8081: clock-ksz8081 {
  22                 compatible = "fixed-clock";
  23                 #clock-cells = <0>;
  24                 clock-frequency = <50000000>;
  25                 clock-output-names = "enet_ref_pad";
  26         };
  27
  28         i2c2-mux {
  29                 compatible = "i2c-mux";
  30                 i2c-parent = <&i2c2>;
  31                 mux-controls = <&i2c_mux>;
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 i2c@1 {
  36                         reg = <1>;
  37                         #address-cells = <1>;
  38                         #size-cells = <0>;
  39                 };
  40
  41                 i2c@2 {
  42                         reg = <2>;
  43                         #address-cells = <1>;
  44                         #size-cells = <0>;
  45                 };
  46         };
  47
  48         i2c4-mux {
  49                 compatible = "i2c-mux";
  50                 i2c-parent = <&i2c4>;
  51                 mux-controls = <&i2c_mux>;
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 i2c@1 {
  56                         reg = <1>;
  57                         #address-cells = <1>;
  58                         #size-cells = <0>;
  59                 };
  60
  61                 i2c@2 {
  62                         reg = <2>;
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65                 };
  66         };
  67
  68         leds {
  69                 compatible = "gpio-leds";
  70                 pinctrl-names = "default";
  71                 pinctrl-0 = <&pinctrl_leds>;
  72
  73                 led-debug0 {
  74                         function = LED_FUNCTION_STATUS;
  75                         gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  76                         linux,default-trigger = "heartbeat";
  77                 };
  78
  79                 led-debug1 {
  80                         function = LED_FUNCTION_SD;
  81                         gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  82                         linux,default-trigger = "disk-activity";
  83                 };
  84         };
  85
  86         i2c_mux: mux-controller {
  87                 compatible = "gpio-mux";
  88                 #mux-control-cells = <0>;
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pinctrl_i2cmux>;
  91
  92                 mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>,
  93                             <&gpio5 11 GPIO_ACTIVE_HIGH>;
  94         };
  95
  96         reg_1v8: regulator-1v8 {
  97                 compatible = "regulator-fixed";
  98                 regulator-name = "1v8";
  99                 regulator-min-microvolt = <1800000>;
 100                 regulator-max-microvolt = <1800000>;
 101         };
 102
 103         reg_3v3: regulator-3v3 {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "3v3";
 106                 regulator-min-microvolt = <3300000>;
 107                 regulator-max-microvolt = <3300000>;
 108         };
 109
 110         reg_5v0: regulator-5v0 {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "5v0";
 113                 regulator-min-microvolt = <5000000>;
 114                 regulator-max-microvolt = <5000000>;
 115         };
 116
 117         reg_h1_vbus: regulator-h1-vbus {
 118                 compatible = "regulator-fixed";
 119                 regulator-name = "h1-vbus";
 120                 regulator-min-microvolt = <5000000>;
 121                 regulator-max-microvolt = <5000000>;
 122                 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 123                 enable-active-high;
 124         };
 125
 126         reg_otg_vbus: regulator-otg-vbus {
 127                 compatible = "regulator-fixed";
 128                 regulator-name = "otg-vbus";
 129                 regulator-min-microvolt = <5000000>;
 130                 regulator-max-microvolt = <5000000>;
 131                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 132                 enable-active-high;
 133         };
 134
 135         sound {
 136                 compatible = "simple-audio-card";
 137                 simple-audio-card,name = "prti6q-sgtl5000";
 138                 simple-audio-card,format = "i2s";
 139                 simple-audio-card,widgets =
 140                         "Microphone", "Microphone Jack",
 141                         "Line", "Line In Jack",
 142                         "Headphone", "Headphone Jack",
 143                         "Speaker", "External Speaker";
 144                 simple-audio-card,routing =
 145                         "MIC_IN", "Microphone Jack",
 146                         "LINE_IN", "Line In Jack",
 147                         "Headphone Jack", "HP_OUT",
 148                         "External Speaker", "LINE_OUT";
 149
 150                 simple-audio-card,cpu {
 151                         sound-dai = <&ssi1>;
 152                         system-clock-frequency = <0>;
 153                 };
 154
 155                 simple-audio-card,codec {
 156                         sound-dai = <&sgtl5000>;
 157                         bitclock-master;
 158                         frame-master;
 159                 };
 160         };
 161 };
 162
 163 &audmux {
 164         pinctrl-names = "default";
 165         pinctrl-0 = <&pinctrl_audmux>;
 166         status = "okay";
 167
 168         mux-ssi1 {
 169                 fsl,audmux-port = <0>;
 170                 fsl,port-config = <
 171                         IMX_AUDMUX_V2_PTCR_SYN          0
 172                         IMX_AUDMUX_V2_PTCR_TFSEL(2)     0
 173                         IMX_AUDMUX_V2_PTCR_TCSEL(2)     0
 174                         IMX_AUDMUX_V2_PTCR_TFSDIR       0
 175                         IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 176                 >;
 177         };
 178
 179         mux-pins3 {
 180                 fsl,audmux-port = <2>;
 181                 fsl,port-config = <
 182                         IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 183                         0                      IMX_AUDMUX_V2_PDCR_TXRXEN
 184                 >;
 185         };
 186 };
 187
 188 &can1 {
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_can1>;
 191         xceiver-supply = <&reg_5v0>;
 192         status = "okay";
 193 };
 194
 195 &clks {
 196         clocks = <&clock_ksz8081>;
 197         clock-names = "enet_ref_pad";
 198         assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
 199         assigned-clock-parents = <&clock_ksz8081>;
 200 };
 201
 202 &ecspi1 {
 203         cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_ecspi1>;
 206         status = "okay";
 207
 208         flash@0 {
 209                 compatible = "jedec,spi-nor";
 210                 reg = <0>;
 211                 spi-max-frequency = <20000000>;
 212         };
 213 };
 214
 215 &fec {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_enet>;
 218         phy-mode = "rmii";
 219         status = "okay";
 220
 221         mdio {
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224
 225                 /* Microchip KSZ8081RNA PHY */
 226                 rgmii_phy: ethernet-phy@0 {
 227                         reg = <0>;
 228                         interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>;
 229                         reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
 230                         reset-assert-us = <10000>;
 231                         reset-deassert-us = <300>;
 232                 };
 233         };
 234 };
 235
 236 &gpio1 {
 237         gpio-line-names =
 238                 "", "SD1_CD", "", "USB_H1_OC", "", "", "", "",
 239                 "DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
 240                 "", "", "", "", "", "", "", "",
 241                 "", "", "", "", "", "", "", "";
 242 };
 243
 244 &gpio3 {
 245         gpio-line-names =
 246                 "", "", "", "", "", "", "", "",
 247                 "", "", "", "", "", "", "", "",
 248                 "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "",
 249                 "", "", "", "", "", "", "", "";
 250 };
 251
 252 &gpio4 {
 253         gpio-line-names =
 254                 "", "", "", "", "", "", "", "",
 255                 "", "", "", "", "", "", "", "",
 256                 "", "", "", "", "", "", "", "",
 257                 "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", "";
 258 };
 259
 260 &gpio5 {
 261         gpio-line-names =
 262                 "", "", "", "", "", "", "", "",
 263                 "", "", "I2C_EN13", "I2C_EN24", "", "", "", "",
 264                 "", "", "", "", "", "AUDIO_RESET", "", "",
 265                 "", "", "", "", "", "", "", "";
 266 };
 267
 268 &hdmi {
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&pinctrl_hdmi>;
 271         ddc-i2c-bus = <&i2c1>;
 272         status = "okay";
 273 };
 274
 275 /* DDC */
 276 &i2c1 {
 277         clock-frequency = <100000>;
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_i2c1>;
 280         status = "okay";
 281
 282         sgtl5000: audio-codec@a {
 283                 compatible = "fsl,sgtl5000";
 284                 reg = <0xa>;
 285                 #sound-dai-cells = <0>;
 286                 clocks = <&clks 201>;
 287                 VDDA-supply = <&reg_3v3>;
 288                 VDDIO-supply = <&reg_3v3>;
 289                 VDDD-supply = <&reg_1v8>;
 290         };
 291
 292         /* additional i2c devices are added automatically by the boot loader */
 293 };
 294
 295 &i2c2 {
 296         clock-frequency = <50000>;
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_i2c2>;
 299         status = "okay";
 300
 301         /* external interface, device are configured from user space */
 302 };
 303
 304 &i2c3 {
 305         clock-frequency = <100000>;
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_i2c3>;
 308         status = "okay";
 309
 310         rtc@51 {
 311                 compatible = "nxp,pcf8563";
 312                 reg = <0x51>;
 313         };
 314
 315         temperature-sensor@70 {
 316                 compatible = "ti,tmp103";
 317                 reg = <0x70>;
 318         };
 319 };
 320
 321 &i2c4 {
 322         clock-frequency = <50000>;
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_i2c4>;
 325         status = "okay";
 326 };
 327
 328 &pwm1 {
 329         pinctrl-names = "default";
 330         pinctrl-0 = <&pinctrl_pwm1>;
 331         status = "okay";
 332 };
 333
 334 &ssi1 {
 335         #sound-dai-cells = <0>;
 336         fsl,mode = "ac97-slave";
 337         status = "okay";
 338 };
 339
 340 &uart2 {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_uart2>;
 343         status = "okay";
 344 };
 345
 346 &uart4 {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_uart4>;
 349         status = "okay";
 350 };
 351
 352 &uart5 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_uart5>;
 355         status = "okay";
 356 };
 357
 358 &usbh1 {
 359         vbus-supply = <&reg_h1_vbus>;
 360         pinctrl-names = "default";
 361         pinctrl-0 = <&pinctrl_usbh1>;
 362         phy_type = "utmi";
 363         dr_mode = "host";
 364         over-current-active-low;
 365         status = "okay";
 366 };
 367
 368 &usbotg {
 369         vbus-supply = <&reg_otg_vbus>;
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_usbotg>;
 372         phy_type = "utmi";
 373         dr_mode = "host";
 374         over-current-active-low;
 375         status = "okay";
 376 };
 377
 378 &usbphynop1 {
 379         status = "disabled";
 380 };
 381
 382 &usbphynop2 {
 383         status = "disabled";
 384 };
 385
 386 &usdhc1 {
 387         pinctrl-names = "default";
 388         pinctrl-0 = <&pinctrl_usdhc1>;
 389         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 390         no-1-8-v;
 391         disable-wp;
 392         cap-sd-highspeed;
 393         no-mmc;
 394         no-sdio;
 395         status = "okay";
 396 };
 397
 398 &usdhc3 {
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_usdhc3>;
 401         bus-width = <8>;
 402         no-1-8-v;
 403         non-removable;
 404         no-sd;
 405         no-sdio;
 406         status = "okay";
 407 };
 408
 409 &iomuxc {
 410         pinctrl_audmux: audmuxgrp {
 411                 fsl,pins = <
 412                         MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1                 0x030b0
 413                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD                  0x130b0
 414                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC                  0x130b0
 415                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD                  0x110b0
 416                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS                 0x130b0
 417                 >;
 418         };
 419
 420         pinctrl_can1: can1grp {
 421                 fsl,pins = <
 422                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX                0x1b000
 423                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX                0x3008
 424                 >;
 425         };
 426
 427         pinctrl_ecspi1: ecspi1grp {
 428                 fsl,pins = <
 429                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO                 0x1b000
 430                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI                 0x3008
 431                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK                 0x3008
 432                         /* CS */
 433                         MX6QDL_PAD_EIM_D19__GPIO3_IO19                  0x3008
 434                 >;
 435         };
 436
 437         pinctrl_enet: enetgrp {
 438                 fsl,pins = <
 439                         /* MX6QDL_ENET_PINGRP4 */
 440                         MX6QDL_PAD_ENET_MDC__ENET_MDC                   0x1b0b0
 441                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO                 0x1b0b0
 442                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0             0x1b0b0
 443                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1             0x1b0b0
 444                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER               0x1b0b0
 445                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN               0x1b0b0
 446                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0             0x1b0b0
 447                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1             0x1b0b0
 448                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN              0x1b0b0
 449
 450                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK                0x1b0b0
 451                         /* Phy reset */
 452                         MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26               0x1b0b0
 453                         /* nINTRP */
 454                         MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30               0x1b0b0
 455                 >;
 456         };
 457
 458         pinctrl_hdmi: hdmigrp {
 459                 fsl,pins = <
 460                         /* NOTE: DDC is done via I2C2, so DON'T configure DDC
 461                          * pins for HDMI!
 462                          */
 463                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE            0x1f8b0
 464                 >;
 465         };
 466
 467         pinctrl_i2c1: i2c1grp {
 468                 fsl,pins = <
 469                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA                  0x4001f8b1
 470                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL                  0x4001f8b1
 471                 >;
 472         };
 473
 474         pinctrl_i2c2: i2c2grp {
 475                 fsl,pins = <
 476                         MX6QDL_PAD_KEY_COL3__I2C2_SCL                   0x4001b8b1
 477                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA                   0x4001b8b1
 478                 >;
 479         };
 480
 481         pinctrl_i2c3: i2c3grp {
 482                 fsl,pins = <
 483                         MX6QDL_PAD_GPIO_5__I2C3_SCL                     0x4001b8b1
 484                         MX6QDL_PAD_GPIO_6__I2C3_SDA                     0x4001b8b1
 485                 >;
 486         };
 487
 488         pinctrl_i2c4: i2c4grp {
 489                 fsl,pins = <
 490                         MX6QDL_PAD_NANDF_CS3__I2C4_SDA                  0x4001f8b1
 491                         MX6QDL_PAD_NANDF_WP_B__I2C4_SCL                 0x4001f8b1
 492                 >;
 493         };
 494
 495         pinctrl_i2cmux: i2cmuxgrp {
 496                 fsl,pins = <
 497                         MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10              0x1b0b0
 498                         MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11              0x1b0b0
 499                 >;
 500         };
 501
 502         pinctrl_leds: ledsgrp {
 503                 fsl,pins = <
 504                         MX6QDL_PAD_GPIO_8__GPIO1_IO08                   0x1b0b0
 505                         MX6QDL_PAD_GPIO_9__GPIO1_IO09                   0x1b0b0
 506                 >;
 507         };
 508
 509         pinctrl_pwm1: pwm1grp {
 510                 fsl,pins = <
 511                         MX6QDL_PAD_DISP0_DAT8__PWM1_OUT                 0x8
 512                 >;
 513         };
 514
 515         pinctrl_uart2: uart2grp {
 516                 fsl,pins = <
 517                         MX6QDL_PAD_EIM_D26__UART2_TX_DATA               0x1b0b1
 518                         MX6QDL_PAD_EIM_D27__UART2_RX_DATA               0x1b0b1
 519                 >;
 520         };
 521
 522         pinctrl_uart4: uart4grp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA              0x1b0b1
 525                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA              0x1b0b1
 526                 >;
 527         };
 528
 529         pinctrl_uart5: uart5grp {
 530                 fsl,pins = <
 531                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA              0x1b0b1
 532                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA              0x1b0b1
 533                 >;
 534         };
 535
 536         pinctrl_usbh1: usbh1grp {
 537                 fsl,pins = <
 538                         MX6QDL_PAD_GPIO_3__USB_H1_OC                    0x1B058
 539                         MX6QDL_PAD_GPIO_0__GPIO1_IO00                   0x1B058
 540
 541                 >;
 542         };
 543
 544         pinctrl_usbotg: usbotggrp {
 545                 fsl,pins = <
 546                         MX6QDL_PAD_EIM_D21__USB_OTG_OC                  0x1b0b0
 547                         MX6QDL_PAD_EIM_D22__GPIO3_IO22                  0x1b0b0
 548                 >;
 549         };
 550
 551         pinctrl_usdhc1: usdhc1grp {
 552                 fsl,pins = <
 553                         MX6QDL_PAD_SD1_CMD__SD1_CMD                     0x170f9
 554                         MX6QDL_PAD_SD1_CLK__SD1_CLK                     0x100f9
 555                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0                  0x170f9
 556                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1                  0x170f9
 557                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2                  0x170f9
 558                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3                  0x170f9
 559                         MX6QDL_PAD_GPIO_1__GPIO1_IO01                   0x1b0b0
 560                 >;
 561         };
 562
 563         pinctrl_usdhc3: usdhc3grp {
 564                 fsl,pins = <
 565                         MX6QDL_PAD_SD3_CMD__SD3_CMD                     0x17099
 566                         MX6QDL_PAD_SD3_CLK__SD3_CLK                     0x10099
 567                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0                  0x17099
 568                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1                  0x17099
 569                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2                  0x17099
 570                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3                  0x17099
 571                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4                  0x17099
 572                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5                  0x17099
 573                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6                  0x17099
 574                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7                  0x17099
 575                         MX6QDL_PAD_SD3_RST__SD3_RESET                   0x1b0b1
 576                 >;
 577         };
 578 };