src/arm/nxp/imx/imx6qdl-pico.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 //
   3 // Copyright 2018 Technexion Ltd.
   4 //
   5 // Author: Wig Cheng <wig.cheng@technexion.com>
   6 //         Richard Hu <richard.hu@technexion.com>
   7 //         Tapani Utriainen <tapani@technexion.com>
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 / {
  12         chosen {
  13                 stdout-path = &uart1;
  14         };
  15
  16         reg_2p5v: regulator-2p5v {
  17                 compatible = "regulator-fixed";
  18                 regulator-name = "2P5V";
  19                 regulator-min-microvolt = <2500000>;
  20                 regulator-max-microvolt = <2500000>;
  21                 regulator-always-on;
  22         };
  23
  24         reg_3p3v: regulator-3p3v {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "3P3V";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 regulator-always-on;
  30         };
  31
  32         reg_1p8v: regulator-1p8v {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "1P8V";
  35                 regulator-min-microvolt = <1800000>;
  36                 regulator-max-microvolt = <1800000>;
  37                 regulator-always-on;
  38         };
  39
  40         reg_1p5v: regulator-1p5v {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "1P5V";
  43                 regulator-min-microvolt = <1500000>;
  44                 regulator-max-microvolt = <1500000>;
  45                 regulator-always-on;
  46         };
  47
  48         reg_2p8v: regulator-2p8v {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "2P8V";
  51                 regulator-min-microvolt = <2800000>;
  52                 regulator-max-microvolt = <2800000>;
  53                 regulator-always-on;
  54         };
  55
  56         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  57                 pinctrl-names = "default";
  58                 pinctrl-0 = <&pinctrl_usbotg_vbus>;
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "usb_otg_vbus";
  61                 regulator-min-microvolt = <5000000>;
  62                 regulator-max-microvolt = <5000000>;
  63                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
  64         };
  65
  66         codec_osc: clock {
  67                 compatible = "fixed-clock";
  68                 #clock-cells = <0>;
  69                 clock-frequency = <24576000>;
  70         };
  71
  72         sound {
  73                 compatible = "fsl,imx-audio-sgtl5000";
  74                 model = "imx6-pico-sgtl5000";
  75                 ssi-controller = <&ssi1>;
  76                 audio-codec = <&sgtl5000>;
  77                 audio-routing =
  78                         "MIC_IN", "Mic Jack",
  79                         "Mic Jack", "Mic Bias",
  80                         "Headphone Jack", "HP_OUT";
  81                 mux-int-port = <1>;
  82                 mux-ext-port = <3>;
  83         };
  84
  85         backlight: backlight {
  86                 compatible = "pwm-backlight";
  87                 pwms = <&pwm4 0 50000 0>;
  88                 brightness-levels = <0 36 72 108 144 180 216 255>;
  89                 default-brightness-level = <6>;
  90                 status = "okay";
  91         };
  92
  93         reg_lcd_3v3: regulator-lcd-3v3 {
  94                 compatible = "regulator-fixed";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_reg_lcd>;
  97                 regulator-name = "lcd-3v3";
  98                 regulator-min-microvolt = <3300000>;
  99                 regulator-max-microvolt = <3300000>;
 100                 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
 101                 enable-active-high;
 102         };
 103
 104         lcd_display: disp0 {
 105                 compatible = "fsl,imx-parallel-display";
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_ipu1>;
 110                 status = "okay";
 111
 112                 port@0 {
 113                         reg = <0>;
 114
 115                         lcd_display_in: endpoint {
 116                                 remote-endpoint = <&ipu1_di0_disp0>;
 117                         };
 118                 };
 119
 120                 port@1 {
 121                         reg = <1>;
 122
 123                         lcd_display_out: endpoint {
 124                                 remote-endpoint = <&lcd_panel_in>;
 125                         };
 126                 };
 127         };
 128
 129         panel {
 130                 compatible = "vxt,vl050-8048nt-c01";
 131                 backlight = <&backlight>;
 132                 power-supply = <&reg_lcd_3v3>;
 133
 134                 port {
 135                         lcd_panel_in: endpoint {
 136                                 remote-endpoint = <&lcd_display_out>;
 137                         };
 138                 };
 139         };
 140 };
 141
 142 &audmux {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_audmux>;
 145         status = "okay";
 146 };
 147
 148 &can1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_flexcan1>;
 151         status = "okay";
 152 };
 153
 154 &can2 {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_flexcan2>;
 157         status = "okay";
 158 };
 159
 160 &clks {
 161         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 162                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 163         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 164                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 165 };
 166
 167 &ecspi2 {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_ecspi2>;
 170         cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
 171         status = "okay";
 172 };
 173
 174 &fec {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_enet>;
 177         phy-mode = "rgmii-id";
 178         phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
 179         phy-handle = <&phy>;
 180         status = "okay";
 181
 182         mdio {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185
 186                 phy: ethernet-phy@1 {
 187                         reg = <1>;
 188                         qca,clk-out-frequency = <125000000>;
 189                 };
 190         };
 191 };
 192
 193 &hdmi {
 194         ddc-i2c-bus = <&i2c2>;
 195         status = "okay";
 196 };
 197
 198 &i2c1 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&pinctrl_i2c1>;
 201         status = "okay";
 202
 203         sgtl5000: audio-codec@a {
 204                 #sound-dai-cells = <0>;
 205                 reg = <0x0a>;
 206                 compatible = "fsl,sgtl5000";
 207                 clocks = <&codec_osc>;
 208                 VDDA-supply = <&reg_2p5v>;
 209                 VDDIO-supply = <&reg_1p8v>;
 210         };
 211 };
 212
 213 &i2c2 {
 214         clock-frequency = <100000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c2>;
 217         status = "okay";
 218
 219         touchscreen@38 {
 220                 compatible = "edt,edt-ft5x06";
 221                 reg = <0x38>;
 222                 interrupt-parent = <&gpio5>;
 223                 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
 224                 reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
 225                 touchscreen-size-x = <800>;
 226                 touchscreen-size-y = <480>;
 227                 wakeup-source;
 228         };
 229
 230         camera@3c {
 231                 compatible = "ovti,ov5645";
 232                 pinctrl-names = "default";
 233                 pinctrl-0 = <&pinctrl_ov5645>;
 234                 reg = <0x3c>;
 235                 clocks = <&clks IMX6QDL_CLK_CKO2>;
 236                 clock-frequency = <24000000>;
 237                 vdddo-supply = <&reg_1p8v>;
 238                 vdda-supply = <&reg_2p8v>;
 239                 vddd-supply = <&reg_1p5v>;
 240                 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 241                 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 242
 243                 port {
 244                         ov5645_to_mipi_csi2: endpoint {
 245                                 remote-endpoint = <&mipi_csi2_in>;
 246                                 clock-lanes = <0>;
 247                                 data-lanes = <1 2>;
 248                         };
 249                 };
 250         };
 251 };
 252
 253 &i2c3 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_i2c3>;
 256         status = "okay";
 257 };
 258
 259 &ipu1_di0_disp0 {
 260         remote-endpoint = <&lcd_display_in>;
 261 };
 262
 263 &mipi_csi {
 264         status = "okay";
 265
 266         port@0 {
 267                 reg = <0>;
 268
 269                 mipi_csi2_in: endpoint {
 270                         remote-endpoint = <&ov5645_to_mipi_csi2>;
 271                         clock-lanes = <0>;
 272                         data-lanes = <1 2>;
 273                 };
 274         };
 275 };
 276
 277 &pcie {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_pcie_reset>;
 280         reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
 281 };
 282
 283 &pwm1 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_pwm1>;
 286         status = "okay";
 287 };
 288
 289 &pwm2 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_pwm2>;
 292         status = "okay";
 293 };
 294
 295 &pwm3 {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_pwm3>;
 298         status = "okay";
 299 };
 300
 301 &pwm4 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_pwm4>;
 304         status = "okay";
 305 };
 306
 307 &ssi1 {
 308         status = "okay";
 309 };
 310
 311 &uart1 {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_uart1>;
 314         status = "okay";
 315 };
 316
 317 &uart2 {  /* Bluetooth module */
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&pinctrl_uart2>;
 320         uart-has-rtscts;
 321         status = "okay";
 322 };
 323
 324 &uart3 {
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_uart3>;
 327         uart-has-rtscts;
 328         status = "okay";
 329 };
 330
 331 &usbh1 {
 332         status = "okay";
 333 };
 334
 335 &usbotg {
 336         vbus-supply = <&reg_usb_otg_vbus>;
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_usbotg>;
 339         disable-over-current;
 340         dr_mode = "otg";
 341         status = "okay";
 342 };
 343
 344 &usdhc1 {
 345         pinctrl-names = "default";
 346         pinctrl-0 = <&pinctrl_usdhc1>;
 347         bus-width = <8>;
 348         cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
 349         status = "okay";
 350 };
 351
 352 &usdhc2 {  /* Wifi/BT  */
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_usdhc2>;
 355         bus-width = <4>;
 356         no-1-8-v;
 357         keep-power-in-suspend;
 358         non-removable;
 359         status = "okay";
 360 };
 361
 362 &usdhc3 {
 363         pinctrl-names = "default";
 364         pinctrl-0 = <&pinctrl_usdhc3>;
 365         bus-width = <8>;
 366         no-1-8-v;
 367         non-removable;
 368         status = "okay";
 369 };
 370
 371 &iomuxc {
 372         pinctrl-names = "default";
 373         pinctrl-0 = <&pinctrl_hog>;
 374
 375         pinctrl_hog: hoggrp {
 376                 fsl,pins = <
 377                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x4001b0b5 /* PICO_P24 */
 378                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x4001b0b5 /* PICO_P26 */
 379                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b5 /* PICO_P28 */
 380                         MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26        0x4001b0b5 /* PICO_P30 */
 381                         MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27        0x4001b0b5 /* PICO_P32 */
 382                         MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00       0x4001b0b5 /* PICO_P34 */
 383                         MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30       0x4001b0b5 /* PICO_P42 */
 384                         MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31       0x4001b0b5 /* PICO_P44 */
 385                         MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01       0x4001b0b5 /* PICO_P48 */
 386                 >;
 387         };
 388
 389         pinctrl_audmux: audmuxgrp {
 390                 fsl,pins = <
 391                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 392                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 393                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 394                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 395                 >;
 396         };
 397
 398         pinctrl_ecspi1: ecspi1grp {
 399                 fsl,pins = <
 400                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 401                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 402                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 403                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x000f0b0
 404                 >;
 405         };
 406
 407         pinctrl_ecspi2: ecspi2grp {
 408                 fsl,pins = <
 409                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO          0x1b0b1
 410                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI         0x1b0b1
 411                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK         0x1b0b1
 412                         MX6QDL_PAD_EIM_RW__GPIO2_IO26           0x000f0b0
 413                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27          0x000f0b0
 414                 >;
 415         };
 416
 417         pinctrl_enet: enetgrp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 420                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 421                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 422                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 423                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 424                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 425                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 426                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 427                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 428                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 429                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 430                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 431                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 432                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 433                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 434                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 435                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1f0b1
 436                 >;
 437         };
 438
 439         pinctrl_flexcan1: flexcan1grp {
 440                 fsl,pins = <
 441                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 442                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 443                 >;
 444         };
 445
 446         pinctrl_flexcan2: flexcan2grp {
 447                 fsl,pins = <
 448                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 449                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 450                 >;
 451         };
 452
 453         pinctrl_i2c1: i2c1grp {
 454                 fsl,pins = <
 455                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 456                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 457                 >;
 458         };
 459
 460         pinctrl_i2c2: i2c2grp {
 461                 fsl,pins = <
 462                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 463                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 464                 >;
 465         };
 466
 467         pinctrl_i2c3: i2c3grp {
 468                 fsl,pins = <
 469                         MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
 470                         MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 471                 >;
 472         };
 473
 474         pinctrl_ipu1: ipu1grp {
 475                 fsl,pins = <
 476                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
 477                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x10
 478                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
 479                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
 480                         MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04             0x10
 481                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
 482                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
 483                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
 484                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
 485                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
 486                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
 487                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
 488                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
 489                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
 490                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
 491                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
 492                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
 493                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
 494                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
 495                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
 496                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
 497                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
 498                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
 499                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
 500                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
 501                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
 502                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
 503                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
 504                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
 505                 >;
 506         };
 507
 508         pinctrl_ov5645: ov5645grp {
 509                 fsl,pins = <
 510                         MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x0b0b0
 511                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0b0b0
 512                         MX6QDL_PAD_GPIO_3__CCM_CLKO2            0x000b0
 513                 >;
 514         };
 515
 516         pinctrl_pcie_reset: pciegrp {
 517                 fsl,pins = <
 518                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x130b0
 519                 >;
 520         };
 521
 522         pinctrl_pwm1: pwm1grp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 525                 >;
 526         };
 527
 528         pinctrl_pwm2: pwm2grp {
 529                 fsl,pins = <
 530                         MX6QDL_PAD_GPIO_1__PWM2_OUT             0x1b0b1
 531                 >;
 532         };
 533
 534         pinctrl_pwm3: pwm3grp {
 535                 fsl,pins = <
 536                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 537                 >;
 538         };
 539
 540         pinctrl_pwm4: pwm4grp {
 541                 fsl,pins = <
 542                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 543                 >;
 544         };
 545
 546         pinctrl_reg_lcd: reglcdgrp {
 547                 fsl,pins = <
 548                         MX6QDL_PAD_SD4_DAT3__GPIO2_IO11         0x1b0b0
 549                 >;
 550         };
 551
 552         pinctrl_uart1: uart1grp {
 553                 fsl,pins = <
 554                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 555                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 556                 >;
 557         };
 558
 559         pinctrl_uart2: uart2grp {
 560                 fsl,pins = <
 561                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 562                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 563                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 564                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 565                 >;
 566         };
 567
 568         pinctrl_uart3: uart3grp {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 571                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 572                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 573                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 574                 >;
 575         };
 576
 577         pinctrl_usbotg: usbotggrp {
 578                 fsl,pins = <
 579                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 580                 >;
 581         };
 582
 583         pinctrl_usbotg_vbus: usbotgvbusgrp {
 584                 fsl,pins = <
 585                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
 586                 >;
 587         };
 588
 589         pinctrl_usdhc1: usdhc1grp {
 590                 fsl,pins = <
 591                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x17071
 592                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x17071
 593                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x17071
 594                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x17071
 595                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x17071
 596                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x17071
 597                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 598                 >;
 599         };
 600
 601         pinctrl_usdhc2: usdhc2grp {
 602                 fsl,pins = <
 603                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 604                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 605                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 606                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 607                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 608                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 609                 >;
 610         };
 611
 612         pinctrl_usdhc3: usdhc3grp {
 613                 fsl,pins = <
 614                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 615                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 616                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 617                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 618                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 619                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 620                         MX6QDL_PAD_EIM_DA9__GPIO3_IO09          0xb0b1
 621                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 622                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 623                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 624                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 625                 >;
 626         };
 627 };