src/arm64/freescale/imx93-tqma9352.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>,
   4  * D-82229 Seefeld, Germany.
   5  * Author: Markus Niebel
   6  */
   7
   8 #include "imx93.dtsi"
   9
  10 /{
  11         model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";
  12         compatible = "tq,imx93-tqma9352", "fsl,imx93";
  13
  14         reserved-memory {
  15                 #address-cells = <2>;
  16                 #size-cells = <2>;
  17                 ranges;
  18
  19                 linux,cma {
  20                         compatible = "shared-dma-pool";
  21                         reusable;
  22                         alloc-ranges = <0 0x60000000 0 0x40000000>;
  23                         size = <0 0x10000000>;
  24                         linux,cma-default;
  25                 };
  26         };
  27
  28         reg_v1v8: regulator-v1v8 {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "V_1V8";
  31                 regulator-min-microvolt = <1800000>;
  32                 regulator-max-microvolt = <1800000>;
  33         };
  34
  35         reg_v3v3: regulator-v3v3 {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "V_3V3";
  38                 regulator-min-microvolt = <3300000>;
  39                 regulator-max-microvolt = <3300000>;
  40         };
  41
  42         /* SD2 RST# via PMIC SW_EN */
  43         reg_usdhc2_vmmc: regulator-usdhc2 {
  44                 compatible = "regulator-fixed";
  45                 pinctrl-names = "default";
  46                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  47                 regulator-name = "VSD_3V3";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 vin-supply = <&reg_v3v3>;
  51                 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53         };
  54 };
  55
  56 &adc1 {
  57         vref-supply = <&reg_v1v8>;
  58 };
  59
  60 &flexspi1 {
  61         pinctrl-names = "default";
  62         pinctrl-0 = <&pinctrl_flexspi1>;
  63         status = "okay";
  64
  65         flash0: flash@0 {
  66                 compatible = "jedec,spi-nor";
  67                 reg = <0>;
  68                 /*
  69                  * no DQS, RXCLKSRC internal loop back, max 66 MHz
  70                  * clk framework uses CLK_DIVIDER_ROUND_CLOSEST
  71                  * selected value together with root from
  72                  * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to
  73                  * respect the maximum value.
  74                  */
  75                 spi-max-frequency = <62000000>;
  76                 spi-tx-bus-width = <4>;
  77                 spi-rx-bus-width = <4>;
  78         };
  79 };
  80
  81 &gpio1 {
  82         pmic-irq-hog {
  83                 gpio-hog;
  84                 gpios = <3 GPIO_ACTIVE_LOW>;
  85                 input;
  86                 line-name = "PMIC_IRQ#";
  87         };
  88 };
  89
  90 &lpi2c1 {
  91         clock-frequency = <400000>;
  92         pinctrl-names = "default", "sleep";
  93         pinctrl-0 = <&pinctrl_lpi2c1>;
  94         pinctrl-1 = <&pinctrl_lpi2c1>;
  95         status = "okay";
  96
  97         se97_som: temperature-sensor@1b {
  98                 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
  99                 reg = <0x1b>;
 100         };
 101
 102         pcf85063: rtc@51 {
 103                 compatible = "nxp,pcf85063a";
 104                 reg = <0x51>;
 105                 quartz-load-femtofarads = <7000>;
 106         };
 107
 108         eeprom0: eeprom@53 {
 109                 compatible = "nxp,se97b", "atmel,24c02";
 110                 reg = <0x53>;
 111                 pagesize = <16>;
 112                 read-only;
 113                 vcc-supply = <&reg_v3v3>;
 114         };
 115
 116         eeprom1: eeprom@57 {
 117                 compatible = "atmel,24c64";
 118                 reg = <0x57>;
 119                 pagesize = <32>;
 120                 vcc-supply = <&reg_v3v3>;
 121         };
 122
 123         /* protectable identification memory (part of M24C64-D @57) */
 124         eeprom@5f {
 125                 compatible = "st,24c64", "atmel,24c64";
 126                 reg = <0x5f>;
 127                 size = <32>;
 128                 pagesize = <32>;
 129                 vcc-supply = <&reg_v3v3>;
 130         };
 131
 132         imu@6a {
 133                 compatible = "st,ism330dhcx";
 134                 reg = <0x6a>;
 135                 vdd-supply = <&reg_v3v3>;
 136                 vddio-supply = <&reg_v3v3>;
 137         };
 138 };
 139
 140 &usdhc1 {
 141         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 142         pinctrl-0 = <&pinctrl_usdhc1>;
 143         pinctrl-1 = <&pinctrl_usdhc1>;
 144         pinctrl-2 = <&pinctrl_usdhc1>;
 145         bus-width = <8>;
 146         non-removable;
 147         no-sdio;
 148         no-sd;
 149         status = "okay";
 150 };
 151
 152 &wdog3 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&pinctrl_wdog>;
 155         status = "okay";
 156 };
 157
 158 &iomuxc {
 159         pinctrl_flexspi1: flexspi1grp {
 160                 fsl,pins = <
 161                         MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B      0x3fe
 162                         MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK       0x3fe
 163                         MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00   0x3fe
 164                         MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01   0x3fe
 165                         MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02   0x3fe
 166                         MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03   0x3fe
 167                 >;
 168         };
 169
 170         pinctrl_lpi2c1: lpi2c1grp {
 171                 fsl,pins = <
 172                         MX93_PAD_I2C1_SCL__LPI2C1_SCL           0x40000b9e
 173                         MX93_PAD_I2C1_SDA__LPI2C1_SDA           0x40000b9e
 174                 >;
 175         };
 176
 177         pinctrl_pca9451: pca9451grp {
 178                 fsl,pins = <
 179                         MX93_PAD_I2C2_SDA__GPIO1_IO03           0x1306
 180                 >;
 181         };
 182
 183         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 184                 fsl,pins = <
 185                         MX93_PAD_SD2_RESET_B__GPIO3_IO07        0x1306
 186                 >;
 187         };
 188
 189         pinctrl_usdhc1: usdhc1grp {
 190                 fsl,pins = <
 191                         /* HYS | PU | PD | FSEL_3 | X5 */
 192                         MX93_PAD_SD1_CLK__USDHC1_CLK            0x17be
 193                         MX93_PAD_SD1_STROBE__USDHC1_STROBE      0x17be
 194                         /* HYS | PU | FSEL_3 | X5 */
 195                         MX93_PAD_SD1_CMD__USDHC1_CMD            0x13be
 196                         /* HYS | PU | FSEL_3 | X4 */
 197                         MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x139e
 198                         MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x139e
 199                         MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x139e
 200                         MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x139e
 201                         MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x139e
 202                         MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x139e
 203                         MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x139e
 204                         MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x139e
 205                 >;
 206         };
 207
 208         pinctrl_wdog: wdoggrp {
 209                 fsl,pins = <
 210                         MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY       0x31e
 211                 >;
 212         };
 213 };