src/arm64/marvell/armada-3720-turris-mox.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for CZ.NIC Turris Mox Board
   4  * 2019 by Marek Behún <kabel@kernel.org>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/bus/moxtet.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include "armada-372x.dtsi"
  13
  14 / {
  15         model = "CZ.NIC Turris Mox Board";
  16         compatible = "cznic,turris-mox", "marvell,armada3720",
  17                      "marvell,armada3700";
  18
  19         aliases {
  20                 spi0 = &spi0;
  21                 ethernet0 = &eth0;
  22                 ethernet1 = &eth1;
  23                 mmc0 = &sdhci0;
  24                 mmc1 = &sdhci1;
  25         };
  26
  27         chosen {
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         memory@0 {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38                 led {
  39                         label = "mox:red:activity";
  40                         gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
  41                         linux,default-trigger = "default-on";
  42                 };
  43         };
  44
  45         gpio-keys {
  46                 compatible = "gpio-keys";
  47
  48                 key-reset {
  49                         label = "reset";
  50                         linux,code = <KEY_RESTART>;
  51                         gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
  52                         debounce-interval = <60>;
  53                 };
  54         };
  55
  56         exp_usb3_vbus: usb3-vbus {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "usb3-vbus";
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61                 enable-active-high;
  62                 regulator-always-on;
  63                 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
  64         };
  65
  66         vsdc_reg: vsdc-reg {
  67                 compatible = "regulator-gpio";
  68                 regulator-name = "vsdc";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 regulator-boot-on;
  72
  73                 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
  74                 gpios-states = <0>;
  75                 states = <1800000 0x1
  76                           3300000 0x0>;
  77                 enable-active-high;
  78         };
  79
  80         vsdio_reg: vsdio-reg {
  81                 compatible = "regulator-gpio";
  82                 regulator-name = "vsdio";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <3300000>;
  85                 regulator-boot-on;
  86
  87                 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
  88                 gpios-states = <0>;
  89                 states = <1800000 0x1
  90                           3300000 0x0>;
  91                 enable-active-high;
  92         };
  93
  94         sdhci1_pwrseq: sdhci1-pwrseq {
  95                 compatible = "mmc-pwrseq-simple";
  96                 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
  97                 status = "okay";
  98         };
  99
 100         sfp: sfp {
 101                 compatible = "sff,sfp";
 102                 i2c-bus = <&i2c0>;
 103                 los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
 104                 tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
 105                 mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
 106                 tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
 107                 rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
 108                 maximum-power-milliwatt = <3000>;
 109
 110                 /* enabled by U-Boot if SFP module is present */
 111                 status = "disabled";
 112         };
 113
 114         firmware {
 115                 armada-3700-rwtm {
 116                         compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
 117                 };
 118         };
 119 };
 120
 121 &i2c0 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&i2c1_pins>;
 124         clock-frequency = <100000>;
 125         /delete-property/ mrvl,i2c-fast-mode;
 126         status = "okay";
 127
 128         /* MCP7940MT-I/MNY RTC */
 129         rtc@6f {
 130                 compatible = "microchip,mcp7940x";
 131                 reg = <0x6f>;
 132                 interrupt-parent = <&gpiosb>;
 133                 interrupts = <5 0>; /* GPIO2_5 */
 134         };
 135 };
 136
 137 &pcie0 {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
 140         status = "okay";
 141         reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 142         slot-power-limit-milliwatt = <10000>;
 143         /*
 144          * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
 145          * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
 146          * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
 147          * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
 148          * no remapping) and that this address is the lowest from all specified ranges. If these
 149          * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
 150          * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
 151          * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
 152          * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
 153          * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
 154          * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
 155          * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
 156          * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
 157          * Bug related to requirement of same child and parent addresses for first range is fixed
 158          * in U-Boot version 2022.04 by following commit:
 159          * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
 160          */
 161         #address-cells = <3>;
 162         #size-cells = <2>;
 163         ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
 164                   0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */
 165
 166         /* enabled by U-Boot if PCIe module is present */
 167         status = "disabled";
 168 };
 169
 170 &uart0 {
 171         status = "okay";
 172 };
 173
 174 &eth0 {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&rgmii_pins>;
 177         phy-mode = "rgmii-id";
 178         phy-handle = <&phy1>;
 179         status = "okay";
 180 };
 181
 182 &eth1 {
 183         phy-mode = "2500base-x";
 184         managed = "in-band-status";
 185         phys = <&comphy0 1>;
 186 };
 187
 188 &sdhci0 {
 189         wp-inverted;
 190         bus-width = <4>;
 191         cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
 192         vqmmc-supply = <&vsdc_reg>;
 193         marvell,pad-type = "sd";
 194         status = "okay";
 195 };
 196
 197 &sdhci1 {
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&sdio_pins>;
 200         non-removable;
 201         bus-width = <4>;
 202         marvell,pad-type = "sd";
 203         vqmmc-supply = <&vsdio_reg>;
 204         mmc-pwrseq = <&sdhci1_pwrseq>;
 205         /* forbid SDR104 for FCC purposes */
 206         sdhci-caps-mask = <0x2 0x0>;
 207         status = "okay";
 208 };
 209
 210 &spi0 {
 211         status = "okay";
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
 214         assigned-clocks = <&nb_periph_clk 7>;
 215         assigned-clock-parents = <&tbg 1>;
 216         assigned-clock-rates = <20000000>;
 217
 218         flash@0 {
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 compatible = "jedec,spi-nor";
 222                 reg = <0>;
 223                 spi-max-frequency = <20000000>;
 224
 225                 partitions {
 226                         compatible = "fixed-partitions";
 227                         #address-cells = <1>;
 228                         #size-cells = <1>;
 229
 230                         partition@0 {
 231                                 label = "secure-firmware";
 232                                 reg = <0x0 0x20000>;
 233                         };
 234
 235                         partition@20000 {
 236                                 label = "a53-firmware";
 237                                 reg = <0x20000 0x160000>;
 238                         };
 239
 240                         partition@180000 {
 241                                 label = "u-boot-env";
 242                                 reg = <0x180000 0x10000>;
 243                         };
 244
 245                         partition@190000 {
 246                                 label = "Rescue system";
 247                                 reg = <0x190000 0x660000>;
 248                         };
 249
 250                         partition@7f0000 {
 251                                 label = "dtb";
 252                                 reg = <0x7f0000 0x10000>;
 253                         };
 254                 };
 255         };
 256
 257         moxtet: moxtet@1 {
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 compatible = "cznic,moxtet";
 261                 reg = <1>;
 262                 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
 263                 spi-max-frequency = <10000000>;
 264                 spi-cpol;
 265                 spi-cpha;
 266                 interrupt-controller;
 267                 #interrupt-cells = <1>;
 268                 interrupt-parent = <&gpiosb>;
 269                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 270                 status = "okay";
 271
 272                 moxtet_sfp: gpio@0 {
 273                         compatible = "cznic,moxtet-gpio";
 274                         gpio-controller;
 275                         #gpio-cells = <2>;
 276                         reg = <0>;
 277                         status = "disabled";
 278                 };
 279         };
 280 };
 281
 282 &usb2 {
 283         status = "okay";
 284 };
 285
 286 &comphy2 {
 287         connector {
 288                 compatible = "usb-a-connector";
 289                 phy-supply = <&exp_usb3_vbus>;
 290         };
 291 };
 292
 293 &usb3 {
 294         status = "okay";
 295         phys = <&comphy2 0>;
 296 };
 297
 298 &mdio {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&smi_pins>;
 301         status = "okay";
 302
 303         phy1: ethernet-phy@1 {
 304                 reg = <1>;
 305         };
 306
 307         /* switch nodes are enabled by U-Boot if modules are present */
 308         switch0@10 {
 309                 compatible = "marvell,mv88e6190";
 310                 reg = <0x10>;
 311                 dsa,member = <0 0>;
 312                 interrupt-parent = <&moxtet>;
 313                 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
 314                 status = "disabled";
 315
 316                 mdio {
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319
 320                         switch0phy1: switch0phy1@1 {
 321                                 reg = <0x1>;
 322                         };
 323
 324                         switch0phy2: switch0phy2@2 {
 325                                 reg = <0x2>;
 326                         };
 327
 328                         switch0phy3: switch0phy3@3 {
 329                                 reg = <0x3>;
 330                         };
 331
 332                         switch0phy4: switch0phy4@4 {
 333                                 reg = <0x4>;
 334                         };
 335
 336                         switch0phy5: switch0phy5@5 {
 337                                 reg = <0x5>;
 338                         };
 339
 340                         switch0phy6: switch0phy6@6 {
 341                                 reg = <0x6>;
 342                         };
 343
 344                         switch0phy7: switch0phy7@7 {
 345                                 reg = <0x7>;
 346                         };
 347
 348                         switch0phy8: switch0phy8@8 {
 349                                 reg = <0x8>;
 350                         };
 351                 };
 352
 353                 ports {
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356
 357                         port@1 {
 358                                 reg = <0x1>;
 359                                 label = "lan1";
 360                                 phy-handle = <&switch0phy1>;
 361                         };
 362
 363                         port@2 {
 364                                 reg = <0x2>;
 365                                 label = "lan2";
 366                                 phy-handle = <&switch0phy2>;
 367                         };
 368
 369                         port@3 {
 370                                 reg = <0x3>;
 371                                 label = "lan3";
 372                                 phy-handle = <&switch0phy3>;
 373                         };
 374
 375                         port@4 {
 376                                 reg = <0x4>;
 377                                 label = "lan4";
 378                                 phy-handle = <&switch0phy4>;
 379                         };
 380
 381                         port@5 {
 382                                 reg = <0x5>;
 383                                 label = "lan5";
 384                                 phy-handle = <&switch0phy5>;
 385                         };
 386
 387                         port@6 {
 388                                 reg = <0x6>;
 389                                 label = "lan6";
 390                                 phy-handle = <&switch0phy6>;
 391                         };
 392
 393                         port@7 {
 394                                 reg = <0x7>;
 395                                 label = "lan7";
 396                                 phy-handle = <&switch0phy7>;
 397                         };
 398
 399                         port@8 {
 400                                 reg = <0x8>;
 401                                 label = "lan8";
 402                                 phy-handle = <&switch0phy8>;
 403                         };
 404
 405                         port@9 {
 406                                 reg = <0x9>;
 407                                 label = "cpu";
 408                                 ethernet = <&eth1>;
 409                                 phy-mode = "2500base-x";
 410                                 managed = "in-band-status";
 411                         };
 412
 413                         switch0port10: port@a {
 414                                 reg = <0xa>;
 415                                 label = "dsa";
 416                                 phy-mode = "2500base-x";
 417                                 managed = "in-band-status";
 418                                 link = <&switch1port9 &switch2port9>;
 419                                 status = "disabled";
 420                         };
 421
 422                         port-sfp@a {
 423                                 reg = <0xa>;
 424                                 label = "sfp";
 425                                 sfp = <&sfp>;
 426                                 phy-mode = "sgmii";
 427                                 managed = "in-band-status";
 428                                 status = "disabled";
 429                         };
 430                 };
 431         };
 432
 433         switch0@2 {
 434                 compatible = "marvell,mv88e6085";
 435                 reg = <0x2>;
 436                 dsa,member = <0 0>;
 437                 interrupt-parent = <&moxtet>;
 438                 interrupts = <MOXTET_IRQ_TOPAZ>;
 439                 status = "disabled";
 440
 441                 mdio {
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444
 445                         switch0phy1_topaz: switch0phy1@11 {
 446                                 reg = <0x11>;
 447                         };
 448
 449                         switch0phy2_topaz: switch0phy2@12 {
 450                                 reg = <0x12>;
 451                         };
 452
 453                         switch0phy3_topaz: switch0phy3@13 {
 454                                 reg = <0x13>;
 455                         };
 456
 457                         switch0phy4_topaz: switch0phy4@14 {
 458                                 reg = <0x14>;
 459                         };
 460                 };
 461
 462                 ports {
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465
 466                         port@1 {
 467                                 reg = <0x1>;
 468                                 label = "lan1";
 469                                 phy-handle = <&switch0phy1_topaz>;
 470                         };
 471
 472                         port@2 {
 473                                 reg = <0x2>;
 474                                 label = "lan2";
 475                                 phy-handle = <&switch0phy2_topaz>;
 476                         };
 477
 478                         port@3 {
 479                                 reg = <0x3>;
 480                                 label = "lan3";
 481                                 phy-handle = <&switch0phy3_topaz>;
 482                         };
 483
 484                         port@4 {
 485                                 reg = <0x4>;
 486                                 label = "lan4";
 487                                 phy-handle = <&switch0phy4_topaz>;
 488                         };
 489
 490                         port@5 {
 491                                 reg = <0x5>;
 492                                 label = "cpu";
 493                                 phy-mode = "2500base-x";
 494                                 managed = "in-band-status";
 495                                 ethernet = <&eth1>;
 496                         };
 497                 };
 498         };
 499
 500         switch1@11 {
 501                 compatible = "marvell,mv88e6190";
 502                 reg = <0x11>;
 503                 dsa,member = <0 1>;
 504                 interrupt-parent = <&moxtet>;
 505                 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
 506                 status = "disabled";
 507
 508                 mdio {
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511
 512                         switch1phy1: switch1phy1@1 {
 513                                 reg = <0x1>;
 514                         };
 515
 516                         switch1phy2: switch1phy2@2 {
 517                                 reg = <0x2>;
 518                         };
 519
 520                         switch1phy3: switch1phy3@3 {
 521                                 reg = <0x3>;
 522                         };
 523
 524                         switch1phy4: switch1phy4@4 {
 525                                 reg = <0x4>;
 526                         };
 527
 528                         switch1phy5: switch1phy5@5 {
 529                                 reg = <0x5>;
 530                         };
 531
 532                         switch1phy6: switch1phy6@6 {
 533                                 reg = <0x6>;
 534                         };
 535
 536                         switch1phy7: switch1phy7@7 {
 537                                 reg = <0x7>;
 538                         };
 539
 540                         switch1phy8: switch1phy8@8 {
 541                                 reg = <0x8>;
 542                         };
 543                 };
 544
 545                 ports {
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548
 549                         port@1 {
 550                                 reg = <0x1>;
 551                                 label = "lan9";
 552                                 phy-handle = <&switch1phy1>;
 553                         };
 554
 555                         port@2 {
 556                                 reg = <0x2>;
 557                                 label = "lan10";
 558                                 phy-handle = <&switch1phy2>;
 559                         };
 560
 561                         port@3 {
 562                                 reg = <0x3>;
 563                                 label = "lan11";
 564                                 phy-handle = <&switch1phy3>;
 565                         };
 566
 567                         port@4 {
 568                                 reg = <0x4>;
 569                                 label = "lan12";
 570                                 phy-handle = <&switch1phy4>;
 571                         };
 572
 573                         port@5 {
 574                                 reg = <0x5>;
 575                                 label = "lan13";
 576                                 phy-handle = <&switch1phy5>;
 577                         };
 578
 579                         port@6 {
 580                                 reg = <0x6>;
 581                                 label = "lan14";
 582                                 phy-handle = <&switch1phy6>;
 583                         };
 584
 585                         port@7 {
 586                                 reg = <0x7>;
 587                                 label = "lan15";
 588                                 phy-handle = <&switch1phy7>;
 589                         };
 590
 591                         port@8 {
 592                                 reg = <0x8>;
 593                                 label = "lan16";
 594                                 phy-handle = <&switch1phy8>;
 595                         };
 596
 597                         switch1port9: port@9 {
 598                                 reg = <0x9>;
 599                                 label = "dsa";
 600                                 phy-mode = "2500base-x";
 601                                 managed = "in-band-status";
 602                                 link = <&switch0port10>;
 603                         };
 604
 605                         switch1port10: port@a {
 606                                 reg = <0xa>;
 607                                 label = "dsa";
 608                                 phy-mode = "2500base-x";
 609                                 managed = "in-band-status";
 610                                 link = <&switch2port9>;
 611                                 status = "disabled";
 612                         };
 613
 614                         port-sfp@a {
 615                                 reg = <0xa>;
 616                                 label = "sfp";
 617                                 sfp = <&sfp>;
 618                                 phy-mode = "sgmii";
 619                                 managed = "in-band-status";
 620                                 status = "disabled";
 621                         };
 622                 };
 623         };
 624
 625         switch1@2 {
 626                 compatible = "marvell,mv88e6085";
 627                 reg = <0x2>;
 628                 dsa,member = <0 1>;
 629                 interrupt-parent = <&moxtet>;
 630                 interrupts = <MOXTET_IRQ_TOPAZ>;
 631                 status = "disabled";
 632
 633                 mdio {
 634                         #address-cells = <1>;
 635                         #size-cells = <0>;
 636
 637                         switch1phy1_topaz: switch1phy1@11 {
 638                                 reg = <0x11>;
 639                         };
 640
 641                         switch1phy2_topaz: switch1phy2@12 {
 642                                 reg = <0x12>;
 643                         };
 644
 645                         switch1phy3_topaz: switch1phy3@13 {
 646                                 reg = <0x13>;
 647                         };
 648
 649                         switch1phy4_topaz: switch1phy4@14 {
 650                                 reg = <0x14>;
 651                         };
 652                 };
 653
 654                 ports {
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657
 658                         port@1 {
 659                                 reg = <0x1>;
 660                                 label = "lan9";
 661                                 phy-handle = <&switch1phy1_topaz>;
 662                         };
 663
 664                         port@2 {
 665                                 reg = <0x2>;
 666                                 label = "lan10";
 667                                 phy-handle = <&switch1phy2_topaz>;
 668                         };
 669
 670                         port@3 {
 671                                 reg = <0x3>;
 672                                 label = "lan11";
 673                                 phy-handle = <&switch1phy3_topaz>;
 674                         };
 675
 676                         port@4 {
 677                                 reg = <0x4>;
 678                                 label = "lan12";
 679                                 phy-handle = <&switch1phy4_topaz>;
 680                         };
 681
 682                         port@5 {
 683                                 reg = <0x5>;
 684                                 label = "dsa";
 685                                 phy-mode = "2500base-x";
 686                                 managed = "in-band-status";
 687                                 link = <&switch0port10>;
 688                         };
 689                 };
 690         };
 691
 692         switch2@12 {
 693                 compatible = "marvell,mv88e6190";
 694                 reg = <0x12>;
 695                 dsa,member = <0 2>;
 696                 interrupt-parent = <&moxtet>;
 697                 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
 698                 status = "disabled";
 699
 700                 mdio {
 701                         #address-cells = <1>;
 702                         #size-cells = <0>;
 703
 704                         switch2phy1: switch2phy1@1 {
 705                                 reg = <0x1>;
 706                         };
 707
 708                         switch2phy2: switch2phy2@2 {
 709                                 reg = <0x2>;
 710                         };
 711
 712                         switch2phy3: switch2phy3@3 {
 713                                 reg = <0x3>;
 714                         };
 715
 716                         switch2phy4: switch2phy4@4 {
 717                                 reg = <0x4>;
 718                         };
 719
 720                         switch2phy5: switch2phy5@5 {
 721                                 reg = <0x5>;
 722                         };
 723
 724                         switch2phy6: switch2phy6@6 {
 725                                 reg = <0x6>;
 726                         };
 727
 728                         switch2phy7: switch2phy7@7 {
 729                                 reg = <0x7>;
 730                         };
 731
 732                         switch2phy8: switch2phy8@8 {
 733                                 reg = <0x8>;
 734                         };
 735                 };
 736
 737                 ports {
 738                         #address-cells = <1>;
 739                         #size-cells = <0>;
 740
 741                         port@1 {
 742                                 reg = <0x1>;
 743                                 label = "lan17";
 744                                 phy-handle = <&switch2phy1>;
 745                         };
 746
 747                         port@2 {
 748                                 reg = <0x2>;
 749                                 label = "lan18";
 750                                 phy-handle = <&switch2phy2>;
 751                         };
 752
 753                         port@3 {
 754                                 reg = <0x3>;
 755                                 label = "lan19";
 756                                 phy-handle = <&switch2phy3>;
 757                         };
 758
 759                         port@4 {
 760                                 reg = <0x4>;
 761                                 label = "lan20";
 762                                 phy-handle = <&switch2phy4>;
 763                         };
 764
 765                         port@5 {
 766                                 reg = <0x5>;
 767                                 label = "lan21";
 768                                 phy-handle = <&switch2phy5>;
 769                         };
 770
 771                         port@6 {
 772                                 reg = <0x6>;
 773                                 label = "lan22";
 774                                 phy-handle = <&switch2phy6>;
 775                         };
 776
 777                         port@7 {
 778                                 reg = <0x7>;
 779                                 label = "lan23";
 780                                 phy-handle = <&switch2phy7>;
 781                         };
 782
 783                         port@8 {
 784                                 reg = <0x8>;
 785                                 label = "lan24";
 786                                 phy-handle = <&switch2phy8>;
 787                         };
 788
 789                         switch2port9: port@9 {
 790                                 reg = <0x9>;
 791                                 label = "dsa";
 792                                 phy-mode = "2500base-x";
 793                                 managed = "in-band-status";
 794                                 link = <&switch1port10 &switch0port10>;
 795                         };
 796
 797                         port-sfp@a {
 798                                 reg = <0xa>;
 799                                 label = "sfp";
 800                                 sfp = <&sfp>;
 801                                 phy-mode = "sgmii";
 802                                 managed = "in-band-status";
 803                                 status = "disabled";
 804                         };
 805                 };
 806         };
 807
 808         switch2@2 {
 809                 compatible = "marvell,mv88e6085";
 810                 reg = <0x2>;
 811                 dsa,member = <0 2>;
 812                 interrupt-parent = <&moxtet>;
 813                 interrupts = <MOXTET_IRQ_TOPAZ>;
 814                 status = "disabled";
 815
 816                 mdio {
 817                         #address-cells = <1>;
 818                         #size-cells = <0>;
 819
 820                         switch2phy1_topaz: switch2phy1@11 {
 821                                 reg = <0x11>;
 822                         };
 823
 824                         switch2phy2_topaz: switch2phy2@12 {
 825                                 reg = <0x12>;
 826                         };
 827
 828                         switch2phy3_topaz: switch2phy3@13 {
 829                                 reg = <0x13>;
 830                         };
 831
 832                         switch2phy4_topaz: switch2phy4@14 {
 833                                 reg = <0x14>;
 834                         };
 835                 };
 836
 837                 ports {
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840
 841                         port@1 {
 842                                 reg = <0x1>;
 843                                 label = "lan17";
 844                                 phy-handle = <&switch2phy1_topaz>;
 845                         };
 846
 847                         port@2 {
 848                                 reg = <0x2>;
 849                                 label = "lan18";
 850                                 phy-handle = <&switch2phy2_topaz>;
 851                         };
 852
 853                         port@3 {
 854                                 reg = <0x3>;
 855                                 label = "lan19";
 856                                 phy-handle = <&switch2phy3_topaz>;
 857                         };
 858
 859                         port@4 {
 860                                 reg = <0x4>;
 861                                 label = "lan20";
 862                                 phy-handle = <&switch2phy4_topaz>;
 863                         };
 864
 865                         port@5 {
 866                                 reg = <0x5>;
 867                                 label = "dsa";
 868                                 phy-mode = "2500base-x";
 869                                 managed = "in-band-status";
 870                                 link = <&switch1port10 &switch0port10>;
 871                         };
 872                 };
 873         };
 874 };