src/powerpc/fsl/p2020ds.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * P2020 DS Device Tree Source
   4  *
   5  * Copyright 2009-2011 Freescale Semiconductor Inc.
   6  */
   7
   8 /include/ "p2020si-pre.dtsi"
   9
  10 / {
  11         model = "fsl,P2020DS";
  12         compatible = "fsl,P2020DS";
  13
  14         memory {
  15                 device_type = "memory";
  16         };
  17
  18         board_lbc: lbc: localbus@ffe05000 {
  19                 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  20                           0x1 0x0 0x0 0xe0000000 0x08000000
  21                           0x2 0x0 0x0 0xffa00000 0x00040000
  22                           0x3 0x0 0x0 0xffdf0000 0x00008000
  23                           0x4 0x0 0x0 0xffa40000 0x00040000
  24                           0x5 0x0 0x0 0xffa80000 0x00040000
  25                           0x6 0x0 0x0 0xffac0000 0x00040000>;
  26                 reg = <0 0xffe05000 0 0x1000>;
  27         };
  28
  29         board_soc: soc: soc@ffe00000 {
  30                 ranges = <0x0 0x0 0xffe00000 0x100000>;
  31         };
  32
  33         pci2: pcie@ffe08000 {
  34                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
  35                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
  36                 reg = <0 0xffe08000 0 0x1000>;
  37                 pcie@0 {
  38                         ranges = <0x2000000 0x0 0x80000000
  39                                   0x2000000 0x0 0x80000000
  40                                   0x0 0x20000000
  41
  42                                   0x1000000 0x0 0x0
  43                                   0x1000000 0x0 0x0
  44                                   0x0 0x10000>;
  45                 };
  46         };
  47
  48         board_pci1: pci1: pcie@ffe09000 {
  49                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
  50                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
  51                 reg = <0 0xffe09000 0 0x1000>;
  52                 pcie@0 {
  53                         ranges = <0x2000000 0x0 0xa0000000
  54                                   0x2000000 0x0 0xa0000000
  55                                   0x0 0x20000000
  56
  57                                   0x1000000 0x0 0x0
  58                                   0x1000000 0x0 0x0
  59                                   0x0 0x10000>;
  60                 };
  61         };
  62
  63         pci0: pcie@ffe0a000 {
  64                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
  65                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
  66                 reg = <0 0xffe0a000 0 0x1000>;
  67                 pcie@0 {
  68                         ranges = <0x2000000 0x0 0xc0000000
  69                                   0x2000000 0x0 0xc0000000
  70                                   0x0 0x20000000
  71
  72                                   0x1000000 0x0 0x0
  73                                   0x1000000 0x0 0x0
  74                                   0x0 0x10000>;
  75                 };
  76         };
  77 };
  78
  79 /*
  80  * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
  81  * for interrupt-map & interrupt-map-mask
  82  */
  83
  84 /include/ "p2020si-post.dtsi"
  85 /include/ "p2020ds.dtsi"