sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
- sandbox_nolto:
- TEST_PY_BD: "sandbox"
- BUILD_ENV: "NO_LTO=1"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
-sandbox without LTO test.py:
- variables:
- TEST_PY_BD: "sandbox"
- BUILD_ENV: "NO_LTO=1"
- <<: *buildman_and_testpy_dfn
-
sandbox64 test.py:
variables:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-16"
<<: *buildman_and_testpy_dfn
-sandbox64 without LTO test.py:
- variables:
- TEST_PY_BD: "sandbox64"
- BUILD_ENV: "NO_LTO=1"
- <<: *buildman_and_testpy_dfn
-
sandbox_spl test.py:
variables:
TEST_PY_BD: "sandbox_spl"
Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com>
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
+This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org>
+This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
libs-$(CONFIG_API) += api/
libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
libs-y += boot/
-libs-y += cmd/
+libs-$(CONFIG_CMDLINE) += cmd/
libs-y += common/
libs-$(CONFIG_OF_EMBED) += dts/
libs-y += env/
@# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
- $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not override OF_HAS_PRIOR_STAGE by
@# disabling OF_BOARD.
$(call cmd,ofcheck,$(KCONFIG_CONFIG))
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
-#if defined(CONFIG_SCSI)
- specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
- specs[ENUM_SCSI].enum_started = 0;
- specs[ENUM_SCSI].enum_ended = 0;
- specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
- specs[ENUM_SCSI].name = "scsi";
-#endif
#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV;
specs[ENUM_USB].enum_started = 0;
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
- select CMD_POWEROFF
+ select CMD_POWEROFF if CMDLINE
select DM
select DM_EVENT
select DM_FUZZING_ENGINE
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
- select SYSRESET_CMD_POWEROFF
+ select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ
- select SUPPORT_EXTENSION_SCAN
+ select SUPPORT_EXTENSION_SCAN if CMDLINE
select SUPPORT_ACPI
imply BITREVERSE
select BLOBLIST
imply BINMAN
imply CMD_MBR
imply CMD_MMC
+ imply BOOTSTD_DEFAULTS if BOOTSTD_FULL && CMDLINE
+ imply BOOTMETH_DISTRO if BOOTSTD_FULL && CMDLINE
+ imply CMD_SYSBOOT if BOOTSTD_FULL
config SH
bool "SuperH architecture"
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
- imply DM_SCSI
+ imply SCSI
imply DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
+ imply SYS_THUMB_BUILD
config ARCH_DAVINCI
bool "TI DaVinci"
select DM_SPI_FLASH if SPI
select DM_KEYBOARD
select DM_MMC if MMC
- select DM_SCSI if SCSI
select DM_SERIAL
select OF_BOARD_SETUP
select OF_CONTROL
select PCI
select DM_RNG
select DM_RTC
- select DM_SCSI
+ select SCSI
select DM_SERIAL
select DM_SPI
select GPIO_EXTRA_HEADER
select REGMAP
select SYSCON
select SYSRESET
- select SYS_THUMB_BUILD
+ select SYS_THUMB_BUILD if !ARM64
imply SPL_SYSRESET
imply CMD_DM
imply CMD_POWEROFF
select PCI
select DM_PCI
select SCSI
- select DM_SCSI
select DM_SERIAL
imply CMD_PCI
help
stm32mp15xx-dhcor-drc-compact.dtb \
stm32mp15xx-dhcor-testbench.dtb
+dtb-$(CONFIG_STM32MP25X) += \
+ stm32mp257f-ev1.dtb
+
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+&pinctrl {
+ usart2_pins_a: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_idle_pins_a: usart2-idle-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usart2_sleep_pins_a: usart2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
+ <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2023
+ */
+
+/ {
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ gpio25 = &gpioz;
+ pinctrl0 = &pinctrl;
+ pinctrl1 = &pinctrl_z;
+ };
+
+ firmware {
+ optee {
+ bootph-all;
+ };
+ };
+
+ /* need PSCI for sysreset during board_f */
+ psci {
+ bootph-all;
+ };
+
+ soc@0 {
+ bootph-all;
+ };
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
+&gpioj {
+ bootph-all;
+};
+
+&gpiok {
+ bootph-all;
+};
+
+&gpioz {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&rifsc {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
+&syscfg {
+ bootph-all;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>;
+ interrupt-parent = <&intc>;
+ };
+
+ arm_wdt: watchdog {
+ compatible = "arm,smc-wdt";
+ arm,smc-id = <0xb200005a>;
+ status = "disabled";
+ };
+
+ clocks {
+ ck_flexgen_08: ck-flexgen-08 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ ck_flexgen_51: ck-flexgen-51 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+
+ ck_icn_ls_mcu: ck-icn-ls-mcu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ scmi {
+ compatible = "linaro,scmi-optee";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linaro,optee-channel-id = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ intc: interrupt-controller@4ac00000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0x0 0x4ac10000 0x0 0x1000>,
+ <0x0 0x4ac20000 0x0 0x2000>,
+ <0x0 0x4ac40000 0x0 0x2000>,
+ <0x0 0x4ac60000 0x0 0x2000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ always-on;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges = <0x0 0x0 0x0 0x80000000>;
+
+ rifsc: rifsc-bus@42080000 {
+ compatible = "simple-bus";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usart2: serial@400e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_flexgen_08>;
+ status = "disabled";
+ };
+ };
+
+ syscfg: syscon@44230000 {
+ compatible = "st,stm32mp25-syscfg", "syscon";
+ reg = <0x44230000 0x10000>;
+ };
+
+ pinctrl: pinctrl@44240000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-pinctrl";
+ ranges = <0 0x44240000 0xa0400>;
+ pins-are-numbered;
+
+ gpioa: gpio@44240000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOA";
+ status = "disabled";
+ };
+
+ gpiob: gpio@44250000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x10000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOB";
+ status = "disabled";
+ };
+
+ gpioc: gpio@44260000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOC";
+ status = "disabled";
+ };
+
+ gpiod: gpio@44270000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x30000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOD";
+ status = "disabled";
+ };
+
+ gpioe: gpio@44280000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOE";
+ status = "disabled";
+ };
+
+ gpiof: gpio@44290000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x50000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOF";
+ status = "disabled";
+ };
+
+ gpiog: gpio@442a0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x60000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOG";
+ status = "disabled";
+ };
+
+ gpioh: gpio@442b0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x70000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOH";
+ status = "disabled";
+ };
+
+ gpioi: gpio@442c0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x80000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOI";
+ status = "disabled";
+ };
+
+ gpioj: gpio@442d0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x90000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOJ";
+ status = "disabled";
+ };
+
+ gpiok: gpio@442e0000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa0000 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOK";
+ status = "disabled";
+ };
+ };
+
+ pinctrl_z: pinctrl@46200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp257-z-pinctrl";
+ ranges = <0 0x46200000 0x400>;
+ pins-are-numbered;
+
+ gpioz: gpio@46200000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&ck_icn_ls_mcu>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ status = "disabled";
+ };
+
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp251.dtsi"
+
+/ {
+ cpus {
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a35";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+ };
+
+ arm-pmu {
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp253.dtsi"
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+#include "stm32mp255.dtsi"
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ */
+
+#include "stm32mp25-u-boot.dtsi"
+
+&usart2 {
+ bootph-all;
+};
+
+&usart2_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/dts-v1/;
+
+#include "stm32mp257.dtsi"
+#include "stm32mp25xf.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
+ compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
+
+ aliases {
+ serial0 = &usart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ fw@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x4000000>;
+ no-map;
+ };
+ };
+};
+
+&arm_wdt {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&usart2 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_idle_pins_a>;
+ pinctrl-2 = <&usart2_sleep_pins_a>;
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+/ {
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AI>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio@442d0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio@442e0000 {
+ status = "okay";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AK>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
+ */
+
+&pinctrl {
+ st,package = <STM32MP_PKG_AL>;
+
+ gpioa: gpio@44240000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@44250000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio@44260000 {
+ status = "okay";
+ ngpios = <14>;
+ gpio-ranges = <&pinctrl 0 32 14>;
+ };
+
+ gpiod: gpio@44270000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio@44280000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio@44290000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio@442a0000 {
+ status = "okay";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio@442b0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 2 114 12>;
+ };
+
+ gpioi: gpio@442c0000 {
+ status = "okay";
+ ngpios = <12>;
+ gpio-ranges = <&pinctrl 0 128 12>;
+ };
+};
+
+&pinctrl_z {
+ gpioz: gpio@46200000 {
+ status = "okay";
+ ngpios = <10>;
+ gpio-ranges = <&pinctrl_z 0 400 10>;
+ };
+};
#ifndef _CPU_H
#define _CPU_H
+#include <asm/arch/omap.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
};
#endif
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
-#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
-#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
-#endif
-
/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE
#endif /* CONFIG_ARM64 */
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK)
+#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK
+#endif
+
#ifndef __ASSEMBLY__
/**
* save_boot_params() - Save boot parameters before starting reset sequence
#include <cpu_func.h>
#include <efi_loader.h>
#include <irq_func.h>
+#include <semihosting.h>
#include <asm/global_data.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/ptrace.h>
regs->ARM_pc = pc | (regs->ARM_pc & PCMASK);
}
+/*
+ * Try to "emulate" a semihosting call in the event that we don't have a
+ * debugger attached.
+ */
+static bool smh_emulate_trap(struct pt_regs *regs)
+{
+ if (regs->ARM_cpsr & T_BIT) {
+ u16 *insn = (u16 *)(regs->ARM_pc - 2);
+
+ if (*insn != SMH_T32_SVC)
+ return false;
+ } else {
+ u32 *insn = (u32 *)(regs->ARM_pc - 4);
+
+ if (*insn != SMH_A32_SVC)
+ return false;
+ }
+
+ /* Avoid future semihosting calls */
+ disable_semihosting();
+
+ /* Just pretend the call failed */
+ regs->ARM_r0 = -1;
+ return true;
+}
+
void do_undefined_instruction (struct pt_regs *pt_regs)
{
efi_restore_gd();
void do_software_interrupt (struct pt_regs *pt_regs)
{
+ if (CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK) &&
+ smh_emulate_trap(pt_regs))
+ return;
+
efi_restore_gd();
printf ("software interrupt\n");
fixup_pc(pt_regs, -4);
#elif defined(CONFIG_SYS_THUMB_BUILD)
svc #0xab
#else
+#if CONFIG_SYS_ARM_ARCH < 7
+ /* Before the ARMv7 exception model, svc (swi) clobbers lr */
+ mov r2, lr
+#endif
svc #0x123456
#endif
#if defined(CONFIG_ARM64)
ret
+#elif CONFIG_SYS_ARM_ARCH < 7
+ bx r2
#else
bx lr
#endif
movs pc, lr @ jump to next instruction & switch modes.
.endm
+ .macro get_bad_stack_swi
+ sub r13, r13, #4 @ space on current stack for scratch reg.
+ str r0, [r13] @ save R0's value.
+ ldr r0, IRQ_STACK_START_IN @ get data regions start
+ str lr, [r0] @ save caller lr in position 0 of saved stack
+ mrs lr, spsr @ get the spsr
+ str lr, [r0, #4] @ save spsr in position 1 of saved stack
+ ldr lr, [r0] @ restore lr
+ ldr r0, [r13] @ restore r0
+ add r13, r13, #4 @ pop stack entry
+ .endm
+
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.align 5
software_interrupt:
- get_bad_stack
+ get_bad_stack_swi
bad_save_user_regs
bl do_software_interrupt
+#if CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ movs pc, lr @ return & move spsr_svc into cpsr
+#endif
.align 5
prefetch_abort:
#ifndef __DM365_LOWLEVEL_H
#define __DM365_LOWLEVEL_H
-#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
select DM_GPIO
select DM_MMC
select PCI
- select DM_SCSI
+ select SCSI
select VIDEO
select OF_CONTROL
select SUPPORT_SPL
#ifndef _PINCTRL_SNAPDRAGON_H
#define _PINCTRL_SNAPDRAGON_H
-#include <common.h>
-
struct msm_pinctrl_data {
int pin_count;
int functions_count;
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
-#include <common.h>
#include <asm/arch/hardware.h>
#include "common.h"
* Dave Gerlach <d-gerlach@ti.com>
*/
-#include <common.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/io.h>
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <fdt_support.h>
#include <init.h>
#include <asm/global_data.h>
*
*/
-#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <image.h>
#include <init.h>
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
* David Huang <d-huang@ti.com>
*/
-#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
* Lokesh Vutla <lokeshvutla@ti.com>
*/
-#include <common.h>
#include <asm/io.h>
#include <linux/kernel.h>
#include "common.h"
*/
#include <asm/io.h>
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
* Andreas Dannenberg <dannenberg@ti.com>
*/
-#include <common.h>
#include <dm.h>
#include <image.h>
#include <log.h>
#ifndef __ASM_ARCH_MUX_K2G_H
#define __ASM_ARCH_MUX_K2G_H
-#include <common.h>
#include <asm/io.h>
#define K2G_PADCFG_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x1000)
return 0;
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
- printf("MVEBU SATA INIT\n");
- board_ahci_enable();
- ahci_init((void __iomem *)MVEBU_SATA0_BASE);
-}
-#endif
-
#ifdef CONFIG_USB_XHCI_MVEBU
#define USB3_MAX_WINDOWS 4
#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
#ifndef _MVEBU_EFUSE_H
#define _MVEBU_EFUSE_H
-#include <common.h>
-
struct efuse_val {
union {
struct {
obj-y += abb.o
endif
-ifneq ($(CONFIG_OMAP54XX),)
-ifeq ($(CONFIG_DM_SCSI),)
-obj-y += pipe3-phy.o
-obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
-endif
-endif
-
ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
}
#endif
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void arch_preboot_os(void)
-{
- ahci_reset((void __iomem *)DWC_AHSATA_BASE);
-}
-#endif
-
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(const void *fit, int node, void **p_image,
size_t *p_size)
(*prcm)->cm_l4per_gpio6_clkctrl,
(*prcm)->cm_l4per_gpio7_clkctrl,
(*prcm)->cm_l4per_gpio8_clkctrl,
-#ifdef CONFIG_SCSI_AHCI_PLAT
- (*prcm)->cm_l3init_ocp2scp3_clkctrl,
-#endif
0
};
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
-#endif
-#ifdef CONFIG_SCSI_AHCI_PLAT
- (*prcm)->cm_l3init_sata_clkctrl,
#endif
0
};
setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
#endif
-#ifdef CONFIG_SCSI_AHCI_PLAT
- /* Enable optional functional clock for SATA */
- setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
- SATA_CLKCTRL_OPTFCLKEN_MASK);
-#endif
-
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#include <common.h>
-#include <sata.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include "pipe3-phy.h"
-
-/* PLLCTRL Registers */
-#define PLL_STATUS 0x00000004
-#define PLL_GO 0x00000008
-#define PLL_CONFIGURATION1 0x0000000C
-#define PLL_CONFIGURATION2 0x00000010
-#define PLL_CONFIGURATION3 0x00000014
-#define PLL_CONFIGURATION4 0x00000020
-
-#define PLL_REGM_MASK 0x001FFE00
-#define PLL_REGM_SHIFT 9
-#define PLL_REGM_F_MASK 0x0003FFFF
-#define PLL_REGM_F_SHIFT 0
-#define PLL_REGN_MASK 0x000001FE
-#define PLL_REGN_SHIFT 1
-#define PLL_SELFREQDCO_MASK 0x0000000E
-#define PLL_SELFREQDCO_SHIFT 1
-#define PLL_SD_MASK 0x0003FC00
-#define PLL_SD_SHIFT 10
-#define SET_PLL_GO 0x1
-#define PLL_TICOPWDN BIT(16)
-#define PLL_LDOPWDN BIT(15)
-#define PLL_LOCK 0x2
-#define PLL_IDLE 0x1
-
-/* PHY POWER CONTROL Register */
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
-
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
-#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
-
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
-#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
-
-
-#define PLL_IDLE_TIME 100 /* in milliseconds */
-#define PLL_LOCK_TIME 100 /* in milliseconds */
-
-static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
-{
- return __raw_readl(addr + offset);
-}
-
-static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
- u32 data)
-{
- __raw_writel(data, addr + offset);
-}
-
-static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
- *pipe3)
-{
- u32 rate;
- struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
-
- rate = get_sys_clk_freq();
-
- for (; dpll_map->rate; dpll_map++) {
- if (rate == dpll_map->rate)
- return &dpll_map->params;
- }
-
- printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
- __func__, rate);
- return NULL;
-}
-
-
-static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_LOCK_TIME;
-
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (val & PLL_LOCK)
- break;
- } while (--timeout);
-
- if (!(val & PLL_LOCK)) {
- printf("%s: DPLL failed to lock\n", __func__);
- return -EBUSY;
- }
-
- return 0;
-}
-
-static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
-{
- u32 val;
- struct pipe3_dpll_params *dpll_params;
-
- dpll_params = omap_pipe3_get_dpll_params(phy);
- if (!dpll_params) {
- printf("%s: Invalid DPLL parameters\n", __func__);
- return -EINVAL;
- }
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGN_MASK;
- val |= dpll_params->n << PLL_REGN_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val &= ~PLL_SELFREQDCO_MASK;
- val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
- val &= ~PLL_REGM_MASK;
- val |= dpll_params->m << PLL_REGM_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
- val &= ~PLL_REGM_F_MASK;
- val |= dpll_params->mf << PLL_REGM_F_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
-
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
- val &= ~PLL_SD_MASK;
- val |= dpll_params->sd << PLL_SD_SHIFT;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
-
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- return omap_pipe3_wait_lock(phy);
-}
-
-static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
-{
- u32 val, rate;
-
- val = readl(phy->power_reg);
-
- rate = get_sys_clk_freq();
- rate = rate/1000000;
-
- if (on) {
- val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- val |= rate <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
- } else {
- val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
- val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
- }
-
- writel(val, phy->power_reg);
-}
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy)
-{
- int ret;
- u32 val;
-
- /* Program the DPLL only if not locked */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if (!(val & PLL_LOCK)) {
- ret = omap_pipe3_dpll_program(phy);
- if (ret)
- return ret;
- } else {
- /* else just bring it out of IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- if (val & PLL_IDLE) {
- val &= ~PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base,
- PLL_CONFIGURATION2, val);
- ret = omap_pipe3_wait_lock(phy);
- if (ret)
- return ret;
- }
- }
-
- /* Power up the PHY */
- omap_control_phy_power(phy, 1);
-
- return 0;
-}
-
-int phy_pipe3_power_off(struct omap_pipe3 *phy)
-{
- u32 val;
- int timeout = PLL_IDLE_TIME;
-
- /* Power down the PHY */
- omap_control_phy_power(phy, 0);
-
- /* Put DPLL in IDLE mode */
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- /* wait for LDO and Oscillator to power down */
- do {
- mdelay(1);
- val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
- if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
- break;
- } while (--timeout);
-
- if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
- printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
- __func__, val);
- return -EBUSY;
- }
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * TI PIPE3 PHY
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#ifndef __OMAP_PIPE3_PHY_H
-#define __OMAP_PIPE3_PHY_H
-
-struct pipe3_dpll_params {
- u16 m;
- u8 n;
- u8 freq:3;
- u8 sd;
- u32 mf;
-};
-
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-struct omap_pipe3 {
- void __iomem *pll_ctrl_base;
- void __iomem *power_reg;
- struct pipe3_dpll_map *dpll_map;
-};
-
-
-int phy_pipe3_power_on(struct omap_pipe3 *phy);
-int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
-
-#endif /* __OMAP_PIPE3_PHY_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TI SATA platform driver
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#include <common.h>
-#include <ahci.h>
-#include <scsi.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sata.h>
-#include <sata.h>
-#include <asm/io.h>
-#include <asm/omap_common.h>
-#include "pipe3-phy.h"
-
-static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
- {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
- { }, /* Terminator */
-};
-
-struct omap_pipe3 sata_phy = {
- .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
- /* .power_reg is updated at runtime */
- .dpll_map = dpll_map_sata,
-};
-
-int init_sata(int dev)
-{
- int ret;
- u32 val;
-
- sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
-
- /* Power up the PHY */
- phy_pipe3_power_on(&sata_phy);
-
- /* Enable SATA module, No Idle, No Standby */
- val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
- writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
-
- ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
-
- return ret;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-/* On OMAP platforms SATA provides the SCSI subsystem */
-void scsi_init(void)
-{
- init_sata(0);
- scsi_scan(1);
-}
-
-int scsi_bus_reset(struct udevice *dev)
-{
- ahci_reset((void __iomem *)DWC_AHSATA_BASE);
- ahci_init((void __iomem *)DWC_AHSATA_BASE);
-
- return 0;
-}
STM32MP157, STM32MP153 or STM32MP151
STMicroelectronics MPU with core ARMv7
dual core A7 for STM32MP157/3, monocore for STM32MP151
+
+config STM32MP25X
+ bool "Support STMicroelectronics STM32MP25x Soc"
+ select ARM64
+ select CLK_STM32MP25
+ select OF_BOARD
+ select PINCTRL_STM32
+ select STM32_RCC
+ select STM32_RESET
+ select STM32_SERIAL
+ select SYS_ARCH_TIMER
+ select TFABOOT
+ imply CLK_SCMI
+ imply CMD_NVEDIT_INFO
+ imply DM_REGULATOR
+ imply DM_REGULATOR_SCMI
+ imply OPTEE
+ imply RESET_SCMI
+ imply SYSRESET_PSCI
+ imply TEE
+ imply VERSION_VARIABLE
+ help
+ Support of STMicroelectronics SOC STM32MP25x family
+ STMicroelectronics MPU with 2 * A53 core and 1 M33 core
endchoice
config NR_DRAM_BANKS
source "arch/arm/mach-stm32mp/Kconfig.13x"
source "arch/arm/mach-stm32mp/Kconfig.15x"
-
+source "arch/arm/mach-stm32mp/Kconfig.25x"
source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
endif
--- /dev/null
+if STM32MP25X
+
+choice
+ prompt "STM32MP25x board select"
+ optional
+
+config TARGET_ST_STM32MP25X
+ bool "STMicroelectronics STM32MP25x boards"
+ imply BOOTSTAGE
+ imply CMD_BOOTSTAGE
+ help
+ target the STMicroelectronics board with SOC STM32MP25x
+ managed by board/st/stm32mp2
+ The difference between board are managed with devicetree
+
+endchoice
+
+config TEXT_BASE
+ default 0x84000000
+
+config PRE_CON_BUF_ADDR
+ default 0x84800000
+
+config PRE_CON_BUF_SZ
+ default 4096
+
+config BOOTSTAGE_STASH_ADDR
+ default 0x87000000
+
+if DEBUG_UART
+
+config DEBUG_UART_BOARD_INIT
+ default y
+
+# debug on USART2 by default
+config DEBUG_UART_BASE
+ default 0x400e0000
+
+endif
+
+source "board/st/stm32mp2/Kconfig"
+
+endif
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
#
-obj-y += cpu.o
obj-y += dram_init.o
obj-y += syscon.o
obj-y += bsec.o
-obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
-obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp1/
+obj-$(CONFIG_STM32MP13x) += stm32mp1/
+obj-$(CONFIG_STM32MP25X) += stm32mp2/
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-obj-y += tzc400.o
-else
+ifndef CONFIG_SPL_BUILD
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
-obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_TFABOOT) += boot_params.o
endif
-
-obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
-obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_lock(u32 address, u32 otp)
+static bool bsec_read_lock(void __iomem *address, u32 otp)
{
u32 bit;
u32 bank;
bit = 1 << (otp & OTP_LOCK_MASK);
bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
- return !!(readl(address + bank) & bit);
+ return !!(readl((address + bank)) & bit);
}
/**
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error, -EAGAIN or -ENOTSUPP
*/
-static u32 bsec_check_error(u32 base, u32 otp)
+static u32 bsec_check_error(void __iomem *base, u32 otp)
{
u32 bit;
u32 bank;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SR_lock(u32 base, u32 otp)
+static bool bsec_read_SR_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
}
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SP_lock(u32 base, u32 otp)
+static bool bsec_read_SP_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
}
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: true if locked else false
*/
-static bool bsec_read_SW_lock(u32 base, u32 otp)
+static bool bsec_read_SW_lock(void __iomem *base, u32 otp)
{
return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
}
* @power: true to power up , false to power down
* Return: 0 if succeed
*/
-static int bsec_power_safmem(u32 base, bool power)
+static int bsec_power_safmem(void __iomem *base, bool power)
{
u32 val;
u32 mask;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
+static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp)
{
u32 val;
int ret;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
+static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val,
+ u32 otp)
{
*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
+static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
{
/* check if programming of otp is locked */
if (bsec_read_SW_lock(base, otp))
* after the function the otp data is not refreshed in shadow
* Return: 0 if no error
*/
-static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
+static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp)
{
u32 ret;
bool power_up = false;
* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
* Return: 0 if no error
*/
-static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
+static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp)
{
int ret;
bool power_up = false;
/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
- u32 base;
+ void __iomem *base;
};
struct stm32mp_bsec_priv {
{
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
- plat->base = (u32)dev_read_addr_ptr(dev);
+ plat->base = dev_read_addr_ptr(dev);
return 0;
}
int ret;
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- log_debug("RAM init failed: %d\n", ret);
+ /* in case there is no RAM driver, retrieve DDR size from DT */
+ if (ret == -ENODEV) {
+ return fdtdec_setup_mem_size_base();
+ } else if (ret) {
+ log_err("RAM init failed: %d\n", ret);
return ret;
}
ret = ram_get_info(dev, &ram);
log_debug("Cannot get RAM size: %d\n", ret);
return ret;
}
- log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+ log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
gd->ram_size = ram.size;
if (!total_size)
return gd->ram_top;
+ /*
+ * make sure U-Boot uses address space below 4GB boundaries even
+ * if the effective available memory is bigger
+ */
+ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
+
/* found enough not-reserved memory to relocated U-Boot */
lmb_init(&lmb);
- lmb_add(&lmb, gd->ram_base, get_effective_memsize());
+ lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
/* add 8M for reserved memory for display, fdt, gd,... */
size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
+#include <linux/sizes.h>
#ifndef __ASSEMBLY__
#include <linux/bitops.h>
+
+enum boot_device {
+ BOOT_FLASH_SD = 0x10,
+ BOOT_FLASH_SD_1 = 0x11,
+ BOOT_FLASH_SD_2 = 0x12,
+ BOOT_FLASH_SD_3 = 0x13,
+
+ BOOT_FLASH_EMMC = 0x20,
+ BOOT_FLASH_EMMC_1 = 0x21,
+ BOOT_FLASH_EMMC_2 = 0x22,
+ BOOT_FLASH_EMMC_3 = 0x23,
+
+ BOOT_FLASH_NAND = 0x30,
+ BOOT_FLASH_NAND_FMC = 0x31,
+
+ BOOT_FLASH_NOR = 0x40,
+ BOOT_FLASH_NOR_QSPI = 0x41,
+
+ BOOT_SERIAL_UART = 0x50,
+ BOOT_SERIAL_UART_1 = 0x51,
+ BOOT_SERIAL_UART_2 = 0x52,
+ BOOT_SERIAL_UART_3 = 0x53,
+ BOOT_SERIAL_UART_4 = 0x54,
+ BOOT_SERIAL_UART_5 = 0x55,
+ BOOT_SERIAL_UART_6 = 0x56,
+ BOOT_SERIAL_UART_7 = 0x57,
+ BOOT_SERIAL_UART_8 = 0x58,
+
+ BOOT_SERIAL_USB = 0x60,
+ BOOT_SERIAL_USB_OTG = 0x62,
+
+ BOOT_FLASH_SPINAND = 0x70,
+ BOOT_FLASH_SPINAND_1 = 0x71,
+};
+
+#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
+#define TAMP_BOOT_MODE_SHIFT 8
+#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
+#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+#define TAMP_BOOT_DEBUG_ON BIT(16)
+
+enum forced_boot_mode {
+ BOOT_NORMAL = 0x00,
+ BOOT_FASTBOOT = 0x01,
+ BOOT_RECOVERY = 0x02,
+ BOOT_STM32PROG = 0x03,
+ BOOT_UMS_MMC0 = 0x10,
+ BOOT_UMS_MMC1 = 0x11,
+ BOOT_UMS_MMC2 = 0x12,
+};
+
#endif
/*
* Peripheral memory map
* only address used before device tree parsing
*/
+
+#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x)
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_SYSCFG_BASE 0x50020000
#define STM32_DDR_SIZE SZ_1G
#ifndef __ASSEMBLY__
-/* enumerated used to identify the SYSCON driver instance */
-enum {
- STM32MP_SYSCON_UNKNOWN,
- STM32MP_SYSCON_SYSCFG,
-};
-
/*
* enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
* - boot device = bit 8:4
#define BOOT_INSTANCE_MASK 0x0F
#define BOOT_INSTANCE_SHIFT 0
-enum boot_device {
- BOOT_FLASH_SD = 0x10,
- BOOT_FLASH_SD_1 = 0x11,
- BOOT_FLASH_SD_2 = 0x12,
- BOOT_FLASH_SD_3 = 0x13,
-
- BOOT_FLASH_EMMC = 0x20,
- BOOT_FLASH_EMMC_1 = 0x21,
- BOOT_FLASH_EMMC_2 = 0x22,
- BOOT_FLASH_EMMC_3 = 0x23,
-
- BOOT_FLASH_NAND = 0x30,
- BOOT_FLASH_NAND_FMC = 0x31,
-
- BOOT_FLASH_NOR = 0x40,
- BOOT_FLASH_NOR_QSPI = 0x41,
-
- BOOT_SERIAL_UART = 0x50,
- BOOT_SERIAL_UART_1 = 0x51,
- BOOT_SERIAL_UART_2 = 0x52,
- BOOT_SERIAL_UART_3 = 0x53,
- BOOT_SERIAL_UART_4 = 0x54,
- BOOT_SERIAL_UART_5 = 0x55,
- BOOT_SERIAL_UART_6 = 0x56,
- BOOT_SERIAL_UART_7 = 0x57,
- BOOT_SERIAL_UART_8 = 0x58,
-
- BOOT_SERIAL_USB = 0x60,
- BOOT_SERIAL_USB_OTG = 0x62,
-
- BOOT_FLASH_SPINAND = 0x70,
- BOOT_FLASH_SPINAND_1 = 0x71,
-};
-
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0
-
#define TAMP_COPRO_STATE_OFF 0
#define TAMP_COPRO_STATE_INIT 1
#define TAMP_COPRO_STATE_CRUN 2
#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
#endif
-#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
-#define TAMP_BOOT_MODE_SHIFT 8
-#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
-#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
-#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
-enum forced_boot_mode {
- BOOT_NORMAL = 0x00,
- BOOT_FASTBOOT = 0x01,
- BOOT_RECOVERY = 0x02,
- BOOT_STM32PROG = 0x03,
- BOOT_UMS_MMC0 = 0x10,
- BOOT_UMS_MMC1 = 0x11,
- BOOT_UMS_MMC2 = 0x12,
-};
+#if CONFIG_STM32MP25X
+#define STM32_RCC_BASE 0x44200000
+#define STM32_TAMP_BASE 0x46010000
+
+#define STM32_DDR_BASE 0x80000000
+
+#define STM32_DDR_SIZE SZ_4G
+
+/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */
+#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x))
+
+/* TAMP registers zone 3 RIF 1 (RW) at 96*/
+#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96)
+#endif /* STM32MP25X */
/* offset used for BSEC driver: misc_read and misc_write */
#define STM32_BSEC_SHADOW_OFFSET 0x0
#define BSEC_OTP_MAC 57
#define BSEC_OTP_BOARD 60
#endif
+#ifdef CONFIG_STM32MP25X
+#define BSEC_OTP_SERIAL 5
+#define BSEC_OTP_RPN 9
+#define BSEC_OTP_PKG 246
+#endif
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* enumerated used to identify the SYSCON driver instance */
+enum {
+ STM32MP_SYSCON_UNKNOWN,
+ STM32MP_SYSCON_SYSCFG,
+};
+#endif /* __ASSEMBLY__*/
-#endif /* __ASSEMBLY__ */
#endif /* _MACH_STM32_H_ */
#define CPU_STM32MP131Fxx 0x05010EC8
#define CPU_STM32MP131Dxx 0x05010EC9
+/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */
+#define CPU_STM32MP257Cxx 0x00002000
+#define CPU_STM32MP255Cxx 0x00082000
+#define CPU_STM32MP253Cxx 0x000B2004
+#define CPU_STM32MP251Cxx 0x000B3065
+#define CPU_STM32MP257Axx 0x40002E00
+#define CPU_STM32MP255Axx 0x40082E00
+#define CPU_STM32MP253Axx 0x400B2E04
+#define CPU_STM32MP251Axx 0x400B3E65
+#define CPU_STM32MP257Fxx 0x80002000
+#define CPU_STM32MP255Fxx 0x80082000
+#define CPU_STM32MP253Fxx 0x800B2004
+#define CPU_STM32MP251Fxx 0x800B3065
+#define CPU_STM32MP257Dxx 0xC0002E00
+#define CPU_STM32MP255Dxx 0xC0082E00
+#define CPU_STM32MP253Dxx 0xC00B2E04
+#define CPU_STM32MP251Dxx 0xC00B3E65
+
/* return CPU_STMP32MP...Xxx constants */
u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500
#define CPU_DEV_STM32MP13 0x501
+#define CPU_DEV_STM32MP25 0x505
/* return CPU_DEV constants */
u32 get_cpu_dev(void);
#define STM32MP15_PKG_AD_TFBGA257 1
#define STM32MP15_PKG_UNKNOWN 0
+/* package used for STM32MP25x */
+#define STM32MP25_PKG_CUSTOM 0
+#define STM32MP25_PKG_AL_TBGA361 3
+#define STM32MP25_PKG_AK_TBGA424 4
+#define STM32MP25_PKG_AI_TBGA436 5
+#define STM32MP25_PKG_UNKNOWN 7
+
/* Get SOC name */
#define SOC_NAME_SIZE 20
void get_soc_name(char name[SOC_NAME_SIZE]);
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += cpu.o
+
+obj-$(CONFIG_STM32MP13x) += stm32mp13x.o
+obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
+
+obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += tzc400.o
+else
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
+endif
+
+obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+#
+# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += cpu.o
+obj-y += arm64-mmu.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
+obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <mach/stm32.h>
+
+#define MP2_MEM_MAP_MAX 10
+
+#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \
+ (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE))
+#error "invalid CONFIG_TEXT_BASE value"
+#endif
+
+struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = {
+ {
+ /* PCIe */
+ .virt = 0x10000000UL,
+ .phys = 0x10000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Peripherals: alias1 */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* OSPI and FMC: memory-map area */
+ .virt = 0x60000000UL,
+ .phys = 0x60000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /*
+ * DDR = STM32_DDR_BASE / STM32_DDR_SIZE
+ * the beginning of DDR (before CONFIG_TEXT_BASE) is not
+ * mapped, protected by RIF and reserved for other firmware
+ * (OP-TEE / TF-M / Cube M33)
+ */
+ .virt = CONFIG_TEXT_BASE,
+ .phys = CONFIG_TEXT_BASE,
+ .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE),
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = stm32mp2_mem_map;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <clk.h>
+#include <cpu_func.h>
+#include <debug_uart.h>
+#include <env_internal.h>
+#include <init.h>
+#include <misc.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/system.h>
+#include <dm/device.h>
+#include <dm/lists.h>
+#include <dm/uclass.h>
+
+/*
+ * early TLB into the .data section so that it not get cleared
+ * with 16kB alignment
+ */
+#define EARLY_TLB_SIZE 0xA000
+u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
+
+/*
+ * initialize the MMU and activate cache in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ */
+static void early_enable_caches(void)
+{
+ if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+ gd->arch.tlb_size = EARLY_TLB_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ }
+ /* enable MMU (default configuration) */
+ dcache_enable();
+}
+
+/*
+ * Early system init
+ */
+int arch_cpu_init(void)
+{
+ icache_enable();
+ early_enable_caches();
+
+ return 0;
+}
+
+void enable_caches(void)
+{
+ /* deactivate the data cache, early enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
+ * to update the TLB location udpated in board_f.c::reserve_mmu
+ */
+ gd->arch.tlb_fillptr = 0;
+ dcache_enable();
+}
+
+/* used when CONFIG_DISPLAY_CPUINFO is activated */
+int print_cpuinfo(void)
+{
+ char name[SOC_NAME_SIZE];
+
+ get_soc_name(name);
+ printf("CPU: %s\n", name);
+
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ return 0;
+}
+
+/*
+ * Force data-section, as .bss will not be valid
+ * when save_boot_params is invoked.
+ */
+static uintptr_t nt_fw_dtb __section(".data");
+
+uintptr_t get_stm32mp_bl2_dtb(void)
+{
+ return nt_fw_dtb;
+}
+
+/*
+ * Save the FDT address provided by TF-A in r2 at boot time
+ * This function is called from start.S
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+{
+ nt_fw_dtb = r2;
+
+ save_boot_params_ret();
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <asm/u-boot.h>
+
+/*
+ * This function is called right before the kernel is booted. "blob" is the
+ * device tree that will be passed to the kernel.
+ */
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <log.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+
+/* SYSCFG register */
+#define SYSCFG_DEVICEID_OFFSET 0x6400
+#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
+#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
+#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
+#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
+
+/* Device Part Number (RPN) = OTP9 */
+#define RPN_SHIFT 0
+#define RPN_MASK GENMASK(31, 0)
+
+/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
+ * - 000: Custom package
+ * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
+ * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
+ * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
+ * - others: Reserved
+ */
+#define PKG_SHIFT 0
+#define PKG_MASK GENMASK(2, 0)
+
+static u32 read_deviceid(void)
+{
+ void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ return readl(syscfg + SYSCFG_DEVICEID_OFFSET);
+}
+
+u32 get_cpu_dev(void)
+{
+ return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT;
+}
+
+u32 get_cpu_rev(void)
+{
+ return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
+}
+
+/* Get Device Part Number (RPN) from OTP */
+u32 get_cpu_type(void)
+{
+ return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
+}
+
+/* Get Package options from OTP */
+u32 get_cpu_package(void)
+{
+ return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
+}
+
+int get_eth_nb(void)
+{
+ int nb_eth;
+
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ fallthrough;
+ case CPU_STM32MP257Dxx:
+ fallthrough;
+ case CPU_STM32MP257Cxx:
+ fallthrough;
+ case CPU_STM32MP257Axx:
+ nb_eth = 5; /* dual ETH with TSN support */
+ break;
+ case CPU_STM32MP253Fxx:
+ fallthrough;
+ case CPU_STM32MP253Dxx:
+ fallthrough;
+ case CPU_STM32MP253Cxx:
+ fallthrough;
+ case CPU_STM32MP253Axx:
+ nb_eth = 2; /* dual ETH */
+ break;
+ case CPU_STM32MP251Fxx:
+ fallthrough;
+ case CPU_STM32MP251Dxx:
+ fallthrough;
+ case CPU_STM32MP251Cxx:
+ fallthrough;
+ case CPU_STM32MP251Axx:
+ nb_eth = 1; /* single ETH */
+ break;
+ default:
+ nb_eth = 0;
+ break;
+ }
+
+ return nb_eth;
+}
+
+void get_soc_name(char name[SOC_NAME_SIZE])
+{
+ char *cpu_s, *cpu_r, *package;
+
+ cpu_s = "????";
+ cpu_r = "?";
+ package = "??";
+ if (get_cpu_dev() == CPU_DEV_STM32MP25) {
+ switch (get_cpu_type()) {
+ case CPU_STM32MP257Fxx:
+ cpu_s = "257F";
+ break;
+ case CPU_STM32MP257Dxx:
+ cpu_s = "257D";
+ break;
+ case CPU_STM32MP257Cxx:
+ cpu_s = "257C";
+ break;
+ case CPU_STM32MP257Axx:
+ cpu_s = "257A";
+ break;
+ case CPU_STM32MP255Fxx:
+ cpu_s = "255F";
+ break;
+ case CPU_STM32MP255Dxx:
+ cpu_s = "255D";
+ break;
+ case CPU_STM32MP255Cxx:
+ cpu_s = "255C";
+ break;
+ case CPU_STM32MP255Axx:
+ cpu_s = "255A";
+ break;
+ case CPU_STM32MP253Fxx:
+ cpu_s = "253F";
+ break;
+ case CPU_STM32MP253Dxx:
+ cpu_s = "253D";
+ break;
+ case CPU_STM32MP253Cxx:
+ cpu_s = "253C";
+ break;
+ case CPU_STM32MP253Axx:
+ cpu_s = "253A";
+ break;
+ case CPU_STM32MP251Fxx:
+ cpu_s = "251F";
+ break;
+ case CPU_STM32MP251Dxx:
+ cpu_s = "251D";
+ break;
+ case CPU_STM32MP251Cxx:
+ cpu_s = "251C";
+ break;
+ case CPU_STM32MP251Axx:
+ cpu_s = "251A";
+ break;
+ default:
+ cpu_s = "25??";
+ break;
+ }
+ /* REVISION */
+ switch (get_cpu_rev()) {
+ case CPU_REV1:
+ cpu_r = "A";
+ break;
+ default:
+ break;
+ }
+ /* PACKAGE */
+ switch (get_cpu_package()) {
+ case STM32MP25_PKG_CUSTOM:
+ package = "XX";
+ break;
+ case STM32MP25_PKG_AL_TBGA361:
+ package = "AL";
+ break;
+ case STM32MP25_PKG_AK_TBGA424:
+ package = "AK";
+ break;
+ case STM32MP25_PKG_AI_TBGA436:
+ package = "AI";
+ break;
+ default:
+ break;
+ }
+ }
+
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r);
+}
#include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = {
- { .compatible = "st,stm32mp157-syscfg",
- .data = STM32MP_SYSCON_SYSCFG },
+ { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG },
+ { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG},
{ }
};
#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
#define _TEGRA_XUSB_PADCTL_COMMON_H_
-#include <common.h>
#include <fdtdec.h>
#include <dm/ofnode.h>
#define _PSU_INIT_GPL_H_
#include <asm/io.h>
-#include <common.h>
int mask_pollonvalue(unsigned long add, u32 mask, u32 value);
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef fsl_mcdmafec_h
-#define fsl_mcdmafec_h
-
-/* Re-use of the definitions */
-#include <asm/fec.h>
-
-typedef struct fecdma {
- u32 rsvd0; /* 0x000 */
- u32 eir; /* 0x004 */
- u32 eimr; /* 0x008 */
- u32 rsvd1[6]; /* 0x00C - 0x023 */
- u32 ecr; /* 0x024 */
- u32 rsvd2[6]; /* 0x028 - 0x03F */
- u32 mmfr; /* 0x040 */
- u32 mscr; /* 0x044 */
- u32 rsvd3[7]; /* 0x048 - 0x063 */
- u32 mibc; /* 0x064 */
- u32 rsvd4[7]; /* 0x068 - 0x083 */
- u32 rcr; /* 0x084 */
- u32 rhr; /* 0x088 */
- u32 rsvd5[14]; /* 0x08C - 0x0C3 */
- u32 tcr; /* 0x0C4 */
- u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
- u32 palr; /* 0x0E4 */
- u32 paur; /* 0x0E8 */
- u32 opd; /* 0x0EC */
- u32 rsvd7[10]; /* 0x0F0 - 0x117 */
- u32 iaur; /* 0x118 */
- u32 ialr; /* 0x11C */
- u32 gaur; /* 0x120 */
- u32 galr; /* 0x124 */
- u32 rsvd8[7]; /* 0x128 - 0x143 */
- u32 tfwr; /* 0x144 */
- u32 rsvd9[14]; /* 0x148 - 0x17F */
- u32 fmc; /* 0x180 */
- u32 rfdr; /* 0x184 */
- u32 rfsr; /* 0x188 */
- u32 rfcr; /* 0x18C */
- u32 rlrfp; /* 0x190 */
- u32 rlwfp; /* 0x194 */
- u32 rfar; /* 0x198 */
- u32 rfrp; /* 0x19C */
- u32 rfwp; /* 0x1A0 */
- u32 tfdr; /* 0x1A4 */
- u32 tfsr; /* 0x1A8 */
- u32 tfcr; /* 0x1AC */
- u32 tlrfp; /* 0x1B0 */
- u32 tlwfp; /* 0x1B4 */
- u32 tfar; /* 0x1B8 */
- u32 tfrp; /* 0x1BC */
- u32 tfwp; /* 0x1C0 */
- u32 frst; /* 0x1C4 */
- u32 ctcwr; /* 0x1C8 */
-} fecdma_t;
-
-struct fec_info_dma {
- int index;
- u32 iobase;
- u32 pinmux;
- u32 miibase;
- int phy_addr;
- int dup_spd;
- char *phy_name;
- int phyname_init;
- cbd_t *rxbd; /* Rx BD */
- cbd_t *txbd; /* Tx BD */
- uint rx_idx;
- uint tx_idx;
- char *txbuf;
- int initialized;
- struct fec_info_dma *next;
- u16 rx_task; /* DMA receive Task Number */
- u16 tx_task; /* DMA Transmit Task Number */
- u16 rx_pri; /* DMA Receive Priority */
- u16 tx_pri; /* DMA Transmit Priority */
- u16 rx_init; /* DMA Receive Initiator */
- u16 tx_init; /* DMA Transmit Initiator */
- u16 used_tbd_idx; /* next transmit BD to clean */
- u16 clean_tbd_num; /* the number of available transmit BDs */
- int to_loop;
- struct mii_dev *bus;
-};
-
-/* Bit definitions and macros for IEVENT */
-#define FEC_EIR_TXERR (0x00040000)
-#define FEC_EIR_RXERR (0x00020000)
-#undef FEC_EIR_CLEAR_ALL
-#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
-
-/* Bit definitions and macros for R_HASH */
-#define FEC_RHASH_FCE_DC (0x80000000)
-#define FEC_RHASH_MULTCAST (0x40000000)
-#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
-
-/* Bit definitions and macros for FEC_TFWR */
-#undef FEC_TFWR_X_WMRK
-#undef FEC_TFWR_X_WMRK_64
-#undef FEC_TFWR_X_WMRK_128
-#undef FEC_TFWR_X_WMRK_192
-
-#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
-#define FEC_TFWR_X_WMRK_64 (0x00)
-#define FEC_TFWR_X_WMRK_128 (0x01)
-#define FEC_TFWR_X_WMRK_192 (0x02)
-#define FEC_TFWR_X_WMRK_256 (0x03)
-#define FEC_TFWR_X_WMRK_320 (0x04)
-#define FEC_TFWR_X_WMRK_384 (0x05)
-#define FEC_TFWR_X_WMRK_448 (0x06)
-#define FEC_TFWR_X_WMRK_512 (0x07)
-#define FEC_TFWR_X_WMRK_576 (0x08)
-#define FEC_TFWR_X_WMRK_640 (0x09)
-#define FEC_TFWR_X_WMRK_704 (0x0A)
-#define FEC_TFWR_X_WMRK_768 (0x0B)
-#define FEC_TFWR_X_WMRK_832 (0x0C)
-#define FEC_TFWR_X_WMRK_896 (0x0D)
-#define FEC_TFWR_X_WMRK_960 (0x0E)
-#define FEC_TFWR_X_WMRK_1024 (0x0F)
-
-/* FIFO definitions */
-/* Bit definitions and macros for FSTAT */
-#define FIFO_STAT_IP (0x80000000)
-#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
-#define FIFO_STAT_FAE (0x00800000)
-#define FIFO_STAT_RXW (0x00400000)
-#define FIFO_STAT_UF (0x00200000)
-#define FIFO_STAT_OF (0x00100000)
-#define FIFO_STAT_FR (0x00080000)
-#define FIFO_STAT_FULL (0x00040000)
-#define FIFO_STAT_ALARM (0x00020000)
-#define FIFO_STAT_EMPTY (0x00010000)
-
-/* Bit definitions and macros for FCTRL */
-#define FIFO_CTRL_WCTL (0x40000000)
-#define FIFO_CTRL_WFR (0x20000000)
-#define FIFO_CTRL_FRAME (0x08000000)
-#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
-#define FIFO_CTRL_IPMASK (0x00800000)
-#define FIFO_CTRL_FAEMASK (0x00400000)
-#define FIFO_CTRL_RXWMASK (0x00200000)
-#define FIFO_CTRL_UFMASK (0x00100000)
-#define FIFO_CTRL_OFMASK (0x00080000)
-
-#endif /* fsl_mcdmafec_h */
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
-#ifdef CONFIG_FSLDMAFEC
-#define FEC0_RX_TASK 0
-#define FEC0_TX_TASK 1
-#define FEC0_RX_PRIORITY 6
-#define FEC0_TX_PRIORITY 7
-#define FEC0_RX_INIT 16
-#define FEC0_TX_INIT 17
-#define FEC1_RX_TASK 2
-#define FEC1_TX_TASK 3
-#define FEC1_RX_PRIORITY 6
-#define FEC1_TX_PRIORITY 7
-#define FEC1_RX_INIT 30
-#define FEC1_TX_INIT 31
-#endif
-
#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC)
+#if defined(CONFIG_MCFFEC)
static int fec_get_node(int fec_idx)
{
char fec_alias[5] = {"fec"};
return fec_get_fdt_prop(fec_idx, "mii-base", mii_base);
}
-#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC
+#endif //CONFIG_MCFFEC
dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_INTENO_XG6846) += inteno,xg6846.dtb
dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Linus Walleij <linusw@kernel.org>
+ *
+ * This is a diet version of the device tree from Linux,
+ * suitable for U-Boot.
+ */
+
+/dts-v1/;
+
+#include "brcm,bcm6328.dtsi"
+
+/ {
+ model = "Inteno XG6846";
+ compatible = "inteno,xg6846", "brcm,bcm6328";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&leds {
+ status = "okay";
+
+ led@18 {
+ reg = <18>;
+ active-low;
+ label = "red:pwr";
+ };
+
+ led@20 {
+ reg = <20>;
+ active-low;
+ label = "green:pwr";
+ };
+};
+
+&spi {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <33333334>;
+ };
+};
+
+&uart0 {
+ bootph-all;
+ status = "okay";
+};
ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
a RT3062F/AR9223 (PCI).
+config BOARD_INTENO_XG6846
+ bool "Inteno XG6846"
+ depends on SOC_BMIPS_BCM6328
+ select BMIPS_SUPPORTS_BOOT_RAM
+ help
+ Inteno XG6846 boards have a BCM6328 SoC with 64 MB of RAM and 16
+ MB of flash (SPI).
+ Between its different peripherals there's an integrated switch with 4
+ ethernet ports, 1 UART, GPIO buttons and LEDs, and a Marvell
+ DSA switch connected to a fiber SFP.
+
config BOARD_NETGEAR_CG3100D
bool "Netgear CG3100D"
depends on SOC_BMIPS_BCM3380
source "board/comtrend/vr3032u/Kconfig"
source "board/comtrend/wap5813n/Kconfig"
source "board/huawei/hg556a/Kconfig"
+source "board/inteno/xg6846/Kconfig"
source "board/netgear/cg3100d/Kconfig"
source "board/netgear/dgnd3700v2/Kconfig"
source "board/sagem/f@st1704/Kconfig"
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <asm-offsets.h>
#include <mpc83xx.h>
#include <system-constants.h>
#ifdef CONFIG_QE
#include <fsl_qe.h>
#endif
+#include <asm/ppc.h>
+#include <asm/fsl_lbc.h>
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
#include <asm/cache.h>
#include <asm/mmu.h>
+#include <asm/fsl_lbc.h>
#include <asm/u-boot.h>
#include "hrcw/hrcw.h"
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <display_options.h>
#include <env.h>
#include <init.h>
#ifndef __ASM_PPC_FSL_LBC_H
#define __ASM_PPC_FSL_LBC_H
-#include <config.h>
-#include <common.h>
-
#ifdef CONFIG_MPC85xx
void lbc_sdram_init(void);
#endif
#define __ASM_GBL_DATA_H
#include <config.h>
-#include "asm/types.h"
+#include <linux/types.h>
/* Architecture-specific global data */
struct arch_global_data {
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#define nop()
#ifndef __SANDBOX_CLK_H
#define __SANDBOX_CLK_H
-#include <common.h>
#include <clk.h>
#include <dt-structs.h>
#include <linux/clk-provider.h>
#ifndef __SANDBOX_MBOX_H
#define __SANDBOX_MBOX_H
-#include <common.h>
-
#define SANDBOX_MBOX_PING_XOR 0x12345678
struct udevice;
#ifndef __SANDBOX_POWER_DOMAIN_H
#define __SANDBOX_POWER_DOMAIN_H
-#include <common.h>
-
struct udevice;
int sandbox_power_domain_query(struct udevice *dev, unsigned long id);
#ifndef __SANDBOX_RESET_H
#define __SANDBOX_RESET_H
-#include <common.h>
-
struct udevice;
int sandbox_reset_query(struct udevice *dev, unsigned long id);
#ifndef __SLIMBOOTLOADER_ARCH_H__
#define __SLIMBOOTLOADER_ARCH_H__
-#include <common.h>
#include <asm/hob.h>
/**
#ifndef __ASM_X86_DMA_MAPPING_H
#define __ASM_X86_DMA_MAPPING_H
-#include <common.h>
#include <asm/cache.h>
#include <cpu_func.h>
#include <linux/dma-direction.h>
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select CMD_QFW
- select QFW_MMIO
+ select QFW_MMIO if CMD_QFW
imply VIRTIO_MMIO
imply VIRTIO_PCI
imply VIRTIO_NET
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply SCSI
- imply DM_SCSI
imply SYS_NS16550
imply SIFIVE_SERIAL
imply HTIF_CONSOLE if 64BIT
def_bool y
select X86_RESET_VECTOR
select QEMU
- select QFW_PIO
+ select QFW_PIO if CMD_QFW
select BOARD_ROMSIZE_KB_1024
imply VIRTIO_PCI
imply VIRTIO_NET
* Copyright 2014 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
* Copyright 2014 Freescale Semiconductor, Inc.
*/
-#include <common.h>
#include <log.h>
+#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/immap_85xx.h>
#include "sleep.h"
* Copyright 2019, 2021 NXP
*/
-#include <common.h>
#include <clock_legacy.h>
#include <fdt_support.h>
#include <i2c.h>
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2019, 2021 NXP
*/
-#include <common.h>
#include <clock_legacy.h>
#include <fdt_support.h>
#include <init.h>
* Copyright 2019, 2021-2022 NXP
*/
-#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <fdt_support.h>
* Copyright 2021-2022 NXP
*/
-#include <common.h>
#include <i2c.h>
#include <init.h>
#include <asm/global_data.h>
* Copyright 2017 NXP
*/
+#include <vsprintf.h>
+#include <linux/string.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
* Copyright 2015 Freescale Semiconductor, Inc.
*/
+#include <vsprintf.h>
+#include <linux/string.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/fsl_mc.h>
return 0;
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
- u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
-
- cphy_disable_overrides();
- if (reg & PWRDOM_STAT_SATA) {
- ahci_init((void __iomem *)HB_AHCI_BASE);
- scsi_scan(true);
- }
-}
-#endif
-
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
--- /dev/null
+if BOARD_INTENO_XG6846
+
+config SYS_BOARD
+ default "xg6846"
+
+config SYS_VENDOR
+ default "inteno"
+
+config SYS_CONFIG_NAME
+ default "inteno_xg6846"
+
+endif
--- /dev/null
+INTENO XG6846 BOARD
+M: Linus Walleij <linusw@kernel.org>
+S: Maintained
+F: board/inteno/xg6846
+F: include/configs/inteno_xg6846.h
+F: configs/inteno_xg6846_ram_defconfig
* Copyright 2020 Hitachi Power Grids. All rights reserved.
*/
-#include <common.h>
+#include <config.h>
#include <event.h>
#include <i2c.h>
#include <asm/io.h>
--- /dev/null
+if TARGET_ST_STM32MP25X
+
+config SYS_BOARD
+ default "stm32mp2"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "stm32mp25_common"
+
+source "board/st/common/Kconfig"
+endif
--- /dev/null
+STM32MP2 BOARD
+M: Patrice Chotard <patrice.chotard@st.com>
+M: Patrick Delaunay <patrick.delaunay@st.com>
+L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/dts/stm32mp25*
+F: board/st/stm32mp2/
+F: configs/stm32mp25_defconfig
+F: include/configs/stm32mp25_common.h
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+#
+# Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+#
+
+obj-y += stm32mp2.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY LOGC_BOARD
+
+#include <config.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const void *fdt_compat;
+ int fdt_compat_len;
+ char dtb_name[256];
+ int buf_len;
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+ &fdt_compat_len);
+ if (fdt_compat && fdt_compat_len) {
+ if (strncmp(fdt_compat, "st,", 3) != 0) {
+ env_set("board_name", fdt_compat);
+ } else {
+ env_set("board_name", fdt_compat + 3);
+
+ buf_len = sizeof(dtb_name);
+ strlcpy(dtb_name, fdt_compat + 3, buf_len);
+ buf_len -= strlen(fdt_compat + 3);
+ strlcat(dtb_name, ".dtb", buf_len);
+ env_set("fdtfile", dtb_name);
+ }
+ }
+ }
+
+ return 0;
+}
#include <asm/arch/hardware.h>
#include <asm/io.h>
-#include <common.h>
#include <dm/uclass.h>
#include <env.h>
#include <fdt_support.h>
*
*/
-#include <common.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <k3-ddrss.h>
*
*/
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <image.h>
*
*/
-#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <generic-phy.h>
*
*/
-#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <generic-phy.h>
help
Utilities for parsing PXE file formats.
-config BOOT_DEFAULTS
- bool # Common defaults for standard boot and distroboot
+config BOOT_DEFAULTS_FEATURES
+ bool
+ select SUPPORT_RAW_INITRD
+ select ENV_VARS_UBOOT_CONFIG
+ imply USB_STORAGE
+ imply EFI_PARTITION
+ imply ISO_PARTITION
+
+config BOOT_DEFAULTS_CMDS
+ bool
imply USE_BOOTCOMMAND
select CMD_ENV_EXISTS
select CMD_EXT2
select CMD_DHCP if CMD_NET
select CMD_PING if CMD_NET
select CMD_PXE if CMD_NET
- select SUPPORT_RAW_INITRD
- select ENV_VARS_UBOOT_CONFIG
select CMD_BOOTI if ARM64
select CMD_BOOTZ if ARM && !ARM64
imply CMD_MII if NET
- imply USB_STORAGE
- imply EFI_PARTITION
- imply ISO_PARTITION
+
+config BOOT_DEFAULTS
+ bool # Common defaults for standard boot and distroboot
+ select BOOT_DEFAULTS_FEATURES
+ select BOOT_DEFAULTS_CMDS if CMDLINE
help
These are not required but are commonly needed to support a good
selection of booting methods. Enable this to improve the capability
config BOOTSTD_DEFAULTS
bool "Select some common defaults for standard boot"
depends on BOOTSTD
- imply USE_BOOTCOMMAND
select BOOT_DEFAULTS
select BOOTMETH_DISTRO
help
config BOOTMETH_EFILOADER
bool "Bootdev support for EFI boot"
- depends on EFI_LOADER
+ depends on CMD_BOOTEFI
default y
help
Enables support for EFI boot using bootdevs. This makes the
config BOOTMETH_DISTRO
bool # Options needed to boot any distro
- select BOOTMETH_SCRIPT # E.g. Armbian uses scripts
+ select BOOTMETH_SCRIPT if CMDLINE # E.g. Armbian uses scripts
select BOOTMETH_EXTLINUX # E.g. Debian uses these
select BOOTMETH_EXTLINUX_PXE if CMD_PXE && CMD_NET && DM_ETH
- select BOOTMETH_EFILOADER if EFI_LOADER # E.g. Ubuntu uses this
+ select BOOTMETH_EFILOADER if CMD_BOOTEFI # E.g. Ubuntu uses this
config SPL_BOOTMETH_VBE
bool "Bootdev support for Verified Boot for Embedded (SPL)"
config BOOTMETH_SCRIPT
bool "Bootdev support for U-Boot scripts"
default y if BOOTSTD_FULL
+ depends on CMDLINE
select HUSH_PARSER
help
Enables support for booting a distro via a U-Boot script. This makes
event log memory region.
endif # MEASURED_BOOT
+config SYS_BOOTM_LEN
+ hex "Maximum size of a decompresed OS image"
+ depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
+ LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
+ default 0x4000000 if PPC || ARM64
+ default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
+ default 0x800000
+ help
+ This is the maximum size of the buffer that is used to decompress the OS
+ image in to if attempting to boot a compressed image.
+
config SUPPORT_RAW_INITRD
bool "Enable raw initrd images"
help
config DISTRO_DEFAULTS
bool "(deprecated) Script-based booting of Linux distributions"
+ select CMDLINE
select BOOT_DEFAULTS
select AUTO_COMPLETE
select CMDLINE_EDITING
config AUTOBOOT
bool "Autoboot"
+ depends on CMDLINE
default y
help
This enables the autoboot. See doc/README.autoboot for detail.
+if AUTOBOOT
+
config BOOTDELAY
int "delay in seconds before automatically booting"
default 2
- depends on AUTOBOOT
help
Delay before automatically running bootcmd;
set to 0 to autoboot with no delay, but you can stop it by key input.
U-Boot automatic booting process and bring the device
to the U-Boot prompt for user input.
+if AUTOBOOT_KEYED
+
config AUTOBOOT_FLUSH_STDIN
bool "Enable flushing stdin before starting to read the password"
- depends on AUTOBOOT_KEYED && !SANDBOX
+ depends on !SANDBOX
help
When this option is enabled stdin buffer will be flushed before
starting to read the password.
config AUTOBOOT_PROMPT
string "Autoboot stop prompt"
- depends on AUTOBOOT_KEYED
default "Autoboot in %d seconds\\n"
help
This string is displayed before the boot delay selected by
config AUTOBOOT_ENCRYPTION
bool "Enable encryption in autoboot stopping"
- depends on AUTOBOOT_KEYED
help
This option allows a string to be entered into U-Boot to stop the
autoboot.
config AUTOBOOT_DELAY_STR
string "Delay autobooting via specific input key / string"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ depends on !AUTOBOOT_ENCRYPTION
help
This option delays the automatic boot feature by issuing
a specific input key or string. If CONFIG_AUTOBOOT_DELAY_STR
config AUTOBOOT_STOP_STR
string "Stop autobooting via specific input key / string"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ depends on !AUTOBOOT_ENCRYPTION
help
This option enables stopping (aborting) of the automatic
boot feature only by issuing a specific input key or
config AUTOBOOT_KEYED_CTRLC
bool "Enable Ctrl-C autoboot interruption"
- depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION
+ depends on !AUTOBOOT_ENCRYPTION
help
This option allows for the boot sequence to be interrupted
by ctrl-c, in addition to the "bootdelaykey" and "bootstopkey".
config AUTOBOOT_NEVER_TIMEOUT
bool "Make the password entry never time-out"
- depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION && CRYPT_PW
+ depends on AUTOBOOT_ENCRYPTION && CRYPT_PW
help
This option removes the timeout from the password entry
when the user first presses the <Enter> key before entering
config AUTOBOOT_STOP_STR_ENABLE
bool "Enable fixed string to stop autobooting"
- depends on AUTOBOOT_KEYED && AUTOBOOT_ENCRYPTION
+ depends on AUTOBOOT_ENCRYPTION
help
This option enables the feature to add a fixed stop
string that is defined at compile time.
includes a ":", the portion prior to the ":" will be treated
as a salt value.
+endif # AUTOBOOT_KEYED
+
+if !AUTOBOOT_KEYED
+
config AUTOBOOT_USE_MENUKEY
bool "Allow a specify key to run a menu from the environment"
- depends on !AUTOBOOT_KEYED
help
If a specific key is pressed to stop autoboot, then the commands in
the environment variable 'menucmd' are executed before boot starts.
For example, 33 means "!" in ASCII, so pressing ! at boot would take
this action.
+endif
+
+endif # AUTOBOOT
+
config AUTOBOOT_MENU_SHOW
bool "Show a menu on boot"
depends on CMD_BOOTMENU
config USE_BOOTCOMMAND
bool "Enable a default value for bootcmd"
+ depends on CMDLINE
help
Provide a default value for the bootcmd entry in the environment. If
autoboot is enabled this is what will be run automatically. Enable
config USE_PREBOOT
bool "Enable preboot"
+ depends on CMDLINE
help
When this option is enabled, the existence of the environment
variable "preboot" will be checked immediately before starting the
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFILOADER) += bootmeth_efi.o
-obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootmeth_cros.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_CROS) += bootm.o bootm_os.o bootmeth_cros.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o
ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL
-menu "Command line interface"
-
-config CMDLINE
- bool "Support U-Boot commands"
+menuconfig CMDLINE
+ bool "Command line interface"
default y
help
Enable U-Boot's command-line functions. This provides a means
Depending on the number of commands enabled, this can add
substantially to the size of U-Boot.
+if CMDLINE
+
config HUSH_PARSER
bool "Use hush shell"
- depends on CMDLINE
help
This option enables the "hush" shell (from Busybox) as command line
interpreter, thus enabling powerful command line syntax like
config CMDLINE_EDITING
bool "Enable command line editing"
- depends on CMDLINE
default y
help
Enable editing and History functions for interactive command line
config AUTO_COMPLETE
bool "Enable auto complete using TAB"
- depends on CMDLINE
default y
help
Enable auto completion of commands using TAB.
config SYS_LONGHELP
bool "Enable long help messages"
- depends on CMDLINE
- default y if CMDLINE
+ default y
help
Defined when you want long help messages included
Do not set this option when short of memory.
int "Maximum number arguments accepted by commands"
default 16
-config SYS_CBSIZE
- int "Console input buffer size"
- default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \
- RCAR_GEN3 || TARGET_SOCFPGA_SOC64
- default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \
- FSL_LSCH3 || X86
- default 256 if M68K || PPC
- default 1024
-
-config SYS_PBSIZE
- int "Buffer size for console output"
- default 1024 if ARCH_SUNXI
- default 1044
-
config SYS_XTRACE
bool "Command execution tracer"
- depends on CMDLINE
- default y if CMDLINE
+ default y
help
This option enables the possiblity to print all commands before
executing them and after all variables are evaluated (similar
help
Support booting VxWorks images via the bootm command.
-config SYS_BOOTM_LEN
- hex "Maximum size of a decompresed OS image"
- depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
- LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
- default 0x4000000 if PPC || ARM64
- default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
- default 0x800000
- help
- This is the maximum size of the buffer that is used to decompress the OS
- image in to, if passing a compressed image to bootm/booti/bootz.
-
config CMD_BOOTEFI
bool "bootefi"
depends on EFI_LOADER
help
Boot an EFI image from memory.
+config CMD_BOOTEFI_BOOTMGR
+ bool "UEFI Boot Manager command"
+ depends on BOOTEFI_BOOTMGR && CMD_BOOTEFI
+ default y
+ help
+ Select this option to enable the 'bootmgr' subcommand of 'bootefi'.
+ This subcommand will allow you to select the UEFI binary to be booted
+ via UEFI variables Boot####, BootOrder, and BootNext.
+
config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
depends on CMD_BOOTEFI && !CPU_V7M
Enable the 'gpt' command to ready and write GPT style partition
tables.
-config RANDOM_UUID
- bool "GPT Random UUID generation"
- select LIB_UUID
- help
- Enable the generation of partitions with random UUIDs if none
- are provided.
-
config CMD_GPT_RENAME
bool "GPT partition renaming commands"
depends on CMD_GPT
default 0x15 if ARM
default 0x0 if X86
+config BOOTP_PXE_DHCP_OPTION
+ bool "Request & store 'pxe_configfile' from BOOTP/DHCP server"
+ depends on BOOTP_PXE
+
config BOOTP_VCI_STRING
string
depends on CMD_BOOTP
config CMD_EFICONFIG
bool "eficonfig - provide menu-driven uefi variables maintenance interface"
default y if !HAS_BOARD_SIZE_LIMIT
- depends on CMD_BOOTEFI_BOOTMGR
+ depends on BOOTEFI_BOOTMGR
select MENU
help
Enable the 'eficonfig' command which provides the menu-driven UEFI
config CMD_QFW
bool "qfw"
select QFW
+ default y if TARGET_QEMU_ARM_32BIT || TARGET_QEMU_ARM_64BIT || \
+ TARGET_QEMU_X86 || TARGET_QEMU_X86_64
help
This provides access to the QEMU firmware interface. The main
feature is to allow easy loading of files passed to qemu-system
config CMD_SELECT_FONT
bool "select font size"
depends on VIDEO
+ default y if CONSOLE_TRUETYPE
help
Enabling this will provide 'font' command.
Allows font selection at runtime.
default y
help
Enable useful commands for the Meson Soc family developed by Amlogic Inc.
-endmenu
+
+endif
obj-$(CONFIG_CMD_MUX) += mux.o
obj-$(CONFIG_CMD_NAND) += nand.o
obj-$(CONFIG_CMD_NET) += net.o
+obj-$(CONFIG_ENV_SUPPORT) += nvedit.o
obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o
obj-$(CONFIG_CMD_ONENAND) += onenand.o
obj-$(CONFIG_CMD_OSD) += osd.o
obj-$(CONFIG_$(SPL_)CMD_TLV_EEPROM) += tlv_eeprom.o
-# core command
-obj-y += nvedit.o
-
obj-$(CONFIG_CMD_BCM_EXT_UTILS) += broadcom/
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
*/
#define MAX_ENV_SIZE (1 << 20) /* 1 MiB */
-/*
- * This variable is incremented on each do_env_set(), so it can
- * be used via env_get_id() as an indication, if the environment
- * has changed or not. So it is possible to reread an environment
- * variable only if the environment was changed ... done so for
- * example in NetInitLoop()
- */
-static int env_id = 1;
-
-int env_get_id(void)
-{
- return env_id;
-}
-
#ifndef CONFIG_SPL_BUILD
/*
* Command interface: print one or all environment variables
#endif
#endif /* CONFIG_SPL_BUILD */
-/*
- * Set a new environment variable,
- * or replace or delete an existing one.
- */
-static int _do_env_set(int flag, int argc, char *const argv[], int env_flag)
-{
- int i, len;
- char *name, *value, *s;
- struct env_entry e, *ep;
-
- debug("Initial value for argc=%d\n", argc);
-
-#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI)
- if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e')
- return do_env_set_efi(NULL, flag, --argc, ++argv);
-#endif
-
- while (argc > 1 && **(argv + 1) == '-') {
- char *arg = *++argv;
-
- --argc;
- while (*++arg) {
- switch (*arg) {
- case 'f': /* force */
- env_flag |= H_FORCE;
- break;
- default:
- return CMD_RET_USAGE;
- }
- }
- }
- debug("Final value for argc=%d\n", argc);
- name = argv[1];
-
- if (strchr(name, '=')) {
- printf("## Error: illegal character '='"
- "in variable name \"%s\"\n", name);
- return 1;
- }
-
- env_id++;
-
- /* Delete only ? */
- if (argc < 3 || argv[2] == NULL) {
- int rc = hdelete_r(name, &env_htab, env_flag);
-
- /* If the variable didn't exist, don't report an error */
- return rc && rc != -ENOENT ? 1 : 0;
- }
-
- /*
- * Insert / replace new value
- */
- for (i = 2, len = 0; i < argc; ++i)
- len += strlen(argv[i]) + 1;
-
- value = malloc(len);
- if (value == NULL) {
- printf("## Can't malloc %d bytes\n", len);
- return 1;
- }
- for (i = 2, s = value; i < argc; ++i) {
- char *v = argv[i];
-
- while ((*s++ = *v++) != '\0')
- ;
- *(s - 1) = ' ';
- }
- if (s != value)
- *--s = '\0';
-
- e.key = name;
- e.data = value;
- hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag);
- free(value);
- if (!ep) {
- printf("## Error inserting \"%s\" variable, errno=%d\n",
- name, errno);
- return 1;
- }
-
- return 0;
-}
-
-int env_set(const char *varname, const char *varvalue)
-{
- const char * const argv[4] = { "setenv", varname, varvalue, NULL };
-
- /* before import into hashtable */
- if (!(gd->flags & GD_FLG_ENV_READY))
- return 1;
-
- if (varvalue == NULL || varvalue[0] == '\0')
- return _do_env_set(0, 2, (char * const *)argv, H_PROGRAMMATIC);
- else
- return _do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC);
-}
-
#ifndef CONFIG_SPL_BUILD
static int do_env_set(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
if (argc < 2)
return CMD_RET_USAGE;
- return _do_env_set(flag, argc, argv, H_INTERACTIVE);
+ return env_do_env_set(flag, argc, argv, H_INTERACTIVE);
}
/*
}
/* Continue calling setenv code */
- return _do_env_set(flag, len, local_args, H_INTERACTIVE);
+ return env_do_env_set(flag, len, local_args, H_INTERACTIVE);
}
#endif
if (buffer[0] == '\0') {
const char * const _argv[3] = { "setenv", argv[1], NULL };
- return _do_env_set(0, 2, (char * const *)_argv, H_INTERACTIVE);
+ return env_do_env_set(0, 2, (char * const *)_argv, H_INTERACTIVE);
} else {
const char * const _argv[4] = { "setenv", argv[1], buffer,
NULL };
- return _do_env_set(0, 3, (char * const *)_argv, H_INTERACTIVE);
+ return env_do_env_set(0, 3, (char * const *)_argv, H_INTERACTIVE);
}
}
#endif /* CONFIG_CMD_EDITENV */
}
debug("Final value for argc=%d\n", argc);
- env_id++;
+ env_inc_id();
while (--argc > 0) {
char *name = *++argv;
env_get("bootfile"), use_ipv6))
return -ENOMEM;
+ if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION) &&
+ pxelinux_configfile && !use_ipv6) {
+ if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0)
+ goto done;
+
+ goto error_exit;
+ }
+
if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION) &&
pxelinux_configfile && use_ipv6) {
if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0)
if (argc == 2) {
if (strncmp(argv[1], "res", 3) == 0) {
printf("\nReset SCSI\n");
-#ifndef CONFIG_DM_SCSI
- scsi_bus_reset(NULL);
-#endif
ret = scsi_scan(true);
if (ret)
return CMD_RET_FAILURE;
#include <common.h>
#include <command.h>
#include <display_options.h>
-#include <timestamp.h>
-#include <version.h>
#include <version_string.h>
#include <linux/compiler.h>
#ifdef CONFIG_SYS_COREBOOT
#include <asm/cb_sysinfo.h>
#endif
-#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
- U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
-
-const char version_string[] = U_BOOT_VERSION_STRING;
-const unsigned short version_num = U_BOOT_VERSION_NUM;
-const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH;
-
static int do_version(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
The buffer is allocated immediately after the malloc() region is
ready.
+config SYS_CBSIZE
+ int "Console input buffer size"
+ default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \
+ RCAR_GEN3 || TARGET_SOCFPGA_SOC64
+ default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \
+ FSL_LSCH3 || X86
+ default 256 if M68K || PPC
+ default 1024
+ help
+ Set the size of the console input buffer. This is used both in the
+ case of reading input literally from the user in some manner as well
+ as when we need to construct or modify that type of input, for
+ example when constructing "bootargs" for the OS.
+
+config SYS_PBSIZE
+ int "Console output buffer size"
+ default 1024 if ARCH_SUNXI
+ default 1044
+ help
+ Set the size of the console output buffer. This is used when we need
+ to work with some form of a buffer while providing output in some
+ form to the user.
+
config DISABLE_CONSOLE
bool "Add functionality to disable console completely"
help
obj-y += init/
obj-y += main.o
obj-y += exports.o
+obj-y += cli_getch.o cli_simple.o cli_readline.o
obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
+obj-y += version.o
# # boards
obj-y += board_f.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_UPDATE_COMMON) += update.o
obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
-obj-$(CONFIG_CMDLINE) += cli_getch.o cli_readline.o cli_simple.o
endif # !CONFIG_SPL_BUILD
}
#endif
-#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
-static int initr_scsi(void)
-{
- puts("SCSI: ");
- scsi_init();
- puts("\n");
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_CMD_NET
static int initr_net(void)
{
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
-#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
- INIT_FUNC_WATCHDOG_RESET
- initr_scsi,
-#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init,
#endif
#define debug_parser(fmt, args...) \
debug_cond(DEBUG_PARSER, fmt, ##args)
-
-int cli_simple_parse_line(char *line, char *argv[])
-{
- int nargs = 0;
-
- debug_parser("%s: \"%s\"\n", __func__, line);
- while (nargs < CONFIG_SYS_MAXARGS) {
- /* skip any white space */
- while (isblank(*line))
- ++line;
-
- if (*line == '\0') { /* end of line, no more args */
- argv[nargs] = NULL;
- debug_parser("%s: nargs=%d\n", __func__, nargs);
- return nargs;
- }
-
- argv[nargs++] = line; /* begin of argument string */
-
- /* find end of string */
- while (*line && !isblank(*line))
- ++line;
-
- if (*line == '\0') { /* end of line, no more args */
- argv[nargs] = NULL;
- debug_parser("parse_line: nargs=%d\n", nargs);
- return nargs;
- }
-
- *line++ = '\0'; /* terminate current arg */
- }
-
- printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
-
- debug_parser("%s: nargs=%d\n", __func__, nargs);
- return nargs;
-}
-
int cli_simple_process_macros(const char *input, char *output, int max_size)
{
char c, prev;
return ret;
}
+#ifdef CONFIG_CMDLINE
+int cli_simple_parse_line(char *line, char *argv[])
+{
+ int nargs = 0;
+
+ debug_parser("%s: \"%s\"\n", __func__, line);
+ while (nargs < CONFIG_SYS_MAXARGS) {
+ /* skip any white space */
+ while (isblank(*line))
+ ++line;
+
+ if (*line == '\0') { /* end of line, no more args */
+ argv[nargs] = NULL;
+ debug_parser("%s: nargs=%d\n", __func__, nargs);
+ return nargs;
+ }
+
+ argv[nargs++] = line; /* begin of argument string */
+
+ /* find end of string */
+ while (*line && !isblank(*line))
+ ++line;
+
+ if (*line == '\0') { /* end of line, no more args */
+ argv[nargs] = NULL;
+ debug_parser("parse_line: nargs=%d\n", nargs);
+ return nargs;
+ }
+
+ *line++ = '\0'; /* terminate current arg */
+ }
+
+ printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
+
+ debug_parser("%s: nargs=%d\n", __func__, nargs);
+ return nargs;
+}
+
/*
* WARNING:
*
return rcode;
}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#include <timestamp.h>
+#include <version.h>
+#include <version_string.h>
+
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+ U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
+
+const char version_string[] = U_BOOT_VERSION_STRING;
+const unsigned short version_num = U_BOOT_VERSION_NUM;
+const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH;
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_OF_TRANSLATE is not set
-# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_TIMER=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
+# CONFIG_CMD_SCSI is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_SYS_PBSIZE=532
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
+# CONFIG_CMD_SCSI is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_DEVRES=y
-# CONFIG_SPL_BLK is not set
CONFIG_MXS_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_MXS=y
--- /dev/null
+CONFIG_MIPS=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_TEXT_BASE=0x81c00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="inteno,xg6846"
+CONFIG_DM_RESET=y
+CONFIG_IDENT_STRING="Inteno XG6846"
+CONFIG_SYS_LOAD_ADDR=0x81000000
+CONFIG_ARCH_BMIPS=y
+CONFIG_SOC_BMIPS_BCM6328=y
+CONFIG_SYS_MIPS_TIMER_FREQ=160000000
+CONFIG_MIPS_CACHE_SETUP=y
+CONFIG_MIPS_CACHE_DISABLE=y
+# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
+# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
+CONFIG_MIPS_BOOT_FDT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTDELAY=1
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Boot XG6846 in %d seconds\n"
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe; sf read 0x81000000 0x40000 0x500000; bootm 0x81000000"
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_MALLOC_BOOTPARAMS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="XG6846 # "
+CONFIG_SYS_MAXARGS=24
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=541
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_SYS_BOOTM_LEN=0x1000000
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_SLEEP is not set
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_DMA=y
+CONFIG_BCM6348_IUDMA=y
+CONFIG_LED=y
+CONFIG_LED_BCM6328=y
+CONFIG_LED_BLINK=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_RESET_DELAY=20
+CONFIG_POWER_DOMAIN=y
+CONFIG_BCM6328_POWER_DOMAIN=y
+CONFIG_RESET_BCM6345=y
+CONFIG_DM_SERIAL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
+CONFIG_LZMA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-# CONFIG_SPL_BLK is not set
CONFIG_CLK=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SPL_DM=y
# CONFIG_SIMPLE_BUS is not set
# CONFIG_SPL_SIMPLE_BUS is not set
-# CONFIG_SPL_BLK is not set
CONFIG_GPIO_HOG=y
# CONFIG_INPUT is not set
CONFIG_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_MEASURED_BOOT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_ECDSA=y
CONFIG_ECDSA_VERIFY=y
CONFIG_TPM=y
-CONFIG_SHA384=y
CONFIG_ERRNO_STR=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MBR=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_BOOTFILE="zImage"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_DM_BOOTCOUNT_RTC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x400000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1"
+CONFIG_STM32MP25X=y
+CONFIG_DDR_CACHEABLE_SIZE=0x10000000
+CONFIG_TARGET_ST_STM32MP25X=y
+CONFIG_SYS_LOAD_ADDR=0x84000000
+CONFIG_SYS_MEMTEST_START=0x84000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_FIT=y
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_BOOTDELAY=1
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_ADTIMG=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_LOG=y
+CONFIG_OF_LIVE=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+# CONFIG_MMC is not set
+CONFIG_PINCONF=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+# CONFIG_STM32MP1_DDR is not set
+CONFIG_DM_RNG=y
+CONFIG_SERIAL_RX_BUFFER=y
+# CONFIG_OPTEE_TA_AVB is not set
+CONFIG_WDT=y
+CONFIG_WDT_STM32MP=y
+CONFIG_WDT_ARM_SMC=y
+CONFIG_ERRNO_STR=y
+# CONFIG_LMB_USE_MAX_REGIONS is not set
+CONFIG_LMB_MEMORY_REGIONS=2
+CONFIG_LMB_RESERVED_REGIONS=32
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_USB=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
+# CONFIG_CMD_SCSI is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_MAX313XX=y
-CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_DM_THERMAL=y
* U-Boot v2024.01-rc1 was released on Mon 23 October 2023.
-.. * U-Boot v2024.01-rc2 was released on Mon 06 November 2023.
+* U-Boot v2024.01-rc2 was released on Mon 06 November 2023.
.. * U-Boot v2024.01-rc3 was released on Mon 20 November 2023.
See also CMD_SATA which provides command-line support.
-config SYS_SATA_MAX_PORTS
- int "Maximum supported SATA ports"
- depends on SCSI_AHCI && !DM_SCSI
- default 1
- help
- Sets the maximum number of ports to scan when looking for devices.
- Ports from 0 to (this value - 1) are scanned.
-
config LIBATA
bool
help
config AHCI_PCI
bool "Support for PCI-based AHCI controller"
depends on PCI
- depends on DM_SCSI
+ depends on SCSI
depends on SCSI_AHCI
help
Enables support for the PCI-based AHCI controller.
bool "Support for PCI-based AHCI controller for SPL"
depends on SPL
depends on SPL_PCI
- depends on SPL_SATA && DM_SCSI
+ depends on SPL_SATA && SCSI
config DWC_AHCI
bool "Enable Synopsys DWC AHCI driver support"
select SCSI_AHCI
select PHY
- depends on DM_SCSI
+ depends on SCSI
help
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
bool "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU || ARCH_OCTEON
select SCSI_AHCI
- select DM_SCSI
+ select SCSI
help
This option enables support for the Marvell EBU SoC's
onboard AHCI SATA.
config SATA_CEVA
bool "Ceva Sata controller"
depends on AHCI
- depends on DM_SCSI
+ depends on SCSI
help
This option enables Ceva Sata controller hard IP available on Xilinx
ZynqMP. Support up to 2 external devices. Compliant with SATA 3.1 and
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
-obj-$(CONFIG_SANDBOX) += sata_sandbox.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
-#ifndef CONFIG_DM_SCSI
-struct ahci_uc_priv *probe_ent = NULL;
-#endif
-
#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
/*
static int ahci_host_init(struct ahci_uc_priv *uc_priv)
{
-#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
- struct udevice *dev = uc_priv->dev;
- struct pci_child_plat *pplat = dev_get_parent_plat(dev);
- u16 tmp16;
-#endif
void __iomem *mmio = uc_priv->mmio_base;
u32 tmp, cap_save, cmd;
int i, j, ret;
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
-#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
- if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
- u16 tmp16;
-
- dm_pci_read_config16(dev, 0x92, &tmp16);
- dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
- }
-#endif
uc_priv->cap = readl(mmio + HOST_CAP);
uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
port_map = uc_priv->port_map;
debug("cap 0x%x port_map 0x%x n_ports %d\n",
uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
-#if !defined(CONFIG_DM_SCSI)
- if (uc_priv->n_ports > CONFIG_SYS_SATA_MAX_PORTS)
- uc_priv->n_ports = CONFIG_SYS_SATA_MAX_PORTS;
-#endif
-
for (i = 0; i < uc_priv->n_ports; i++) {
if (!(port_map & (1 << i)))
continue;
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
-#if !defined(CONFIG_DM_SCSI)
-#ifndef CONFIG_SCSI_AHCI_PLAT
- dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
- tmp |= PCI_COMMAND_MASTER;
- dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
-#endif
-#endif
return 0;
}
static void ahci_print_info(struct ahci_uc_priv *uc_priv)
{
-#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
- struct udevice *dev = uc_priv->dev;
- u16 cc;
-#endif
void __iomem *mmio = uc_priv->mmio_base;
u32 vers, cap, cap2, impl, speed;
const char *speed_s;
else
speed_s = "?";
-#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
scc_s = "SATA";
-#else
- dm_pci_read_config16(dev, 0x0a, &cc);
- if (cc == 0x0101)
- scc_s = "IDE";
- else if (cc == 0x0106)
- scc_s = "SATA";
- else if (cc == 0x0104)
- scc_s = "RAID";
- else
- scc_s = "unknown";
-#endif
printf("AHCI %02x%02x.%02x%02x "
"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
(vers >> 24) & 0xff,
cap2 & (1 << 0) ? "boh " : "");
}
-#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
{
-#if !defined(CONFIG_DM_SCSI)
- u16 vendor;
-#endif
int rc;
uc_priv->dev = dev;
uc_priv->pio_mask = 0x1f;
uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
-#if !defined(CONFIG_DM_SCSI)
- uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0,
- PCI_REGION_TYPE, PCI_REGION_MEM);
-
- /* Take from kernel:
- * JMicron-specific fixup:
- * make sure we're in AHCI mode
- */
- dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
- if (vendor == 0x197b)
- dm_pci_write_config8(dev, 0x41, 0xa1);
-#else
struct scsi_plat *plat = dev_get_uclass_plat(dev);
uc_priv->mmio_base = (void *)plat->base;
-#endif
debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
/* initialize adapter */
err_out:
return rc;
}
-#endif
#define MAX_DATA_BYTE_COUNT (4*1024*1024)
static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
{
- struct ahci_uc_priv *uc_priv;
-#ifdef CONFIG_DM_SCSI
- uc_priv = dev_get_uclass_priv(dev->parent);
-#else
- uc_priv = probe_ent;
-#endif
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent);
int ret;
switch (pccb->cmd[0]) {
return 0;
}
-#ifndef CONFIG_DM_SCSI
-void scsi_low_level_init(int busdevfunc)
-{
- struct ahci_uc_priv *uc_priv;
-
-#ifndef CONFIG_SCSI_AHCI_PLAT
- probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
- if (!probe_ent) {
- printf("%s: No memory for uc_priv\n", __func__);
- return;
- }
- uc_priv = probe_ent;
- struct udevice *dev;
- int ret;
-
- ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
- if (ret)
- return;
- ahci_init_one(uc_priv, dev);
-#else
- uc_priv = probe_ent;
-#endif
-
- ahci_start_ports(uc_priv);
-}
-#endif
-
-#ifndef CONFIG_SCSI_AHCI_PLAT
int ahci_init_one_dm(struct udevice *dev)
{
struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
return ahci_init_one(uc_priv, dev);
}
-#endif
int ahci_start_ports_dm(struct udevice *dev)
{
return ahci_start_ports(uc_priv);
}
-#ifdef CONFIG_SCSI_AHCI_PLAT
-static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
-{
- int rc;
-
- uc_priv->host_flags = ATA_FLAG_SATA
- | ATA_FLAG_NO_LEGACY
- | ATA_FLAG_MMIO
- | ATA_FLAG_PIO_DMA
- | ATA_FLAG_NO_ATAPI;
- uc_priv->pio_mask = 0x1f;
- uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
-
- uc_priv->mmio_base = base;
-
- /* initialize adapter */
- rc = ahci_host_init(uc_priv);
- if (rc)
- goto err_out;
-
- ahci_print_info(uc_priv);
-
- rc = ahci_start_ports(uc_priv);
-
-err_out:
- return rc;
-}
-
-#ifndef CONFIG_DM_SCSI
-int ahci_init(void __iomem *base)
-{
- struct ahci_uc_priv *uc_priv;
-
- probe_ent = malloc(sizeof(struct ahci_uc_priv));
- if (!probe_ent) {
- printf("%s: No memory for uc_priv\n", __func__);
- return -ENOMEM;
- }
-
- uc_priv = probe_ent;
- memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
-
- return ahci_init_common(uc_priv, base);
-}
-#endif
-
-int ahci_init_dm(struct udevice *dev, void __iomem *base)
-{
- struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
-
- return ahci_init_common(uc_priv, base);
-}
-
-void __weak scsi_init(void)
-{
-}
-
-#endif /* CONFIG_SCSI_AHCI_PLAT */
-
/*
* In the general case of generic rotating media it makes sense to have a
* flush capability. It probably even makes sense in the case of SSDs because
return 0;
}
-#ifdef CONFIG_DM_SCSI
int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
{
struct udevice *dev;
.id = UCLASS_SCSI,
.ops = &scsi_ops,
};
-#else
-int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
-{
- return ahci_scsi_exec(dev, pccb);
-}
-
-__weak int scsi_bus_reset(struct udevice *dev)
-{
- return ahci_scsi_bus_reset(dev);
-
- return 0;
-}
-#endif
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
-#ifndef CONFIG_AHCI
-struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-#endif
-
int sata_reset(struct udevice *dev)
{
struct ahci_ops *ops = ahci_get_ops(dev);
return ret;
}
-#ifndef CONFIG_AHCI
-#ifdef CONFIG_PARTITIONS
-struct blk_desc *sata_get_dev(int dev)
-{
- return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL;
-}
-#endif
-#endif
-
static unsigned long sata_bread(struct udevice *dev, lbaint_t start,
lbaint_t blkcnt, void *dst)
{
return -ENOSYS;
}
-#ifndef CONFIG_AHCI
-int __sata_initialize(void)
-{
- int rc, ret = -1;
- int i;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) {
- memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc));
- sata_dev_desc[i].uclass_id = UCLASS_AHCI;
- sata_dev_desc[i].devnum = i;
- sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
- sata_dev_desc[i].type = DEV_TYPE_HARDDISK;
- sata_dev_desc[i].lba = 0;
- sata_dev_desc[i].blksz = 512;
- sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz);
- rc = init_sata(i);
- if (!rc) {
- rc = scan_sata(i);
- if (!rc && sata_dev_desc[i].lba > 0 &&
- sata_dev_desc[i].blksz > 0) {
- part_init(&sata_dev_desc[i]);
- ret = i;
- }
- }
- }
-
- return ret;
-}
-int sata_initialize(void) __attribute__((weak, alias("__sata_initialize")));
-
-__weak int __sata_stop(void)
-{
- int i, err = 0;
-
- for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
- err |= reset_sata(i);
-
- if (err)
- printf("Could not reset some SATA devices\n");
-
- return err;
-}
-int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
-#endif
-
static const struct blk_ops sata_blk_ops = {
.read = sata_bread,
.write = sata_bwrite,
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- */
-
-#include <common.h>
-#include <blk.h>
-
-int init_sata(int dev)
-{
- return 0;
-}
-
-int reset_sata(int dev)
-{
- return 0;
-}
-
-int scan_sata(int dev)
-{
- return 0;
-}
-
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
- return 0;
-}
-
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
- return 0;
-}
config RKMTD
bool "Rockchip rkmtd virtual block device"
+ select RANDOM_UUID
help
Enable "rkmtd" class and driver to create a virtual block device
to transfer Rockchip boot block data to and from NAND with block
#include <dt-bindings/mfd/k210-sysctl.h>
#include <k210/pll.h>
#include <linux/bitfield.h>
+#include <asm/barrier.h>
DECLARE_GLOBAL_DATA_PTR;
[CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2,
EXTERNAL_XTAL
),
+ [CLKID_USB_CTRL_IN] = CLK_GATE("usb_ctrl_in", A1_SYS_OSCIN_CTRL, 3,
+ EXTERNAL_XTAL
+ ),
+ [CLKID_USB_CTRL] = CLK_GATE("usb_ctrl", A1_SYS_CLK_EN0, 28,
+ CLKID_SYS
+ ),
[CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27,
CLKID_SYS
),
config DFU_TFTP
bool "DFU via TFTP"
+ depends on NETDEVICES
select UPDATE_COMMON
select DFU_OVER_TFTP
help
config DMA_LEGACY
bool "Legacy DMA support"
- default y if FSLDMAFEC
help
Enable legacy DMA support. This does not use driver model and should
be migrated to the new API.
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-/*Main C file for multi-channel DMA API. */
-
-#include <common.h>
-
-#include <MCD_dma.h>
-#include <MCD_tasksInit.h>
-#include <MCD_progCheck.h>
-
-/********************************************************************/
-/* This is an API-internal pointer to the DMA's registers */
-dmaRegs *MCD_dmaBar;
-
-/*
- * These are the real and model task tables as generated by the
- * build process
- */
-extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
-extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
-
-/*
- * However, this (usually) gets relocated to on-chip SRAM, at which
- * point we access them as these tables
- */
-volatile TaskTableEntry *MCD_taskTable;
-TaskTableEntry *MCD_modelTaskTable;
-
-/*
- * MCD_chStatus[] is an array of status indicators for remembering
- * whether a DMA has ever been attempted on each channel, pausing
- * status, etc.
- */
-static int MCD_chStatus[NCHANNELS] = {
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
-};
-
-/* Prototypes for local functions */
-static void MCD_memcpy(int *dest, int *src, u32 size);
-static void MCD_resmActions(int channel);
-
-/*
- * Buffer descriptors used for storage of progress info for single Dmas
- * Also used as storage for the DMA for CRCs for single DMAs
- * Otherwise, the DMA does not parse these buffer descriptors
- */
-#ifdef MCD_INCLUDE_EU
-extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
-#else
-MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
-#endif
-MCD_bufDesc *MCD_relocBuffDesc;
-
-/* Defines for the debug control register's functions */
-#define DBG_CTL_COMP1_TASK (0x00002000)
-#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
- DBG_CTL_BREAK | \
- DBG_CTL_INT_BREAK | \
- DBG_CTL_COMP1_TASK)
-#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
- DBG_CTL_INT_BREAK | \
- DBG_CTL_COMP1_TASK)
-#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
-
-/* Offset to context save area where progress info is stored */
-#define CSAVE_OFFSET 10
-
-/* Defines for Byte Swapping */
-#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
-#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
-
-/* Execution Unit Identifiers */
-#define MAC 0 /* legacy - not used */
-#define LUAC 1 /* legacy - not used */
-#define CRC 2 /* legacy - not used */
-#define LURC 3 /* Logic Unit with CRC */
-
-/* Task Identifiers */
-#define TASK_CHAINNOEU 0
-#define TASK_SINGLENOEU 1
-#ifdef MCD_INCLUDE_EU
-#define TASK_CHAINEU 2
-#define TASK_SINGLEEU 3
-#define TASK_FECRX 4
-#define TASK_FECTX 5
-#else
-#define TASK_CHAINEU 0
-#define TASK_SINGLEEU 1
-#define TASK_FECRX 2
-#define TASK_FECTX 3
-#endif
-
-/*
- * Structure to remember which variant is on which channel
- * TBD- need this?
- */
-typedef struct MCD_remVariants_struct MCD_remVariant;
-struct MCD_remVariants_struct {
- int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
- int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
- s16 remDestIncr[NCHANNELS]; /* DestIncr */
- s16 remSrcIncr[NCHANNELS]; /* srcIncr */
- u32 remXferSize[NCHANNELS]; /* xferSize */
-};
-
-/* Structure to remember the startDma parameters for each channel */
-MCD_remVariant MCD_remVariants;
-/********************************************************************/
-/* Function: MCD_initDma
- * Purpose: Initializes the DMA API by setting up a pointer to the DMA
- * registers, relocating and creating the appropriate task
- * structures, and setting up some global settings
- * Arguments:
- * dmaBarAddr - pointer to the multichannel DMA registers
- * taskTableDest - location to move DMA task code and structs to
- * flags - operational parameters
- * Return Value:
- * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
- * MCD_OK otherwise
- */
-extern u32 MCD_funcDescTab0[];
-
-int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags)
-{
- int i;
- TaskTableEntry *entryPtr;
-
- /* setup the local pointer to register set */
- MCD_dmaBar = dmaBarAddr;
-
- /* do we need to move/create a task table */
- if ((flags & MCD_RELOC_TASKS) != 0) {
- int fixedSize;
- u32 *fixedPtr;
- /*int *tablePtr = taskTableDest;TBD */
- int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
- int taskDescTabsOffset;
- int taskTableSize, varTabsSize, funcDescTabsSize,
- contextSavesSize;
- int taskDescTabSize;
-
- int i;
-
- /* check if physical address is aligned on 512 byte boundary */
- if (((u32) taskTableDest & 0x000001ff) != 0)
- return (MCD_TABLE_UNALIGNED);
-
- /* set up local pointer to task Table */
- MCD_taskTable = taskTableDest;
-
- /*
- * Create a task table:
- * - compute aligned base offsets for variable tables and
- * function descriptor tables, then
- * - loop through the task table and setup the pointers
- * - copy over model task table with the the actual task
- * descriptor tables
- */
-
- taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
- /* align variable tables to size */
- varTabsOffset = taskTableSize + (u32) taskTableDest;
- if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
- varTabsOffset =
- (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
- /* align function descriptor tables */
- varTabsSize = NCHANNELS * VAR_TAB_SIZE;
- funcDescTabsOffset = varTabsOffset + varTabsSize;
-
- if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
- funcDescTabsOffset =
- (funcDescTabsOffset +
- FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE);
-
- funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
- contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
- contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
- fixedSize =
- taskTableSize + varTabsSize + funcDescTabsSize +
- contextSavesSize;
-
- /* zero the thing out */
- fixedPtr = (u32 *) taskTableDest;
- for (i = 0; i < (fixedSize / 4); i++)
- fixedPtr[i] = 0;
-
- entryPtr = (TaskTableEntry *) MCD_taskTable;
- /* set up fixed pointers */
- for (i = 0; i < NCHANNELS; i++) {
- /* update ptr to local value */
- entryPtr[i].varTab = (u32) varTabsOffset;
- entryPtr[i].FDTandFlags =
- (u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF;
- entryPtr[i].contextSaveSpace = (u32) contextSavesOffset;
- varTabsOffset += VAR_TAB_SIZE;
-#ifdef MCD_INCLUDE_EU
- /* if not there is only one, just point to the
- same one */
- funcDescTabsOffset += FUNCDESC_TAB_SIZE;
-#endif
- contextSavesOffset += CONTEXT_SAVE_SIZE;
- }
- /* copy over the function descriptor table */
- for (i = 0; i < FUNCDESC_TAB_NUM; i++) {
- MCD_memcpy((void *)(entryPtr[i].
- FDTandFlags & ~MCD_TT_FLAGS_MASK),
- (void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
- }
-
- /* copy model task table to where the context saves stuff
- leaves off */
- MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset;
-
- MCD_memcpy((void *)MCD_modelTaskTable,
- (void *)MCD_modelTaskTableSrc,
- NUMOFVARIANTS * sizeof(TaskTableEntry));
-
- /* point to local version of model task table */
- entryPtr = MCD_modelTaskTable;
- taskDescTabsOffset = (u32) MCD_modelTaskTable +
- (NUMOFVARIANTS * sizeof(TaskTableEntry));
-
- /* copy actual task code and update TDT ptrs in local
- model task table */
- for (i = 0; i < NUMOFVARIANTS; i++) {
- taskDescTabSize =
- entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
- MCD_memcpy((void *)taskDescTabsOffset,
- (void *)entryPtr[i].TDTstart,
- taskDescTabSize);
- entryPtr[i].TDTstart = (u32) taskDescTabsOffset;
- taskDescTabsOffset += taskDescTabSize;
- entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4;
- }
-#ifdef MCD_INCLUDE_EU
- /* Tack single DMA BDs onto end of code so API controls
- where they are since DMA might write to them */
- MCD_relocBuffDesc =
- (MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
-#else
- /* DMA does not touch them so they can be wherever and we
- don't need to waste SRAM on them */
- MCD_relocBuffDesc = MCD_singleBufDescs;
-#endif
- } else {
- /* point the would-be relocated task tables and the
- buffer descriptors to the ones the linker generated */
-
- if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0)
- return (MCD_TABLE_UNALIGNED);
-
- /* need to add code to make sure that every thing else is
- aligned properly TBD. this is problematic if we init
- more than once or after running tasks, need to add
- variable to see if we have aleady init'd */
- entryPtr = MCD_realTaskTableSrc;
- for (i = 0; i < NCHANNELS; i++) {
- if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
- ((entryPtr[i].
- FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
- return (MCD_TABLE_UNALIGNED);
- }
-
- MCD_taskTable = MCD_realTaskTableSrc;
- MCD_modelTaskTable = MCD_modelTaskTableSrc;
- MCD_relocBuffDesc = MCD_singleBufDescs;
- }
-
- /* Make all channels as totally inactive, and remember them as such: */
-
- MCD_dmaBar->taskbar = (u32) MCD_taskTable;
- for (i = 0; i < NCHANNELS; i++) {
- MCD_dmaBar->taskControl[i] = 0x0;
- MCD_chStatus[i] = MCD_NO_DMA;
- }
-
- /* Set up pausing mechanism to inactive state: */
- /* no particular values yet for either comparator registers */
- MCD_dmaBar->debugComp1 = 0;
- MCD_dmaBar->debugComp2 = 0;
- MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
- MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
-
- /* enable or disable commbus prefetch, really need an ifdef or
- something to keep from trying to set this in the 8220 */
- if ((flags & MCD_COMM_PREFETCH_EN) != 0)
- MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
- else
- MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
-
- return (MCD_OK);
-}
-
-/*********************** End of MCD_initDma() ***********************/
-
-/********************************************************************/
-/* Function: MCD_dmaStatus
- * Purpose: Returns the status of the DMA on the requested channel
- * Arguments: channel - channel number
- * Returns: Predefined status indicators
- */
-int MCD_dmaStatus(int channel)
-{
- u16 tcrValue;
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- tcrValue = MCD_dmaBar->taskControl[channel];
- if ((tcrValue & TASK_CTL_EN) == 0) { /* nothing running */
- /* if last reported with task enabled */
- if (MCD_chStatus[channel] == MCD_RUNNING
- || MCD_chStatus[channel] == MCD_IDLE)
- MCD_chStatus[channel] = MCD_DONE;
- } else { /* something is running */
-
- /* There are three possibilities: paused, running or idle. */
- if (MCD_chStatus[channel] == MCD_RUNNING
- || MCD_chStatus[channel] == MCD_IDLE) {
- MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
- /* This register is selected to know which initiator is
- actually asserted. */
- if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
- MCD_chStatus[channel] = MCD_RUNNING;
- else
- MCD_chStatus[channel] = MCD_IDLE;
- /* do not change the status if it is already paused. */
- }
- }
- return MCD_chStatus[channel];
-}
-
-/******************** End of MCD_dmaStatus() ************************/
-
-/********************************************************************/
-/* Function: MCD_startDma
- * Ppurpose: Starts a particular kind of DMA
- * Arguments:
- * srcAddr - the channel on which to run the DMA
- * srcIncr - the address to move data from, or buffer-descriptor address
- * destAddr - the amount to increment the source address per transfer
- * destIncr - the address to move data to
- * dmaSize - the amount to increment the destination address per transfer
- * xferSize - the number bytes in of each data movement (1, 2, or 4)
- * initiator - what device initiates the DMA
- * priority - priority of the DMA
- * flags - flags describing the DMA
- * funcDesc - description of byte swapping, bit swapping, and CRC actions
- * srcAddrVirt - virtual buffer descriptor address TBD
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- */
-
-int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
- s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
- int priority, u32 flags, u32 funcDesc
-#ifdef MCD_NEED_ADDR_TRANS
- s8 * srcAddrVirt
-#endif
- )
-{
- int srcRsdIncr, destRsdIncr;
- int *cSave;
- short xferSizeIncr;
- int tcrCount = 0;
-#ifdef MCD_INCLUDE_EU
- u32 *realFuncArray;
-#endif
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- /* tbd - need to determine the proper response to a bad funcDesc when
- not including EU functions, for now, assign a benign funcDesc, but
- maybe should return an error */
-#ifndef MCD_INCLUDE_EU
- funcDesc = MCD_FUNC_NOEU1;
-#endif
-
-#ifdef MCD_DEBUG
- printf("startDma:Setting up params\n");
-#endif
- /* Set us up for task-wise priority. We don't technically need to do
- this on every start, but since the register involved is in the same
- longword as other registers that users are in control of, setting
- it more than once is probably preferable. That since the
- documentation doesn't seem to be completely consistent about the
- nature of the PTD control register. */
- MCD_dmaBar->ptdControl |= (u16) 0x8000;
-
- /* Not sure what we need to keep here rtm TBD */
-#if 1
- /* Calculate additional parameters to the regular DMA calls. */
- srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
- destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
-
- xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
-
- /* Remember for each channel which variant is running. */
- MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
- MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
- MCD_remVariants.remDestIncr[channel] = destIncr;
- MCD_remVariants.remSrcIncr[channel] = srcIncr;
- MCD_remVariants.remXferSize[channel] = xferSize;
-#endif
-
- cSave =
- (int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET +
- CURRBD;
-
-#ifdef MCD_INCLUDE_EU
- /* may move this to EU specific calls */
- realFuncArray =
- (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
- /* Modify the LURC's normal and byte-residue-loop functions according
- to parameter. */
- realFuncArray[(LURC * 16)] = xferSize == 4 ?
- funcDesc : xferSize == 2 ?
- funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
- realFuncArray[(LURC * 16 + 1)] =
- (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
-#endif
- /* Write the initiator field in the TCR, and also set the
- initiator-hold bit. Note that,due to a hardware quirk, this could
- collide with an MDE access to the initiator-register file, so we
- have to verify that the write reads back correctly. */
-
- MCD_dmaBar->taskControl[channel] =
- (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
-
- while (((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
- ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM))
- && (tcrCount < 1000)) {
- tcrCount++;
- /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */
- MCD_dmaBar->taskControl[channel] =
- (initiator << 8) | TASK_CTL_HIPRITSKEN |
- TASK_CTL_HLDINITNUM;
- }
-
- MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK;
- /* should be albe to handle this stuff with only one write to ts reg
- - tbd */
- if (channel < 8 && channel >= 0) {
- MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4);
- MCD_dmaBar->taskSize0 |=
- (xferSize & 3) << (((7 - channel) * 4) + 2);
- MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4);
- } else {
- MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4);
- MCD_dmaBar->taskSize1 |=
- (xferSize & 3) << (((15 - channel) * 4) + 2);
- MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4);
- }
-
- /* setup task table flags/options which mostly control the line
- buffers */
- MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
- MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
-
- if (flags & MCD_FECTX_DMA) {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_FECTX].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_FECTX].TDTend;
- MCD_startDmaENetXmit((char *)srcAddr, (char *)srcAddr,
- (char *)destAddr, MCD_taskTable,
- channel);
- } else if (flags & MCD_FECRX_DMA) {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_FECRX].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_FECRX].TDTend;
- MCD_startDmaENetRcv((char *)srcAddr, (char *)srcAddr,
- (char *)destAddr, MCD_taskTable,
- channel);
- } else if (flags & MCD_SINGLE_DMA) {
- /* this buffer descriptor is used for storing off initial
- parameters for later progress query calculation and for the
- DMA to write the resulting checksum. The DMA does not use
- this to determine how to operate, that info is passed with
- the init routine */
- MCD_relocBuffDesc[channel].srcAddr = srcAddr;
- MCD_relocBuffDesc[channel].destAddr = destAddr;
-
- /* definitely not its final value */
- MCD_relocBuffDesc[channel].lastDestAddr = destAddr;
-
- MCD_relocBuffDesc[channel].dmaSize = dmaSize;
- MCD_relocBuffDesc[channel].flags = 0; /* not used */
- MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
- MCD_relocBuffDesc[channel].next = 0; /* not used */
-
- /* Initialize the progress-querying stuff to show no
- progress: */
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
-(u32) & (MCD_relocBuffDesc[channel]);
- /* tbd - need to keep the user from trying to call the EU
- routine when MCD_INCLUDE_EU is not defined */
- if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
- MCD_startDmaSingleNoEu((char *)srcAddr, srcIncr,
- (char *)destAddr, destIncr,
- (int)dmaSize, xferSizeIncr,
- flags, (int *)
- &(MCD_relocBuffDesc[channel]),
- cSave, MCD_taskTable, channel);
- } else {
- /* TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
- MCD_startDmaSingleEu((char *)srcAddr, srcIncr,
- (char *)destAddr, destIncr,
- (int)dmaSize, xferSizeIncr,
- flags, (int *)
- &(MCD_relocBuffDesc[channel]),
- cSave, MCD_taskTable, channel);
- }
- } else { /* chained DMAS */
- /* Initialize the progress-querying stuff to show no
- progress: */
-#if 1
- /* (!defined(MCD_NEED_ADDR_TRANS)) */
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddr)->srcAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddr)->destAddr;
-#else
- /* if using address translation, need the virtual addr of the
- first buffdesc */
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
- = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr;
-#endif
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
-
- if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
- /*TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
- MCD_startDmaChainNoEu((int *)srcAddr, srcIncr,
- destIncr, xferSize,
- xferSizeIncr, cSave,
- MCD_taskTable, channel);
- } else {
- /*TDTStart and TDTEnd */
- MCD_taskTable[channel].TDTstart =
- MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
- MCD_taskTable[channel].TDTend =
- MCD_modelTaskTable[TASK_CHAINEU].TDTend;
- MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr,
- xferSize, xferSizeIncr, cSave,
- MCD_taskTable, channel);
- }
- }
- MCD_chStatus[channel] = MCD_IDLE;
- return (MCD_OK);
-}
-
-/************************ End of MCD_startDma() *********************/
-
-/********************************************************************/
-/* Function: MCD_XferProgrQuery
- * Purpose: Returns progress of DMA on requested channel
- * Arguments: channel - channel to retrieve progress for
- * progRep - pointer to user supplied MCD_XferProg struct
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- *
- * Notes:
- * MCD_XferProgrQuery() upon completing or after aborting a DMA, or
- * while the DMA is in progress, this function returns the first
- * DMA-destination address not (or not yet) used in the DMA. When
- * encountering a non-ready buffer descriptor, the information for
- * the last completed descriptor is returned.
- *
- * MCD_XferProgQuery() has to avoid the possibility of getting
- * partially-updated information in the event that we should happen
- * to query DMA progress just as the DMA is updating it. It does that
- * by taking advantage of the fact context is not saved frequently for
- * the most part. We therefore read it at least twice until we get the
- * same information twice in a row.
- *
- * Because a small, but not insignificant, amount of time is required
- * to write out the progress-query information, especially upon
- * completion of the DMA, it would be wise to guarantee some time lag
- * between successive readings of the progress-query information.
- */
-
-/* How many iterations of the loop below to execute to stabilize values */
-#define STABTIME 0
-
-int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep)
-{
- MCD_XferProg prevRep;
- int again; /* true if we are to try again to ge
- consistent results */
- int i; /* used as a time-waste counter */
- int destDiffBytes; /* Total no of bytes that we think actually
- got xfered. */
- int numIterations; /* number of iterations */
- int bytesNotXfered; /* bytes that did not get xfered. */
- s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
- int subModVal, addModVal; /* Mode values to added and subtracted
- from the final destAddr */
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- /* Read a trial value for the progress-reporting values */
- prevRep.lastSrcAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
- prevRep.lastDestAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
- prevRep.dmaSize =
- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT +
- CSAVE_OFFSET];
- prevRep.currBufDesc =
- (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET];
- /* Repeatedly reread those values until they match previous values: */
- do {
- /* Waste a little bit of time to ensure stability: */
- for (i = 0; i < STABTIME; i++) {
- /* make sure this loop does something so that it
- doesn't get optimized out */
- i += i >> 2;
- }
- /* Check them again: */
- progRep->lastSrcAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
- progRep->lastDestAddr =
- (s8 *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
- progRep->dmaSize =
- ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
- progRep->currBufDesc =
- (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
- contextSaveSpace)[CURRBD + CSAVE_OFFSET];
- /* See if they match: */
- if (prevRep.lastSrcAddr != progRep->lastSrcAddr
- || prevRep.lastDestAddr != progRep->lastDestAddr
- || prevRep.dmaSize != progRep->dmaSize
- || prevRep.currBufDesc != progRep->currBufDesc) {
- /* If they don't match, remember previous values and
- try again: */
- prevRep.lastSrcAddr = progRep->lastSrcAddr;
- prevRep.lastDestAddr = progRep->lastDestAddr;
- prevRep.dmaSize = progRep->dmaSize;
- prevRep.currBufDesc = progRep->currBufDesc;
- again = MCD_TRUE;
- } else
- again = MCD_FALSE;
- } while (again == MCD_TRUE);
-
- /* Update the dCount, srcAddr and destAddr */
- /* To calculate dmaCount, we consider destination address. C
- overs M1,P1,Z for destination */
- switch (MCD_remVariants.remDestRsdIncr[channel]) {
- case MINUS1:
- subModVal =
- ((int)progRep->
- lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
- 1);
- addModVal =
- ((int)progRep->currBufDesc->
- destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
- LWAlignedInitDestAddr =
- (progRep->currBufDesc->destAddr) - addModVal;
- LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
- destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
- bytesNotXfered =
- (destDiffBytes / MCD_remVariants.remDestIncr[channel]) *
- (MCD_remVariants.remDestIncr[channel]
- + MCD_remVariants.remXferSize[channel]);
- progRep->dmaSize =
- destDiffBytes - bytesNotXfered + addModVal - subModVal;
- break;
- case ZERO:
- progRep->lastDestAddr = progRep->currBufDesc->destAddr;
- break;
- case PLUS1:
- /* This value has to be subtracted from the final
- calculated dCount. */
- subModVal =
- ((int)progRep->currBufDesc->
- destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
- /* These bytes are already in lastDestAddr. */
- addModVal =
- ((int)progRep->
- lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
- 1);
- LWAlignedInitDestAddr =
- (progRep->currBufDesc->destAddr) - subModVal;
- LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
- destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
- numIterations =
- (LWAlignedCurrDestAddr -
- LWAlignedInitDestAddr) /
- MCD_remVariants.remDestIncr[channel];
- bytesNotXfered =
- numIterations * (MCD_remVariants.remDestIncr[channel]
- - MCD_remVariants.remXferSize[channel]);
- progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
- break;
- default:
- break;
- }
-
- /* This covers M1,P1,Z for source */
- switch (MCD_remVariants.remSrcRsdIncr[channel]) {
- case MINUS1:
- progRep->lastSrcAddr =
- progRep->currBufDesc->srcAddr +
- (MCD_remVariants.remSrcIncr[channel] *
- (progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
- break;
- case ZERO:
- progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
- break;
- case PLUS1:
- progRep->lastSrcAddr =
- progRep->currBufDesc->srcAddr +
- (MCD_remVariants.remSrcIncr[channel] *
- (progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
- break;
- default:
- break;
- }
-
- return (MCD_OK);
-}
-
-/******************* End of MCD_XferProgrQuery() ********************/
-
-/********************************************************************/
-/* MCD_resmActions() does the majority of the actions of a DMA resume.
- * It is called from MCD_killDma() and MCD_resumeDma(). It has to be
- * a separate function because the kill function has to negate the task
- * enable before resuming it, but the resume function has to do nothing
- * if there is no DMA on that channel (i.e., if the enable bit is 0).
- */
-static void MCD_resmActions(int channel)
-{
- MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
- MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
- /* This register is selected to know which initiator is
- actually asserted. */
- MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
-
- if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
- MCD_chStatus[channel] = MCD_RUNNING;
- else
- MCD_chStatus[channel] = MCD_IDLE;
-}
-
-/********************* End of MCD_resmActions() *********************/
-
-/********************************************************************/
-/* Function: MCD_killDma
- * Purpose: Halt the DMA on the requested channel, without any
- * intention of resuming the DMA.
- * Arguments: channel - requested channel
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- *
- * Notes:
- * A DMA may be killed from any state, including paused state, and it
- * always goes to the MCD_HALTED state even if it is killed while in
- * the MCD_NO_DMA or MCD_IDLE states.
- */
-int MCD_killDma(int channel)
-{
- /* MCD_XferProg progRep; */
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- MCD_dmaBar->taskControl[channel] = 0x0;
- MCD_resumeDma(channel);
- /*
- * This must be after the write to the TCR so that the task doesn't
- * start up again momentarily, and before the status assignment so
- * as to override whatever MCD_resumeDma() may do to the channel
- * status.
- */
- MCD_chStatus[channel] = MCD_HALTED;
-
- /*
- * Update the current buffer descriptor's lastDestAddr field
- *
- * MCD_XferProgrQuery (channel, &progRep);
- * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
- */
- return (MCD_OK);
-}
-
-/************************ End of MCD_killDma() **********************/
-
-/********************************************************************/
-/* Function: MCD_continDma
- * Purpose: Continue a DMA which as stopped due to encountering an
- * unready buffer descriptor.
- * Arguments: channel - channel to continue the DMA on
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- *
- * Notes:
- * This routine does not check to see if there is a task which can
- * be continued. Also this routine should not be used with single DMAs.
- */
-int MCD_continDma(int channel)
-{
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
- MCD_chStatus[channel] = MCD_RUNNING;
-
- return (MCD_OK);
-}
-
-/********************** End of MCD_continDma() **********************/
-
-/*********************************************************************
- * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
- * to freeze a task and resume it. We freeze a task by breakpointing
- * on the stated task. That is, not any specific place in the task,
- * but any time that task executes. In particular, when that task
- * executes, we want to freeze that task and only that task.
- *
- * The bits of the debug control register influence interrupts vs.
- * breakpoints as follows:
- * - Bits 14 and 0 enable or disable debug functions. If enabled, you
- * will get the interrupt but you may or may not get a breakpoint.
- * - Bits 2 and 1 decide whether you also get a breakpoint in addition
- * to an interrupt.
- *
- * The debug unit can do these actions in response to either internally
- * detected breakpoint conditions from the comparators, or in response
- * to the external breakpoint pin, or both.
- * - Bits 14 and 1 perform the above-described functions for
- * internally-generated conditions, i.e., the debug comparators.
- * - Bits 0 and 2 perform the above-described functions for external
- * conditions, i.e., the breakpoint external pin.
- *
- * Note that, although you "always" get the interrupt when you turn
- * the debug functions, the interrupt can nevertheless, if desired, be
- * masked by the corresponding bit in the PTD's IMR. Note also that
- * this means that bits 14 and 0 must enable debug functions before
- * bits 1 and 2, respectively, have any effect.
- *
- * NOTE: It's extremely important to not pause more than one DMA channel
- * at a time.
- ********************************************************************/
-
-/********************************************************************/
-/* Function: MCD_pauseDma
- * Purpose: Pauses the DMA on a given channel (if any DMA is running
- * on that channel).
- * Arguments: channel
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- */
-int MCD_pauseDma(int channel)
-{
- /* MCD_XferProg progRep; */
-
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) {
- MCD_dmaBar->debugComp1 = channel;
- MCD_dmaBar->debugControl =
- DBG_CTL_ENABLE | (1 << (channel + 16));
- MCD_chStatus[channel] = MCD_PAUSED;
-
- /*
- * Update the current buffer descriptor's lastDestAddr field
- *
- * MCD_XferProgrQuery (channel, &progRep);
- * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
- */
- }
- return (MCD_OK);
-}
-
-/************************* End of MCD_pauseDma() ********************/
-
-/********************************************************************/
-/* Function: MCD_resumeDma
- * Purpose: Resumes the DMA on a given channel (if any DMA is
- * running on that channel).
- * Arguments: channel - channel on which to resume DMA
- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
- */
-int MCD_resumeDma(int channel)
-{
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
- MCD_resmActions(channel);
-
- return (MCD_OK);
-}
-
-/************************ End of MCD_resumeDma() ********************/
-
-/********************************************************************/
-/* Function: MCD_csumQuery
- * Purpose: Provide the checksum after performing a non-chained DMA
- * Arguments: channel - channel to report on
- * csum - pointer to where to write the checksum/CRC
- * Returns: MCD_ERROR if the channel is invalid, else MCD_OK
- *
- * Notes:
- *
- */
-int MCD_csumQuery(int channel, u32 * csum)
-{
-#ifdef MCD_INCLUDE_EU
- if ((channel < 0) || (channel >= NCHANNELS))
- return (MCD_CHANNEL_INVALID);
-
- *csum = MCD_relocBuffDesc[channel].csumResult;
- return (MCD_OK);
-#else
- return (MCD_ERROR);
-#endif
-}
-
-/*********************** End of MCD_resumeDma() *********************/
-
-/********************************************************************/
-/* Function: MCD_getCodeSize
- * Purpose: Provide the size requirements of the microcoded tasks
- * Returns: Size in bytes
- */
-int MCD_getCodeSize(void)
-{
-#ifdef MCD_INCLUDE_EU
- return (0x2b5c);
-#else
- return (0x173c);
-#endif
-}
-
-/********************** End of MCD_getCodeSize() ********************/
-
-/********************************************************************/
-/* Function: MCD_getVersion
- * Purpose: Provide the version string and number
- * Arguments: longVersion - user supplied pointer to a pointer to a char
- * which points to the version string
- * Returns: Version number and version string (by reference)
- */
-char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
-#define MCD_REV_MAJOR 0x00
-#define MCD_REV_MINOR 0x03
-
-int MCD_getVersion(char **longVersion)
-{
- *longVersion = MCD_versionString;
- return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
-}
-
-/********************** End of MCD_getVersion() *********************/
-
-/********************************************************************/
-/* Private version of memcpy()
- * Note that everything this is used for is longword-aligned.
- */
-static void MCD_memcpy(int *dest, int *src, u32 size)
-{
- u32 i;
-
- for (i = 0; i < size; i += sizeof(int), dest++, src++)
- *dest = *src;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-/* Contains task code and structures for Multi-channel DMA */
-
-#include <common.h>
-
-#include <MCD_dma.h>
-
-u32 MCD_varTab0[];
-u32 MCD_varTab1[];
-u32 MCD_varTab2[];
-u32 MCD_varTab3[];
-u32 MCD_varTab4[];
-u32 MCD_varTab5[];
-u32 MCD_varTab6[];
-u32 MCD_varTab7[];
-u32 MCD_varTab8[];
-u32 MCD_varTab9[];
-u32 MCD_varTab10[];
-u32 MCD_varTab11[];
-u32 MCD_varTab12[];
-u32 MCD_varTab13[];
-u32 MCD_varTab14[];
-u32 MCD_varTab15[];
-
-u32 MCD_funcDescTab0[];
-#ifdef MCD_INCLUDE_EU
-u32 MCD_funcDescTab1[];
-u32 MCD_funcDescTab2[];
-u32 MCD_funcDescTab3[];
-u32 MCD_funcDescTab4[];
-u32 MCD_funcDescTab5[];
-u32 MCD_funcDescTab6[];
-u32 MCD_funcDescTab7[];
-u32 MCD_funcDescTab8[];
-u32 MCD_funcDescTab9[];
-u32 MCD_funcDescTab10[];
-u32 MCD_funcDescTab11[];
-u32 MCD_funcDescTab12[];
-u32 MCD_funcDescTab13[];
-u32 MCD_funcDescTab14[];
-u32 MCD_funcDescTab15[];
-#endif
-
-u32 MCD_contextSave0[];
-u32 MCD_contextSave1[];
-u32 MCD_contextSave2[];
-u32 MCD_contextSave3[];
-u32 MCD_contextSave4[];
-u32 MCD_contextSave5[];
-u32 MCD_contextSave6[];
-u32 MCD_contextSave7[];
-u32 MCD_contextSave8[];
-u32 MCD_contextSave9[];
-u32 MCD_contextSave10[];
-u32 MCD_contextSave11[];
-u32 MCD_contextSave12[];
-u32 MCD_contextSave13[];
-u32 MCD_contextSave14[];
-u32 MCD_contextSave15[];
-
-u32 MCD_realTaskTableSrc[] = {
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab0, /* Task 0 Variable Table */
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave0, /* Task 0 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab1, /* Task 1 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab1, /* Task 1 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave1, /* Task 1 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab2, /* Task 2 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab2, /* Task 2 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave2, /* Task 2 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab3, /* Task 3 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab3, /* Task 3 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave3, /* Task 3 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab4, /* Task 4 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab4, /* Task 4 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave4, /* Task 4 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab5, /* Task 5 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab5, /* Task 5 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave5, /* Task 5 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab6, /* Task 6 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab6, /* Task 6 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave6, /* Task 6 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab7, /* Task 7 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab7, /* Task 7 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave7, /* Task 7 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab8, /* Task 8 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab8, /* Task 8 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave8, /* Task 8 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab9, /* Task 9 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab9, /* Task 9 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave9, /* Task 9 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab10, /* Task 10 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab10, /* Task 10 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave10, /* Task 10 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab11, /* Task 11 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab11, /* Task 11 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave11, /* Task 11 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab12, /* Task 12 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab12, /* Task 12 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave12, /* Task 12 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab13, /* Task 13 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab13, /* Task 13 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave13, /* Task 13 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab14, /* Task 14 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab14, /* Task 14 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave14, /* Task 14 context save space */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_varTab15, /* Task 15 Variable Table */
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_funcDescTab15, /* Task 15 Fn Desc. Table & Flags */
-#else
- (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
-#endif
- 0x00000000,
- 0x00000000,
- (u32) MCD_contextSave15, /* Task 15 context save space */
- 0x00000000,
-};
-
-u32 MCD_varTab0[] = { /* Task 0 Variable Table */
- 0x00000000, /* var[0] */
- 0x00000000, /* var[1] */
- 0x00000000, /* var[2] */
- 0x00000000, /* var[3] */
- 0x00000000, /* var[4] */
- 0x00000000, /* var[5] */
- 0x00000000, /* var[6] */
- 0x00000000, /* var[7] */
- 0x00000000, /* var[8] */
- 0x00000000, /* var[9] */
- 0x00000000, /* var[10] */
- 0x00000000, /* var[11] */
- 0x00000000, /* var[12] */
- 0x00000000, /* var[13] */
- 0x00000000, /* var[14] */
- 0x00000000, /* var[15] */
- 0x00000000, /* var[16] */
- 0x00000000, /* var[17] */
- 0x00000000, /* var[18] */
- 0x00000000, /* var[19] */
- 0x00000000, /* var[20] */
- 0x00000000, /* var[21] */
- 0x00000000, /* var[22] */
- 0x00000000, /* var[23] */
- 0xe0000000, /* inc[0] */
- 0x20000000, /* inc[1] */
- 0x2000ffff, /* inc[2] */
- 0x00000000, /* inc[3] */
- 0x00000000, /* inc[4] */
- 0x00000000, /* inc[5] */
- 0x00000000, /* inc[6] */
- 0x00000000, /* inc[7] */
-};
-
-u32 MCD_varTab1[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab2[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab3[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab4[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab5[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab6[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab7[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab8[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab9[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab10[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab11[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab12[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab13[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab14[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_varTab15[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xe0000000,
- 0x20000000,
- 0x2000ffff,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_funcDescTab0[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-#ifdef MCD_INCLUDE_EU
-u32 MCD_funcDescTab1[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
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-};
-
-u32 MCD_funcDescTab2[] = {
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-};
-
-u32 MCD_funcDescTab3[] = {
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- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab4[] = {
- 0x00000000,
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- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab5[] = {
- 0x00000000,
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-};
-
-u32 MCD_funcDescTab6[] = {
- 0x00000000,
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-};
-
-u32 MCD_funcDescTab7[] = {
- 0x00000000,
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- 0x202fa000,
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- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab8[] = {
- 0x00000000,
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- 0xa0045670,
- 0xa0000000,
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- 0x21800000,
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- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab9[] = {
- 0x00000000,
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-};
-
-u32 MCD_funcDescTab10[] = {
- 0x00000000,
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- 0x202da000,
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- 0x202f2000,
-};
-
-u32 MCD_funcDescTab11[] = {
- 0x00000000,
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- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab12[] = {
- 0x00000000,
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- 0x202fa000,
- 0x202f9000,
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- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab13[] = {
- 0x00000000,
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- 0x21800000,
- 0x21e00000,
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- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab14[] = {
- 0x00000000,
- 0x00000000,
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- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-
-u32 MCD_funcDescTab15[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
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- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0xa0045670,
- 0xa0000000,
- 0xa0000000,
- 0x20000000,
- 0x21800000,
- 0x21e00000,
- 0x20400000,
- 0x20500000,
- 0x205a0000,
- 0x20a00000,
- 0x202fa000,
- 0x202f9000,
- 0x202ea000,
- 0x202da000,
- 0x202e2000,
- 0x202f2000,
-};
-#endif /*MCD_INCLUDE_EU */
-
-u32 MCD_contextSave0[128]; /* Task 0 context save space */
-u32 MCD_contextSave1[128]; /* Task 1 context save space */
-u32 MCD_contextSave2[128]; /* Task 2 context save space */
-u32 MCD_contextSave3[128]; /* Task 3 context save space */
-u32 MCD_contextSave4[128]; /* Task 4 context save space */
-u32 MCD_contextSave5[128]; /* Task 5 context save space */
-u32 MCD_contextSave6[128]; /* Task 6 context save space */
-u32 MCD_contextSave7[128]; /* Task 7 context save space */
-u32 MCD_contextSave8[128]; /* Task 8 context save space */
-u32 MCD_contextSave9[128]; /* Task 9 context save space */
-u32 MCD_contextSave10[128]; /* Task 10 context save space */
-u32 MCD_contextSave11[128]; /* Task 11 context save space */
-u32 MCD_contextSave12[128]; /* Task 12 context save space */
-u32 MCD_contextSave13[128]; /* Task 13 context save space */
-u32 MCD_contextSave14[128]; /* Task 14 context save space */
-u32 MCD_contextSave15[128]; /* Task 15 context save space */
-
-u32 MCD_ChainNoEu_TDT[];
-u32 MCD_SingleNoEu_TDT[];
-#ifdef MCD_INCLUDE_EU
-u32 MCD_ChainEu_TDT[];
-u32 MCD_SingleEu_TDT[];
-#endif
-u32 MCD_ENetRcv_TDT[];
-u32 MCD_ENetXmit_TDT[];
-
-u32 MCD_modelTaskTableSrc[] = {
- (u32) MCD_ChainNoEu_TDT,
- (u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_SingleNoEu_TDT,
- (u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-#ifdef MCD_INCLUDE_EU
- (u32) MCD_ChainEu_TDT,
- (u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_SingleEu_TDT,
- (u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-#endif
- (u32) MCD_ENetRcv_TDT,
- (u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- (u32) MCD_ENetXmit_TDT,
- (u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0],
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-u32 MCD_ChainNoEu_TDT[] = {
- 0x80004000,
- 0x8118801b,
- 0xb8c60018,
- 0x10002b10,
- 0x7000000d,
- 0x018cf89f,
- 0x6000000a,
- 0x080cf89f,
- 0x000001f8,
- 0x98180364,
- 0x8118801b,
- 0xf8c6001a,
- 0xb8c6601b,
- 0x10002710,
- 0x00000f18,
- 0xb8c6001d,
- 0x10001310,
- 0x60000007,
- 0x014cf88b,
- 0x98c6001c,
- 0x00000710,
- 0x98c70018,
- 0x10001f10,
- 0x0000c818,
- 0x000001f8,
- 0xc1476018,
- 0xc003231d,
- 0x811a601b,
- 0xc1862102,
- 0x849be009,
- 0x03fed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x1000cb20,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0xc1476018,
- 0xc003241d,
- 0x811a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc1862102,
- 0x849be009,
- 0x0bfed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x1000cb20,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88f,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0x8118801b,
- 0xd8c60018,
- 0x98c6601c,
- 0x6000000b,
- 0x0c8cfc9f,
- 0x000001f8,
- 0xa146001e,
- 0x10000b08,
- 0x10002050,
- 0xb8c60018,
- 0x10002b10,
- 0x7000000a,
- 0x080cf89f,
- 0x6000000d,
- 0x018cf89f,
- 0x000001f8,
- 0x8618801b,
- 0x7000000e,
- 0x084cf21f,
- 0xd8990336,
- 0x8019801b,
- 0x040001f8,
- 0x000001f8,
- 0x000001f8,
-};
-
-u32 MCD_SingleNoEu_TDT[] = {
- 0x8198001b,
- 0x7000000d,
- 0x080cf81f,
- 0x8198801b,
- 0x6000000e,
- 0x084cf85f,
- 0x000001f8,
- 0x8298001b,
- 0x7000000d,
- 0x010cf81f,
- 0x6000000e,
- 0x018cf81f,
- 0xc202601b,
- 0xc002221c,
- 0x809a601b,
- 0xc10420c2,
- 0x839be009,
- 0x03fed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000006,
- 0x088cf889,
- 0x1000cb28,
- 0x70000006,
- 0x088cf889,
- 0x1000cb30,
- 0x70000006,
- 0x088cf889,
- 0x0000cb38,
- 0x000001f8,
- 0xc202601b,
- 0xc002229c,
- 0x809a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc10420c2,
- 0x839be009,
- 0x0bfed7b8,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000006,
- 0x088cf889,
- 0x1000cb28,
- 0x70000006,
- 0x088cf889,
- 0x1000cb30,
- 0x70000006,
- 0x088cf889,
- 0x0000cb38,
- 0x000001f8,
- 0xc318022d,
- 0x8018801b,
- 0x040001f8,
-};
-
-#ifdef MCD_INCLUDE_EU
-u32 MCD_ChainEu_TDT[] = {
- 0x80004000,
- 0x8198801b,
- 0xb8c68018,
- 0x10002f10,
- 0x7000000d,
- 0x01ccf89f,
- 0x6000000a,
- 0x080cf89f,
- 0x000001f8,
- 0x981803a4,
- 0x8198801b,
- 0xf8c6801a,
- 0xb8c6e01b,
- 0x10002b10,
- 0x00001318,
- 0xb8c6801d,
- 0x10001710,
- 0x60000007,
- 0x018cf88c,
- 0x98c6801c,
- 0x00000b10,
- 0x98c78018,
- 0x10002310,
- 0x0000c820,
- 0x000001f8,
- 0x8698801b,
- 0x7000000f,
- 0x084cf2df,
- 0xd899042d,
- 0x8019801b,
- 0x60000003,
- 0x2cd7c7df,
- 0xd8990364,
- 0x8019801b,
- 0x60000003,
- 0x2c17c7df,
- 0x000001f8,
- 0xc1c7e018,
- 0xc003a35e,
- 0x819a601b,
- 0xc206a142,
- 0x851be009,
- 0x63fe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf81f,
- 0x1000cb20,
- 0x70000006,
- 0x088cf891,
- 0x1000cb28,
- 0x70000006,
- 0x088cf891,
- 0x1000cb30,
- 0x70000006,
- 0x088cf891,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0xc1c7e018,
- 0xc003a49e,
- 0x819a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc206a142,
- 0x851be009,
- 0x6bfe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf81f,
- 0x1000cb20,
- 0x70000006,
- 0x088cf891,
- 0x1000cb28,
- 0x70000006,
- 0x088cf891,
- 0x1000cb30,
- 0x70000006,
- 0x088cf891,
- 0x1000cb38,
- 0x0000c728,
- 0x000001f8,
- 0x8198801b,
- 0xd8c68018,
- 0x98c6e01c,
- 0x6000000b,
- 0x0c8cfc9f,
- 0x0000cc08,
- 0xa1c6801e,
- 0x10000f08,
- 0x10002458,
- 0xb8c68018,
- 0x10002f10,
- 0x7000000a,
- 0x080cf89f,
- 0x6000000d,
- 0x01ccf89f,
- 0x000001f8,
- 0x8698801b,
- 0x7000000e,
- 0x084cf25f,
- 0xd899037f,
- 0x8019801b,
- 0x040001f8,
- 0x000001f8,
- 0x000001f8,
-};
-
-u32 MCD_SingleEu_TDT[] = {
- 0x8218001b,
- 0x7000000d,
- 0x080cf81f,
- 0x8218801b,
- 0x6000000e,
- 0x084cf85f,
- 0x000001f8,
- 0x8318001b,
- 0x7000000d,
- 0x014cf81f,
- 0x6000000e,
- 0x01ccf81f,
- 0x8498001b,
- 0x7000000f,
- 0x080cf19f,
- 0xd81882a4,
- 0x8019001b,
- 0x60000003,
- 0x2c97c7df,
- 0xd818826d,
- 0x8019001b,
- 0x60000003,
- 0x2c17c7df,
- 0x000001f8,
- 0xc282e01b,
- 0xc002a25e,
- 0x811a601b,
- 0xc184a102,
- 0x841be009,
- 0x63fe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf99f,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88b,
- 0x0000cb38,
- 0x000001f8,
- 0xc282e01b,
- 0xc002a31e,
- 0x811a601b,
- 0xda9b001b,
- 0x9b9be01b,
- 0x0000d3a0,
- 0xc184a102,
- 0x841be009,
- 0x6bfe0000,
- 0x0d4cfddf,
- 0xda9b001b,
- 0x9b9be01b,
- 0x70000002,
- 0x004cf99f,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb28,
- 0x70000006,
- 0x088cf88b,
- 0x1000cb30,
- 0x70000006,
- 0x088cf88b,
- 0x0000cb38,
- 0x000001f8,
- 0x8144801c,
- 0x0000c008,
- 0xc398027f,
- 0x8018801b,
- 0x040001f8,
-};
-#endif
-u32 MCD_ENetRcv_TDT[] = {
- 0x80004000,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0x98180209,
- 0x81c40004,
- 0x7000000e,
- 0x010cf05f,
- 0x7000000c,
- 0x01ccf05f,
- 0x70000004,
- 0x014cf049,
- 0x70000004,
- 0x004cf04a,
- 0x00000b88,
- 0xc4030150,
- 0x8119e012,
- 0x03e0cf90,
- 0x81188000,
- 0x000ac788,
- 0xc4030000,
- 0x8199e000,
- 0x70000004,
- 0x084cfc8b,
- 0x60000005,
- 0x0cccf841,
- 0x81c60000,
- 0xc399021b,
- 0x80198000,
- 0x00008400,
- 0x00000f08,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0xc2188209,
- 0x80190000,
- 0x040001f8,
- 0x000001f8,
-};
-
-u32 MCD_ENetXmit_TDT[] = {
- 0x80004000,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0x98180309,
- 0x80004003,
- 0x81c60004,
- 0x7000000e,
- 0x014cf05f,
- 0x7000000c,
- 0x028cf05f,
- 0x7000000d,
- 0x018cf05f,
- 0x70000004,
- 0x01ccf04d,
- 0x10000b90,
- 0x60000004,
- 0x020cf0a1,
- 0xc3188312,
- 0x83c70000,
- 0x00001f10,
- 0xc583a3c3,
- 0x81042325,
- 0x03e0c798,
- 0xd8990000,
- 0x9999e000,
- 0x000acf98,
- 0xd8992306,
- 0x9999e03f,
- 0x03eac798,
- 0xd8990000,
- 0x9999e000,
- 0x000acf98,
- 0xd8990000,
- 0x99832302,
- 0x0beac798,
- 0x81988000,
- 0x6000000b,
- 0x0c4cfc5f,
- 0x81c80000,
- 0xc5190312,
- 0x80198000,
- 0x00008400,
- 0x00000f08,
- 0x81988000,
- 0x10000788,
- 0x6000000a,
- 0x080cf05f,
- 0xc2988309,
- 0x80190000,
- 0x040001f8,
- 0x000001f8,
-};
-
-#ifdef MCD_INCLUDE_EU
-MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-/* Functions for initializing variable tables of different types of tasks. */
-
-/*
- * Do not edit!
- */
-
-#include <MCD_dma.h>
-
-extern dmaRegs *MCD_dmaBar;
-
-/* Task 0 */
-
-void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
- MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */
- MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */
- MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
- MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 1 */
-
-void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */
- MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 2 */
-
-void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
- MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */
- MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */
- MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */
- MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */
- MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */
- MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */
- MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
- MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 3 */
-
-void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */
- MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
- MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */
- MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
- MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */
- MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
- MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */
- MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
- MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */
- MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
- MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 4 */
-
-void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
- MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
- MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */
- MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */
- MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
- MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
- MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */
- MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
-
-/* Task 5 */
-
-void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
- volatile TaskTableEntry * taskTable, int channel)
-{
- volatile TaskTableEntry *taskChan = taskTable + channel;
-
- MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
- MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
- MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */
- MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
- MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
- MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
- MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
- MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
- MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
- MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
- MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
- MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
- MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
- MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */
- MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */
- MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
- MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */
- MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
- MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
- MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */
- MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */
- MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */
- MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
- MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */
- MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */
-
- /* Set the task's Enable bit in its Task Control Register */
- MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
-}
obj-$(CONFIG_DMA) += dma-uclass.o
-obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
obj-$(CONFIG_APBH_DMA) += apbh_dma.o
obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
menu "Fastboot support"
+ depends on CMDLINE
config FASTBOOT
bool
depends on MCFFEC
bool "Invalidate icache during ethernet operations"
-config FSLDMAFEC
- bool "ColdFire DMA Ethernet Support"
- select PHYLIB
- select SYS_DISCOVER_PHY
- help
- This driver supports the network interface units in the
- ColdFire family.
-
config KS8851_MLL
bool "Microchip KS8851-MLL controller driver"
help
This Driver support MediaTek Ethernet GMAC
Say Y to enable support for the MediaTek Ethernet GMAC.
+config HIFEMAC_ETH
+ bool "HiSilicon Fast Ethernet Controller"
+ select DM_CLK
+ select DM_RESET
+ select PHYLIB
+ help
+ This driver supports HIFEMAC Ethernet controller found on
+ HiSilicon SoCs.
+
+config HIFEMAC_MDIO
+ bool "HiSilicon Fast Ethernet Controller MDIO interface"
+ depends on DM_MDIO
+ select DM_CLK
+ help
+ This driver supports the internal MDIO interface of HIFEMAC
+ Ethernet controller.
+
config HIGMACV300_ETH
bool "HiSilicon Gigabit Ethernet Controller"
select DM_RESET
obj-$(CONFIG_FEC_MXC) += fec_mxc.o
obj-$(CONFIG_FMAN_ENET) += fm/
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
-obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o
obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o
obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
obj-$(CONFIG_FTGMAC100) += ftgmac100.o
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
+obj-$(CONFIG_HIFEMAC_ETH) += hifemac.o
+obj-$(CONFIG_HIFEMAC_MDIO) += hifemac_mdio.o
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_KSZ9477) += ksz9477.o
#include <net.h>
#include <pci.h>
#include <reset.h>
+#include <phys2bus.h>
#include <asm/cache.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE];
- desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
+ desc_p->dmamac_addr = dev_phys_to_bus(priv->dev,
+ (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]);
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev,
+ (ulong)&desc_table_p[idx + 1]);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = (ulong)&desc_table_p[0];
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]);
/* Flush all Tx buffer descriptors at once */
flush_dcache_range((ulong)priv->tx_mac_descrtable,
(ulong)priv->tx_mac_descrtable +
sizeof(priv->tx_mac_descrtable));
- writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+ writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]),
+ &dma_p->txdesclistaddr);
priv->tx_currdescnum = 0;
}
for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
- desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE];
- desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
+ desc_p->dmamac_addr = dev_phys_to_bus(priv->dev,
+ (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]);
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev,
+ (ulong)&desc_table_p[idx + 1]);
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
}
/* Correcting the last pointer of the chain */
- desc_p->dmamac_next = (ulong)&desc_table_p[0];
+ desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]);
/* Flush all Rx buffer descriptors at once */
flush_dcache_range((ulong)priv->rx_mac_descrtable,
(ulong)priv->rx_mac_descrtable +
sizeof(priv->rx_mac_descrtable));
- writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+ writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]),
+ &dma_p->rxdesclistaddr);
priv->rx_currdescnum = 0;
}
ulong desc_start = (ulong)desc_p;
ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- ulong data_start = desc_p->dmamac_addr;
+ ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
/*
* Strictly we only need to invalidate the "txrx_status" field
ulong desc_start = (ulong)desc_p;
ulong desc_end = desc_start +
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
- ulong data_start = desc_p->dmamac_addr;
+ ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr);
ulong data_end;
/* Invalidate entire buffer descriptor */
/* Invalidate received data */
data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
invalidate_dcache_range(data_start, data_end);
- *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
+ *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev,
+ desc_p->dmamac_addr);
}
return length;
goto mdio_err;
}
priv->bus = miiphy_get_dev_by_name(dev->name);
+ priv->dev = dev;
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
int clock_count; /* number of clock in clock list */
#endif
+ struct udevice *dev;
struct phy_device *phydev;
struct mii_dev *bus;
};
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
ulong desc_pad;
+ ulong addr64;
debug("%s(dev=%p):\n", __func__, dev);
for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE));
+
+ addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
- eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
- (i * EQOS_MAX_PACKET_SIZE),
- EQOS_MAX_PACKET_SIZE);
+ eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE);
}
- writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, false),
- &eqos->dma_regs->ch0_txdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, false);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address);
writel(EQOS_DESCRIPTORS_TX - 1,
&eqos->dma_regs->ch0_txdesc_ring_length);
- writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
- writel((ulong)eqos_get_desc(eqos, 0, true),
- &eqos->dma_regs->ch0_rxdesc_list_address);
+ addr64 = (ulong)eqos_get_desc(eqos, 0, true);
+ writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress);
+ writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address);
writel(EQOS_DESCRIPTORS_RX - 1,
&eqos->dma_regs->ch0_rxdesc_ring_length);
eqos->tx_desc_idx++;
eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
- tx_desc->des0 = (ulong)eqos->tx_dma_buf;
- tx_desc->des1 = 0;
+ tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf);
+ tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf);
tx_desc->des2 = length;
/*
* Make sure that if HW sees the _OWN write below, it will see all the
for (idx = eqos->rx_desc_idx - idx_mask;
idx <= eqos->rx_desc_idx;
idx++) {
+ ulong addr64;
+
rx_desc = eqos_get_desc(eqos, idx, true);
rx_desc->des0 = 0;
+ rx_desc->des1 = 0;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
eqos->config->ops->eqos_inval_buffer(packet, length);
- rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
- (idx * EQOS_MAX_PACKET_SIZE));
- rx_desc->des1 = 0;
+ addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des0 = lower_32_bits(addr64);
+ rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des2 = 0;
/*
* Make sure that if HW sees the _OWN write below,
.write_hwaddr = e1000_write_hwaddr,
};
-static const struct udevice_id e1000_eth_ids[] = {
- { .compatible = "intel,e1000" },
- { }
-};
-
U_BOOT_DRIVER(eth_e1000) = {
.name = "eth_e1000",
.id = UCLASS_ETH,
- .of_match = e1000_eth_ids,
.bind = e1000_eth_bind,
.probe = e1000_eth_probe,
.ops = &e1000_eth_ops,
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*/
-#include <common.h>
#include <env.h>
#include <fs_loader.h>
#include <image.h>
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * Conversion to DM
- * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <hang.h>
-#include <malloc.h>
-#include <command.h>
-#include <config.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/mii.h>
-#include <asm/immap.h>
-#include <asm/fsl_mcdmafec.h>
-
-#include "MCD_dma.h"
-
-#undef ET_DEBUG
-#undef MII_DEBUG
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH 1520
-#define PKT_MAXBUF_SIZE 1518
-#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
-
-/* RxBD bits definitions */
-#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
- BD_ENET_RX_OV | BD_ENET_RX_TR)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void init_eth_info(struct fec_info_dma *info)
-{
- /* setup Receive and Transmit buffer descriptor */
-#ifdef CFG_SYS_FEC_BUF_USE_SRAM
- static u32 tmp;
-
- if (info->index == 0)
- tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
- else
- info->rxbd = (cbd_t *)DBUF_LENGTH;
-
- info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
- tmp = (u32)info->rxbd;
- info->txbd =
- (cbd_t *)((u32)info->txbd + tmp +
- (PKTBUFSRX * sizeof(cbd_t)));
- tmp = (u32)info->txbd;
- info->txbuf =
- (char *)((u32)info->txbuf + tmp +
- (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- tmp = (u32)info->txbuf;
-#else
- info->rxbd =
- (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- (PKTBUFSRX * sizeof(cbd_t)));
- info->txbd =
- (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
- (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
- info->txbuf =
- (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
-#endif
-
-#ifdef ET_DEBUG
- printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
-#endif
- info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
-}
-
-static void fec_halt(struct udevice *dev)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
- int counter = 0xffff;
-
- /* issue graceful stop command to the FEC transmitter if necessary */
- fecp->tcr |= FEC_TCR_GTS;
-
- /* wait for graceful stop to register */
- while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
- ;
-
- /* Disable DMA tasks */
- MCD_killDma(info->tx_task);
- MCD_killDma(info->rx_task);
-
- /* Disable the Ethernet Controller */
- fecp->ecr &= ~FEC_ECR_ETHER_EN;
-
- /* Clear FIFO status registers */
- fecp->rfsr &= FIFO_ERRSTAT;
- fecp->tfsr &= FIFO_ERRSTAT;
-
- fecp->frst = 0x01000000;
-
- /* Issue a reset command to the FEC chip */
- fecp->ecr |= FEC_ECR_RESET;
-
- /* wait at least 20 clock cycles */
- mdelay(10);
-
-#ifdef ET_DEBUG
- printf("Ethernet task stopped\n");
-#endif
-}
-
-#ifdef ET_DEBUG
-static void dbg_fec_regs(struct eth_device *dev)
-{
- struct fec_info_dma *info = dev->priv;
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
-
- printf("=====\n");
- printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
- printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
- printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
- printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
- printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
- printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
- printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
- printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
- printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
- printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
- printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
- printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
- printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
- printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
- printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
- printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
- printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
- printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
- printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
- printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
- printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
- printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
- printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
- printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
- printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
- printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
- printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
- printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
- printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
- printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
- printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
- printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
- printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
- printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
- printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
-}
-#endif
-
-static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
-{
- struct bd_info *bd = gd->bd;
-
- if ((dup_spd >> 16) == FULL) {
- /* Set maximum frame length */
- fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
- FEC_RCR_PROM | 0x100;
- fecp->tcr = FEC_TCR_FDEN;
- } else {
- /* Half duplex mode */
- fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
- FEC_RCR_MII_MODE | FEC_RCR_DRT;
- fecp->tcr &= ~FEC_TCR_FDEN;
- }
-
- if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef MII_DEBUG
- printf("100Mbps\n");
-#endif
- bd->bi_ethspeed = 100;
- } else {
-#ifdef MII_DEBUG
- printf("10Mbps\n");
-#endif
- bd->bi_ethspeed = 10;
- }
-}
-
-static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
-{
- u8 curr_byte; /* byte for which to compute the CRC */
- int byte; /* loop - counter */
- int bit; /* loop - counter */
- u32 crc = 0xffffffff; /* initial value */
-
- for (byte = 0; byte < 6; byte++) {
- curr_byte = mac[byte];
- for (bit = 0; bit < 8; bit++) {
- if ((curr_byte & 0x01) ^ (crc & 0x01)) {
- crc >>= 1;
- crc = crc ^ 0xedb88320;
- } else {
- crc >>= 1;
- }
- curr_byte >>= 1;
- }
- }
-
- crc = crc >> 26;
-
- /* Set individual hash table register */
- if (crc >= 32) {
- fecp->ialr = (1 << (crc - 32));
- fecp->iaur = 0;
- } else {
- fecp->ialr = 0;
- fecp->iaur = (1 << crc);
- }
-
- /* Set physical address */
- fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
- fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
-
- /* Clear multicast address hash table */
- fecp->gaur = 0;
- fecp->galr = 0;
-}
-
-static int fec_init(struct udevice *dev)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
- int rval, i;
- uchar enetaddr[6];
-
-#ifdef ET_DEBUG
- printf("fec_init: iobase 0x%08x ...\n", info->iobase);
-#endif
-
- fecpin_setclear(info, 1);
- fec_halt(dev);
-
- mii_init();
- set_fec_duplex_speed(fecp, info->dup_spd);
-
- /* We use strictly polling mode only */
- fecp->eimr = 0;
-
- /* Clear any pending interrupt */
- fecp->eir = 0xffffffff;
-
- /* Set station address */
- if (info->index == 0)
- rval = eth_env_get_enetaddr("ethaddr", enetaddr);
- else
- rval = eth_env_get_enetaddr("eth1addr", enetaddr);
-
- if (!rval) {
- puts("Please set a valid MAC address\n");
- return -EINVAL;
- }
-
- fec_set_hwaddr(fecp, enetaddr);
-
- /* Set Opcode/Pause Duration Register */
- fecp->opd = 0x00010020;
-
- /* Setup Buffers and Buffer Descriptors */
- info->rx_idx = 0;
- info->tx_idx = 0;
-
- /* Setup Receiver Buffer Descriptors (13.14.24.18)
- * Settings: Empty, Wrap */
- for (i = 0; i < PKTBUFSRX; i++) {
- info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
- info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
- }
- info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
-
- /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
- * Settings: Last, Tx CRC */
- for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) {
- info->txbd[i].cbd_sc = 0;
- info->txbd[i].cbd_datlen = 0;
- info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
- }
- info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
-
- info->used_tbd_idx = 0;
- info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER;
-
- /* Set Rx FIFO alarm and granularity value */
- fecp->rfcr = 0x0c000000;
- fecp->rfar = 0x0000030c;
-
- /* Set Tx FIFO granularity value */
- fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
- fecp->tfar = 0x00000080;
-
- fecp->tfwr = 0x2;
- fecp->ctcwr = 0x03000000;
-
- /* Enable DMA receive task */
- MCD_startDma(info->rx_task,
- (s8 *)info->rxbd,
- 0,
- (s8 *)&fecp->rfdr,
- 4,
- 0,
- 4,
- info->rx_init,
- info->rx_pri,
- (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
- (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
- );
-
- /* Enable DMA tx task with no ready buffer descriptors */
- MCD_startDma(info->tx_task,
- (s8 *)info->txbd,
- 0,
- (s8 *)&fecp->tfdr,
- 4,
- 0,
- 4,
- info->tx_init,
- info->tx_pri,
- (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
- (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
- );
-
- /* Now enable the transmit and receive processing */
- fecp->ecr |= FEC_ECR_ETHER_EN;
-
- return 0;
-}
-
-static int mcdmafec_init(struct udevice *dev)
-{
- return fec_init(dev);
-}
-
-static int mcdmafec_send(struct udevice *dev, void *packet, int length)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- cbd_t *p_tbd, *p_used_tbd;
- u16 phy_status;
-
- miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
-
- /* process all the consumed TBDs */
- while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) {
- p_used_tbd = &info->txbd[info->used_tbd_idx];
- if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
-#ifdef ET_DEBUG
- printf("Cannot clean TBD %d, in use\n",
- info->clean_tbd_num);
-#endif
- return 0;
- }
-
- /* clean this buffer descriptor */
- if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1))
- p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
- else
- p_used_tbd->cbd_sc = 0;
-
- /* update some indeces for a correct handling of TBD ring */
- info->clean_tbd_num++;
- info->used_tbd_idx = (info->used_tbd_idx + 1)
- % CFG_SYS_TX_ETH_BUFFER;
- }
-
- /* Check for valid length of data. */
- if (length > 1500 || length <= 0)
- return -1;
-
- /* Check the number of vacant TxBDs. */
- if (info->clean_tbd_num < 1) {
- printf("No available TxBDs ...\n");
- return -1;
- }
-
- /* Get the first TxBD to send the mac header */
- p_tbd = &info->txbd[info->tx_idx];
- p_tbd->cbd_datlen = length;
- p_tbd->cbd_bufaddr = (u32)packet;
- p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
- info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER;
-
- /* Enable DMA transmit task */
- MCD_continDma(info->tx_task);
-
- info->clean_tbd_num -= 1;
-
- /* wait until frame is sent . */
- while (p_tbd->cbd_sc & BD_ENET_TX_READY)
- udelay(10);
-
- return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
-}
-
-static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
-
- cbd_t *prbd = &info->rxbd[info->rx_idx];
- u32 ievent;
- int frame_length, len = 0;
-
- /* Check if any critical events have happened */
- ievent = fecp->eir;
- if (ievent != 0) {
- fecp->eir = ievent;
-
- if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
- printf("fec_recv: error\n");
- fec_halt(dev);
- fec_init(dev);
- return 0;
- }
-
- if (ievent & FEC_EIR_HBERR) {
- /* Heartbeat error */
- fecp->tcr |= FEC_TCR_GTS;
- }
-
- if (ievent & FEC_EIR_GRA) {
- /* Graceful stop complete */
- if (fecp->tcr & FEC_TCR_GTS) {
- printf("fec_recv: tcr_gts\n");
- fec_halt(dev);
- fecp->tcr &= ~FEC_TCR_GTS;
- fec_init(dev);
- }
- }
- }
-
- if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
- if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
- !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
- ((prbd->cbd_datlen - 4) > 14)) {
- /* Get buffer address and size */
- frame_length = prbd->cbd_datlen - 4;
-
- /* Fill the buffer and pass it to upper layers */
- net_process_received_packet((uchar *)prbd->cbd_bufaddr,
- frame_length);
- len = frame_length;
- }
-
- /* Reset buffer descriptor as empty */
- if (info->rx_idx == (PKTBUFSRX - 1))
- prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
- else
- prbd->cbd_sc = BD_ENET_RX_EMPTY;
-
- prbd->cbd_datlen = PKTSIZE_ALIGN;
-
- /* Now, we have an empty RxBD, restart the DMA receive task */
- MCD_continDma(info->rx_task);
-
- /* Increment BD count */
- info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
- }
-
- return len;
-}
-
-static void mcdmafec_halt(struct udevice *dev)
-{
- fec_halt(dev);
-}
-
-static const struct eth_ops mcdmafec_ops = {
- .start = mcdmafec_init,
- .send = mcdmafec_send,
- .recv = mcdmafec_recv,
- .stop = mcdmafec_halt,
-};
-
-/*
- * Boot sequence, called just after mcffec_of_to_plat,
- * as DM way, it replaces old mcffec_initialize.
- */
-static int mcdmafec_probe(struct udevice *dev)
-{
- struct fec_info_dma *info = dev_get_priv(dev);
- struct eth_pdata *pdata = dev_get_plat(dev);
- int node = dev_of_offset(dev);
- int retval;
- const u32 *val;
-
- info->index = dev_seq(dev);
- info->iobase = pdata->iobase;
- info->miibase = pdata->iobase;
- info->phy_addr = -1;
-
- val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
- if (val)
- info->rx_task = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
- if (val)
- info->tx_task = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
- if (val)
- info->rx_pri = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
- if (val)
- info->tx_pri = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
- if (val)
- info->rx_init = fdt32_to_cpu(*val);
-
- val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
- if (val)
- info->tx_init = fdt32_to_cpu(*val);
-
-#ifdef CFG_SYS_FEC_BUF_USE_SRAM
- u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000;
-#endif
- init_eth_info(info);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- info->bus = mdio_alloc();
- if (!info->bus)
- return -ENOMEM;
- strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN);
- info->bus->read = mcffec_miiphy_read;
- info->bus->write = mcffec_miiphy_write;
-
- retval = mdio_register(info->bus);
- if (retval < 0)
- return retval;
-#endif
-
- return 0;
-}
-
-static int mcdmafec_remove(struct udevice *dev)
-{
- struct fec_info_dma *priv = dev_get_priv(dev);
-
- mdio_unregister(priv->bus);
- mdio_free(priv->bus);
-
- return 0;
-}
-
-/*
- * Boot sequence, called 1st
- */
-static int mcdmafec_of_to_plat(struct udevice *dev)
-{
- struct eth_pdata *pdata = dev_get_plat(dev);
- const u32 *val;
-
- pdata->iobase = dev_read_addr(dev);
- /* Default to 10Mbit/s */
- pdata->max_speed = 10;
-
- val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
- if (val)
- pdata->max_speed = fdt32_to_cpu(*val);
-
- return 0;
-}
-
-static const struct udevice_id mcdmafec_ids[] = {
- { .compatible = "fsl,mcf-dma-fec" },
- { }
-};
-
-U_BOOT_DRIVER(mcffec) = {
- .name = "mcdmafec",
- .id = UCLASS_ETH,
- .of_match = mcdmafec_ids,
- .of_to_plat = mcdmafec_of_to_plat,
- .probe = mcdmafec_probe,
- .remove = mcdmafec_remove,
- .ops = &mcdmafec_ops,
- .priv_auto = sizeof(struct fec_info_dma),
- .plat_auto = sizeof(struct eth_pdata),
-};
#include <common.h>
#include <clk.h>
+#include <reset.h>
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
u32 max_speed;
struct clk_bulk clks;
+ struct reset_ctl *reset_ctl;
/* End of RX/TX ring buffer bits. Depend on model */
u32 rxdes0_edorr_mask;
priv->txdes0_edotr_mask = BIT(15);
}
+ priv->reset_ctl = devm_reset_control_get_optional(dev, NULL);
+
return clk_get_bulk(dev, &priv->clks);
}
if (ret)
goto out;
+ if (priv->reset_ctl) {
+ ret = reset_deassert(priv->reset_ctl);
+ if (ret)
+ goto out;
+ }
+
/*
* If DM MDIO is enabled, the MDIO bus will be initialized later in
* dm_eth_phy_connect
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+ if (priv->reset_ctl)
+ reset_assert(priv->reset_ctl);
clk_release_bulk(&priv->clks);
return 0;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Hisilicon Fast Ethernet MAC Driver
+ * Adapted from linux
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ * Copyright (c) 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <miiphy.h>
+#include <net.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+
+/* MAC control register list */
+#define MAC_PORTSEL 0x0200
+#define MAC_PORTSEL_STAT_CPU BIT(0)
+#define MAC_PORTSEL_RMII BIT(1)
+#define MAC_PORTSET 0x0208
+#define MAC_PORTSET_DUPLEX_FULL BIT(0)
+#define MAC_PORTSET_LINKED BIT(1)
+#define MAC_PORTSET_SPEED_100M BIT(2)
+#define MAC_SET 0x0210
+#define MAX_FRAME_SIZE 1600
+#define MAX_FRAME_SIZE_MASK GENMASK(10, 0)
+#define BIT_PAUSE_EN BIT(18)
+#define RX_COALESCE_SET 0x0340
+#define RX_COALESCED_FRAME_OFFSET 24
+#define RX_COALESCED_FRAMES 8
+#define RX_COALESCED_TIMER 0x74
+#define QLEN_SET 0x0344
+#define RX_DEPTH_OFFSET 8
+#define MAX_HW_FIFO_DEPTH 64
+#define HW_TX_FIFO_DEPTH 1
+#define MAX_HW_RX_FIFO_DEPTH (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH)
+#define HW_RX_FIFO_DEPTH min(PKTBUFSRX, MAX_HW_RX_FIFO_DEPTH)
+#define IQFRM_DES 0x0354
+#define RX_FRAME_LEN_MASK GENMASK(11, 0)
+#define RX_FRAME_IN_INDEX_MASK GENMASK(17, 12)
+#define IQ_ADDR 0x0358
+#define EQ_ADDR 0x0360
+#define EQFRM_LEN 0x0364
+#define ADDRQ_STAT 0x036C
+#define TX_CNT_INUSE_MASK GENMASK(5, 0)
+#define BIT_TX_READY BIT(24)
+#define BIT_RX_READY BIT(25)
+/* global control register list */
+#define GLB_HOSTMAC_L32 0x0000
+#define GLB_HOSTMAC_H16 0x0004
+#define GLB_SOFT_RESET 0x0008
+#define SOFT_RESET_ALL BIT(0)
+#define GLB_FWCTRL 0x0010
+#define FWCTRL_VLAN_ENABLE BIT(0)
+#define FWCTRL_FW2CPU_ENA BIT(5)
+#define FWCTRL_FWALL2CPU BIT(7)
+#define GLB_MACTCTRL 0x0014
+#define MACTCTRL_UNI2CPU BIT(1)
+#define MACTCTRL_MULTI2CPU BIT(3)
+#define MACTCTRL_BROAD2CPU BIT(5)
+#define MACTCTRL_MACT_ENA BIT(7)
+#define GLB_IRQ_STAT 0x0030
+#define GLB_IRQ_ENA 0x0034
+#define IRQ_ENA_PORT0_MASK GENMASK(7, 0)
+#define IRQ_ENA_PORT0 BIT(18)
+#define IRQ_ENA_ALL BIT(19)
+#define GLB_IRQ_RAW 0x0038
+#define IRQ_INT_RX_RDY BIT(0)
+#define IRQ_INT_TX_PER_PACKET BIT(1)
+#define IRQ_INT_TX_FIFO_EMPTY BIT(6)
+#define IRQ_INT_MULTI_RXRDY BIT(7)
+#define DEF_INT_MASK (IRQ_INT_MULTI_RXRDY | \
+ IRQ_INT_TX_PER_PACKET | \
+ IRQ_INT_TX_FIFO_EMPTY)
+#define GLB_MAC_L32_BASE 0x0100
+#define GLB_MAC_H16_BASE 0x0104
+#define MACFLT_HI16_MASK GENMASK(15, 0)
+#define BIT_MACFLT_ENA BIT(17)
+#define BIT_MACFLT_FW2CPU BIT(21)
+#define GLB_MAC_H16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8))
+#define GLB_MAC_L32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8))
+#define MAX_MAC_FILTER_NUM 8
+#define MAX_UNICAST_ADDRESSES 2
+#define MAX_MULTICAST_ADDRESSES (MAX_MAC_FILTER_NUM - \
+ MAX_UNICAST_ADDRESSES)
+/* software tx and rx queue number, should be power of 2 */
+#define TXQ_NUM 64
+#define RXQ_NUM 128
+
+#define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
+#define MAC_RESET_DELAY_PROPERTY "hisilicon,mac-reset-delay-us"
+#define MAC_RESET_ASSERT_PERIOD 200000
+
+enum phy_reset_delays {
+ PRE_DELAY,
+ PULSE,
+ POST_DELAY,
+ DELAYS_NUM,
+};
+
+enum clk_type {
+ CLK_MAC,
+ CLK_BUS,
+ CLK_PHY,
+ CLK_NUM,
+};
+
+struct hisi_femac_priv {
+ void __iomem *port_base;
+ void __iomem *glb_base;
+ struct clk *clks[CLK_NUM];
+ struct reset_ctl *mac_rst;
+ struct reset_ctl *phy_rst;
+ u32 phy_reset_delays[DELAYS_NUM];
+ u32 mac_reset_delay;
+
+ struct phy_device *phy;
+
+ u32 link_status;
+};
+
+static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs)
+{
+ u32 val;
+
+ val = readl(priv->glb_base + GLB_IRQ_ENA);
+ writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
+}
+
+static void hisi_femac_irq_disable(struct hisi_femac_priv *priv, int irqs)
+{
+ u32 val;
+
+ val = readl(priv->glb_base + GLB_IRQ_ENA);
+ writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
+}
+
+static void hisi_femac_port_init(struct hisi_femac_priv *priv)
+{
+ u32 val;
+
+ /* MAC gets link status info and phy mode by software config */
+ val = MAC_PORTSEL_STAT_CPU;
+ if (priv->phy->interface == PHY_INTERFACE_MODE_RMII)
+ val |= MAC_PORTSEL_RMII;
+ writel(val, priv->port_base + MAC_PORTSEL);
+
+ /*clear all interrupt status */
+ writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
+ hisi_femac_irq_disable(priv, IRQ_ENA_PORT0_MASK | IRQ_ENA_PORT0);
+
+ val = readl(priv->glb_base + GLB_FWCTRL);
+ val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU);
+ val |= FWCTRL_FW2CPU_ENA;
+ writel(val, priv->glb_base + GLB_FWCTRL);
+
+ val = readl(priv->glb_base + GLB_MACTCTRL);
+ val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA);
+ writel(val, priv->glb_base + GLB_MACTCTRL);
+
+ val = readl(priv->port_base + MAC_SET);
+ val &= ~MAX_FRAME_SIZE_MASK;
+ val |= MAX_FRAME_SIZE;
+ writel(val, priv->port_base + MAC_SET);
+
+ val = RX_COALESCED_TIMER |
+ (RX_COALESCED_FRAMES << RX_COALESCED_FRAME_OFFSET);
+ writel(val, priv->port_base + RX_COALESCE_SET);
+
+ val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH;
+ writel(val, priv->port_base + QLEN_SET);
+}
+
+static void hisi_femac_rx_refill(struct hisi_femac_priv *priv)
+{
+ int i;
+ ulong addr;
+
+ for (i = 0; i < HW_RX_FIFO_DEPTH; i++) {
+ addr = (ulong)net_rx_packets[i];
+ writel(addr, priv->port_base + IQ_ADDR);
+ }
+}
+
+static void hisi_femac_adjust_link(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ struct phy_device *phy = priv->phy;
+ u32 status = 0;
+
+ if (phy->link)
+ status |= MAC_PORTSET_LINKED;
+ if (phy->duplex == DUPLEX_FULL)
+ status |= MAC_PORTSET_DUPLEX_FULL;
+ if (phy->speed == SPEED_100)
+ status |= MAC_PORTSET_SPEED_100M;
+
+ writel(status, priv->port_base + MAC_PORTSET);
+}
+
+static int hisi_femac_port_reset(struct hisi_femac_priv *priv)
+{
+ u32 val;
+
+ val = readl(priv->glb_base + GLB_SOFT_RESET);
+ val |= SOFT_RESET_ALL;
+ writel(val, priv->glb_base + GLB_SOFT_RESET);
+
+ udelay(800);
+
+ val &= ~SOFT_RESET_ALL;
+ writel(val, priv->glb_base + GLB_SOFT_RESET);
+
+ return 0;
+}
+
+static int hisi_femac_set_hw_mac_addr(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *plat = dev_get_plat(dev);
+ unsigned char *mac = plat->enetaddr;
+ u32 reg;
+
+ reg = mac[1] | (mac[0] << 8);
+ writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
+
+ reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
+ writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
+
+ return 0;
+}
+
+static int hisi_femac_start(struct udevice *dev)
+{
+ int ret;
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+
+ hisi_femac_port_reset(priv);
+ hisi_femac_set_hw_mac_addr(dev);
+ hisi_femac_rx_refill(priv);
+
+ ret = phy_startup(priv->phy);
+ if (ret)
+ return log_msg_ret("Failed to startup phy", ret);
+
+ if (!priv->phy->link) {
+ debug("%s: link down\n", __func__);
+ return -ENODEV;
+ }
+
+ hisi_femac_adjust_link(dev);
+
+ writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
+ hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK);
+
+ return 0;
+}
+
+static int hisi_femac_send(struct udevice *dev, void *packet, int length)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ ulong addr = (ulong)packet;
+ int ret;
+
+ // clear previous irq
+ writel(IRQ_INT_TX_PER_PACKET, priv->glb_base + GLB_IRQ_RAW);
+
+ // flush cache
+ flush_cache(addr, length + ETH_FCS_LEN);
+
+ // write packet address
+ writel(addr, priv->port_base + EQ_ADDR);
+
+ // write packet length (and send it)
+ writel(length + ETH_FCS_LEN, priv->port_base + EQFRM_LEN);
+
+ // wait until FIFO is empty
+ ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, IRQ_INT_TX_PER_PACKET, true, 50, false);
+ if (ret == -ETIMEDOUT)
+ return log_msg_ret("FIFO timeout", ret);
+
+ return 0;
+}
+
+static int hisi_femac_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ int val, index, length;
+
+ val = readl(priv->glb_base + GLB_IRQ_RAW);
+ if (!(val & IRQ_INT_RX_RDY))
+ return -EAGAIN;
+
+ val = readl(priv->port_base + IQFRM_DES);
+ index = (val & RX_FRAME_IN_INDEX_MASK) >> 12;
+ length = val & RX_FRAME_LEN_MASK;
+
+ // invalidate cache
+ invalidate_dcache_range((ulong)net_rx_packets[index], (ulong)net_rx_packets[index] + length);
+ *packetp = net_rx_packets[index];
+
+ // Tell hardware we will process the packet
+ writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
+
+ return length;
+}
+
+static int hisi_femac_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ ulong addr = (ulong)packet;
+
+ // Tell hardware the packet can be reused
+ writel(addr, priv->port_base + IQ_ADDR);
+
+ return 0;
+}
+
+static void hisi_femac_stop(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+
+ // assert internal reset
+ writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET);
+}
+
+int hisi_femac_of_to_plat(struct udevice *dev)
+{
+ int ret, i;
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ static const char * const clk_strs[] = {
+ [CLK_MAC] = "mac",
+ [CLK_BUS] = "bus",
+ [CLK_PHY] = "phy",
+ };
+
+ priv->port_base = dev_remap_addr_name(dev, "port");
+ if (IS_ERR(priv->port_base))
+ return log_msg_ret("Failed to remap port address space", PTR_ERR(priv->port_base));
+
+ priv->glb_base = dev_remap_addr_name(dev, "glb");
+ if (IS_ERR(priv->glb_base))
+ return log_msg_ret("Failed to remap global address space", PTR_ERR(priv->glb_base));
+
+ for (i = 0; i < ARRAY_SIZE(clk_strs); i++) {
+ priv->clks[i] = devm_clk_get(dev, clk_strs[i]);
+ if (IS_ERR(priv->clks[i])) {
+ dev_err(dev, "Error getting clock %s\n", clk_strs[i]);
+ return log_msg_ret("Failed to get clocks", PTR_ERR(priv->clks[i]));
+ }
+ }
+
+ priv->mac_rst = devm_reset_control_get(dev, "mac");
+ if (IS_ERR(priv->mac_rst))
+ return log_msg_ret("Failed to get MAC reset", PTR_ERR(priv->mac_rst));
+
+ priv->phy_rst = devm_reset_control_get(dev, "phy");
+ if (IS_ERR(priv->phy_rst))
+ return log_msg_ret("Failed to get PHY reset", PTR_ERR(priv->phy_rst));
+
+ ret = dev_read_u32_array(dev,
+ PHY_RESET_DELAYS_PROPERTY,
+ priv->phy_reset_delays,
+ DELAYS_NUM);
+ if (ret < 0)
+ return log_msg_ret("Failed to get PHY reset delays", ret);
+
+ priv->mac_reset_delay = dev_read_u32_default(dev,
+ MAC_RESET_DELAY_PROPERTY,
+ MAC_RESET_ASSERT_PERIOD);
+
+ return 0;
+}
+
+static int hisi_femac_phy_reset(struct hisi_femac_priv *priv)
+{
+ struct reset_ctl *rst = priv->phy_rst;
+ u32 *delays = priv->phy_reset_delays;
+ int ret;
+
+ // Disable MAC clk before phy reset
+ ret = clk_disable(priv->clks[CLK_MAC]);
+ if (ret < 0)
+ return log_msg_ret("Failed to disable MAC clock", ret);
+ ret = clk_disable(priv->clks[CLK_BUS]);
+ if (ret < 0)
+ return log_msg_ret("Failed to disable bus clock", ret);
+
+ udelay(delays[PRE_DELAY]);
+
+ ret = reset_assert(rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to assert reset", ret);
+
+ udelay(delays[PULSE]);
+
+ ret = reset_deassert(rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to deassert reset", ret);
+
+ udelay(delays[POST_DELAY]);
+
+ ret = clk_enable(priv->clks[CLK_MAC]);
+ if (ret < 0)
+ return log_msg_ret("Failed to enable MAC clock", ret);
+ ret = clk_enable(priv->clks[CLK_BUS]);
+ if (ret < 0)
+ return log_msg_ret("Failed to enable MAC bus clock", ret);
+
+ return 0;
+}
+
+int hisi_femac_probe(struct udevice *dev)
+{
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ int ret, i;
+
+ // Enable clocks
+ for (i = 0; i < CLK_NUM; i++) {
+ ret = clk_prepare_enable(priv->clks[i]);
+ if (ret < 0)
+ return log_msg_ret("Failed to enable clks", ret);
+ }
+
+ // Reset MAC
+ ret = reset_assert(priv->mac_rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to assert MAC reset", ret);
+
+ udelay(priv->mac_reset_delay);
+
+ ret = reset_deassert(priv->mac_rst);
+ if (ret < 0)
+ return log_msg_ret("Failed to deassert MAC reset", ret);
+
+ // Reset PHY
+ ret = hisi_femac_phy_reset(priv);
+ if (ret < 0)
+ return log_msg_ret("Failed to reset phy", ret);
+
+ // Connect to PHY
+ priv->phy = dm_eth_phy_connect(dev);
+ if (!priv->phy)
+ return log_msg_ret("Failed to connect to phy", -EINVAL);
+
+ hisi_femac_port_init(priv);
+ return 0;
+}
+
+static const struct eth_ops hisi_femac_ops = {
+ .start = hisi_femac_start,
+ .send = hisi_femac_send,
+ .recv = hisi_femac_recv,
+ .free_pkt = hisi_femac_free_pkt,
+ .stop = hisi_femac_stop,
+ .write_hwaddr = hisi_femac_set_hw_mac_addr,
+};
+
+static const struct udevice_id hisi_femac_ids[] = {
+ {.compatible = "hisilicon,hisi-femac-v1",},
+ {.compatible = "hisilicon,hisi-femac-v2",},
+ {.compatible = "hisilicon,hi3516cv300-femac",},
+ {.compatible = "hisilicon,hi3798mv200-femac",},
+ {},
+};
+
+U_BOOT_DRIVER(hisi_femac_driver) = {
+ .name = "eth_hisi_femac",
+ .id = UCLASS_ETH,
+ .of_match = of_match_ptr(hisi_femac_ids),
+ .of_to_plat = hisi_femac_of_to_plat,
+ .ops = &hisi_femac_ops,
+ .probe = hisi_femac_probe,
+ .plat_auto = sizeof(struct eth_pdata),
+ .priv_auto = sizeof(struct hisi_femac_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hisilicon Fast Ethernet MDIO Bus Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <miiphy.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#define MDIO_RWCTRL 0x00
+#define MDIO_RO_DATA 0x04
+#define MDIO_WRITE BIT(13)
+#define MDIO_RW_FINISH BIT(15)
+#define BIT_PHY_ADDR_OFFSET 8
+#define BIT_WR_DATA_OFFSET 16
+
+struct hisi_femac_mdio_data {
+ struct clk *clk;
+ void __iomem *membase;
+};
+
+static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
+{
+ u32 val;
+
+ return readl_poll_timeout(data->membase + MDIO_RWCTRL,
+ val, val & MDIO_RW_FINISH, 10000);
+}
+
+static int hisi_femac_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ writel((addr << BIT_PHY_ADDR_OFFSET) | reg,
+ data->membase + MDIO_RWCTRL);
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
+}
+
+static int hisi_femac_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = hisi_femac_mdio_wait_ready(data);
+ if (ret)
+ return ret;
+
+ writel(MDIO_WRITE | (val << BIT_WR_DATA_OFFSET) |
+ (addr << BIT_PHY_ADDR_OFFSET) | reg,
+ data->membase + MDIO_RWCTRL);
+
+ return hisi_femac_mdio_wait_ready(data);
+}
+
+static int hisi_femac_mdio_of_to_plat(struct udevice *dev)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ data->membase = dev_remap_addr(dev);
+ if (IS_ERR(data->membase)) {
+ ret = PTR_ERR(data->membase);
+ return log_msg_ret("Failed to remap base addr", ret);
+ }
+
+ // clk is optional
+ data->clk = devm_clk_get_optional(dev, NULL);
+
+ return 0;
+}
+
+static int hisi_femac_mdio_probe(struct udevice *dev)
+{
+ struct hisi_femac_mdio_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_prepare_enable(data->clk);
+ if (ret)
+ return log_msg_ret("Failed to enable clk", ret);
+
+ return 0;
+}
+
+static const struct mdio_ops hisi_femac_mdio_ops = {
+ .read = hisi_femac_mdio_read,
+ .write = hisi_femac_mdio_write,
+};
+
+static const struct udevice_id hisi_femac_mdio_dt_ids[] = {
+ { .compatible = "hisilicon,hisi-femac-mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(hisi_femac_mdio_driver) = {
+ .name = "hisi-femac-mdio",
+ .id = UCLASS_MDIO,
+ .of_match = hisi_femac_mdio_dt_ids,
+ .of_to_plat = hisi_femac_mdio_of_to_plat,
+ .probe = hisi_femac_mdio_probe,
+ .ops = &hisi_femac_mdio_ops,
+ .priv_auto = sizeof(struct hisi_femac_mdio_data),
+};
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/of_extra.h>
+#include <linux/bitfield.h>
#include <linux/delay.h>
#include <miiphy.h>
#include <net/dsa.h>
*/
#define SMI_BUSY BIT(15)
#define SMI_CMD_CLAUSE_22 BIT(12)
-#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
-#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
-#define SMI_CMD_ADDR_SHIFT 5
-#define SMI_CMD_ADDR_MASK 0x1f
-#define SMI_CMD_REG_SHIFT 0
-#define SMI_CMD_REG_MASK 0x1f
+#define SMI_CMD_OP_MASK GENMASK(11, 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE 0x1
+#define SMI_CMD_CLAUSE_22_OP_READ 0x2
+#define SMI_CMD_CLAUSE_45_OP_WRITE_ADDR 0x0
+#define SMI_CMD_CLAUSE_45_OP_WRITE 0x1
+#define SMI_CMD_CLAUSE_45_OP_READ 0x3
+
+#define SMI_CMD_ADDR_MASK GENMASK(9, 5)
+#define SMI_CMD_REG_MASK GENMASK(4, 0)
#define SMI_CMD_READ(addr, reg) \
- (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \
- (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
- (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
+ (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_READ)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, reg))
#define SMI_CMD_WRITE(addr, reg) \
- (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \
- (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
- (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
+ (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_WRITE)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, reg))
+#define SMI_CMD_SET_C45_ADDR(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE_ADDR)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
+#define SMI_CMD_READ_C45(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_READ)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
+#define SMI_CMD_WRITE_C45(phyad, devad) \
+ (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE)) | \
+ (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \
+ (FIELD_PREP(SMI_CMD_REG_MASK, devad))
/* ID register values for different switch models */
#define PORT_SWITCH_ID_6020 0x0200
static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int devad, int reg)
{
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ u16 smi_cmd;
int res;
+ if (devad >= 0) {
+ /*
+ * For C45 we need to write the register address into the
+ * PHY Data register first and then call the Write Address
+ * Register OP in the PHY command register.
+ */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA,
+ reg);
+
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_SET_C45_ADDR(phyad, devad));
+
+ /* Wait for busy bit to clear */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Set the actual C45 or C22 OP-s */
+ smi_cmd = SMI_CMD_READ_C45(phyad, devad);
+ } else
+ smi_cmd = SMI_CMD_READ(phyad, reg);
+
/* Issue command to read */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_CMD,
- SMI_CMD_READ(phyad, reg));
+ smi_cmd);
/* Wait for data to be read */
res = mv88e6xxx_phy_wait(dev);
int devad, int reg, u16 data)
{
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
+ u16 smi_cmd;
int res;
+ if (devad >= 0) {
+ /*
+ * For C45 we need to write the register address into the
+ * PHY Data register first and then call the Write Address
+ * Register OP in the PHY command register.
+ */
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_DATA,
+ reg);
+
+ res = mv88e6xxx_reg_write(dev, priv->global2,
+ GLOBAL2_REG_PHY_CMD,
+ SMI_CMD_SET_C45_ADDR(phyad, devad));
+
+ /* Wait for busy bit to clear */
+ res = mv88e6xxx_phy_wait(dev);
+ if (res < 0)
+ return res;
+
+ /* Set the actual C45 or C22 OP-s */
+ smi_cmd = SMI_CMD_WRITE_C45(phyad, devad);
+ } else
+ smi_cmd = SMI_CMD_WRITE(phyad, reg);
+
/* Set the data to write */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_DATA, data);
/* Issue the write command */
res = mv88e6xxx_reg_write(dev, priv->global2,
GLOBAL2_REG_PHY_CMD,
- SMI_CMD_WRITE(phyad, reg));
+ smi_cmd);
if (res < 0)
return res;
/* RGMIIDCTL bits */
#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4
-#define DP83869_CLK_DELAY_DEF 7
+#define DP83869_CLK_DELAY_STEP 250
+#define DP83869_CLK_DELAY_MIN 250
+#define DP83869_CLK_DELAY_MAX 4000
+#define DP83869_CLK_DELAY_DEFAULT 2000
/* CFG2 bits */
#define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040
return 0;
}
-static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
- 1750, 2000, 2250, 2500, 2750, 3000,
- 3250, 3500, 3750, 4000};
-
static int dp83869_set_strapped_mode(struct phy_device *phydev)
{
struct dp83869_private *dp83869 = phydev->priv;
static int dp83869_of_init(struct phy_device *phydev)
{
struct dp83869_private * const dp83869 = phydev->priv;
- const int delay_entries = ARRAY_SIZE(dp83869_internal_delay);
int ret;
ofnode node;
dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth",
DP83869_PHYCR_FIFO_DEPTH_4_B_NIB);
+ /* Internal clock delay values can be configured in steps of
+ * 250ps (0.25ns). The register field for clock delay is 4-bits wide,
+ * the values range from 0b0000 for 0.25ns to 0b1111 for 4ns.
+ */
+
/* RX delay *must* be specified if internal delay of RX is used. */
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
- dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps",
- DP83869_CLK_DELAY_DEF);
- if (dp83869->rx_int_delay > delay_entries) {
- dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF;
- pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n",
- dp83869_internal_delay[dp83869->rx_int_delay]);
+ dp83869->rx_int_delay = ofnode_read_u32_default(node,
+ "rx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT);
+ if (dp83869->rx_int_delay > DP83869_CLK_DELAY_MAX ||
+ dp83869->rx_int_delay < DP83869_CLK_DELAY_MIN ||
+ dp83869->rx_int_delay % DP83869_CLK_DELAY_STEP) {
+ dp83869->rx_int_delay = DP83869_CLK_DELAY_DEFAULT;
+ pr_warn("rx-internal-delay-ps not set/invalid, default"
+ " to %ups\n", DP83869_CLK_DELAY_DEFAULT);
}
- dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay];
+ dp83869->rx_int_delay =
+ (dp83869->rx_int_delay - DP83869_CLK_DELAY_STEP)
+ / DP83869_CLK_DELAY_STEP;
}
- /* TX delay *must* be specified if internal delay of RX is used. */
+ /* TX delay *must* be specified if internal delay of TX is used. */
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
- dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps",
- DP83869_CLK_DELAY_DEF);
- if (dp83869->tx_int_delay > delay_entries) {
- dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF;
- pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n",
- dp83869_internal_delay[dp83869->tx_int_delay]);
+ dp83869->tx_int_delay = ofnode_read_u32_default(node,
+ "tx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT);
+ if (dp83869->tx_int_delay > DP83869_CLK_DELAY_MAX ||
+ dp83869->tx_int_delay < DP83869_CLK_DELAY_MIN ||
+ dp83869->tx_int_delay % DP83869_CLK_DELAY_STEP) {
+ dp83869->tx_int_delay = DP83869_CLK_DELAY_DEFAULT;
+ pr_warn("tx-internal-delay-ps not set/invalid, default"
+ " to %ups\n", DP83869_CLK_DELAY_DEFAULT);
}
- dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay];
+ dp83869->tx_int_delay =
+ (dp83869->tx_int_delay - DP83869_CLK_DELAY_STEP)
+ / DP83869_CLK_DELAY_STEP;
}
return 0;
* based on source code of Shlomi Gridish
*/
-#include <common.h>
#include <malloc.h>
#include <linux/errno.h>
#include <asm/io.h>
{ .compatible = "st,stm32mp157-pinctrl" },
{ .compatible = "st,stm32mp157-z-pinctrl" },
{ .compatible = "st,stm32mp135-pinctrl" },
+ { .compatible = "st,stm32mp257-pinctrl" },
+ { .compatible = "st,stm32mp257-z-pinctrl" },
{ }
};
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
* based on source code of Shlomi Gridish
*/
-#include <common.h>
#include <malloc.h>
#include <command.h>
#include <asm/global_data.h>
#include <asm/armv8/mmu.h>
#include <asm/arch/cpu.h>
#endif
+#ifdef CONFIG_PPC
+#include <asm/ppc.h>
+#endif
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
config SCSI
- bool "Support SCSI controllers"
+ bool "Support SCSI controllers with driver model"
help
This enables support for SCSI (Small Computer System Interface),
a parallel interface widely used with storage peripherals such as
hard drives and optical drives. The SCSI standards define physical
interfaces as well as protocols for controlling devices and
- tranferring data.
-
-config DM_SCSI
- bool "Support SCSI controllers with driver model"
- help
- This option enables the SCSI (Small Computer System Interface) uclass
- which supports SCSI and SATA HDDs. For every device configuration
- (IDs/LUNs) a block device is created with RAW read/write and
- filesystem support.
-
-if SCSI && !DM_SCSI
-
-config SCSI_AHCI_PLAT
- bool "Platform-specific init of AHCI"
- help
- This enables a way for boards to set up an AHCI device manually, by
- called ahci_init() and providing an ahci_reset() mechanism.
-
- This is deprecated. An AHCI driver should be provided instead.
-
-config SYS_SCSI_MAX_SCSI_ID
- int "Maximum supported SCSI ID"
- default 1
- help
- Sets the maximum number of SCSI IDs to scan when looking for devices.
- IDs from 0 to (this value - 1) are scanned.
-
- This is deprecated and is not needed when BLK is enabled.
-
-config SYS_SCSI_MAX_LUN
- int "Maximum support SCSI LUN"
- default 1
- help
- Sets the maximum number of SCSI Logical Unit Numbers (LUNs) to scan on
- devices. LUNs from 0 to (this value - 1) are scanned.
-
- This is deprecated and is not needed when CONFIG_DM_SCSI is enabled.
-
-endif
+ tranferring data. For every device configuration (IDs/LUNs) a block
+ device is created with RAW read/write and filesystem support.
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
-obj-$(CONFIG_SCSI) += scsi.o
-
+obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o
ifdef CONFIG_SCSI
-ifdef CONFIG_DM_SCSI
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += scsi_bootdev.o
+obj-$(CONFIG_SANDBOX) += sandbox_scsi.o
+obj-$(CONFIG_SANDBOX) += scsi_emul.o
endif
endif
-endif
-
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_SATA
-obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
-obj-$(CONFIG_SCSI) += scsi.o
+obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o
endif
endif
-
-ifdef CONFIG_SCSI
-obj-$(CONFIG_SANDBOX) += sandbox_scsi.o
-obj-$(CONFIG_SANDBOX) += scsi_emul.o
-endif
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
-#if !defined(CONFIG_DM_SCSI)
-# ifdef CFG_SCSI_DEV_LIST
-# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST
-# else
-# ifdef CONFIG_SATA_ULI5288
-
-# define SCSI_VEND_ID 0x10b9
-# define SCSI_DEV_ID 0x5288
-
-# elif !defined(CONFIG_SCSI_AHCI_PLAT)
-# error no scsi device defined
-# endif
-# define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-# endif
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \
- !defined(CONFIG_DM_SCSI)
-const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
-#endif
static struct scsi_cmd tempccb; /* temporary scsi command buffer */
DEFINE_CACHE_ALIGN_BUFFER(u8, tempbuff, 512); /* temporary data buffer */
-#if !defined(CONFIG_DM_SCSI)
-static int scsi_max_devs; /* number of highest available scsi device */
-
-static int scsi_curr_dev; /* current device */
-
-static struct blk_desc scsi_dev_desc[SCSI_MAX_DEVICE];
-#endif
-
/* almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_BLK 0xFFFF
#define SCSI_LBA48_READ 0xFFFFFFF
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
}
-#ifdef CONFIG_BLK
static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start,
unsigned short blocks)
{
return 1;
}
#endif /* CONFIG_BOUNCE_BUFFER */
-#endif
-
-#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \
- !defined(CONFIG_DM_SCSI)
-void scsi_init(void)
-{
- int busdevfunc = -1;
- int i;
- /*
- * Find a device from the list, this driver will support a single
- * controller.
- */
- for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
- /* get PCI Device ID */
- struct udevice *dev;
- int ret;
-
- ret = dm_pci_find_device(scsi_device_list[i].vendor,
- scsi_device_list[i].device, 0, &dev);
- if (!ret) {
- busdevfunc = dm_pci_get_bdf(dev);
- break;
- }
- if (busdevfunc != -1)
- break;
- }
-
- if (busdevfunc == -1) {
- printf("Error: SCSI Controller(s) ");
- for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
- printf("%04X:%04X ",
- scsi_device_list[i].vendor,
- scsi_device_list[i].device);
- }
- printf("not found\n");
- return;
- }
-#ifdef DEBUG
- else {
- printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n",
- scsi_device_list[i].vendor,
- scsi_device_list[i].device,
- (busdevfunc >> 16) & 0xFF,
- (busdevfunc >> 11) & 0x1F,
- (busdevfunc >> 8) & 0x7);
- }
-#endif
- bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
- scsi_low_level_init(busdevfunc);
- scsi_scan(true);
- bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
-}
-#endif
/* copy src to dest, skipping leading and trailing blanks
* and null terminate the string
#endif /* CONFIG_BOUNCE_BUFFER */
}
-#if !defined(CONFIG_DM_SCSI)
-/**
- * scsi_init_dev_desc - initialize all SCSI specific blk_desc properties
- *
- * @dev_desc: Block device description pointer
- * @devnum: Device number
- */
-static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum)
-{
- dev_desc->lba = 0;
- dev_desc->blksz = 0;
- dev_desc->uclass_id = UCLASS_SCSI;
- dev_desc->devnum = devnum;
- dev_desc->part_type = PART_TYPE_UNKNOWN;
-
- scsi_init_dev_desc_priv(dev_desc);
-}
-#endif
-
/**
* scsi_detect_dev - Detect scsi device
*
* (re)-scan the scsi bus and reports scsi device info
* to the user if mode = 1
*/
-#if defined(CONFIG_DM_SCSI)
static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose)
{
int ret;
return 0;
}
-#else
-int scsi_scan(bool verbose)
-{
- unsigned char i, lun;
- int ret;
-
- if (verbose)
- printf("scanning bus for devices...\n");
- for (i = 0; i < SCSI_MAX_DEVICE; i++)
- scsi_init_dev_desc(&scsi_dev_desc[i], i);
-
- scsi_max_devs = 0;
- for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
- for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
- struct blk_desc *bdesc = &scsi_dev_desc[scsi_max_devs];
-
- ret = scsi_detect_dev(NULL, i, lun, bdesc);
- if (ret)
- continue;
- part_init(bdesc);
-
- if (verbose) {
- printf(" Device %d: ", bdesc->devnum);
- dev_print(bdesc);
- }
- scsi_max_devs++;
- } /* next LUN */
- }
- if (scsi_max_devs > 0)
- scsi_curr_dev = 0;
- else
- scsi_curr_dev = -1;
-
- printf("Found %d device(s).\n", scsi_max_devs);
-#ifndef CONFIG_SPL_BUILD
- env_set_ulong("scsidevs", scsi_max_devs);
-#endif
- return 0;
-}
-#endif
-#ifdef CONFIG_BLK
static const struct blk_ops scsi_blk_ops = {
.read = scsi_read,
.write = scsi_write,
.id = UCLASS_BLK,
.ops = &scsi_blk_ops,
};
-#else
-U_BOOT_LEGACY_BLK(scsi) = {
- .uclass_idname = "scsi",
- .uclass_id = UCLASS_SCSI,
- .max_devs = SCSI_MAX_DEVICE,
- .desc = scsi_dev_desc,
-};
-#endif
*/
#define ONE_BYTE_B115200_US 87
-static void _stm32_serial_setbrg(fdt_addr_t base,
+static void _stm32_serial_setbrg(void __iomem *base,
struct stm32_uart_info *uart_info,
u32 clock_rate,
int baudrate)
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
- u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
+ void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4);
u32 config = 0;
uint parity = SERIAL_GET_PARITY(serial_config);
uint bits = SERIAL_GET_BITS(serial_config);
{
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ void __iomem *base = plat->base;
u32 isr = readl(base + ISR_OFFSET(stm32f4));
if ((isr & USART_ISR_RXNE) == 0)
return readl(base + RDR_OFFSET(stm32f4));
}
-static int _stm32_serial_putc(fdt_addr_t base,
+static int _stm32_serial_putc(void __iomem *base,
struct stm32_uart_info *uart_info,
const char c)
{
{
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ void __iomem *base = plat->base;
if (input)
return readl(base + ISR_OFFSET(stm32f4)) &
USART_ISR_TXE ? 0 : 1;
}
-static void _stm32_serial_init(fdt_addr_t base,
+static void _stm32_serial_init(void __iomem *base,
struct stm32_uart_info *uart_info)
{
bool stm32f4 = uart_info->stm32f4;
static int stm32_serial_of_to_plat(struct udevice *dev)
{
struct stm32x7_serial_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
- plat->base = dev_read_addr(dev);
- if (plat->base == FDT_ADDR_T_NONE)
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
+ plat->base = (void __iomem *)addr;
+
return 0;
}
static inline void _debug_uart_init(void)
{
- fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
struct stm32_uart_info *uart_info = _debug_uart_info();
_stm32_serial_init(base, uart_info);
static inline void _debug_uart_putc(int c)
{
- fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
+ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
struct stm32_uart_info *uart_info = _debug_uart_info();
while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
/* Information about a serial port */
struct stm32x7_serial_plat {
- fdt_addr_t base; /* address of registers in physical memory */
+ void __iomem *base; /* address of registers in physical memory */
struct stm32_uart_info *uart_info;
unsigned long int clock_rate;
};
.id = UCLASS_SM,
.of_match = meson_sm_ids,
.probe = meson_sm_probe,
+ .bind = dm_scan_fdt_dev,
.priv_auto = sizeof(struct meson_sm_priv),
.ops = &sm_ops,
};
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <spi.h>
config UFS
bool "Support UFS controllers"
- depends on DM_SCSI
+ depends on SCSI
select CHARSET
help
This selects support for Universal Flash Subsystem (UFS).
config CONSOLE_TRUETYPE
bool "Support a console that uses TrueType fonts"
- select CMD_SELECT_FONT
help
TrueTrype fonts can provide outline-drawing capability rather than
needing to provide a bitmap for each font and size that is needed.
config VIRTIO_NET
bool "virtio net driver"
- depends on VIRTIO
+ depends on VIRTIO && NETDEVICES
help
This is the virtual net driver for virtio. It can be used with
QEMU based targets.
};
/*
- * This env_set() function is defined in cmd/nvedit.c, since it calls
- * _do_env_set(), whis is a static function in that file.
- *
- * int env_set(const char *varname, const char *varvalue);
+ * This variable is incremented each time we set an environment variable so we
+ * can be check via env_get_id() to see if the environment has changed or not.
+ * This makes it possible to reread an environment variable only if the
+ * environment was changed, typically used by networking code.
*/
+static int env_id = 1;
+
+int env_get_id(void)
+{
+ return env_id;
+}
+
+void env_inc_id(void)
+{
+ env_id++;
+}
+
+int env_do_env_set(int flag, int argc, char *const argv[], int env_flag)
+{
+ int i, len;
+ char *name, *value, *s;
+ struct env_entry e, *ep;
+
+ debug("Initial value for argc=%d\n", argc);
+
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_CMD_NVEDIT_EFI)
+ if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e')
+ return do_env_set_efi(NULL, flag, --argc, ++argv);
+#endif
+
+ while (argc > 1 && **(argv + 1) == '-') {
+ char *arg = *++argv;
+
+ --argc;
+ while (*++arg) {
+ switch (*arg) {
+ case 'f': /* force */
+ env_flag |= H_FORCE;
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+ }
+ }
+ debug("Final value for argc=%d\n", argc);
+ name = argv[1];
+
+ if (strchr(name, '=')) {
+ printf("## Error: illegal character '='"
+ "in variable name \"%s\"\n", name);
+ return 1;
+ }
+
+ env_inc_id();
+
+ /* Delete only ? */
+ if (argc < 3 || argv[2] == NULL) {
+ int rc = hdelete_r(name, &env_htab, env_flag);
+
+ /* If the variable didn't exist, don't report an error */
+ return rc && rc != -ENOENT ? 1 : 0;
+ }
+
+ /*
+ * Insert / replace new value
+ */
+ for (i = 2, len = 0; i < argc; ++i)
+ len += strlen(argv[i]) + 1;
+
+ value = malloc(len);
+ if (value == NULL) {
+ printf("## Can't malloc %d bytes\n", len);
+ return 1;
+ }
+ for (i = 2, s = value; i < argc; ++i) {
+ char *v = argv[i];
+
+ while ((*s++ = *v++) != '\0')
+ ;
+ *(s - 1) = ' ';
+ }
+ if (s != value)
+ *--s = '\0';
+
+ e.key = name;
+ e.data = value;
+ hsearch_r(e, ENV_ENTER, &ep, &env_htab, env_flag);
+ free(value);
+ if (!ep) {
+ printf("## Error inserting \"%s\" variable, errno=%d\n",
+ name, errno);
+ return 1;
+ }
+
+ return 0;
+}
+
+int env_set(const char *varname, const char *varvalue)
+{
+ const char * const argv[4] = { "setenv", varname, varvalue, NULL };
+
+ /* before import into hashtable */
+ if (!(gd->flags & GD_FLG_ENV_READY))
+ return 1;
+
+ if (varvalue == NULL || varvalue[0] == '\0')
+ return env_do_env_set(0, 2, (char * const *)argv, H_PROGRAMMATIC);
+ else
+ return env_do_env_set(0, 3, (char * const *)argv, H_PROGRAMMATIC);
+}
/**
* Set an environment variable to an integer value
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-#ifndef _MCD_API_H
-#define _MCD_API_H
-
-/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
-#undef MCD_INCLUDE_EU
-
-/* Number of DMA channels */
-#define NCHANNELS 16
-
-/* Total number of variants */
-#ifdef MCD_INCLUDE_EU
-#define NUMOFVARIANTS 6
-#else
-#define NUMOFVARIANTS 4
-#endif
-
-/* Define sizes of the various tables */
-#define TASK_TABLE_SIZE (NCHANNELS*32)
-#define VAR_TAB_SIZE (128)
-#define CONTEXT_SAVE_SIZE (128)
-#define FUNCDESC_TAB_SIZE (256)
-
-#ifdef MCD_INCLUDE_EU
-#define FUNCDESC_TAB_NUM 16
-#else
-#define FUNCDESC_TAB_NUM 1
-#endif
-
-#ifndef DEFINESONLY
-
-/* Portability typedefs */
-#if 1
-#include "common.h"
-#else
-#ifndef s32
-typedef int s32;
-#endif
-#ifndef u32
-typedef unsigned int u32;
-#endif
-#ifndef s16
-typedef short s16;
-#endif
-#ifndef u16
-typedef unsigned short u16;
-#endif
-#ifndef s8
-typedef char s8;
-#endif
-#ifndef u8
-typedef unsigned char u8;
-#endif
-#endif
-
-/*
- * These structures represent the internal registers of the
- * multi-channel DMA
- */
-struct dmaRegs_s {
- u32 taskbar; /* task table base address */
- u32 currPtr;
- u32 endPtr;
- u32 varTablePtr;
- u16 dma_rsvd0;
- u16 ptdControl; /* ptd control */
- u32 intPending; /* interrupt pending */
- u32 intMask; /* interrupt mask */
- u16 taskControl[16]; /* task control */
- u8 priority[32]; /* priority */
- u32 initiatorMux; /* initiator mux control */
- u32 taskSize0; /* task size control 0. */
- u32 taskSize1; /* task size control 1. */
- u32 dma_rsvd1; /* reserved */
- u32 dma_rsvd2; /* reserved */
- u32 debugComp1; /* debug comparator 1 */
- u32 debugComp2; /* debug comparator 2 */
- u32 debugControl; /* debug control */
- u32 debugStatus; /* debug status */
- u32 ptdDebug; /* priority task decode debug */
- u32 dma_rsvd3[31]; /* reserved */
-};
-typedef volatile struct dmaRegs_s dmaRegs;
-
-#endif
-
-/* PTD contrl reg bits */
-#define PTD_CTL_TSK_PRI 0x8000
-#define PTD_CTL_COMM_PREFETCH 0x0001
-
-/* Task Control reg bits and field masks */
-#define TASK_CTL_EN 0x8000
-#define TASK_CTL_VALID 0x4000
-#define TASK_CTL_ALWAYS 0x2000
-#define TASK_CTL_INIT_MASK 0x1f00
-#define TASK_CTL_ASTRT 0x0080
-#define TASK_CTL_HIPRITSKEN 0x0040
-#define TASK_CTL_HLDINITNUM 0x0020
-#define TASK_CTL_ASTSKNUM_MASK 0x000f
-
-/* Priority reg bits and field masks */
-#define PRIORITY_HLD 0x80
-#define PRIORITY_PRI_MASK 0x07
-
-/* Debug Control reg bits and field masks */
-#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
-#define DBG_CTL_AUTO_ARM 0x00008000
-#define DBG_CTL_BREAK 0x00004000
-#define DBG_CTL_COMP1_TYP_MASK 0x00003800
-#define DBG_CTL_COMP2_TYP_MASK 0x00000070
-#define DBG_CTL_EXT_BREAK 0x00000004
-#define DBG_CTL_INT_BREAK 0x00000002
-
-/*
- * PTD Debug reg selector addresses
- * This reg must be written with a value to show the contents of
- * one of the desired internal register.
- */
-#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
-#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
- have initiators asserted */
-
-/* General return values */
-#define MCD_OK 0
-#define MCD_ERROR -1
-#define MCD_TABLE_UNALIGNED -2
-#define MCD_CHANNEL_INVALID -3
-
-/* MCD_initDma input flags */
-#define MCD_RELOC_TASKS 0x00000001
-#define MCD_NO_RELOC_TASKS 0x00000000
-#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
-
-/*
- * MCD_dmaStatus Status Values for each channel:
- * MCD_NO_DMA - No DMA has been requested since reset
- * MCD_IDLE - DMA active, but the initiator is currently inactive
- * MCD_RUNNING - DMA active, and the initiator is currently active
- * MCD_PAUSED - DMA active but it is currently paused
- * MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
- * MCD_DONE - the most recent DMA has completed
- */
-#define MCD_NO_DMA 1
-#define MCD_IDLE 2
-#define MCD_RUNNING 3
-#define MCD_PAUSED 4
-#define MCD_HALTED 5
-#define MCD_DONE 6
-
-/* MCD_startDma parameter defines */
-
-/* Constants for the funcDesc parameter */
-/*
- * MCD_NO_BYTE_SWAP - to disable byte swapping
- * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
- * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
- * value being DMAed
- * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
- * each 32-bit data value DMAed
- * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
- * MCD_BIT_REV - reverse the bits of each byte DMAed
- * MCD_CRC16 - to perform CRC-16 on DMAed data
- * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
- * MCD_CRC32 - to perform CRC-32 on DMAed data
- * MCD_CSUMINET - to perform internet checksums on DMAed data
- * MCD_NO_CSUM - to perform no checksumming
- */
-#define MCD_NO_BYTE_SWAP 0x00045670
-#define MCD_BYTE_REVERSE 0x00076540
-#define MCD_U16_REVERSE 0x00067450
-#define MCD_U16_BYTE_REVERSE 0x00054760
-#define MCD_NO_BIT_REV 0x00000000
-#define MCD_BIT_REV 0x00088880
-/* CRCing: */
-#define MCD_CRC16 0xc0100000
-#define MCD_CRCCCITT 0xc0200000
-#define MCD_CRC32 0xc0300000
-#define MCD_CSUMINET 0xc0400000
-#define MCD_NO_CSUM 0xa0000000
-
-#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
- MCD_NO_CSUM)
-#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
-
-/* Constants for the flags parameter */
-#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
-#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
-#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
-#define MCD_TT_FLAGS_MASK 0x000000ff
-#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
-
-#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
-#define MCD_CHAIN_DMA /* TBD */
-#define MCD_EU_DMA /* TBD */
-#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
-#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
-
-/* these flags are valid for MCD_startDma and the chained buffer descriptors */
-/*
- * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
- * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
- * MCD_INTERRUPT - to generate an interrupt after completion of the DMA
- * MCD_END_FRAME - tell the DMA to end the frame when transferring
- * last byte of data in buffer
- * MCD_CRC_RESTART - to empty out the accumulated checksum prior to
- * performing the DMA
- */
-#define MCD_BUF_READY 0x80000000
-#define MCD_WRAP 0x20000000
-#define MCD_INTERRUPT 0x10000000
-#define MCD_END_FRAME 0x08000000
-#define MCD_CRC_RESTART 0x40000000
-
-/* Defines for the FEC buffer descriptor control/status word*/
-#define MCD_FEC_BUF_READY 0x8000
-#define MCD_FEC_WRAP 0x2000
-#define MCD_FEC_INTERRUPT 0x1000
-#define MCD_FEC_END_FRAME 0x0800
-
-/* Defines for general intuitiveness */
-
-#define MCD_TRUE 1
-#define MCD_FALSE 0
-
-/* Three different cases for destination and source. */
-#define MINUS1 -1
-#define ZERO 0
-#define PLUS1 1
-
-#ifndef DEFINESONLY
-
-/* Task Table Entry struct*/
-typedef struct {
- u32 TDTstart; /* task descriptor table start */
- u32 TDTend; /* task descriptor table end */
- u32 varTab; /* variable table start */
- u32 FDTandFlags; /* function descriptor table start & flags */
- volatile u32 descAddrAndStatus;
- volatile u32 modifiedVarTab;
- u32 contextSaveSpace; /* context save space start */
- u32 literalBases;
-} TaskTableEntry;
-
-/* Chained buffer descriptor:
- * flags - flags describing the DMA
- * csumResult - checksum performed since last checksum reset
- * srcAddr - the address to move data from
- * destAddr - the address to move data to
- * lastDestAddr - the last address written to
- * dmaSize - the no of bytes to xfer independent of the xfer sz
- * next - next buffer descriptor in chain
- * info - private info about this descriptor; DMA does not affect it
- */
-typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
-struct MCD_bufDesc_struct {
- u32 flags;
- u32 csumResult;
- s8 *srcAddr;
- s8 *destAddr;
- s8 *lastDestAddr;
- u32 dmaSize;
- MCD_bufDesc *next;
- u32 info;
-};
-
-/* Progress Query struct:
- * lastSrcAddr - the most-recent or last, post-increment source address
- * lastDestAddr - the most-recent or last, post-increment destination address
- * dmaSize - the amount of data transferred for the current buffer
- * currBufDesc - pointer to the current buffer descriptor being DMAed
- */
-
-typedef volatile struct MCD_XferProg_struct {
- s8 *lastSrcAddr;
- s8 *lastDestAddr;
- u32 dmaSize;
- MCD_bufDesc *currBufDesc;
-} MCD_XferProg;
-
-/* FEC buffer descriptor */
-typedef volatile struct MCD_bufDescFec_struct {
- u16 statCtrl;
- u16 length;
- u32 dataPointer;
-} MCD_bufDescFec;
-
-/*************************************************************************/
-/* API function Prototypes - see MCD_dmaApi.c for further notes */
-
-/* MCD_startDma starts a particular kind of DMA:
- * srcAddr - the channel on which to run the DMA
- * srcIncr - the address to move data from, or buffer-descriptor address
- * destAddr - the amount to increment the source address per transfer
- * destIncr - the address to move data to
- * dmaSize - the amount to increment the destination address per transfer
- * xferSize - the number bytes in of each data movement (1, 2, or 4)
- * initiator - what device initiates the DMA
- * priority - priority of the DMA
- * flags - flags describing the DMA
- * funcDesc - description of byte swapping, bit swapping, and CRC actions
- */
-int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
- s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
- int priority, u32 flags, u32 funcDesc);
-
-/*
- * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
- * registers, relocating and creating the appropriate task structures, and
- * setting up some global settings
- */
-int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
-
-/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
-int MCD_dmaStatus(int channel);
-
-/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
-int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
-
-/*
- * MCD_killDma() halts the DMA on the requested channel, without any
- * intention of resuming the DMA.
- */
-int MCD_killDma(int channel);
-
-/*
- * MCD_continDma() continues a DMA which as stopped due to encountering an
- * unready buffer descriptor.
- */
-int MCD_continDma(int channel);
-
-/*
- * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
- * running on that channel).
- */
-int MCD_pauseDma(int channel);
-
-/*
- * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
- * running on that channel).
- */
-int MCD_resumeDma(int channel);
-
-/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
-int MCD_csumQuery(int channel, u32 * csum);
-
-/*
- * MCD_getCodeSize provides the packed size required by the microcoded task
- * and structures.
- */
-int MCD_getCodeSize(void);
-
-/*
- * MCD_getVersion provides a pointer to a version string and returns a
- * version number.
- */
-int MCD_getVersion(char **longVersion);
-
-/* macro for setting a location in the variable table */
-#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
-/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
- so I'm avoiding surrounding it with "do {} while(0)" */
-
-#endif /* DEFINESONLY */
-
-#endif /* _MCD_API_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
- /* This file is autogenerated. Do not change */
-#define CURRBD 4
-#define DCOUNT 6
-#define DESTPTR 5
-#define SRCPTR 7
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- */
-
-#ifndef MCD_TSK_INIT_H
-#define MCD_TSK_INIT_H 1
-
-/*
- * Do not edit!
- */
-
-/* Task 0 */
-void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 1 */
-void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 2 */
-void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
- int xferSize, short xferSizeIncr, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 3 */
-void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
- short destIncr, int dmaSize, short xferSizeIncr,
- int flags, int *currBD, int *cSave,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 4 */
-void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
- volatile TaskTableEntry * taskTable, int channel);
-
-/* Task 5 */
-void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
- volatile TaskTableEntry * taskTable, int channel);
-
-#endif /* MCD_TSK_INIT_H */
*/
int sata_scan(struct udevice *dev);
-int ahci_init(void __iomem *base);
-int ahci_reset(void __iomem *base);
-
/**
* ahci_init_one_dm() - set up a single AHCI port
*
#ifndef _BOOTCOUNT_H__
#define _BOOTCOUNT_H__
-#include <common.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/byteorder.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Linus Walleij <linusw@kernel.org>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6328.h>
+
#define BOOT_TARGET_DEVICES(func) \
func(ROMUSB, romusb, na) \
+ func(USB_DFU, usbdfu, na) \
func(MMC, mmc, 0) \
BOOT_TARGET_DEVICES_USB(func) \
func(PXE, pxe, na) \
* MMC
*/
-/* SATA */
-#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
-#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440
-#endif
-#define CFG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \
- PCI_DEVICE_ID_FREESCALE_AHCI}
-
/* SPI */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
CSOR_NOR_TRHZ_80)
#endif
-/* SATA */
-#define SCSI_VEND_ID 0x1b4b
-#define SCSI_DEV_ID 0x9170
-#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-
/* Initial environment variables */
#ifndef SPL_NO_ENV
#undef CFG_EXTRA_ENV_SETTINGS
#endif
#endif
-/* SATA */
-#ifndef SPL_NO_SATA
-#define SCSI_VEND_ID 0x1b4b
-#define SCSI_DEV_ID 0x9170
-#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
#include <asm/fsl_secure_boot.h>
#endif /* __LS1043ARDB_H__ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP25x CPU
+ */
+
+#ifndef __CONFIG_STM32MP25_COMMMON_H
+#define __CONFIG_STM32MP25_COMMMON_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE
+
+/*
+ * For booting Linux, use the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_SYS_BOOTMAPSZ SZ_256M
+
+#endif /* __CONFIG_STM32MP25_COMMMON_H */
#ifndef __DFU_ENTITY_H_
#define __DFU_ENTITY_H_
-#include <common.h>
#include <linux/list.h>
#include <mmc.h>
#include <spi_flash.h>
#ifndef __DISPLAY_OPTIONS_H
#define __DISPLAY_OPTIONS_H
+#include <linux/types.h>
+
/**
* print_size() - Print a size with a suffix
*
* @size: Size to print
* @suffix String to print after the size
*/
-#include <display_options.h>
void print_size(uint64_t size, const char *suffix);
/**
#define STM32MP_PKG_AB 0x2
#define STM32MP_PKG_AC 0x4
#define STM32MP_PKG_AD 0x8
+#define STM32MP_PKG_AI 0x100
+#define STM32MP_PKG_AK 0x400
+#define STM32MP_PKG_AL 0x800
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
#ifndef _EFI_LOADER_H
#define _EFI_LOADER_H 1
-#include <common.h>
#include <blk.h>
#include <event.h>
#include <log.h>
#ifndef _EFI_SELFTEST_H
#define _EFI_SELFTEST_H
-#include <common.h>
#include <efi.h>
#include <efi_api.h>
#include <efi_loader.h>
*/
int env_get_id(void);
+/**
+ * env_inc_id() - Increase the sequence number for the environment
+ *
+ * Increment the value that is used by env_get_id() to inform callers
+ * if the environment has changed since they last checked.
+ */
+void env_inc_id(void);
+
/**
* env_init() - Set up the pre-relocation environment
*
extern struct hsearch_data env_htab;
+/**
+ * env_do_env_set() - Perform the actual setting of an environment variable
+ *
+ * Due to the number of places we may need to set an environmental variable
+ * from we have an exposed internal function that performs the real work and
+ * then call this from both the command line function as well as other
+ * locations.
+ *
+ * Return: 0 on success or 1 on failure
+ */
+int env_do_env_set(int flag, int argc, char *const argv[], int env_flag);
+
/**
* env_ext4_get_intf() - Provide the interface for env in EXT4
*
#ifndef __FM_ETH_H__
#define __FM_ETH_H__
-#include <common.h>
#include <phy.h>
#include <asm/types.h>
#ifndef _FS_H
#define _FS_H
-#include <common.h>
#include <rtc.h>
struct cmd_tbl;
#ifndef __FSL_MC_H__
#define __FSL_MC_H__
-#include <common.h>
#include <linux/bitops.h>
+struct bd_info;
+
#define MC_CCSR_BASE_ADDR \
((struct mc_ccsr_registers __iomem *)0x8340000)
#ifndef _FSL_ERRATA_H
#define _FSL_ERRATA_H
-#include <common.h>
#if defined(CONFIG_PPC)
#include <asm/processor.h>
#elif defined(CONFIG_ARCH_LS1021A)
#ifdef CONFIG_FSL_IFC
#include <config.h>
-#include <common.h>
#include <part.h>
#ifdef CONFIG_ARM
#include <asm/arch/soc.h>
#ifndef __QE_H__
#define __QE_H__
-#include "common.h"
#ifdef CONFIG_U_QE
#include <linux/immap_qe.h>
#endif
#ifndef __FSL_SEC_H
#define __FSL_SEC_H
-#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_FSL_SEC_LE
#ifndef __FSL_SEC_MON_H
#define __FSL_SEC_MON_H
-#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_SYS_FSL_SEC_MON_LE
#ifndef _FSL_SFP_SNVS_
#define _FSL_SFP_SNVS_
-#include <common.h>
#include <config.h>
#include <asm/io.h>
#ifndef __IOTRACE_H
#define __IOTRACE_H
-//#include <common.h>
#include <linux/types.h>
/* Support up to the machine word length for now */
#ifdef CONFIG_UNIT_TEST
TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
struct k210_pll_config *best);
-#ifndef nop
-#define nop()
-#endif
#endif
#endif /* K210_PLL_H */
#ifndef _KEY_MATRIX_H
#define _KEY_MATRIX_H
-#include <common.h>
/* Information about a matrix keyboard */
struct key_matrix {
#ifndef __LIBATA_H__
#define __LIBATA_H__
-#include <common.h>
enum {
/* various global constants */
#ifndef __LINUX_MII_H__
#define __LINUX_MII_H__
+#include <linux/types.h>
+
/* Generic MII registers. */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
#else
-#include <common.h>
#include <spi.h>
#include <spi-mem.h>
#include <linux/mtd/nand.h>
* the composite model the host can use both functions at the same time.
*/
-#include <common.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/bitmap.h>
#ifndef _miiphy_h_
#define _miiphy_h_
-#include <common.h>
#include <linux/mii.h>
#include <linux/list.h>
#include <net.h>
#ifndef __MPC83XX_H__
#define __MPC83XX_H__
-#include <config.h>
-#include <asm/fsl_lbc.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif
#ifndef __MV886352_H
#define __MV886352_H
-#include <common.h>
/* PHY registers */
#define PHY(itf) (itf)
#include <asm/cache.h>
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
#include <env.h>
+#include <hexdump.h>
#include <log.h>
#include <time.h>
#include <linux/if_ether.h>
#define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */
#define DEBUG_NET_PKT 0 /* Packets on info on the network at large */
#define DEBUG_INT_STATE 0 /* Internal network state changes */
+#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */
/*
* The number of receive packet buffers, and the required packet buffer
/* Transmit a packet */
static inline void net_send_packet(uchar *pkt, int len)
{
+ if (DEBUG_NET_PKT_TRACE)
+ print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len);
/* Currently no way to return errors from eth_send() */
(void) eth_send(pkt, len);
}
* Copyright (C) 2019, IBM Corporation.
*/
-#include <common.h>
#include <phy.h>
bool ncsi_active(void);
#ifndef PALMAS_H
#define PALMAS_H
-#include <common.h>
#include <i2c.h>
/* I2C chip addresses, TW6035/37 */
#define _POST_H
#ifndef __ASSEMBLY__
-#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_POST)
#define __SATA_H__
#include <part.h>
-#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI)
-int init_sata(int dev);
-int reset_sata(int dev);
-int scan_sata(int dev);
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
-
-int sata_initialize(void);
-int __sata_initialize(void);
-int sata_stop(void);
-int __sata_stop(void);
-int sata_port_status(int dev, int port);
-
-extern struct blk_desc sata_dev_desc[];
-#endif
-
int sata_probe(int devnum);
int sata_remove(int devnum);
#include <bouncebuf.h>
#include <linux/dma-direction.h>
-/* Fix this to the maximum */
-#define SCSI_MAX_DEVICE \
- (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-
struct udevice;
/**
*/
int scsi_scan_dev(struct udevice *dev, bool verbose);
-#ifndef CONFIG_DM_SCSI
-void scsi_low_level_init(int busdevfunc);
-void scsi_init(void);
-#endif
-
#define SCSI_IDENTIFY 0xC0 /* not used */
/* Hardware errors */
#ifndef _SPI_H_
#define _SPI_H_
-#include <common.h>
#include <linux/bitops.h>
/* SPI mode flags */
#ifndef __include_tegra_kbc_h__
#define __include_tegra_kbc_h__
-#include <common.h>
#define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER)
#ifndef TWL4030_H
#define TWL4030_H
-#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
#ifndef TWL6030_H
#define TWL6030_H
-#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
#ifndef __UBOOT_UBI_H
#define __UBOOT_UBI_H
-#include <common.h>
#include <compiler.h>
#include <linux/compat.h>
#include <malloc.h>
#ifndef __USBDCORE_H__
#define __USBDCORE_H__
-#include <common.h>
#include "usbdescriptors.h"
config LIB_UUID
bool
+config RANDOM_UUID
+ bool "GPT Random UUID generation"
+ select LIB_UUID
+ help
+ Enable the generation of partitions with random UUIDs if none
+ are provided.
+
config SPL_LIB_UUID
depends on SPL
bool
config SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails"
- depends on SEMIHOSTING && (ARM64 || RISCV)
+ depends on SEMIHOSTING
default y
help
Normally, if U-Boot makes a semihosting call and no debugger is
config SPL_SEMIHOSTING_FALLBACK
bool "Recover gracefully when semihosting fails in SPL"
- depends on SPL_SEMIHOSTING && (ARM64 || RISCV)
+ depends on SPL_SEMIHOSTING
select ARMV8_SPL_EXCEPTION_VECTORS if ARM64
default y
help
if EFI_LOADER
-config CMD_BOOTEFI_BOOTMGR
+config BOOTEFI_BOOTMGR
bool "UEFI Boot Manager"
default y
select BOOTMETH_GLOBAL if BOOTSTD
help
Select this option if you want to select the UEFI binary to be booted
- via UEFI variables Boot####, BootOrder, and BootNext. This enables the
- 'bootefi bootmgr' command.
+ via UEFI variables Boot####, BootOrder, and BootNext. You should also
+ normally enable CMD_BOOTEFI_BOOTMGR so that the command is available.
choice
prompt "Store for non-volatile UEFI variables"
endif
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
-obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += efi_bootmgr.o
+obj-$(CONFIG_BOOTEFI_BOOTMGR) += efi_bootmgr.o
obj-y += efi_boottime.o
obj-y += efi_helper.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
#ifdef CONFIG_BOOTP_RANDOM_DELAY
#include "net_rand.h"
#endif
+#include <malloc.h>
#define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */
*e++ = 42;
*cnt += 1;
#endif
+ if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION)) {
+ *e++ = 209; /* PXELINUX Config File */
+ *cnt += 1;
+ }
/* no options, so back up to avoid sending an empty request list */
if (*cnt == 0)
e -= 2;
net_boot_file_name[size] = 0;
}
break;
+ case 209: /* PXELINUX Config File */
+ if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION)) {
+ /* In case it has already been allocated when get DHCP Offer packet,
+ * free first to avoid memory leak.
+ */
+ if (pxelinux_configfile)
+ free(pxelinux_configfile);
+
+ pxelinux_configfile = (char *)malloc((oplen + 1) * sizeof(char));
+
+ if (pxelinux_configfile)
+ strlcpy(pxelinux_configfile, popt + 2, oplen + 1);
+ else
+ printf("Error: Failed to allocate pxelinux_configfile\n");
+ }
+ break;
default:
#if defined(CONFIG_BOOTP_VENDOREX)
if (dhcp_vendorex_proc(popt))
static void dhcp6_parse_options(uchar *rx_pkt, unsigned int len)
{
uchar *option_ptr;
- int sol_max_rt_sec, option_len;
+ int sol_max_rt_sec, option_len, param_len_1;
char *s, *e;
struct dhcp6_option_hdr *option_hdr;
case DHCP6_OPTION_OPT_BOOTFILE_PARAM:
if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION)) {
debug("DHCP6_OPTION_OPT_BOOTFILE_PARAM FOUND\n");
+ /* if CONFIG_DHCP6_PXE_DHCP_OPTION is set the PXE config file path
+ * is contained in the first OPT_BOOTFILE_PARAM argument
+ */
+ param_len_1 = ntohs(*((u16 *)option_ptr));
+ option_ptr += sizeof(u16);
+ if (param_len_1 + sizeof(u16) > option_len) {
+ debug("Invalid BOOTFILE_PARAM param_len_1. Skipping\n");
+ break;
+ }
if (pxelinux_configfile)
free(pxelinux_configfile);
- pxelinux_configfile = (char *)malloc((option_len + 1) *
+ pxelinux_configfile = (char *)malloc((param_len_1 + 1) *
sizeof(char));
if (pxelinux_configfile)
- strlcpy(pxelinux_configfile, option_ptr, option_len + 1);
+ strlcpy(pxelinux_configfile, option_ptr, param_len_1 + 1);
else
printf("Error: Failed to allocate pxelinux_configfile\n");
/* Check if the device has a valid MAC address in device tree */
if (!eth_dev_get_mac_address(dev, pdata->enetaddr) ||
!is_valid_ethaddr(pdata->enetaddr)) {
- source = "ROM";
/* Check if the device has a MAC address in ROM */
- if (eth_get_ops(dev)->read_rom_hwaddr)
- eth_get_ops(dev)->read_rom_hwaddr(dev);
+ if (eth_get_ops(dev)->read_rom_hwaddr) {
+ int ret;
+
+ ret = eth_get_ops(dev)->read_rom_hwaddr(dev);
+ if (!ret)
+ source = "ROM";
+ }
}
eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr);
eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
pdata->enetaddr);
#else
- printf("\nError: %s address not set.\n",
+ printf("\nError: %s No valid MAC address found.\n",
dev->name);
return -EINVAL;
#endif
ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid;
debug_cond(DEBUG_NET_PKT, "packet received\n");
+ if (DEBUG_NET_PKT_TRACE)
+ print_hex_dump_bytes("rx: ", DUMP_PREFIX_OFFSET, in_packet,
+ len);
#if defined(CONFIG_CMD_PCAP)
pcap_post(in_packet, len, false);
config UNIT_TEST
bool "Unit tests"
+ depends on CMDLINE
help
Select this to compile in unit tests for various parts of
U-Boot. Test suites will be subcommands of the "ut" command.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Copyright 2022 Google LLC
+# Written by Simon Glass <sjg@chromium.org>
+
+import pytest
+
+import u_boot_utils as util
+
+# This is needed for Azure, since the default '..' directory is not writeable
+TMPDIR = '/tmp/test_cmdline'
+
+@pytest.mark.slow
+@pytest.mark.boardspec('sandbox')
+def test_sandbox_cmdline(u_boot_console):
+ """Test building sandbox without CONFIG_CMDLINE"""
+ cons = u_boot_console
+
+ out = util.run_and_log(
+ cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ '-a', '~CMDLINE', '-o', TMPDIR])
+
+@pytest.mark.slow
+@pytest.mark.boardspec('sandbox')
+def test_sandbox_lto(u_boot_console):
+ """Test building sandbox without CONFIG_LTO"""
+ cons = u_boot_console
+
+ out = util.run_and_log(
+ cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+ '-a', '~LTO', '-o', TMPDIR])
Args:
commit: Commit object that is being built
brd: Board object that is being built
- stage: Stage that we are at (mrproper, config, build)
+ stage: Stage that we are at (mrproper, config, oldconfig, build)
cwd: Directory where make should be run
args: Arguments to pass to make
kwargs: Arguments to pass to command.run_pipe()
# Now do the build, if everything looks OK
if result.return_code == 0:
+ if adjust_cfg:
+ oldc_args = list(args) + ['oldconfig']
+ oldc_result = self.make(commit, brd, 'oldconfig', cwd,
+ *oldc_args, env=env)
+ if oldc_result.return_code:
+ return oldc_result
result = self._build(commit, brd, cwd, args, env, cmd_list,
config_only)
if adjust_cfg:
tools.write_file(fname, b'CONFIG_SOMETHING=1')
return command.CommandResult(return_code=0,
combined='Test configuration complete')
+ elif stage == 'oldconfig':
+ return command.CommandResult(return_code=0)
elif stage == 'build':
stderr = ''
fname = os.path.join(cwd or '', out_dir, 'u-boot')
return command.CommandResult(return_code=0)
# Not handled, so abort
- print('make', stage)
+ print('_HandleMake failure: make', stage)
sys.exit(1)
# Example function to print output lines
projects / thirdparty / u-boot.git / commitdiff
