arm64: gic: Add power up sequence for GIC-600

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Power on the redistributor and  wait until
the power on state is reflected by checking the bit
GICR_PWRR.RDPD == 0. While running U-Boot in EL3
without enabling this register, GICR_WAKER.ChildrenAsleep
bit is not getting cleared and loops infinitely.
This register(GICR_PWRR) must be programmed to mark the frame
as powered on, before accessing other registers in the frame.
Rest of initialization sequence remains the same.

ARM GIC-600 IP complies with ARM GICv3 architecture.
Enable this config if GIC-600 IP present.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d978c06d5ae37016ef497ffd173f6556096541e..a0842e193307173c086d46bbb57fda884011eeb7 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -124,6 +124,15 @@ config GIC_V3_ITS
          ARM GICV3 has limitation, once the LPI table is enabled, LPI
          configuration table can not be re-programmed, unless GICV3 reset.
 
+config GICV3_SUPPORT_GIC600
+       bool "ARM GICV3 GIC600 SUPPORT"
+       help
+         ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
+         implements a power control register in the Redistributor frame.This
+         register must be programmed to mark the frame as powered on, before
+         accessing other registers in the frame. Rest of initialization sequence
+         remains the same.
+
 config STATIC_RELA
        bool
        default y if ARM64

diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index bd3a80cdf70add02b4a43ceb9db05833292fe539..fb64ba076d7c377307db9a2d753b9b43b386b6fa 100644 (file)
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -57,6 +57,7 @@
 #define GICR_TYPER             0x0008
 #define GICR_STATUSR           0x0010
 #define GICR_WAKER             0x0014
+#define GICR_PWRR              0x0024
 #define GICR_SETLPIR           0x0040
 #define GICR_CLRLPIR           0x0048
 #define GICR_SEIR              0x0068

diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index 86cd882fc75908088d72a2263e4df2b5cda199fa..7fa48648d9dcc97af30cf39cfcb891e7080d6ea0 100644 (file)
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -92,8 +92,16 @@ ENTRY(gic_init_secure_percpu)
        add     x9, x9, #(2 << 16)
        b       1b
 
+2:
+#if defined(CONFIG_GICV3_SUPPORT_GIC600)
+        mov     w10, #0x0               /* Power on redistributor */
+        str     w10, [x9, GICR_PWRR]
+5:      ldr     w10, [x9, GICR_PWRR]    /* Wait until the power on state is reflected */
+        tbnz    w10, #1, 5b             /* If RDPD == 0 then powered on */
+#endif
+
        /* x9: ReDistributor Base Address of Current CPU */
-2:     mov     w10, #~0x2
+       mov     w10, #~0x2
        ldr     w11, [x9, GICR_WAKER]
        and     w11, w11, w10           /* Clear ProcessorSleep */
        str     w11, [x9, GICR_WAKER]

diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 1b5339993f83410cd6e2da6d1161009cd139b07c..54fb93aeb53a5ff0c69461698284d2410703bed3 100644 (file)
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -35,6 +35,9 @@ config SYS_MEM_RSVD_FOR_MMU
 config GICV3
        def_bool y
 
+config GICV3_SUPPORT_GIC600
+       def_bool y
+
 config SYS_MALLOC_LEN
        default 0x2000000