]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
serial: serial_stm32: Add reset support
authorPatrice Chotard <patrice.chotard@st.com>
Tue, 4 Dec 2018 13:11:36 +0000 (14:11 +0100)
committerTom Rini <trini@konsulko.com>
Sat, 15 Dec 2018 16:49:56 +0000 (11:49 -0500)
In some cases, UART is configured by early boot stage.
To be sure of the initial state of UART and to avoid
spurious chars on console, reset the serial block before
configuring it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/serial/serial_stm32.c

index 31b43ee88dd7ed7857b200cae5ab9ee345bb5ff7..e31c87b9ac5ad2eae5a24397ef0f07a08b6e7d7d 100644 (file)
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <reset.h>
 #include <serial.h>
 #include <watchdog.h>
 #include <asm/io.h>
@@ -171,6 +172,7 @@ static int stm32_serial_probe(struct udevice *dev)
 {
        struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
        struct clk clk;
+       struct reset_ctl reset;
        int ret;
 
        plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
@@ -185,6 +187,13 @@ static int stm32_serial_probe(struct udevice *dev)
                return ret;
        }
 
+       ret = reset_get_by_index(dev, 0, &reset);
+       if (!ret) {
+               reset_assert(&reset);
+               udelay(2);
+               reset_deassert(&reset);
+       }
+
        plat->clock_rate = clk_get_rate(&clk);
        if (plat->clock_rate < 0) {
                clk_disable(&clk);