board/amcc/katmai/katmai.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <ppc4xx.h>
  27 #include <i2c.h>
  28 #include <libfdt.h>
  29 #include <fdt_support.h>
  30 #include <netdev.h>
  31 #include <asm/processor.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/4xx_pcie.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 int board_early_init_f (void)
  39 {
  40         unsigned long mfr;
  41
  42         /*----------------------------------------------------------------------+
  43          * Interrupt controller setup for the Katmai 440SPe Evaluation board.
  44          *-----------------------------------------------------------------------+
  45          *-----------------------------------------------------------------------+
  46          * Interrupt | Source                            | Pol.  | Sensi.| Crit. |
  47          *-----------+-----------------------------------+-------+-------+-------+
  48          * IRQ 00    | UART0                             | High  | Level | Non   |
  49          * IRQ 01    | UART1                             | High  | Level | Non   |
  50          * IRQ 02    | IIC0                              | High  | Level | Non   |
  51          * IRQ 03    | IIC1                              | High  | Level | Non   |
  52          * IRQ 04    | PCI0X0 MSG IN                     | High  | Level | Non   |
  53          * IRQ 05    | PCI0X0 CMD Write                  | High  | Level | Non   |
  54          * IRQ 06    | PCI0X0 Power Mgt                  | High  | Level | Non   |
  55          * IRQ 07    | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
  56          * IRQ 08    | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
  57          * IRQ 09    | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
  58          * IRQ 10    | UIC2 Non-critical Int.            | NA    | NA    | Non   |
  59          * IRQ 11    | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
  60          * IRQ 12    | PCI Express MSI Level 0           | Rising| Edge  | Non   |
  61          * IRQ 13    | PCI Express MSI Level 1           | Rising| Edge  | Non   |
  62          * IRQ 14    | PCI Express MSI Level 2           | Rising| Edge  | Non   |
  63          * IRQ 15    | PCI Express MSI Level 3           | Rising| Edge  | Non   |
  64          * IRQ 16    | UIC3 Non-critical Int.            | NA    | NA    | Non   |
  65          * IRQ 17    | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
  66          * IRQ 18    | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
  67          * IRQ 19    | DMA Channel 0 FIFO Full           | High  | Level | Non   |
  68          * IRQ 20    | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
  69          * IRQ 21    | DMA Channel 1 FIFO Full           | High  | Level | Non   |
  70          * IRQ 22    | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
  71          * IRQ 23    | I2O Inbound Doorbell              | High  | Level | Non   |
  72          * IRQ 24    | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
  73          * IRQ 25    | I2O Region 0 LL PLB Write         | High  | Level | Non   |
  74          * IRQ 26    | I2O Region 1 LL PLB Write         | High  | Level | Non   |
  75          * IRQ 27    | I2O Region 0 HB PLB Write         | High  | Level | Non   |
  76          * IRQ 28    | I2O Region 1 HB PLB Write         | High  | Level | Non   |
  77          * IRQ 29    | GPT Down Count Timer              | Rising| Edge  | Non   |
  78          * IRQ 30    | UIC1 Non-critical Int.            | NA    | NA    | Non   |
  79          * IRQ 31    | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
  80          *------------------------------------------------------------------------
  81          * IRQ 32    | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
  82          * IRQ 33    | MAL Serr                          | High  | Level | Non   |
  83          * IRQ 34    | MAL Txde                          | High  | Level | Non   |
  84          * IRQ 35    | MAL Rxde                          | High  | Level | Non   |
  85          * IRQ 36    | DMC CE or DMC UE                  | High  | Level | Non   |
  86          * IRQ 37    | EBC or UART2                      | High  |Lvl Edg| Non   |
  87          * IRQ 38    | MAL TX EOB                        | High  | Level | Non   |
  88          * IRQ 39    | MAL RX EOB                        | High  | Level | Non   |
  89          * IRQ 40    | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
  90          * IRQ 41    | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
  91          * IRQ 42    | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
  92          * IRQ 43    | L2 Cache                          | Risin | Edge  | Non   |
  93          * IRQ 44    | GPT Compare Timer 0               | Risin | Edge  | Non   |
  94          * IRQ 45    | GPT Compare Timer 1               | Risin | Edge  | Non   |
  95          * IRQ 46    | GPT Compare Timer 2               | Risin | Edge  | Non   |
  96          * IRQ 47    | GPT Compare Timer 3               | Risin | Edge  | Non   |
  97          * IRQ 48    | GPT Compare Timer 4               | Risin | Edge  | Non   |
  98          * IRQ 49    | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
  99          * IRQ 50    | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
 100          * IRQ 51    | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
 101          * IRQ 52    | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 102          * IRQ 53    | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
 103          * IRQ 54    | DMA Error                         | High  | Level | Non   |
 104          * IRQ 55    | DMA I2O Error                     | High  | Level | Non   |
 105          * IRQ 56    | Serial ROM                        | High  | Level | Non   |
 106          * IRQ 57    | PCIX0 Error                       | High  | Edge  | Non   |
 107          * IRQ 58    | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
 108          * IRQ 59    | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
 109          * IRQ 60    | EMAC0 Interrupt                   | High  | Level | Non   |
 110          * IRQ 61    | EMAC0 Wake-up                     | High  | Level | Non   |
 111          * IRQ 62    | Reserved                          | High  | Level | Non   |
 112          * IRQ 63    | XOR                               | High  | Level | Non   |
 113          *-----------------------------------------------------------------------
 114          * IRQ 64    | PE0 AL                            | High  | Level | Non   |
 115          * IRQ 65    | PE0 VPD Access                    | Risin | Edge  | Non   |
 116          * IRQ 66    | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 117          * IRQ 67    | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 118          * IRQ 68    | PE0 TCR                           | High  | Level | Non   |
 119          * IRQ 69    | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 120          * IRQ 70    | PE0 DCR Error                     | High  | Level | Non   |
 121          * IRQ 71    | Reserved                          | N/A   | N/A   | Non   |
 122          * IRQ 72    | PE1 AL                            | High  | Level | Non   |
 123          * IRQ 73    | PE1 VPD Access                    | Risin | Edge  | Non   |
 124          * IRQ 74    | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 125          * IRQ 75    | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 126          * IRQ 76    | PE1 TCR                           | High  | Level | Non   |
 127          * IRQ 77    | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 128          * IRQ 78    | PE1 DCR Error                     | High  | Level | Non   |
 129          * IRQ 79    | Reserved                          | N/A   | N/A   | Non   |
 130          * IRQ 80    | PE2 AL                            | High  | Level | Non   |
 131          * IRQ 81    | PE2 VPD Access                    | Risin | Edge  | Non   |
 132          * IRQ 82    | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 133          * IRQ 83    | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 134          * IRQ 84    | PE2 TCR                           | High  | Level | Non   |
 135          * IRQ 85    | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 136          * IRQ 86    | PE2 DCR Error                     | High  | Level | Non   |
 137          * IRQ 87    | Reserved                          | N/A   | N/A   | Non   |
 138          * IRQ 88    | External IRQ(5)                   | Progr | Progr | Non   |
 139          * IRQ 89    | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 140          * IRQ 90    | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 141          * IRQ 91    | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 142          * IRQ 92    | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 143          * IRQ 93    | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 144          * IRQ 94    | Reserved                          | N/A   | N/A   | Non   |
 145          * IRQ 95    | Reserved                          | N/A   | N/A   | Non   |
 146          *-----------------------------------------------------------------------
 147          * IRQ 96    | PE0 INTA                          | High  | Level | Non   |
 148          * IRQ 97    | PE0 INTB                          | High  | Level | Non   |
 149          * IRQ 98    | PE0 INTC                          | High  | Level | Non   |
 150          * IRQ 99    | PE0 INTD                          | High  | Level | Non   |
 151          * IRQ 100   | PE1 INTA                          | High  | Level | Non   |
 152          * IRQ 101   | PE1 INTB                          | High  | Level | Non   |
 153          * IRQ 102   | PE1 INTC                          | High  | Level | Non   |
 154          * IRQ 103   | PE1 INTD                          | High  | Level | Non   |
 155          * IRQ 104   | PE2 INTA                          | High  | Level | Non   |
 156          * IRQ 105   | PE2 INTB                          | High  | Level | Non   |
 157          * IRQ 106   | PE2 INTC                          | High  | Level | Non   |
 158          * IRQ 107   | PE2 INTD                          | Risin | Edge  | Non   |
 159          * IRQ 108   | PCI Express MSI Level 4           | Risin | Edge  | Non   |
 160          * IRQ 109   | PCI Express MSI Level 5           | Risin | Edge  | Non   |
 161          * IRQ 110   | PCI Express MSI Level 6           | Risin | Edge  | Non   |
 162          * IRQ 111   | PCI Express MSI Level 7           | Risin | Edge  | Non   |
 163          * IRQ 116   | PCI Express MSI Level 12          | Risin | Edge  | Non   |
 164          * IRQ 112   | PCI Express MSI Level 8           | Risin | Edge  | Non   |
 165          * IRQ 113   | PCI Express MSI Level 9           | Risin | Edge  | Non   |
 166          * IRQ 114   | PCI Express MSI Level 10          | Risin | Edge  | Non   |
 167          * IRQ 115   | PCI Express MSI Level 11          | Risin | Edge  | Non   |
 168          * IRQ 117   | PCI Express MSI Level 13          | Risin | Edge  | Non   |
 169          * IRQ 118   | PCI Express MSI Level 14          | Risin | Edge  | Non   |
 170          * IRQ 119   | PCI Express MSI Level 15          | Risin | Edge  | Non   |
 171          * IRQ 120   | PCI Express MSI Level 16          | Risin | Edge  | Non   |
 172          * IRQ 121   | PCI Express MSI Level 17          | Risin | Edge  | Non   |
 173          * IRQ 122   | PCI Express MSI Level 18          | Risin | Edge  | Non   |
 174          * IRQ 123   | PCI Express MSI Level 19          | Risin | Edge  | Non   |
 175          * IRQ 124   | PCI Express MSI Level 20          | Risin | Edge  | Non   |
 176          * IRQ 125   | PCI Express MSI Level 21          | Risin | Edge  | Non   |
 177          * IRQ 126   | PCI Express MSI Level 22          | Risin | Edge  | Non   |
 178          * IRQ 127   | PCI Express MSI Level 23          | Risin | Edge  | Non   |
 179          *-----------+-----------------------------------+-------+-------+-------+ */
 180         /*-------------------------------------------------------------------------+
 181          * Put UICs in PowerPC440SPemode.
 182          * Initialise UIC registers.  Clear all interrupts.  Disable all interrupts.
 183          * Set critical interrupt values.  Set interrupt polarities.  Set interrupt
 184          * trigger levels.  Make bit 0 High  priority.  Clear all interrupts again.
 185          *------------------------------------------------------------------------*/
 186         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
 187         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
 188         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical interrupts: */
 189         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities*/
 190         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
 191         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 192         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts*/
 193         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts*/
 194
 195
 196         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
 197         mtdcr (uic2er, 0x00000000);     /* disable all interrupts*/
 198         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical interrupts*/
 199         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities*/
 200         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
 201         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 202         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
 203         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
 204
 205         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts*/
 206         mtdcr (uic1er, 0x00000000);     /* disable all interrupts*/
 207         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical interrupts*/
 208         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
 209         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels*/
 210         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 211         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts*/
 212         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts*/
 213
 214         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
 215         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted cascade    to be checked */
 216         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical interrupts*/
 217         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities*/
 218         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
 219         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 220         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts*/
 221         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts*/
 222
 223         mfsdr(sdr_mfr, mfr);
 224         mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
 225         mtsdr(sdr_mfr, mfr);
 226
 227         mtsdr(SDR0_PFC0, CFG_PFC0);
 228
 229         out32(GPIO0_OR, CFG_GPIO_OR);
 230         out32(GPIO0_ODR, CFG_GPIO_ODR);
 231         out32(GPIO0_TCR, CFG_GPIO_TCR);
 232
 233         return 0;
 234 }
 235
 236 int checkboard (void)
 237 {
 238         char *s = getenv("serial#");
 239
 240         printf("Board: Katmai - AMCC 440SPe Evaluation Board");
 241         if (s != NULL) {
 242                 puts(", serial# ");
 243                 puts(s);
 244         }
 245         putc('\n');
 246
 247         return 0;
 248 }
 249
 250 /*
 251  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 252  * board specific values.
 253  */
 254 u32 ddr_wrdtr(u32 default_val) {
 255         return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
 256 }
 257
 258 u32 ddr_clktr(u32 default_val) {
 259         return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
 260 }
 261
 262 /*************************************************************************
 263  *  pci_pre_init
 264  *
 265  *  This routine is called just prior to registering the hose and gives
 266  *  the board the opportunity to check things. Returning a value of zero
 267  *  indicates that things are bad & PCI initialization should be aborted.
 268  *
 269  *      Different boards may wish to customize the pci controller structure
 270  *      (add regions, override default access routines, etc) or perform
 271  *      certain pre-initialization actions.
 272  *
 273  ************************************************************************/
 274 #if defined(CONFIG_PCI)
 275 int pci_pre_init(struct pci_controller * hose )
 276 {
 277         unsigned long strap;
 278
 279         /*-------------------------------------------------------------------+
 280          *      The katmai board is always configured as the host & requires the
 281          *      PCI arbiter to be enabled.
 282          *-------------------------------------------------------------------*/
 283         mfsdr(sdr_sdstp1, strap);
 284         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 285                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 286                 return 0;
 287         }
 288
 289         return 1;
 290 }
 291 #endif  /* defined(CONFIG_PCI) */
 292
 293 /*************************************************************************
 294  *  pci_target_init
 295  *
 296  *      The bootstrap configuration provides default settings for the pci
 297  *      inbound map (PIM). But the bootstrap config choices are limited and
 298  *      may not be sufficient for a given board.
 299  *
 300  ************************************************************************/
 301 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 302 void pci_target_init(struct pci_controller * hose )
 303 {
 304         /*-------------------------------------------------------------------+
 305          * Disable everything
 306          *-------------------------------------------------------------------*/
 307         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 308         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 309         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 310         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 311
 312         /*-------------------------------------------------------------------+
 313          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 314          * strapping options to not support sizes such as 128/256 MB.
 315          *-------------------------------------------------------------------*/
 316         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 317         out32r( PCIX0_PIM0LAH, 0 );
 318         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 319         out32r( PCIX0_BAR0, 0 );
 320
 321         /*-------------------------------------------------------------------+
 322          * Program the board's subsystem id/vendor id
 323          *-------------------------------------------------------------------*/
 324         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 325         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 326
 327         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 328 }
 329 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 330
 331 #if defined(CONFIG_PCI)
 332 /*************************************************************************
 333  *  is_pci_host
 334  *
 335  *      This routine is called to determine if a pci scan should be
 336  *      performed. With various hardware environments (especially cPCI and
 337  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 338  *      bit in the strap register, or generic host/adapter assumptions.
 339  *
 340  *      Rather than hard-code a bad assumption in the general 440 code, the
 341  *      440 pci code requires the board to decide at runtime.
 342  *
 343  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 344  *
 345  *
 346  ************************************************************************/
 347 int is_pci_host(struct pci_controller *hose)
 348 {
 349         /* The katmai board is always configured as host. */
 350         return 1;
 351 }
 352
 353 static int katmai_pcie_card_present(int port)
 354 {
 355         u32 val;
 356
 357         val = in32(GPIO0_IR);
 358         switch (port) {
 359         case 0:
 360                 return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
 361         case 1:
 362                 return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
 363         case 2:
 364                 return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
 365         default:
 366                 return 0;
 367         }
 368 }
 369
 370 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 371
 372 void pcie_setup_hoses(int busno)
 373 {
 374         struct pci_controller *hose;
 375         int i, bus;
 376         int ret = 0;
 377         char *env;
 378         unsigned int delay;
 379
 380         /*
 381          * assume we're called after the PCIX hose is initialized, which takes
 382          * bus ID 0 and therefore start numbering PCIe's from 1.
 383          */
 384         bus = busno;
 385         for (i = 0; i <= 2; i++) {
 386                 /* Check for katmai card presence */
 387                 if (!katmai_pcie_card_present(i))
 388                         continue;
 389
 390                 if (is_end_point(i))
 391                         ret = ppc4xx_init_pcie_endport(i);
 392                 else
 393                         ret = ppc4xx_init_pcie_rootport(i);
 394                 if (ret) {
 395                         printf("PCIE%d: initialization as %s failed\n", i,
 396                                is_end_point(i) ? "endpoint" : "root-complex");
 397                         continue;
 398                 }
 399
 400                 hose = &pcie_hose[i];
 401                 hose->first_busno = bus;
 402                 hose->last_busno = bus;
 403                 hose->current_busno = bus;
 404
 405                 /* setup mem resource */
 406                 pci_set_region(hose->regions + 0,
 407                                CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 408                                CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 409                                CFG_PCIE_MEMSIZE,
 410                                PCI_REGION_MEM);
 411                 hose->region_count = 1;
 412                 pci_register_hose(hose);
 413
 414                 if (is_end_point(i)) {
 415                         ppc4xx_setup_pcie_endpoint(hose, i);
 416                         /*
 417                          * Reson for no scanning is endpoint can not generate
 418                          * upstream configuration accesses.
 419                          */
 420                 } else {
 421                         ppc4xx_setup_pcie_rootpoint(hose, i);
 422                         env = getenv ("pciscandelay");
 423                         if (env != NULL) {
 424                                 delay = simple_strtoul(env, NULL, 10);
 425                                 if (delay > 5)
 426                                         printf("Warning, expect noticable delay before "
 427                                                "PCIe scan due to 'pciscandelay' value!\n");
 428                                 mdelay(delay * 1000);
 429                         }
 430
 431                         /*
 432                          * Config access can only go down stream
 433                          */
 434                         hose->last_busno = pci_hose_scan(hose);
 435                         bus = hose->last_busno + 1;
 436                 }
 437         }
 438 }
 439 #endif  /* defined(CONFIG_PCI) */
 440
 441 #ifdef CONFIG_POST
 442 /*
 443  * Returns 1 if keys pressed to start the power-on long-running tests
 444  * Called from board_init_f().
 445  */
 446 int post_hotkeys_pressed(void)
 447 {
 448         return (ctrlc());
 449 }
 450 #endif
 451
 452 int board_eth_init(bd_t *bis)
 453 {
 454         return pci_eth_init(bis);
 455 }