3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
17 #include <gdsys_fpga.h>
19 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
20 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
21 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
23 #define PHYREG_CONTROL 0
24 #define PHYREG_PAGE_ADDRESS 22
25 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
26 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
29 UNITTYPE_CCD_SWITCH
= 1,
39 struct ihs_fpga
*fpga_ptr
[] = CONFIG_SYS_FPGA_PTR
;
44 * Note: DTT has been removed. Please use UCLASS_THERMAL.
54 int configure_gbit_phy(unsigned char addr
)
59 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
60 PHYREG_PAGE_ADDRESS
, 0x0002))
62 /* disable SGMII autonegotiation */
63 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
64 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2
, 0x800a))
67 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
68 PHYREG_PAGE_ADDRESS
, 0x0000))
70 /* switch from powerdown to normal operation */
71 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
72 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1
, &value
))
74 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
75 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1
, value
& ~0x0004))
77 /* reset phy so settings take effect */
78 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
79 PHYREG_CONTROL
, 0x9140))
85 printf("Error writing to the PHY addr=%02x\n", addr
);
90 * Check Board Identity:
94 char *s
= getenv("serial#");
96 puts("Board: CATCenter Io");
108 static void print_fpga_info(void)
114 unsigned hardware_version
;
115 unsigned feature_channels
;
116 unsigned feature_expansion
;
118 FPGA_GET_REG(0, versions
, &versions
);
119 FPGA_GET_REG(0, fpga_version
, &fpga_version
);
120 FPGA_GET_REG(0, fpga_features
, &fpga_features
);
122 unit_type
= (versions
& 0xf000) >> 12;
123 hardware_version
= versions
& 0x000f;
124 feature_channels
= fpga_features
& 0x007f;
125 feature_expansion
= fpga_features
& (1<<15);
130 case UNITTYPE_CCD_SWITCH
:
131 printf("CCD-Switch");
135 printf("UnitType %d(not supported)", unit_type
);
139 switch (hardware_version
) {
141 printf(" HW-Ver 1.00\n");
145 printf(" HW-Ver 1.10\n");
149 printf(" HW-Ver 1.21\n");
153 printf(" HW-Ver 1.22\n");
157 printf(" HW-Ver %d(not supported)\n",
162 printf(" FPGA V %d.%02d, features:",
163 fpga_version
/ 100, fpga_version
% 100);
165 printf(" %d channel(s)", feature_channels
);
167 printf(", expansion %ssupported\n", feature_expansion
? "" : "un");
173 int last_stage_init(void)
180 struct mii_dev
*mdiodev
= mdio_alloc();
183 strncpy(mdiodev
->name
, CONFIG_SYS_GBIT_MII_BUSNAME
, MDIO_NAME_LEN
);
184 mdiodev
->read
= bb_miiphy_read
;
185 mdiodev
->write
= bb_miiphy_write
;
187 retval
= mdio_register(mdiodev
);
191 for (k
= 0; k
< 32; ++k
)
192 configure_gbit_phy(k
);
194 /* take fpga serdes blocks out of reset */
195 FPGA_SET_REG(0, quad_serdes_reset
, 0);
200 void gd405ep_init(void)
204 void gd405ep_set_fpga_reset(unsigned state
)
207 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_RESET
);
208 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_RESET
);
210 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_BOOT
);
211 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_BOOT
);
215 void gd405ep_setup_hw(void)
218 * set "startup-finished"-gpios
220 gpio_write_bit(21, 0);
221 gpio_write_bit(22, 1);
224 int gd405ep_get_fpga_done(unsigned fpga
)
226 return in_le16((void *)LATCH2_BASE
) & CONFIG_SYS_FPGA_DONE(fpga
);