3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #include "../common/osd.h"
19 #include "../common/mclink.h"
20 #include "../common/phy.h"
28 DECLARE_GLOBAL_DATA_PTR
;
30 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
31 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
32 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
34 #define MAX_MUX_CHANNELS 2
37 UNITTYPE_MAIN_SERVER
= 0,
38 UNITTYPE_MAIN_USER
= 1,
39 UNITTYPE_VIDEO_SERVER
= 2,
40 UNITTYPE_VIDEO_USER
= 3,
61 COMPRESSION_TYPE1_DELTA
= 1,
62 COMPRESSION_TYPE1_TYPE2_DELTA
= 3,
83 CARRIER_SPEED_2_5G
= 1,
88 MCFPGA_INIT_N
= 1 << 1,
89 MCFPGA_PROGRAM_N
= 1 << 2,
90 MCFPGA_UPDATE_ENABLE_N
= 1 << 3,
91 MCFPGA_RESET_N
= 1 << 4,
99 unsigned int mclink_fpgacount
;
100 struct ihs_fpga
*fpga_ptr
[] = CONFIG_SYS_FPGA_PTR
;
102 int fpga_set_reg(u32 fpga
, u16
*reg
, off_t regoff
, u16 data
)
111 res
= mclink_send(fpga
- 1, regoff
, data
);
113 printf("mclink_send reg %02lx data %04x returned %d\n",
123 int fpga_get_reg(u32 fpga
, u16
*reg
, off_t regoff
, u16
*data
)
129 *data
= in_le16(reg
);
132 if (fpga
> mclink_fpgacount
)
134 res
= mclink_receive(fpga
- 1, regoff
, data
);
136 printf("mclink_receive reg %02lx returned %d\n",
146 * Check Board Identity:
150 char *s
= getenv("serial#");
166 static void print_fpga_info(unsigned int fpga
, bool rgmii2_present
)
172 unsigned hardware_version
;
173 unsigned feature_compression
;
174 unsigned feature_osd
;
175 unsigned feature_audio
;
176 unsigned feature_sysclock
;
177 unsigned feature_ramconfig
;
178 unsigned feature_carrier_speed
;
179 unsigned feature_carriers
;
180 unsigned feature_video_channels
;
182 int legacy
= get_fpga_state(fpga
) & FPGA_STATE_PLATFORM
;
184 FPGA_GET_REG(fpga
, versions
, &versions
);
185 FPGA_GET_REG(fpga
, fpga_version
, &fpga_version
);
186 FPGA_GET_REG(fpga
, fpga_features
, &fpga_features
);
188 unit_type
= (versions
& 0xf000) >> 12;
189 feature_compression
= (fpga_features
& 0xe000) >> 13;
190 feature_osd
= fpga_features
& (1<<11);
191 feature_audio
= (fpga_features
& 0x0600) >> 9;
192 feature_sysclock
= (fpga_features
& 0x0180) >> 7;
193 feature_ramconfig
= (fpga_features
& 0x0060) >> 5;
194 feature_carrier_speed
= fpga_features
& (1<<4);
195 feature_carriers
= (fpga_features
& 0x000c) >> 2;
196 feature_video_channels
= fpga_features
& 0x0003;
202 case UNITTYPE_MAIN_USER
:
203 printf("Mainchannel");
206 case UNITTYPE_VIDEO_USER
:
207 printf("Videochannel");
211 printf("UnitType %d(not supported)", unit_type
);
215 if (unit_type
== UNITTYPE_MAIN_USER
) {
218 (in_le16((void *)LATCH2_BASE
)>>8) & 0x0f;
221 (!!pca9698_get_value(0x20, 24) << 0)
222 | (!!pca9698_get_value(0x20, 25) << 1)
223 | (!!pca9698_get_value(0x20, 26) << 2)
224 | (!!pca9698_get_value(0x20, 27) << 3);
225 switch (hardware_version
) {
227 printf(" HW-Ver 1.00,");
231 printf(" HW-Ver 1.04,");
235 printf(" HW-Ver 1.10,");
239 printf(" HW-Ver 1.20-1.21,");
243 printf(" HW-Ver 2.00,");
247 printf(" HW-Ver 2.10,");
251 printf(" HW-Ver 2.20,");
255 printf(" HW-Ver 2.30,");
259 printf(" HW-Ver %d(not supported),",
267 if (unit_type
== UNITTYPE_VIDEO_USER
) {
268 hardware_version
= versions
& 0x000f;
269 switch (hardware_version
) {
271 printf(" HW-Ver 2.00,");
275 printf(" HW-Ver 2.10,");
279 printf(" HW-Ver %d(not supported),",
285 printf(" FPGA V %d.%02d\n features:",
286 fpga_version
/ 100, fpga_version
% 100);
289 switch (feature_compression
) {
290 case COMPRESSION_NONE
:
291 printf(" no compression");
294 case COMPRESSION_TYPE1_DELTA
:
295 printf(" type1-deltacompression");
298 case COMPRESSION_TYPE1_TYPE2_DELTA
:
299 printf(" type1-deltacompression, type2-inlinecompression");
303 printf(" compression %d(not supported)", feature_compression
);
307 printf(", %sosd", feature_osd
? "" : "no ");
309 switch (feature_audio
) {
311 printf(", no audio");
315 printf(", audio tx");
319 printf(", audio rx");
323 printf(", audio rx+tx");
327 printf(", audio %d(not supported)", feature_audio
);
333 switch (feature_sysclock
) {
335 printf("clock 147.456 MHz");
339 printf("clock %d(not supported)", feature_sysclock
);
343 switch (feature_ramconfig
) {
345 printf(", RAM 32 bit DDR2");
349 printf(", RAM 32 bit DDR3");
353 printf(", RAM %d(not supported)", feature_ramconfig
);
357 printf(", %d carrier(s) %s", feature_carriers
,
358 feature_carrier_speed
? "2.5Gbit/s" : "1Gbit/s");
360 printf(", %d video channel(s)\n", feature_video_channels
);
363 int last_stage_init(void)
368 unsigned char mclink_controllers
[] = { 0x24, 0x25, 0x26 };
369 int legacy
= get_fpga_state(0) & FPGA_STATE_PLATFORM
;
371 int feature_carrier_speed
;
372 bool ch0_rgmii2_present
= false;
374 FPGA_GET_REG(0, fpga_features
, &fpga_features
);
375 feature_carrier_speed
= fpga_features
& (1<<4);
378 /* Turn on Parade DP501 */
379 pca9698_direction_output(0x20, 9, 1);
381 ch0_rgmii2_present
= !pca9698_get_value(0x20, 30);
384 /* wait for FPGA done; then reset FPGA */
385 for (k
= 0; k
< ARRAY_SIZE(mclink_controllers
); ++k
) {
386 unsigned int ctr
= 0;
388 if (i2c_probe(mclink_controllers
[k
]))
391 while (!(pca953x_get_val(mclink_controllers
[k
])
395 printf("no done for mclink_controller %d\n", k
);
400 pca953x_set_dir(mclink_controllers
[k
], MCFPGA_RESET_N
, 0);
401 pca953x_set_val(mclink_controllers
[k
], MCFPGA_RESET_N
, 0);
403 pca953x_set_val(mclink_controllers
[k
], MCFPGA_RESET_N
,
407 if (!legacy
&& (feature_carrier_speed
== CARRIER_SPEED_1G
)) {
409 struct mii_dev
*mdiodev
= mdio_alloc();
412 strncpy(mdiodev
->name
, bb_miiphy_buses
[0].name
, MDIO_NAME_LEN
);
413 mdiodev
->read
= bb_miiphy_read
;
414 mdiodev
->write
= bb_miiphy_write
;
416 retval
= mdio_register(mdiodev
);
419 for (mux_ch
= 0; mux_ch
< MAX_MUX_CHANNELS
; ++mux_ch
) {
420 if ((mux_ch
== 1) && !ch0_rgmii2_present
)
423 setup_88e1518(bb_miiphy_buses
[0].name
, mux_ch
);
427 /* give slave-PLLs and Parade DP501 some time to be up and running */
430 mclink_fpgacount
= CONFIG_SYS_MCLINK_MAX
;
431 slaves
= mclink_probe();
432 mclink_fpgacount
= 0;
434 print_fpga_info(0, ch0_rgmii2_present
);
440 mclink_fpgacount
= slaves
;
442 for (k
= 1; k
<= slaves
; ++k
) {
443 FPGA_GET_REG(k
, fpga_features
, &fpga_features
);
444 feature_carrier_speed
= fpga_features
& (1<<4);
446 print_fpga_info(k
, false);
448 if (feature_carrier_speed
== CARRIER_SPEED_1G
) {
450 struct mii_dev
*mdiodev
= mdio_alloc();
453 strncpy(mdiodev
->name
, bb_miiphy_buses
[k
].name
,
455 mdiodev
->read
= bb_miiphy_read
;
456 mdiodev
->write
= bb_miiphy_write
;
458 retval
= mdio_register(mdiodev
);
461 setup_88e1518(bb_miiphy_buses
[k
].name
, 0);
469 * provide access to fpga gpios (for I2C bitbang)
470 * (these may look all too simple but make iocon.h much more readable)
472 void fpga_gpio_set(unsigned int bus
, int pin
)
474 FPGA_SET_REG(bus
, gpio
.set
, pin
);
477 void fpga_gpio_clear(unsigned int bus
, int pin
)
479 FPGA_SET_REG(bus
, gpio
.clear
, pin
);
482 int fpga_gpio_get(unsigned int bus
, int pin
)
486 FPGA_GET_REG(bus
, gpio
.read
, &val
);
491 void gd405ep_init(void)
495 if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
496 for (k
= 0; k
< CONFIG_SYS_FPGA_COUNT
; ++k
)
497 gd
->arch
.fpga_state
[k
] |= FPGA_STATE_PLATFORM
;
499 pca9698_direction_output(0x20, 4, 1);
503 void gd405ep_set_fpga_reset(unsigned state
)
505 int legacy
= get_fpga_state(0) & FPGA_STATE_PLATFORM
;
509 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_RESET
);
510 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_RESET
);
512 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_BOOT
);
513 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_BOOT
);
516 pca9698_set_value(0x20, 4, state
? 0 : 1);
520 void gd405ep_setup_hw(void)
523 * set "startup-finished"-gpios
525 gpio_write_bit(21, 0);
526 gpio_write_bit(22, 1);
529 int gd405ep_get_fpga_done(unsigned fpga
)
531 int legacy
= get_fpga_state(0) & FPGA_STATE_PLATFORM
;
534 return in_le16((void *)LATCH2_BASE
)
535 & CONFIG_SYS_FPGA_DONE(fpga
);
537 return pca9698_get_value(0x20, 20);
541 * FPGA MII bitbang implementation
554 static int mii_dummy_init(struct bb_miiphy_bus
*bus
)
559 static int mii_mdio_active(struct bb_miiphy_bus
*bus
)
561 struct fpga_mii
*fpga_mii
= bus
->priv
;
564 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.set
, GPIO_MDIO
);
566 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.clear
, GPIO_MDIO
);
571 static int mii_mdio_tristate(struct bb_miiphy_bus
*bus
)
573 struct fpga_mii
*fpga_mii
= bus
->priv
;
575 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.set
, GPIO_MDIO
);
580 static int mii_set_mdio(struct bb_miiphy_bus
*bus
, int v
)
582 struct fpga_mii
*fpga_mii
= bus
->priv
;
585 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.set
, GPIO_MDIO
);
587 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.clear
, GPIO_MDIO
);
594 static int mii_get_mdio(struct bb_miiphy_bus
*bus
, int *v
)
597 struct fpga_mii
*fpga_mii
= bus
->priv
;
599 FPGA_GET_REG(fpga_mii
->fpga
, gpio
.read
, &gpio
);
601 *v
= ((gpio
& GPIO_MDIO
) != 0);
606 static int mii_set_mdc(struct bb_miiphy_bus
*bus
, int v
)
608 struct fpga_mii
*fpga_mii
= bus
->priv
;
611 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.set
, GPIO_MDC
);
613 FPGA_SET_REG(fpga_mii
->fpga
, gpio
.clear
, GPIO_MDC
);
618 static int mii_delay(struct bb_miiphy_bus
*bus
)
625 struct bb_miiphy_bus bb_miiphy_buses
[] = {
628 .init
= mii_dummy_init
,
629 .mdio_active
= mii_mdio_active
,
630 .mdio_tristate
= mii_mdio_tristate
,
631 .set_mdio
= mii_set_mdio
,
632 .get_mdio
= mii_get_mdio
,
633 .set_mdc
= mii_set_mdc
,
635 .priv
= &fpga_mii
[0],
639 .init
= mii_dummy_init
,
640 .mdio_active
= mii_mdio_active
,
641 .mdio_tristate
= mii_mdio_tristate
,
642 .set_mdio
= mii_set_mdio
,
643 .get_mdio
= mii_get_mdio
,
644 .set_mdc
= mii_set_mdc
,
646 .priv
= &fpga_mii
[1],
650 .init
= mii_dummy_init
,
651 .mdio_active
= mii_mdio_active
,
652 .mdio_tristate
= mii_mdio_tristate
,
653 .set_mdio
= mii_set_mdio
,
654 .get_mdio
= mii_get_mdio
,
655 .set_mdc
= mii_set_mdc
,
657 .priv
= &fpga_mii
[2],
661 .init
= mii_dummy_init
,
662 .mdio_active
= mii_mdio_active
,
663 .mdio_tristate
= mii_mdio_tristate
,
664 .set_mdio
= mii_set_mdio
,
665 .get_mdio
= mii_get_mdio
,
666 .set_mdc
= mii_set_mdc
,
668 .priv
= &fpga_mii
[3],
672 int bb_miiphy_buses_num
= sizeof(bb_miiphy_buses
) /
673 sizeof(bb_miiphy_buses
[0]);