include/configs/cm_t43.h

   1 /*
   2  * cm_t43.h
   3  *
   4  * Copyright (C) 2015 Compulab, Ltd.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_CM_T43_H
  10 #define __CONFIG_CM_T43_H
  11
  12 #define CONFIG_CM_T43
  13 #define CONFIG_ARCH_CPU_INIT
  14 #define CONFIG_MAX_RAM_BANK_SIZE        (2048 << 20)    /* 2GB */
  15 #define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
  16
  17 #include <asm/arch/omap.h>
  18
  19 /* Serial support */
  20 #define CONFIG_SYS_NS16550_SERIAL
  21 #define CONFIG_SYS_NS16550_CLK          48000000
  22 #define CONFIG_SYS_NS16550_COM1         0x44e09000
  23 #if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
  24 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  25 #endif
  26
  27 /* NAND support */
  28 #define CONFIG_SYS_NAND_ONFI_DETECTION
  29 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  30 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  31 #define CONFIG_SYS_NAND_OOBSIZE         64
  32 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
  33 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  34 #define CONFIG_SYS_NAND_ECCSIZE         512
  35 #define CONFIG_SYS_NAND_ECCBYTES        14
  36 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
  37 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
  38                                          CONFIG_SYS_NAND_PAGE_SIZE)
  39 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
  40                                          10, 11, 12, 13, 14, 15, 16, 17, \
  41                                          18, 19, 20, 21, 22, 23, 24, 25, \
  42                                          26, 27, 28, 29, 30, 31, 32, 33, \
  43                                          34, 35, 36, 37, 38, 39, 40, 41, \
  44                                          42, 43, 44, 45, 46, 47, 48, 49, \
  45                                          50, 51, 52, 53, 54, 55, 56, 57, }
  46
  47 /* CPSW Ethernet support */
  48 #define CONFIG_DRIVER_TI_CPSW
  49 #define CONFIG_MII
  50 #define CONFIG_BOOTP_DEFAULT
  51 #define CONFIG_BOOTP_SEND_HOSTNAME
  52 #define CONFIG_BOOTP_GATEWAY
  53 #define CONFIG_PHY_ATHEROS
  54 #define CONFIG_SYS_RX_ETH_BUFFER        64
  55
  56 /* USB support */
  57 #define CONFIG_USB_XHCI_OMAP
  58 #define CONFIG_AM437X_USB2PHY2_HOST
  59
  60 /* SPI Flash support */
  61 #define CONFIG_TI_SPI_MMAP
  62 #define CONFIG_SF_DEFAULT_SPEED         48000000
  63 #define CONFIG_DEFAULT_SPI_MODE         SPI_MODE_3
  64
  65 /* Power */
  66 #define CONFIG_POWER
  67 #define CONFIG_POWER_I2C
  68 #define CONFIG_POWER_TPS65218
  69
  70 /* Enabling L2 Cache */
  71 #define CONFIG_SYS_L2_PL310
  72 #define CONFIG_SYS_PL310_BASE           0x48242000
  73
  74 /*
  75  * Since SPL did pll and ddr initialization for us,
  76  * we don't need to do it twice.
  77  */
  78 #if !defined(CONFIG_SPL_BUILD)
  79 #define CONFIG_SKIP_LOWLEVEL_INIT
  80 #endif
  81
  82 #define CONFIG_HSMMC2_8BIT
  83
  84 #include <configs/ti_armv7_omap.h>
  85 #undef CONFIG_SYS_MONITOR_LEN
  86
  87 #define CONFIG_ENV_SIZE                 (16 * 1024)
  88 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  89
  90 #define V_OSCK                          24000000  /* Clock output from T2 */
  91 #define V_SCLK                          (V_OSCK)
  92
  93 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
  94 #define CONFIG_ENV_OFFSET               (768 * 1024)
  95 #define CONFIG_ENV_SPI_MAX_HZ           48000000
  96
  97 #define CONFIG_EXTRA_ENV_SETTINGS \
  98         "loadaddr=0x80200000\0" \
  99         "fdtaddr=0x81200000\0" \
 100         "bootm_size=0x8000000\0" \
 101         "autoload=no\0" \
 102         "console=ttyO0,115200n8\0" \
 103         "fdtfile=am437x-sb-som-t43.dtb\0" \
 104         "kernel=zImage-cm-t43\0" \
 105         "bootscr=bootscr.img\0" \
 106         "emmcroot=/dev/mmcblk0p2 rw\0" \
 107         "emmcrootfstype=ext4 rootwait\0" \
 108         "emmcargs=setenv bootargs console=${console} " \
 109                 "root=${emmcroot} " \
 110                 "rootfstype=${emmcrootfstype}\0" \
 111         "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
 112         "bootscript=echo Running bootscript from mmc ...; " \
 113                 "source ${loadaddr}\0" \
 114         "emmcboot=echo Booting from emmc ... && " \
 115                 "run emmcargs && " \
 116                 "load mmc 1 ${loadaddr} ${kernel} && " \
 117                 "load mmc 1 ${fdtaddr} ${fdtfile} && " \
 118                 "bootz ${loadaddr} - ${fdtaddr}\0"
 119
 120 #define CONFIG_BOOTCOMMAND \
 121         "mmc dev 0; " \
 122         "if mmc rescan; then " \
 123                 "if run loadbootscript; then " \
 124                         "run bootscript; " \
 125                 "fi; " \
 126         "fi; " \
 127         "mmc dev 1; " \
 128         "if mmc rescan; then " \
 129                 "run emmcboot; " \
 130         "fi;"
 131
 132 #define CONFIG_CONS_INDEX               1
 133
 134 /* SPL defines. */
 135 #define CONFIG_SPL_TEXT_BASE            0x40300350
 136 #define CONFIG_SYS_SPL_ARGS_ADDR        (CONFIG_SYS_SDRAM_BASE + (128 << 20))
 137 #define CONFIG_SYS_SPI_U_BOOT_OFFS      (256 * 1024)
 138 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 139 #define CONFIG_SPL_SPI_LOAD
 140
 141 /* EEPROM */
 142 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 143 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 144 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 146 #define CONFIG_SYS_EEPROM_SIZE                  256
 147
 148 #endif  /* __CONFIG_CM_T43_H */