include/configs/t3corp.h

   1 /*
   2  * (C) Copyright 2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * t3corp.h - configuration for T3CORP (460GT)
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_460GT            1       /* Specific PPC460GT    */
  18 #define CONFIG_440              1
  19
  20 #ifndef CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  22 #endif
  23
  24 #define CONFIG_HOSTNAME         t3corp
  25
  26 /*
  27  * Include common defines/options for all AMCC/APM eval boards
  28  */
  29 #include "amcc-common.h"
  30
  31 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  32
  33 #define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  34 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  35 #define CONFIG_BOARD_TYPES              1       /* support board types */
  36 #define CFG_ALT_MEMTEST
  37
  38 /*
  39  * Base addresses -- Note these are effective addresses where the
  40  * actual resources get mapped (not physical addresses)
  41  */
  42 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory */
  43 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs */
  44 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  45
  46 #define CONFIG_SYS_PCIE_MEMBASE         0xb0000000      /* mapped PCIe mem */
  47 #define CONFIG_SYS_PCIE_MEMSIZE         0x08000000      /* incr for PCIe */
  48 #define CONFIG_SYS_PCIE_BASE            0xc4000000      /* PCIe UTL regs */
  49
  50 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  51 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  52 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  53 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  54
  55 #define CONFIG_SYS_PCIE0_UTLBASE        0xc08010000ULL  /* 36bit phys addr */
  56
  57 /* base address of inbound PCIe window */
  58 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x000000000ULL  /* 36bit phys addr */
  59
  60 /* EBC stuff */
  61 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped here */
  62 #define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  63
  64 #define CONFIG_SYS_FPGA1_BASE           0xe0000000
  65 #define CONFIG_SYS_FPGA2_BASE           0xe2000000
  66 #define CONFIG_SYS_FPGA3_BASE           0xe4000000
  67
  68 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space */
  69 #define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
  70 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
  71 #define CONFIG_SYS_FLASH_BASE_PHYS \
  72         (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
  73         | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
  74
  75 #define CONFIG_SYS_OCM_BASE             0xE7000000      /* OCM: 64k */
  76 #define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k */
  77 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
  78 #define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
  79
  80 /*
  81  * Initial RAM & stack pointer (placed in OCM)
  82  */
  83 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM */
  84 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  85 #define CONFIG_SYS_GBL_DATA_OFFSET \
  86         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  87 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  88
  89 /*
  90  * Serial Port
  91  */
  92 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  93
  94 /*
  95  * Environment
  96  */
  97 /*
  98  * Define here the location of the environment variables (flash).
  99  */
 100 #define CONFIG_ENV_IS_IN_FLASH          /* use flash for environment vars */
 101
 102 /*
 103  * Flash related
 104  */
 105 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 106 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 107 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 108 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 109 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method      */
 110 #define CONFIG_SYS_FLASH_PROTECTION     /* use hardware flash protection */
 111
 112 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, \
 113                         (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
 114 #define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff,      /* don't set    */ \
 115                         0xbddf }                /* set async read mode  */
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors p. chip*/
 118
 119 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms*/
 120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms*/
 121
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buff'd writes (20x faster)*/
 123 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 124
 125 #define CONFIG_ENV_SECT_SIZE            0x20000 /* sector size */
 126 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - \
 127                                          CONFIG_ENV_SECT_SIZE)
 128 #define CONFIG_ENV_SIZE                 0x4000  /* env sector size */
 129
 130 /* Address and size of Redundant Environment Sector     */
 131 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 132 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 133
 134 /*
 135  * DDR2 SDRAM
 136  */
 137 #define CONFIG_SYS_MBYTES_SDRAM         256
 138 #define CONFIG_DDR_ECC
 139 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 140 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 141 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 142 #undef CONFIG_PPC4xx_DDR_METHOD_A
 143 #define CONFIG_DDR_RFDC_FIXED           0x000001D7 /* optimal value */
 144
 145 /* DDR1/2 SDRAM Device Control Register Data Values */
 146 /* Memory Queue */
 147 #define CONFIG_SYS_SDRAM_R0BAS          (SDRAM_RXBAS_SDBA_ENCODE(0) | \
 148                                          SDRAM_RXBAS_SDSZ_256)
 149 #define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 150 #define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 151 #define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 152 #define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 153 #define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 154 #define CONFIG_SYS_SDRAM_CONF1LL        0x80001C00
 155 #define CONFIG_SYS_SDRAM_CONF1HB        0x80001C80
 156 #define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 157
 158 #define CAS_LATENCY                     JEDEC_MA_MR_CL_DDR2_5_0_CLK
 159
 160 /* DDR1/2 SDRAM Device Control Register Data Values */
 161 #define CONFIG_SYS_SDRAM0_MB0CF         (SDRAM_RXBAS_SDAM_MODE7         | \
 162                                          SDRAM_RXBAS_SDBE_ENABLE)
 163 #define CONFIG_SYS_SDRAM0_MB1CF         SDRAM_RXBAS_SDBE_DISABLE
 164 #define CONFIG_SYS_SDRAM0_MB2CF         SDRAM_RXBAS_SDBE_DISABLE
 165 #define CONFIG_SYS_SDRAM0_MB3CF         SDRAM_RXBAS_SDBE_DISABLE
 166 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_MCHK_GEN          | \
 167                                          SDRAM_MCOPT1_PMU_OPEN          | \
 168                                          SDRAM_MCOPT1_DMWD_32           | \
 169                                          SDRAM_MCOPT1_8_BANKS           | \
 170                                          SDRAM_MCOPT1_DDR2_TYPE         | \
 171                                          SDRAM_MCOPT1_QDEP              | \
 172                                          SDRAM_MCOPT1_RWOO_DISABLED     | \
 173                                          SDRAM_MCOPT1_WOOO_DISABLED     | \
 174                                          SDRAM_MCOPT1_DREF_NORMAL)
 175 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 176 #define CONFIG_SYS_SDRAM0_MODT0         SDRAM_MODT_EB0W_ENABLE
 177 #define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 178 #define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 179 #define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 180 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 181                                          SDRAM_CODT_DQS_1_8_V_DDR2      | \
 182                                          SDRAM_CODT_IO_NMODE)
 183 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 184 #define CONFIG_SYS_SDRAM0_INITPLR0                                      \
 185         (SDRAM_INITPLR_ENABLE                                           | \
 186          SDRAM_INITPLR_IMWT_ENCODE(80)                                  | \
 187          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 188 #define CONFIG_SYS_SDRAM0_INITPLR1                                      \
 189         (SDRAM_INITPLR_ENABLE                                           | \
 190          SDRAM_INITPLR_IMWT_ENCODE(3)                                   | \
 191          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)                 | \
 192          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 193          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 194 #define CONFIG_SYS_SDRAM0_INITPLR2                                      \
 195         (SDRAM_INITPLR_ENABLE                                           | \
 196          SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 197          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 198          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                        | \
 199          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 200 #define CONFIG_SYS_SDRAM0_INITPLR3                                      \
 201         (SDRAM_INITPLR_ENABLE                                           | \
 202          SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 203          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 204          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                        | \
 205          SDRAM_INITPLR_IMA_ENCODE(0))
 206 #define CONFIG_SYS_SDRAM0_INITPLR4                                      \
 207         (SDRAM_INITPLR_ENABLE                                           | \
 208          SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 209          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 210          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 211          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE               | \
 212                                   JEDEC_MA_EMR_RTT_150OHM))
 213 #define CONFIG_SYS_SDRAM0_INITPLR5                                      \
 214         (SDRAM_INITPLR_ENABLE                                           | \
 215          SDRAM_INITPLR_IMWT_ENCODE(200)                                 | \
 216          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 217          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 218          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC             | \
 219                                   CAS_LATENCY                           | \
 220                                   JEDEC_MA_MR_BLEN_4                    | \
 221                                   JEDEC_MA_MR_DLL_RESET))
 222 #define CONFIG_SYS_SDRAM0_INITPLR6                                      \
 223         (SDRAM_INITPLR_ENABLE                                           | \
 224          SDRAM_INITPLR_IMWT_ENCODE(3)                                   | \
 225          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)                 | \
 226          SDRAM_INITPLR_IBA_ENCODE(0x0)                                  | \
 227          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 228 #define CONFIG_SYS_SDRAM0_INITPLR7                                      \
 229         (SDRAM_INITPLR_ENABLE                                           | \
 230          SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 231          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 232 #define CONFIG_SYS_SDRAM0_INITPLR8                                      \
 233         (SDRAM_INITPLR_ENABLE                                           | \
 234          SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 235          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 236 #define CONFIG_SYS_SDRAM0_INITPLR9                                      \
 237         (SDRAM_INITPLR_ENABLE                                           | \
 238          SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 239          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 240 #define CONFIG_SYS_SDRAM0_INITPLR10                                     \
 241         (SDRAM_INITPLR_ENABLE                                           | \
 242          SDRAM_INITPLR_IMWT_ENCODE(26)                                  | \
 243          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 244 #define CONFIG_SYS_SDRAM0_INITPLR11                                     \
 245         (SDRAM_INITPLR_ENABLE                                           | \
 246          SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 247          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 248          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                          | \
 249          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC             | \
 250                                   CAS_LATENCY                           | \
 251                                   JEDEC_MA_MR_BLEN_4))
 252 #define CONFIG_SYS_SDRAM0_INITPLR12                                     \
 253         (SDRAM_INITPLR_ENABLE                                           | \
 254          SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 255          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 256          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 257          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER                | \
 258                                   JEDEC_MA_EMR_RDQS_DISABLE             | \
 259                                   JEDEC_MA_EMR_DQS_ENABLE               | \
 260                                   JEDEC_MA_EMR_RTT_150OHM               | \
 261                                   JEDEC_MA_EMR_ODS_NORMAL))
 262 #define CONFIG_SYS_SDRAM0_INITPLR13                                     \
 263         (SDRAM_INITPLR_ENABLE                                           | \
 264          SDRAM_INITPLR_IMWT_ENCODE(2)                                   | \
 265          SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                       | \
 266          SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                         | \
 267          SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT                 | \
 268                                   JEDEC_MA_EMR_RDQS_DISABLE             | \
 269                                   JEDEC_MA_EMR_DQS_ENABLE               | \
 270                                   JEDEC_MA_EMR_RTT_150OHM               | \
 271                                   JEDEC_MA_EMR_ODS_NORMAL))
 272 #define CONFIG_SYS_SDRAM0_INITPLR14     SDRAM_INITPLR_DISABLE
 273 #define CONFIG_SYS_SDRAM0_INITPLR15     SDRAM_INITPLR_DISABLE
 274 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE         | \
 275                                          SDRAM_RQDC_RQFD_ENCODE(56))
 276 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(599)
 277 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 278 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 279                                          SDRAM_DLCR_DLCS_CONT_DONE      | \
 280                                          SDRAM_DLCR_DLCV_ENCODE(155))
 281 #define CONFIG_SYS_SDRAM0_CLKTR         SDRAM_CLKTR_CLKP_90_DEG_ADV
 282 #define CONFIG_SYS_SDRAM0_WRDTR         SDRAM_WRDTR_WTR_90_DEG_ADV
 283 #define CONFIG_SYS_SDRAM0_SDTR1         (SDRAM_SDTR1_LDOF_2_CLK         | \
 284                                          SDRAM_SDTR1_RTW_2_CLK          | \
 285                                          SDRAM_SDTR1_RTRO_1_CLK)
 286 #define CONFIG_SYS_SDRAM0_SDTR2         (SDRAM_SDTR2_RCD_3_CLK          | \
 287                                          SDRAM_SDTR2_WTR_2_CLK          | \
 288                                          SDRAM_SDTR2_XSNR_32_CLK        | \
 289                                          SDRAM_SDTR2_WPC_4_CLK          | \
 290                                          SDRAM_SDTR2_RPC_2_CLK          | \
 291                                          SDRAM_SDTR2_RP_3_CLK           | \
 292                                          SDRAM_SDTR2_RRD_2_CLK)
 293 #define CONFIG_SYS_SDRAM0_SDTR3         (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 294                                          SDRAM_SDTR3_RC_ENCODE(11)      | \
 295                                          SDRAM_SDTR3_XCS                | \
 296                                          SDRAM_SDTR3_RFC_ENCODE(26))
 297 #define CONFIG_SYS_SDRAM0_MMODE         (SDRAM_MMODE_WR_DDR2_3_CYC      | \
 298                                          CAS_LATENCY                    | \
 299                                          SDRAM_MMODE_BLEN_4)
 300 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_ENABLE        | \
 301                                          SDRAM_MEMODE_RTT_150OHM)
 302
 303 /*
 304  * I2C
 305  */
 306 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0                   400000
 307
 308 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 309 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 310 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 311 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 312
 313 /* I2C bootstrap EEPROM */
 314 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 315 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 316 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 317
 318 /*
 319  * Ethernet
 320  */
 321 #define CONFIG_IBM_EMAC4_V4     1
 322
 323 #define CONFIG_HAS_ETH0
 324
 325 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 326 #define CONFIG_M88E1111_PHY
 327 /* Disable fiber since fiber/copper auto-selection doesn't seem to work */
 328 #define CONFIG_M88E1111_DISABLE_FIBER
 329
 330 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 331 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 332 #define CONFIG_PHY_DYNAMIC_ANEG 1
 333
 334 /*
 335  * Default environment variables
 336  */
 337 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 338         CONFIG_AMCC_DEF_ENV                                             \
 339         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 340         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 341         "kernel_addr=fc000000\0"                                        \
 342         "fdt_addr=fc1e0000\0"                                           \
 343         "ramdisk_addr=fc200000\0"                                       \
 344         "pciconfighost=1\0"                                             \
 345         "pcie_mode=RP:RP\0"                                             \
 346         "unlock=yes\0"                                                  \
 347         ""
 348
 349 /*
 350  * Commands additional to the ones defined in amcc-common.h
 351  */
 352 #define CONFIG_CMD_PCI
 353 #define CONFIG_CMD_SDRAM
 354
 355 /*
 356  * PCI stuff
 357  */
 358 /* General PCI */
 359 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 360 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 361 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 362
 363 /* Board-specific PCI, no PCI support, only PCIe */
 364 #undef CONFIG_SYS_PCI_TARGET_INIT
 365 #undef CONFIG_SYS_PCI_MASTER_INIT
 366
 367 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM */
 368 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 369
 370 /*
 371  * External Bus Controller (EBC) Setup
 372  */
 373
 374 /*
 375  * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
 376  * boot EBC mapping only supports a maximum of 16MBytes
 377  * (4.ff00.0000 - 4.ffff.ffff).
 378  * To solve this problem, the flash has to get remapped to another
 379  * EBC address which accepts bigger regions:
 380  *
 381  * 0xfc00.0000 -> 4.cc00.0000
 382  */
 383
 384 /* Memory Bank 0 (NOR-flash) */
 385 #define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED          |       \
 386                                  EBC_BXAP_TWT_ENCODE(16)        |       \
 387                                  EBC_BXAP_BCE_DISABLE           |       \
 388                                  EBC_BXAP_BCT_2TRANS            |       \
 389                                  EBC_BXAP_CSN_ENCODE(1)         |       \
 390                                  EBC_BXAP_OEN_ENCODE(1)         |       \
 391                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 392                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 393                                  EBC_BXAP_TH_ENCODE(7)          |       \
 394                                  EBC_BXAP_RE_DISABLED           |       \
 395                                  EBC_BXAP_SOR_DELAYED           |       \
 396                                  EBC_BXAP_BEM_WRITEONLY         |       \
 397                                  EBC_BXAP_PEN_DISABLED)
 398 #define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
 399                                  EBC_BXCR_BS_16MB               |       \
 400                                  EBC_BXCR_BU_RW                 |       \
 401                                  EBC_BXCR_BW_16BIT)
 402
 403 /* Memory Bank 1 (FPGA 1) */
 404 #define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_DISABLED          |       \
 405                                  EBC_BXAP_TWT_ENCODE(5)         |       \
 406                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 407                                  EBC_BXAP_OEN_ENCODE(3)         |       \
 408                                  EBC_BXAP_WBN_ENCODE(0)         |       \
 409                                  EBC_BXAP_WBF_ENCODE(0)         |       \
 410                                  EBC_BXAP_TH_ENCODE(1)          |       \
 411                                  EBC_BXAP_RE_ENABLED            |       \
 412                                  EBC_BXAP_SOR_DELAYED           |       \
 413                                  EBC_BXAP_BEM_RW                |       \
 414                                  EBC_BXAP_PEN_DISABLED)
 415 #define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
 416                                  EBC_BXCR_BS_32MB               |       \
 417                                  EBC_BXCR_BU_RW                 |       \
 418                                  EBC_BXCR_BW_32BIT)
 419
 420 /* Memory Bank 2 (FPGA 2) */
 421 #define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 422                                  EBC_BXAP_TWT_ENCODE(5)         |       \
 423                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 424                                  EBC_BXAP_OEN_ENCODE(3)         |       \
 425                                  EBC_BXAP_WBN_ENCODE(0)         |       \
 426                                  EBC_BXAP_WBF_ENCODE(0)         |       \
 427                                  EBC_BXAP_TH_ENCODE(1)          |       \
 428                                  EBC_BXAP_RE_ENABLED            |       \
 429                                  EBC_BXAP_SOR_DELAYED           |       \
 430                                  EBC_BXAP_BEM_RW                |       \
 431                                  EBC_BXAP_PEN_DISABLED)
 432 #define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
 433                                  EBC_BXCR_BS_16MB               |       \
 434                                  EBC_BXCR_BU_RW                 |       \
 435                                  EBC_BXCR_BW_32BIT)
 436
 437 /* Memory Bank 3 (FPGA 3) */
 438 #define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_DISABLED          |       \
 439                                  EBC_BXAP_TWT_ENCODE(5)         |       \
 440                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 441                                  EBC_BXAP_OEN_ENCODE(3)         |       \
 442                                  EBC_BXAP_WBN_ENCODE(0)         |       \
 443                                  EBC_BXAP_WBF_ENCODE(0)         |       \
 444                                  EBC_BXAP_TH_ENCODE(1)          |       \
 445                                  EBC_BXAP_RE_ENABLED            |       \
 446                                  EBC_BXAP_SOR_DELAYED           |       \
 447                                  EBC_BXAP_BEM_RW                |       \
 448                                  EBC_BXAP_PEN_DISABLED)
 449 #define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
 450                                  EBC_BXCR_BS_16MB               |       \
 451                                  EBC_BXCR_BU_RW                 |       \
 452                                  EBC_BXCR_BW_32BIT)
 453
 454 /*
 455  * PPC4xx GPIO Configuration
 456  */
 457
 458 #define CONFIG_SYS_4xx_GPIO_TABLE { /*            GPIO  Alternate1      Alternate2      Alternate3 */ \
 459 {                                                                                       \
 460 /* GPIO Core 0 */                                                                       \
 461 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 462 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 463 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 464 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 465 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 466 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 467 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 468 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 469 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 470 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 471 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 472 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 473 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 474 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 475 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 476 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 477 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 478 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 479 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 480 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 481 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 482 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 483 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 484 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 485 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 486 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 487 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 488 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 489 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 490 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 491 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 492 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 493 },                                                                                      \
 494 {                                                                                       \
 495 /* GPIO Core 1 */                                                                       \
 496 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 497 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 498 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 499 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 500 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 501 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 502 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 503 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 504 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 505 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 506 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 507 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 508 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 509 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 510 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 511 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 512 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 513 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 514 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 515 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 516 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 517 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 518 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 519 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 520 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 521 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 522 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 523 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 524 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 525 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 526 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 527 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 528 }                                                                                       \
 529 }
 530
 531 #endif  /* __CONFIG_H */