3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 * This test verifies the CPU data and instruction cache using
15 * several test scenarios.
20 #if CONFIG_POST & CONFIG_SYS_POST_CACHE
25 #define CACHE_POST_SIZE 1024
27 int cache_post_test1 (int tlb
, void *p
, int size
);
28 int cache_post_test2 (int tlb
, void *p
, int size
);
29 int cache_post_test3 (int tlb
, void *p
, int size
);
30 int cache_post_test4 (int tlb
, void *p
, int size
);
31 int cache_post_test5 (int tlb
, void *p
, int size
);
32 int cache_post_test6 (int tlb
, void *p
, int size
);
35 static unsigned char testarea
[CACHE_POST_SIZE
]
36 __attribute__((__aligned__(CACHE_POST_SIZE
)));
39 int cache_post_test (int flags
)
41 void *virt
= (void *)CONFIG_SYS_POST_CACHE_ADDR
;
44 int tlb
= -1; /* index to the victim TLB entry */
47 * All 44x variants deal with cache management differently
48 * because they have the address translation always enabled.
49 * The 40x ppc's don't use address translation in U-Boot at all,
50 * so we have to distinguish here between 40x and 44x.
56 * Allocate a new TLB entry, since we are going to modify
57 * the write-through and caching inhibited storage attributes.
59 program_tlb((u32
)testarea
, (u32
)virt
, CACHE_POST_SIZE
,
62 /* Find the TLB entry */
64 if (i
>= PPC4XX_TLB_SIZE
) {
65 printf ("Failed to program tlb entry\n");
69 if (TLB_WORD0_EPN_DECODE(word0
) == (u32
)virt
) {
75 ints
= disable_interrupts ();
79 res
= cache_post_test1 (tlb
, virt
, CACHE_POST_SIZE
);
82 res
= cache_post_test2 (tlb
, virt
, CACHE_POST_SIZE
);
85 res
= cache_post_test3 (tlb
, virt
, CACHE_POST_SIZE
);
88 res
= cache_post_test4 (tlb
, virt
, CACHE_POST_SIZE
);
91 res
= cache_post_test5 (tlb
, virt
, CACHE_POST_SIZE
);
94 res
= cache_post_test6 (tlb
, virt
, CACHE_POST_SIZE
);
100 remove_tlb((u32
)virt
, CACHE_POST_SIZE
);
106 #endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */