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Commit | Line | Data |
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c906108c SS |
1 | /* |
2 | * Simulator for the Hitachi H8/300 architecture. | |
3 | * | |
4 | * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com | |
5 | * | |
6 | * This file is part of H8/300 sim | |
7 | * | |
8 | * | |
9 | * THIS SOFTWARE IS NOT COPYRIGHTED | |
10 | * | |
11 | * Cygnus offers the following for use in the public domain. Cygnus makes no | |
12 | * warranty with regard to the software or its performance and the user | |
13 | * accepts the software "AS IS" with all faults. | |
14 | * | |
15 | * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS | |
16 | * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY | |
17 | * AND FITNESS FOR A PARTICULAR PURPOSE. | |
18 | */ | |
19 | ||
20 | #include "config.h" | |
21 | ||
22 | #include <stdio.h> | |
23 | #include <signal.h> | |
24 | #ifdef HAVE_TIME_H | |
25 | #include <time.h> | |
26 | #endif | |
27 | #ifdef HAVE_STDLIB_H | |
28 | #include <stdlib.h> | |
29 | #endif | |
30 | #ifdef HAVE_SYS_PARAM_H | |
31 | #include <sys/param.h> | |
32 | #endif | |
c906108c SS |
33 | #include "ansidecl.h" |
34 | #include "bfd.h" | |
35 | #include "callback.h" | |
36 | #include "remote-sim.h" | |
37 | ||
38 | #ifndef SIGTRAP | |
39 | # define SIGTRAP 5 | |
40 | #endif | |
41 | ||
42 | int debug; | |
43 | ||
44 | host_callback *sim_callback; | |
45 | ||
46 | static SIM_OPEN_KIND sim_kind; | |
47 | static char *myname; | |
48 | ||
49 | /* FIXME: Needs to live in header file. | |
50 | This header should also include the things in remote-sim.h. | |
51 | One could move this to remote-sim.h but this function isn't needed | |
52 | by gdb. */ | |
53 | void sim_set_simcache_size PARAMS ((int)); | |
54 | ||
de9b1892 | 55 | #define X(op, size) op * 4 + size |
c906108c | 56 | |
de9b1892 | 57 | #define SP (h8300hmode ? SL : SW) |
c906108c SS |
58 | #define SB 0 |
59 | #define SW 1 | |
60 | #define SL 2 | |
61 | #define OP_REG 1 | |
62 | #define OP_DEC 2 | |
63 | #define OP_DISP 3 | |
64 | #define OP_INC 4 | |
65 | #define OP_PCREL 5 | |
66 | #define OP_MEM 6 | |
67 | #define OP_CCR 7 | |
68 | #define OP_IMM 8 | |
69 | #define OP_ABS 10 | |
70 | #define h8_opcodes ops | |
71 | #define DEFINE_TABLE | |
72 | #include "opcode/h8300.h" | |
73 | ||
74 | #include "inst.h" | |
75 | ||
0ef9643e | 76 | /* The rate at which to call the host's poll_quit callback. */ |
7a292a7a SS |
77 | |
78 | #define POLL_QUIT_INTERVAL 0x80000 | |
79 | ||
c906108c | 80 | #define LOW_BYTE(x) ((x) & 0xff) |
de9b1892 KH |
81 | #define HIGH_BYTE(x) (((x) >> 8) & 0xff) |
82 | #define P(X,Y) ((X << 8) | Y) | |
c906108c | 83 | |
de9b1892 | 84 | #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V << 1) | C; |
c906108c SS |
85 | |
86 | #define GETSR() \ | |
87 | c = (cpu.ccr >> 0) & 1;\ | |
88 | v = (cpu.ccr >> 1) & 1;\ | |
89 | nz = !((cpu.ccr >> 2) & 1);\ | |
90 | n = (cpu.ccr >> 3) & 1; | |
91 | ||
92 | #ifdef __CHAR_IS_SIGNED__ | |
de9b1892 | 93 | #define SEXTCHAR(x) ((char) (x)) |
c906108c SS |
94 | #endif |
95 | ||
96 | #ifndef SEXTCHAR | |
97 | #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) | |
98 | #endif | |
99 | ||
100 | #define UEXTCHAR(x) ((x) & 0xff) | |
101 | #define UEXTSHORT(x) ((x) & 0xffff) | |
de9b1892 | 102 | #define SEXTSHORT(x) ((short) (x)) |
c906108c SS |
103 | |
104 | static cpu_state_type cpu; | |
105 | ||
106 | int h8300hmode = 0; | |
107 | int h8300smode = 0; | |
108 | ||
109 | static int memory_size; | |
110 | ||
c906108c SS |
111 | static int |
112 | get_now () | |
113 | { | |
3b02cf92 | 114 | return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */ |
c906108c SS |
115 | } |
116 | ||
117 | static int | |
118 | now_persec () | |
119 | { | |
120 | return 1; | |
121 | } | |
122 | ||
c906108c SS |
123 | static int |
124 | bitfrom (x) | |
125 | { | |
126 | switch (x & SIZE) | |
127 | { | |
128 | case L_8: | |
129 | return SB; | |
130 | case L_16: | |
131 | return SW; | |
132 | case L_32: | |
133 | return SL; | |
134 | case L_P: | |
135 | return h8300hmode ? SL : SW; | |
136 | } | |
137 | } | |
138 | ||
0ef9643e | 139 | static unsigned int |
c906108c SS |
140 | lvalue (x, rn) |
141 | { | |
142 | switch (x / 4) | |
143 | { | |
144 | case OP_DISP: | |
145 | if (rn == 8) | |
146 | { | |
147 | return X (OP_IMM, SP); | |
148 | } | |
149 | return X (OP_REG, SP); | |
150 | ||
151 | case OP_MEM: | |
c906108c | 152 | return X (OP_MEM, SP); |
0ef9643e | 153 | |
c906108c | 154 | default: |
3b02cf92 | 155 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
156 | } |
157 | } | |
158 | ||
159 | static unsigned int | |
160 | decode (addr, data, dst) | |
161 | int addr; | |
162 | unsigned char *data; | |
163 | decoded_inst *dst; | |
164 | ||
165 | { | |
166 | int rs = 0; | |
167 | int rd = 0; | |
168 | int rdisp = 0; | |
169 | int abs = 0; | |
c906108c | 170 | int bit = 0; |
0ef9643e | 171 | int plen = 0; |
6d028502 | 172 | struct h8_opcode *q; |
c906108c | 173 | int size = 0; |
0ef9643e | 174 | |
c906108c SS |
175 | dst->dst.type = -1; |
176 | dst->src.type = -1; | |
0ef9643e JL |
177 | |
178 | /* Find the exact opcode/arg combo. */ | |
6d028502 | 179 | for (q = h8_opcodes; q->name; q++) |
c906108c | 180 | { |
6d028502 | 181 | op_type *nib = q->data.nib; |
c906108c SS |
182 | unsigned int len = 0; |
183 | ||
c906108c SS |
184 | while (1) |
185 | { | |
186 | op_type looking_for = *nib; | |
187 | int thisnib = data[len >> 1]; | |
188 | ||
189 | thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); | |
190 | ||
191 | if (looking_for < 16 && looking_for >= 0) | |
192 | { | |
193 | if (looking_for != thisnib) | |
194 | goto fail; | |
195 | } | |
196 | else | |
197 | { | |
198 | if ((int) looking_for & (int) B31) | |
199 | { | |
200 | if (!(((int) thisnib & 0x8) != 0)) | |
201 | goto fail; | |
0ef9643e JL |
202 | |
203 | looking_for = (op_type) ((int) looking_for & ~(int) B31); | |
c906108c SS |
204 | thisnib &= 0x7; |
205 | } | |
0ef9643e | 206 | |
c906108c SS |
207 | if ((int) looking_for & (int) B30) |
208 | { | |
209 | if (!(((int) thisnib & 0x8) == 0)) | |
210 | goto fail; | |
0ef9643e | 211 | |
c906108c SS |
212 | looking_for = (op_type) ((int) looking_for & ~(int) B30); |
213 | } | |
0ef9643e | 214 | |
c906108c SS |
215 | if (looking_for & DBIT) |
216 | { | |
0a17cd59 AC |
217 | /* Exclude adds/subs by looking at bit 0 and 2, and |
218 | make sure the operand size, either w or l, | |
219 | matches by looking at bit 1. */ | |
220 | if ((looking_for & 7) != (thisnib & 7)) | |
c906108c | 221 | goto fail; |
0ef9643e | 222 | |
c906108c SS |
223 | abs = (thisnib & 0x8) ? 2 : 1; |
224 | } | |
225 | else if (looking_for & (REG | IND | INC | DEC)) | |
226 | { | |
227 | if (looking_for & REG) | |
228 | { | |
0ef9643e | 229 | /* Can work out size from the register. */ |
c906108c SS |
230 | size = bitfrom (looking_for); |
231 | } | |
232 | if (looking_for & SRC) | |
0ef9643e | 233 | rs = thisnib; |
c906108c | 234 | else |
0ef9643e | 235 | rd = thisnib; |
c906108c SS |
236 | } |
237 | else if (looking_for & L_16) | |
238 | { | |
239 | abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; | |
240 | plen = 16; | |
241 | if (looking_for & (PCREL | DISP)) | |
242 | { | |
243 | abs = (short) (abs); | |
244 | } | |
245 | } | |
246 | else if (looking_for & ABSJMP) | |
247 | { | |
0ef9643e | 248 | abs = (data[1] << 16) | (data[2] << 8) | (data[3]); |
c906108c SS |
249 | } |
250 | else if (looking_for & MEMIND) | |
251 | { | |
252 | abs = data[1]; | |
253 | } | |
254 | else if (looking_for & L_32) | |
255 | { | |
256 | int i = len >> 1; | |
0ef9643e | 257 | |
c906108c SS |
258 | abs = (data[i] << 24) |
259 | | (data[i + 1] << 16) | |
260 | | (data[i + 2] << 8) | |
261 | | (data[i + 3]); | |
262 | ||
263 | plen = 32; | |
264 | } | |
265 | else if (looking_for & L_24) | |
266 | { | |
267 | int i = len >> 1; | |
0ef9643e | 268 | |
c906108c SS |
269 | abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); |
270 | plen = 24; | |
271 | } | |
272 | else if (looking_for & IGNORE) | |
273 | { | |
0ef9643e | 274 | ; |
c906108c SS |
275 | } |
276 | else if (looking_for & DISPREG) | |
277 | { | |
278 | rdisp = thisnib & 0x7; | |
279 | } | |
280 | else if (looking_for & KBIT) | |
281 | { | |
282 | switch (thisnib) | |
283 | { | |
284 | case 9: | |
285 | abs = 4; | |
286 | break; | |
287 | case 8: | |
288 | abs = 2; | |
289 | break; | |
290 | case 0: | |
291 | abs = 1; | |
292 | break; | |
0a17cd59 AC |
293 | default: |
294 | goto fail; | |
c906108c SS |
295 | } |
296 | } | |
297 | else if (looking_for & L_8) | |
298 | { | |
299 | plen = 8; | |
300 | ||
301 | if (looking_for & PCREL) | |
302 | { | |
303 | abs = SEXTCHAR (data[len >> 1]); | |
304 | } | |
305 | else if (looking_for & ABS8MEM) | |
306 | { | |
307 | plen = 8; | |
308 | abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; | |
0ef9643e | 309 | abs |= data[len >> 1] & 0xff; |
c906108c | 310 | } |
0ef9643e | 311 | else |
c906108c SS |
312 | { |
313 | abs = data[len >> 1] & 0xff; | |
314 | } | |
315 | } | |
316 | else if (looking_for & L_3) | |
317 | { | |
318 | plen = 3; | |
319 | ||
320 | bit = thisnib; | |
321 | } | |
322 | else if (looking_for == E) | |
323 | { | |
324 | dst->op = q; | |
325 | ||
0ef9643e | 326 | /* Fill in the args. */ |
c906108c SS |
327 | { |
328 | op_type *args = q->args.nib; | |
329 | int hadone = 0; | |
330 | ||
331 | while (*args != E) | |
332 | { | |
333 | int x = *args; | |
334 | int rn = (x & DST) ? rd : rs; | |
335 | ea_type *p; | |
336 | ||
337 | if (x & DST) | |
0ef9643e | 338 | p = &(dst->dst); |
c906108c | 339 | else |
0ef9643e | 340 | p = &(dst->src); |
c906108c | 341 | |
0ef9643e | 342 | if (x & L_3) |
c906108c SS |
343 | { |
344 | p->type = X (OP_IMM, size); | |
345 | p->literal = bit; | |
346 | } | |
347 | else if (x & (IMM | KBIT | DBIT)) | |
348 | { | |
349 | p->type = X (OP_IMM, size); | |
350 | p->literal = abs; | |
351 | } | |
352 | else if (x & REG) | |
353 | { | |
6d028502 KH |
354 | /* Reset the size. |
355 | Some ops (like mul) have two sizes. */ | |
c906108c SS |
356 | |
357 | size = bitfrom (x); | |
358 | p->type = X (OP_REG, size); | |
359 | p->reg = rn; | |
360 | } | |
361 | else if (x & INC) | |
362 | { | |
363 | p->type = X (OP_INC, size); | |
364 | p->reg = rn & 0x7; | |
365 | } | |
366 | else if (x & DEC) | |
367 | { | |
368 | p->type = X (OP_DEC, size); | |
369 | p->reg = rn & 0x7; | |
370 | } | |
371 | else if (x & IND) | |
372 | { | |
373 | p->type = X (OP_DISP, size); | |
374 | p->reg = rn & 0x7; | |
375 | p->literal = 0; | |
376 | } | |
377 | else if (x & (ABS | ABSJMP | ABS8MEM)) | |
378 | { | |
379 | p->type = X (OP_DISP, size); | |
380 | p->literal = abs; | |
381 | p->reg = 8; | |
382 | } | |
383 | else if (x & MEMIND) | |
384 | { | |
385 | p->type = X (OP_MEM, size); | |
386 | p->literal = abs; | |
387 | } | |
388 | else if (x & PCREL) | |
389 | { | |
390 | p->type = X (OP_PCREL, size); | |
391 | p->literal = abs + addr + 2; | |
392 | if (x & L_16) | |
393 | p->literal += 2; | |
394 | } | |
395 | else if (x & ABSJMP) | |
396 | { | |
397 | p->type = X (OP_IMM, SP); | |
398 | p->literal = abs; | |
399 | } | |
400 | else if (x & DISP) | |
401 | { | |
402 | p->type = X (OP_DISP, size); | |
403 | p->literal = abs; | |
404 | p->reg = rdisp & 0x7; | |
405 | } | |
406 | else if (x & CCR) | |
407 | { | |
408 | p->type = OP_CCR; | |
409 | } | |
410 | else | |
411 | printf ("Hmmmm %x", x); | |
412 | ||
413 | args++; | |
414 | } | |
415 | } | |
416 | ||
0ef9643e JL |
417 | /* But a jmp or a jsr gets automagically lvalued, |
418 | since we branch to their address not their | |
419 | contents. */ | |
c906108c SS |
420 | if (q->how == O (O_JSR, SB) |
421 | || q->how == O (O_JMP, SB)) | |
422 | { | |
423 | dst->src.type = lvalue (dst->src.type, dst->src.reg); | |
424 | } | |
425 | ||
426 | if (dst->dst.type == -1) | |
427 | dst->dst = dst->src; | |
428 | ||
429 | dst->opcode = q->how; | |
430 | dst->cycles = q->time; | |
431 | ||
0ef9643e | 432 | /* And a jsr to 0xc4 is turned into a magic trap. */ |
c906108c SS |
433 | |
434 | if (dst->opcode == O (O_JSR, SB)) | |
435 | { | |
436 | if (dst->src.literal == 0xc4) | |
437 | { | |
438 | dst->opcode = O (O_SYSCALL, SB); | |
439 | } | |
440 | } | |
441 | ||
442 | dst->next_pc = addr + len / 2; | |
443 | return; | |
444 | } | |
445 | else | |
98ecb0a7 | 446 | printf ("Don't understand %x \n", looking_for); |
c906108c SS |
447 | } |
448 | ||
449 | len++; | |
450 | nib++; | |
451 | } | |
452 | ||
453 | fail: | |
6d028502 | 454 | ; |
c906108c SS |
455 | } |
456 | ||
0ef9643e | 457 | /* Fell off the end. */ |
c906108c SS |
458 | dst->opcode = O (O_ILL, SB); |
459 | } | |
460 | ||
c906108c SS |
461 | static void |
462 | compile (pc) | |
463 | { | |
464 | int idx; | |
465 | ||
2ea716f6 | 466 | /* Find the next cache entry to use. */ |
c906108c SS |
467 | idx = cpu.cache_top + 1; |
468 | cpu.compiles++; | |
469 | if (idx >= cpu.csize) | |
470 | { | |
471 | idx = 1; | |
472 | } | |
473 | cpu.cache_top = idx; | |
474 | ||
2ea716f6 | 475 | /* Throw away its old meaning. */ |
c906108c SS |
476 | cpu.cache_idx[cpu.cache[idx].oldpc] = 0; |
477 | ||
2ea716f6 | 478 | /* Set to new address. */ |
c906108c SS |
479 | cpu.cache[idx].oldpc = pc; |
480 | ||
2ea716f6 | 481 | /* Fill in instruction info. */ |
c906108c SS |
482 | decode (pc, cpu.memory + pc, cpu.cache + idx); |
483 | ||
2ea716f6 | 484 | /* Point to new cache entry. */ |
c906108c SS |
485 | cpu.cache_idx[pc] = idx; |
486 | } | |
487 | ||
488 | ||
489 | static unsigned char *breg[18]; | |
490 | static unsigned short *wreg[18]; | |
491 | static unsigned int *lreg[18]; | |
492 | ||
493 | #define GET_B_REG(x) *(breg[x]) | |
494 | #define SET_B_REG(x,y) (*(breg[x])) = (y) | |
495 | #define GET_W_REG(x) *(wreg[x]) | |
496 | #define SET_W_REG(x,y) (*(wreg[x])) = (y) | |
497 | ||
498 | #define GET_L_REG(x) *(lreg[x]) | |
499 | #define SET_L_REG(x,y) (*(lreg[x])) = (y) | |
500 | ||
501 | #define GET_MEMORY_L(x) \ | |
502 | (x < memory_size \ | |
503 | ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ | |
504 | | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ | |
505 | : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ | |
506 | | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) | |
507 | ||
508 | #define GET_MEMORY_W(x) \ | |
509 | (x < memory_size \ | |
510 | ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ | |
511 | : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) | |
512 | ||
513 | ||
514 | #define GET_MEMORY_B(x) \ | |
515 | (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) | |
516 | ||
517 | #define SET_MEMORY_L(x,y) \ | |
518 | { register unsigned char *_p; register int __y = y; \ | |
519 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
520 | _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ | |
521 | _p[2] = (__y)>>8; _p[3] = (__y)>>0;} | |
522 | ||
523 | #define SET_MEMORY_W(x,y) \ | |
524 | { register unsigned char *_p; register int __y = y; \ | |
525 | _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ | |
526 | _p[0] = (__y)>>8; _p[1] =(__y);} | |
527 | ||
528 | #define SET_MEMORY_B(x,y) \ | |
529 | (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) | |
530 | ||
531 | int | |
532 | fetch (arg, n) | |
533 | ea_type *arg; | |
534 | { | |
535 | int rn = arg->reg; | |
536 | int abs = arg->literal; | |
537 | int r; | |
538 | int t; | |
539 | ||
540 | switch (arg->type) | |
541 | { | |
542 | case X (OP_REG, SB): | |
543 | return GET_B_REG (rn); | |
544 | case X (OP_REG, SW): | |
545 | return GET_W_REG (rn); | |
546 | case X (OP_REG, SL): | |
547 | return GET_L_REG (rn); | |
548 | case X (OP_IMM, SB): | |
549 | case X (OP_IMM, SW): | |
550 | case X (OP_IMM, SL): | |
551 | return abs; | |
552 | case X (OP_DEC, SB): | |
553 | abort (); | |
554 | ||
555 | case X (OP_INC, SB): | |
556 | t = GET_L_REG (rn); | |
557 | t &= cpu.mask; | |
558 | r = GET_MEMORY_B (t); | |
559 | t++; | |
560 | t = t & cpu.mask; | |
561 | SET_L_REG (rn, t); | |
562 | return r; | |
563 | break; | |
564 | case X (OP_INC, SW): | |
565 | t = GET_L_REG (rn); | |
566 | t &= cpu.mask; | |
567 | r = GET_MEMORY_W (t); | |
568 | t += 2; | |
569 | t = t & cpu.mask; | |
570 | SET_L_REG (rn, t); | |
571 | return r; | |
572 | case X (OP_INC, SL): | |
573 | t = GET_L_REG (rn); | |
574 | t &= cpu.mask; | |
575 | r = GET_MEMORY_L (t); | |
576 | ||
577 | t += 4; | |
578 | t = t & cpu.mask; | |
579 | SET_L_REG (rn, t); | |
580 | return r; | |
581 | ||
582 | case X (OP_DISP, SB): | |
583 | t = GET_L_REG (rn) + abs; | |
584 | t &= cpu.mask; | |
585 | return GET_MEMORY_B (t); | |
586 | ||
587 | case X (OP_DISP, SW): | |
588 | t = GET_L_REG (rn) + abs; | |
589 | t &= cpu.mask; | |
590 | return GET_MEMORY_W (t); | |
591 | ||
592 | case X (OP_DISP, SL): | |
593 | t = GET_L_REG (rn) + abs; | |
594 | t &= cpu.mask; | |
595 | return GET_MEMORY_L (t); | |
596 | ||
597 | case X (OP_MEM, SL): | |
598 | t = GET_MEMORY_L (abs); | |
599 | t &= cpu.mask; | |
600 | return t; | |
601 | ||
602 | case X (OP_MEM, SW): | |
603 | t = GET_MEMORY_W (abs); | |
604 | t &= cpu.mask; | |
605 | return t; | |
606 | ||
607 | default: | |
3b02cf92 | 608 | abort (); /* ?? May be something more usefull? */ |
c906108c SS |
609 | |
610 | } | |
611 | } | |
612 | ||
613 | ||
de9b1892 | 614 | static void |
c906108c SS |
615 | store (arg, n) |
616 | ea_type *arg; | |
617 | int n; | |
618 | { | |
619 | int rn = arg->reg; | |
620 | int abs = arg->literal; | |
621 | int t; | |
622 | ||
623 | switch (arg->type) | |
624 | { | |
625 | case X (OP_REG, SB): | |
626 | SET_B_REG (rn, n); | |
627 | break; | |
628 | case X (OP_REG, SW): | |
629 | SET_W_REG (rn, n); | |
630 | break; | |
631 | case X (OP_REG, SL): | |
632 | SET_L_REG (rn, n); | |
633 | break; | |
634 | ||
635 | case X (OP_DEC, SB): | |
636 | t = GET_L_REG (rn) - 1; | |
637 | t &= cpu.mask; | |
638 | SET_L_REG (rn, t); | |
639 | SET_MEMORY_B (t, n); | |
640 | ||
641 | break; | |
642 | case X (OP_DEC, SW): | |
643 | t = (GET_L_REG (rn) - 2) & cpu.mask; | |
644 | SET_L_REG (rn, t); | |
645 | SET_MEMORY_W (t, n); | |
646 | break; | |
647 | ||
648 | case X (OP_DEC, SL): | |
649 | t = (GET_L_REG (rn) - 4) & cpu.mask; | |
650 | SET_L_REG (rn, t); | |
651 | SET_MEMORY_L (t, n); | |
652 | break; | |
653 | ||
654 | case X (OP_DISP, SB): | |
655 | t = GET_L_REG (rn) + abs; | |
656 | t &= cpu.mask; | |
657 | SET_MEMORY_B (t, n); | |
658 | break; | |
659 | ||
660 | case X (OP_DISP, SW): | |
661 | t = GET_L_REG (rn) + abs; | |
662 | t &= cpu.mask; | |
663 | SET_MEMORY_W (t, n); | |
664 | break; | |
665 | ||
666 | case X (OP_DISP, SL): | |
667 | t = GET_L_REG (rn) + abs; | |
668 | t &= cpu.mask; | |
669 | SET_MEMORY_L (t, n); | |
670 | break; | |
671 | default: | |
672 | abort (); | |
673 | } | |
674 | } | |
675 | ||
676 | ||
677 | static union | |
678 | { | |
679 | short int i; | |
680 | struct | |
681 | { | |
682 | char low; | |
683 | char high; | |
684 | } | |
685 | u; | |
686 | } | |
687 | ||
688 | littleendian; | |
689 | ||
de9b1892 | 690 | static void |
c906108c SS |
691 | init_pointers () |
692 | { | |
693 | static int init; | |
694 | ||
695 | if (!init) | |
696 | { | |
697 | int i; | |
698 | ||
699 | init = 1; | |
700 | littleendian.i = 1; | |
701 | ||
702 | if (h8300hmode) | |
703 | memory_size = H8300H_MSIZE; | |
704 | else | |
705 | memory_size = H8300_MSIZE; | |
706 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
707 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
708 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
709 | ||
2ea716f6 | 710 | /* `msize' must be a power of two. */ |
c906108c SS |
711 | if ((memory_size & (memory_size - 1)) != 0) |
712 | abort (); | |
713 | cpu.mask = memory_size - 1; | |
714 | ||
715 | for (i = 0; i < 9; i++) | |
716 | { | |
717 | cpu.regs[i] = 0; | |
718 | } | |
719 | ||
720 | for (i = 0; i < 8; i++) | |
721 | { | |
722 | unsigned char *p = (unsigned char *) (cpu.regs + i); | |
723 | unsigned char *e = (unsigned char *) (cpu.regs + i + 1); | |
724 | unsigned short *q = (unsigned short *) (cpu.regs + i); | |
725 | unsigned short *u = (unsigned short *) (cpu.regs + i + 1); | |
726 | cpu.regs[i] = 0x00112233; | |
727 | while (p < e) | |
728 | { | |
729 | if (*p == 0x22) | |
730 | { | |
731 | breg[i] = p; | |
732 | } | |
733 | if (*p == 0x33) | |
734 | { | |
735 | breg[i + 8] = p; | |
736 | } | |
737 | p++; | |
738 | } | |
739 | while (q < u) | |
740 | { | |
741 | if (*q == 0x2233) | |
742 | { | |
743 | wreg[i] = q; | |
744 | } | |
745 | if (*q == 0x0011) | |
746 | { | |
747 | wreg[i + 8] = q; | |
748 | } | |
749 | q++; | |
750 | } | |
751 | cpu.regs[i] = 0; | |
752 | lreg[i] = &cpu.regs[i]; | |
753 | } | |
754 | ||
755 | lreg[8] = &cpu.regs[8]; | |
756 | ||
2ea716f6 | 757 | /* Initialize the seg registers. */ |
c906108c SS |
758 | if (!cpu.cache) |
759 | sim_set_simcache_size (CSIZE); | |
760 | } | |
761 | } | |
762 | ||
763 | static void | |
764 | control_c (sig, code, scp, addr) | |
765 | int sig; | |
766 | int code; | |
767 | char *scp; | |
768 | char *addr; | |
769 | { | |
770 | cpu.state = SIM_STATE_STOPPED; | |
771 | cpu.exception = SIGINT; | |
772 | } | |
773 | ||
774 | #define C (c != 0) | |
775 | #define Z (nz == 0) | |
776 | #define V (v != 0) | |
777 | #define N (n != 0) | |
778 | ||
779 | static int | |
780 | mop (code, bsize, sign) | |
781 | decoded_inst *code; | |
782 | int bsize; | |
783 | int sign; | |
784 | { | |
785 | int multiplier; | |
786 | int multiplicand; | |
787 | int result; | |
788 | int n, nz; | |
789 | ||
790 | if (sign) | |
791 | { | |
792 | multiplicand = | |
793 | bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : | |
794 | SEXTSHORT (GET_W_REG (code->dst.reg)); | |
795 | multiplier = | |
796 | bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : | |
797 | SEXTSHORT (GET_W_REG (code->src.reg)); | |
798 | } | |
799 | else | |
800 | { | |
801 | multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : | |
802 | UEXTSHORT (GET_W_REG (code->dst.reg)); | |
803 | multiplier = | |
804 | bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : | |
805 | UEXTSHORT (GET_W_REG (code->src.reg)); | |
806 | ||
807 | } | |
808 | result = multiplier * multiplicand; | |
809 | ||
810 | if (sign) | |
811 | { | |
812 | n = result & (bsize ? 0x8000 : 0x80000000); | |
813 | nz = result & (bsize ? 0xffff : 0xffffffff); | |
814 | } | |
815 | if (bsize) | |
816 | { | |
817 | SET_W_REG (code->dst.reg, result); | |
818 | } | |
819 | else | |
820 | { | |
821 | SET_L_REG (code->dst.reg, result); | |
822 | } | |
de9b1892 KH |
823 | #if 0 |
824 | return ((n == 1) << 1) | (nz == 1); | |
825 | #endif | |
c906108c SS |
826 | } |
827 | ||
828 | #define ONOT(name, how) \ | |
829 | case O(name, SB): \ | |
830 | { \ | |
831 | int t; \ | |
832 | int hm = 0x80; \ | |
833 | rd = GET_B_REG (code->src.reg); \ | |
834 | how; \ | |
835 | goto shift8; \ | |
836 | } \ | |
837 | case O(name, SW): \ | |
838 | { \ | |
839 | int t; \ | |
840 | int hm = 0x8000; \ | |
841 | rd = GET_W_REG (code->src.reg); \ | |
842 | how; \ | |
843 | goto shift16; \ | |
844 | } \ | |
845 | case O(name, SL): \ | |
846 | { \ | |
847 | int t; \ | |
848 | int hm = 0x80000000; \ | |
849 | rd = GET_L_REG (code->src.reg); \ | |
850 | how; \ | |
851 | goto shift32; \ | |
852 | } | |
853 | ||
854 | #define OSHIFTS(name, how1, how2) \ | |
855 | case O(name, SB): \ | |
856 | { \ | |
857 | int t; \ | |
858 | int hm = 0x80; \ | |
859 | rd = GET_B_REG (code->src.reg); \ | |
860 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
861 | { \ | |
862 | how1; \ | |
863 | } \ | |
864 | else \ | |
865 | { \ | |
866 | how2; \ | |
867 | } \ | |
868 | goto shift8; \ | |
869 | } \ | |
870 | case O(name, SW): \ | |
871 | { \ | |
872 | int t; \ | |
873 | int hm = 0x8000; \ | |
874 | rd = GET_W_REG (code->src.reg); \ | |
875 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
876 | { \ | |
877 | how1; \ | |
878 | } \ | |
879 | else \ | |
880 | { \ | |
881 | how2; \ | |
882 | } \ | |
883 | goto shift16; \ | |
884 | } \ | |
885 | case O(name, SL): \ | |
886 | { \ | |
887 | int t; \ | |
888 | int hm = 0x80000000; \ | |
889 | rd = GET_L_REG (code->src.reg); \ | |
890 | if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ | |
891 | { \ | |
892 | how1; \ | |
893 | } \ | |
894 | else \ | |
895 | { \ | |
896 | how2; \ | |
897 | } \ | |
898 | goto shift32; \ | |
899 | } | |
900 | ||
901 | #define OBITOP(name,f, s, op) \ | |
902 | case O(name, SB): \ | |
903 | { \ | |
904 | int m; \ | |
905 | int b; \ | |
906 | if (f) ea = fetch (&code->dst); \ | |
907 | m=1<< fetch(&code->src); \ | |
908 | op; \ | |
909 | if(s) store (&code->dst,ea); goto next; \ | |
910 | } | |
911 | ||
912 | int | |
913 | sim_stop (sd) | |
914 | SIM_DESC sd; | |
915 | { | |
916 | cpu.state = SIM_STATE_STOPPED; | |
917 | cpu.exception = SIGINT; | |
918 | return 1; | |
919 | } | |
920 | ||
921 | void | |
922 | sim_resume (sd, step, siggnal) | |
923 | SIM_DESC sd; | |
924 | { | |
925 | static int init1; | |
926 | int cycles = 0; | |
927 | int insts = 0; | |
928 | int tick_start = get_now (); | |
929 | void (*prev) (); | |
930 | int poll_count = 0; | |
931 | int res; | |
932 | int tmp; | |
933 | int rd; | |
934 | int ea; | |
935 | int bit; | |
936 | int pc; | |
937 | int c, nz, v, n; | |
938 | int oldmask; | |
939 | init_pointers (); | |
940 | ||
941 | prev = signal (SIGINT, control_c); | |
942 | ||
943 | if (step) | |
944 | { | |
945 | cpu.state = SIM_STATE_STOPPED; | |
946 | cpu.exception = SIGTRAP; | |
947 | } | |
948 | else | |
949 | { | |
950 | cpu.state = SIM_STATE_RUNNING; | |
951 | cpu.exception = 0; | |
952 | } | |
953 | ||
954 | pc = cpu.pc; | |
955 | ||
956 | /* The PC should never be odd. */ | |
957 | if (pc & 0x1) | |
958 | abort (); | |
959 | ||
960 | GETSR (); | |
961 | oldmask = cpu.mask; | |
962 | if (!h8300hmode) | |
963 | cpu.mask = 0xffff; | |
964 | do | |
965 | { | |
966 | int cidx; | |
967 | decoded_inst *code; | |
968 | ||
969 | top: | |
970 | cidx = cpu.cache_idx[pc]; | |
971 | code = cpu.cache + cidx; | |
972 | ||
973 | ||
974 | #define ALUOP(STORE, NAME, HOW) \ | |
975 | case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ | |
976 | case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ | |
977 | case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; | |
978 | ||
979 | ||
980 | #define LOGOP(NAME, HOW) \ | |
981 | case O(NAME,SB): HOW; goto log8;\ | |
982 | case O(NAME, SW): HOW; goto log16;\ | |
983 | case O(NAME,SL): HOW; goto log32; | |
984 | ||
985 | ||
986 | ||
987 | #if ADEBUG | |
988 | if (debug) | |
989 | { | |
990 | printf ("%x %d %s\n", pc, code->opcode, | |
991 | code->op ? code->op->name : "**"); | |
992 | } | |
993 | cpu.stats[code->opcode]++; | |
994 | ||
995 | #endif | |
996 | ||
3b02cf92 AV |
997 | if (code->opcode) |
998 | { | |
999 | cycles += code->cycles; | |
1000 | insts++; | |
1001 | } | |
1002 | ||
c906108c SS |
1003 | switch (code->opcode) |
1004 | { | |
1005 | case 0: | |
1006 | /* | |
1007 | * This opcode is a fake for when we get to an | |
1008 | * instruction which hasnt been compiled | |
1009 | */ | |
1010 | compile (pc); | |
1011 | goto top; | |
1012 | break; | |
1013 | ||
1014 | ||
1015 | case O (O_SUBX, SB): | |
1016 | rd = fetch (&code->dst); | |
1017 | ea = fetch (&code->src); | |
1018 | ea = -(ea + C); | |
1019 | res = rd + ea; | |
1020 | goto alu8; | |
1021 | ||
1022 | case O (O_ADDX, SB): | |
1023 | rd = fetch (&code->dst); | |
1024 | ea = fetch (&code->src); | |
1025 | ea = C + ea; | |
1026 | res = rd + ea; | |
1027 | goto alu8; | |
1028 | ||
1029 | #define EA ea = fetch(&code->src); | |
1030 | #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); | |
1031 | ||
1032 | ALUOP (1, O_SUB, RD_EA; | |
1033 | ea = -ea; | |
1034 | res = rd + ea); | |
1035 | ALUOP (1, O_NEG, EA; | |
1036 | ea = -ea; | |
1037 | rd = 0; | |
1038 | res = rd + ea); | |
1039 | ||
1040 | case O (O_ADD, SB): | |
1041 | rd = GET_B_REG (code->dst.reg); | |
1042 | ea = fetch (&code->src); | |
1043 | res = rd + ea; | |
1044 | goto alu8; | |
1045 | case O (O_ADD, SW): | |
1046 | rd = GET_W_REG (code->dst.reg); | |
1047 | ea = fetch (&code->src); | |
1048 | res = rd + ea; | |
1049 | goto alu16; | |
1050 | case O (O_ADD, SL): | |
1051 | rd = GET_L_REG (code->dst.reg); | |
1052 | ea = fetch (&code->src); | |
1053 | res = rd + ea; | |
1054 | goto alu32; | |
1055 | ||
1056 | ||
1057 | LOGOP (O_AND, RD_EA; | |
1058 | res = rd & ea); | |
1059 | ||
1060 | LOGOP (O_OR, RD_EA; | |
1061 | res = rd | ea); | |
1062 | ||
1063 | LOGOP (O_XOR, RD_EA; | |
1064 | res = rd ^ ea); | |
1065 | ||
1066 | ||
1067 | case O (O_MOV_TO_MEM, SB): | |
1068 | res = GET_B_REG (code->src.reg); | |
1069 | goto log8; | |
1070 | case O (O_MOV_TO_MEM, SW): | |
1071 | res = GET_W_REG (code->src.reg); | |
1072 | goto log16; | |
1073 | case O (O_MOV_TO_MEM, SL): | |
1074 | res = GET_L_REG (code->src.reg); | |
1075 | goto log32; | |
1076 | ||
1077 | ||
1078 | case O (O_MOV_TO_REG, SB): | |
1079 | res = fetch (&code->src); | |
1080 | SET_B_REG (code->dst.reg, res); | |
1081 | goto just_flags_log8; | |
1082 | case O (O_MOV_TO_REG, SW): | |
1083 | res = fetch (&code->src); | |
1084 | SET_W_REG (code->dst.reg, res); | |
1085 | goto just_flags_log16; | |
1086 | case O (O_MOV_TO_REG, SL): | |
1087 | res = fetch (&code->src); | |
1088 | SET_L_REG (code->dst.reg, res); | |
1089 | goto just_flags_log32; | |
1090 | ||
1091 | ||
1092 | case O (O_ADDS, SL): | |
1093 | SET_L_REG (code->dst.reg, | |
1094 | GET_L_REG (code->dst.reg) | |
1095 | + code->src.literal); | |
1096 | ||
1097 | goto next; | |
1098 | ||
1099 | case O (O_SUBS, SL): | |
1100 | SET_L_REG (code->dst.reg, | |
1101 | GET_L_REG (code->dst.reg) | |
1102 | - code->src.literal); | |
1103 | goto next; | |
1104 | ||
1105 | case O (O_CMP, SB): | |
1106 | rd = fetch (&code->dst); | |
1107 | ea = fetch (&code->src); | |
1108 | ea = -ea; | |
1109 | res = rd + ea; | |
1110 | goto just_flags_alu8; | |
1111 | ||
1112 | case O (O_CMP, SW): | |
1113 | rd = fetch (&code->dst); | |
1114 | ea = fetch (&code->src); | |
1115 | ea = -ea; | |
1116 | res = rd + ea; | |
1117 | goto just_flags_alu16; | |
1118 | ||
1119 | case O (O_CMP, SL): | |
1120 | rd = fetch (&code->dst); | |
1121 | ea = fetch (&code->src); | |
1122 | ea = -ea; | |
1123 | res = rd + ea; | |
1124 | goto just_flags_alu32; | |
1125 | ||
1126 | ||
1127 | case O (O_DEC, SB): | |
1128 | rd = GET_B_REG (code->src.reg); | |
1129 | ea = -1; | |
1130 | res = rd + ea; | |
1131 | SET_B_REG (code->src.reg, res); | |
1132 | goto just_flags_inc8; | |
1133 | ||
1134 | case O (O_DEC, SW): | |
1135 | rd = GET_W_REG (code->dst.reg); | |
1136 | ea = -code->src.literal; | |
1137 | res = rd + ea; | |
1138 | SET_W_REG (code->dst.reg, res); | |
1139 | goto just_flags_inc16; | |
1140 | ||
1141 | case O (O_DEC, SL): | |
1142 | rd = GET_L_REG (code->dst.reg); | |
1143 | ea = -code->src.literal; | |
1144 | res = rd + ea; | |
1145 | SET_L_REG (code->dst.reg, res); | |
1146 | goto just_flags_inc32; | |
1147 | ||
1148 | ||
1149 | case O (O_INC, SB): | |
1150 | rd = GET_B_REG (code->src.reg); | |
1151 | ea = 1; | |
1152 | res = rd + ea; | |
1153 | SET_B_REG (code->src.reg, res); | |
1154 | goto just_flags_inc8; | |
1155 | ||
1156 | case O (O_INC, SW): | |
1157 | rd = GET_W_REG (code->dst.reg); | |
1158 | ea = code->src.literal; | |
1159 | res = rd + ea; | |
1160 | SET_W_REG (code->dst.reg, res); | |
1161 | goto just_flags_inc16; | |
1162 | ||
1163 | case O (O_INC, SL): | |
1164 | rd = GET_L_REG (code->dst.reg); | |
1165 | ea = code->src.literal; | |
1166 | res = rd + ea; | |
1167 | SET_L_REG (code->dst.reg, res); | |
1168 | goto just_flags_inc32; | |
1169 | ||
1170 | ||
1171 | #define GET_CCR(x) BUILDSR();x = cpu.ccr | |
1172 | ||
1173 | case O (O_ANDC, SB): | |
1174 | GET_CCR (rd); | |
1175 | ea = code->src.literal; | |
1176 | res = rd & ea; | |
1177 | goto setc; | |
1178 | ||
1179 | case O (O_ORC, SB): | |
1180 | GET_CCR (rd); | |
1181 | ea = code->src.literal; | |
1182 | res = rd | ea; | |
1183 | goto setc; | |
1184 | ||
1185 | case O (O_XORC, SB): | |
1186 | GET_CCR (rd); | |
1187 | ea = code->src.literal; | |
1188 | res = rd ^ ea; | |
1189 | goto setc; | |
1190 | ||
1191 | ||
1192 | case O (O_BRA, SB): | |
1193 | if (1) | |
1194 | goto condtrue; | |
1195 | goto next; | |
1196 | ||
1197 | case O (O_BRN, SB): | |
1198 | if (0) | |
1199 | goto condtrue; | |
1200 | goto next; | |
1201 | ||
1202 | case O (O_BHI, SB): | |
1203 | if ((C || Z) == 0) | |
1204 | goto condtrue; | |
1205 | goto next; | |
1206 | ||
1207 | ||
1208 | case O (O_BLS, SB): | |
1209 | if ((C || Z)) | |
1210 | goto condtrue; | |
1211 | goto next; | |
1212 | ||
1213 | case O (O_BCS, SB): | |
1214 | if ((C == 1)) | |
1215 | goto condtrue; | |
1216 | goto next; | |
1217 | ||
1218 | case O (O_BCC, SB): | |
1219 | if ((C == 0)) | |
1220 | goto condtrue; | |
1221 | goto next; | |
1222 | ||
1223 | case O (O_BEQ, SB): | |
1224 | if (Z) | |
1225 | goto condtrue; | |
1226 | goto next; | |
1227 | case O (O_BGT, SB): | |
1228 | if (((Z || (N ^ V)) == 0)) | |
1229 | goto condtrue; | |
1230 | goto next; | |
1231 | ||
1232 | ||
1233 | case O (O_BLE, SB): | |
1234 | if (((Z || (N ^ V)) == 1)) | |
1235 | goto condtrue; | |
1236 | goto next; | |
1237 | ||
1238 | case O (O_BGE, SB): | |
1239 | if ((N ^ V) == 0) | |
1240 | goto condtrue; | |
1241 | goto next; | |
1242 | case O (O_BLT, SB): | |
1243 | if ((N ^ V)) | |
1244 | goto condtrue; | |
1245 | goto next; | |
1246 | case O (O_BMI, SB): | |
1247 | if ((N)) | |
1248 | goto condtrue; | |
1249 | goto next; | |
1250 | case O (O_BNE, SB): | |
1251 | if ((Z == 0)) | |
1252 | goto condtrue; | |
1253 | goto next; | |
1254 | ||
1255 | case O (O_BPL, SB): | |
1256 | if (N == 0) | |
1257 | goto condtrue; | |
1258 | goto next; | |
1259 | case O (O_BVC, SB): | |
1260 | if ((V == 0)) | |
1261 | goto condtrue; | |
1262 | goto next; | |
1263 | case O (O_BVS, SB): | |
1264 | if ((V == 1)) | |
1265 | goto condtrue; | |
1266 | goto next; | |
1267 | ||
1268 | case O (O_SYSCALL, SB): | |
1269 | { | |
1270 | char c = cpu.regs[2]; | |
1271 | sim_callback->write_stdout (sim_callback, &c, 1); | |
1272 | } | |
1273 | goto next; | |
1274 | ||
1275 | ONOT (O_NOT, rd = ~rd; v = 0;); | |
1276 | OSHIFTS (O_SHLL, | |
1277 | c = rd & hm; v = 0; rd <<= 1, | |
1278 | c = rd & (hm >> 1); v = 0; rd <<= 2); | |
1279 | OSHIFTS (O_SHLR, | |
1280 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, | |
1281 | c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); | |
1282 | OSHIFTS (O_SHAL, | |
1283 | c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, | |
1284 | c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); | |
1285 | OSHIFTS (O_SHAR, | |
1286 | t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, | |
1287 | t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); | |
1288 | OSHIFTS (O_ROTL, | |
1289 | c = rd & hm; v = 0; rd <<= 1; rd |= C, | |
1290 | c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); | |
1291 | OSHIFTS (O_ROTR, | |
1292 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, | |
1293 | c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); | |
1294 | OSHIFTS (O_ROTXL, | |
1295 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, | |
1296 | t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); | |
1297 | OSHIFTS (O_ROTXR, | |
1298 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, | |
1299 | t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); | |
1300 | ||
1301 | case O (O_JMP, SB): | |
1302 | { | |
1303 | pc = fetch (&code->src); | |
1304 | goto end; | |
1305 | ||
1306 | } | |
1307 | ||
1308 | case O (O_JSR, SB): | |
1309 | { | |
1310 | int tmp; | |
1311 | pc = fetch (&code->src); | |
1312 | call: | |
1313 | tmp = cpu.regs[7]; | |
1314 | ||
1315 | if (h8300hmode) | |
1316 | { | |
1317 | tmp -= 4; | |
1318 | SET_MEMORY_L (tmp, code->next_pc); | |
1319 | } | |
1320 | else | |
1321 | { | |
1322 | tmp -= 2; | |
1323 | SET_MEMORY_W (tmp, code->next_pc); | |
1324 | } | |
1325 | cpu.regs[7] = tmp; | |
1326 | ||
1327 | goto end; | |
1328 | } | |
1329 | case O (O_BSR, SB): | |
1330 | pc = code->src.literal; | |
1331 | goto call; | |
1332 | ||
1333 | case O (O_RTS, SN): | |
1334 | { | |
1335 | int tmp; | |
1336 | ||
1337 | tmp = cpu.regs[7]; | |
1338 | ||
1339 | if (h8300hmode) | |
1340 | { | |
1341 | pc = GET_MEMORY_L (tmp); | |
1342 | tmp += 4; | |
1343 | } | |
1344 | else | |
1345 | { | |
1346 | pc = GET_MEMORY_W (tmp); | |
1347 | tmp += 2; | |
1348 | } | |
1349 | ||
1350 | cpu.regs[7] = tmp; | |
1351 | goto end; | |
1352 | } | |
1353 | ||
1354 | case O (O_ILL, SB): | |
1355 | cpu.state = SIM_STATE_STOPPED; | |
1356 | cpu.exception = SIGILL; | |
1357 | goto end; | |
1358 | case O (O_SLEEP, SN): | |
c906108c SS |
1359 | /* FIXME: Doesn't this break for breakpoints when r0 |
1360 | contains just the right (er, wrong) value? */ | |
1361 | cpu.state = SIM_STATE_STOPPED; | |
97ee9e5a FCE |
1362 | /* The format of r0 is defined by target newlib. Expand |
1363 | the macros here instead of looking for .../sys/wait.h. */ | |
1364 | #define SIM_WIFEXITED(v) (((v) & 0xff) == 0) | |
1365 | #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f)) | |
1366 | if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0])) | |
c906108c SS |
1367 | cpu.exception = SIGILL; |
1368 | else | |
1369 | cpu.exception = SIGTRAP; | |
c906108c SS |
1370 | goto end; |
1371 | case O (O_BPT, SN): | |
1372 | cpu.state = SIM_STATE_STOPPED; | |
1373 | cpu.exception = SIGTRAP; | |
1374 | goto end; | |
1375 | ||
1376 | OBITOP (O_BNOT, 1, 1, ea ^= m); | |
1377 | OBITOP (O_BTST, 1, 0, nz = ea & m); | |
1378 | OBITOP (O_BCLR, 1, 1, ea &= ~m); | |
1379 | OBITOP (O_BSET, 1, 1, ea |= m); | |
1380 | OBITOP (O_BLD, 1, 0, c = ea & m); | |
1381 | OBITOP (O_BILD, 1, 0, c = !(ea & m)); | |
1382 | OBITOP (O_BST, 1, 1, ea &= ~m; | |
1383 | if (C) ea |= m); | |
1384 | OBITOP (O_BIST, 1, 1, ea &= ~m; | |
1385 | if (!C) ea |= m); | |
1386 | OBITOP (O_BAND, 1, 0, c = (ea & m) && C); | |
1387 | OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); | |
1388 | OBITOP (O_BOR, 1, 0, c = (ea & m) || C); | |
1389 | OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); | |
1390 | OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); | |
1391 | OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); | |
1392 | ||
de9b1892 KH |
1393 | #define MOP(bsize, signed) \ |
1394 | mop (code, bsize, signed); \ | |
1395 | goto next; | |
c906108c SS |
1396 | |
1397 | case O (O_MULS, SB): | |
1398 | MOP (1, 1); | |
1399 | break; | |
1400 | case O (O_MULS, SW): | |
1401 | MOP (0, 1); | |
1402 | break; | |
1403 | case O (O_MULU, SB): | |
1404 | MOP (1, 0); | |
1405 | break; | |
1406 | case O (O_MULU, SW): | |
1407 | MOP (0, 0); | |
1408 | break; | |
1409 | ||
1410 | ||
1411 | case O (O_DIVU, SB): | |
1412 | { | |
1413 | rd = GET_W_REG (code->dst.reg); | |
1414 | ea = GET_B_REG (code->src.reg); | |
1415 | if (ea) | |
1416 | { | |
de9b1892 KH |
1417 | tmp = (unsigned) rd % ea; |
1418 | rd = (unsigned) rd / ea; | |
c906108c SS |
1419 | } |
1420 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1421 | n = ea & 0x80; | |
1422 | nz = ea & 0xff; | |
1423 | ||
1424 | goto next; | |
1425 | } | |
1426 | case O (O_DIVU, SW): | |
1427 | { | |
1428 | rd = GET_L_REG (code->dst.reg); | |
1429 | ea = GET_W_REG (code->src.reg); | |
1430 | n = ea & 0x8000; | |
1431 | nz = ea & 0xffff; | |
1432 | if (ea) | |
1433 | { | |
de9b1892 KH |
1434 | tmp = (unsigned) rd % ea; |
1435 | rd = (unsigned) rd / ea; | |
c906108c SS |
1436 | } |
1437 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1438 | goto next; | |
1439 | } | |
1440 | ||
1441 | case O (O_DIVS, SB): | |
1442 | { | |
1443 | ||
1444 | rd = SEXTSHORT (GET_W_REG (code->dst.reg)); | |
1445 | ea = SEXTCHAR (GET_B_REG (code->src.reg)); | |
1446 | if (ea) | |
1447 | { | |
1448 | tmp = (int) rd % (int) ea; | |
1449 | rd = (int) rd / (int) ea; | |
1450 | n = rd & 0x8000; | |
1451 | nz = 1; | |
1452 | } | |
1453 | else | |
1454 | nz = 0; | |
1455 | SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); | |
1456 | goto next; | |
1457 | } | |
1458 | case O (O_DIVS, SW): | |
1459 | { | |
1460 | rd = GET_L_REG (code->dst.reg); | |
1461 | ea = SEXTSHORT (GET_W_REG (code->src.reg)); | |
1462 | if (ea) | |
1463 | { | |
1464 | tmp = (int) rd % (int) ea; | |
1465 | rd = (int) rd / (int) ea; | |
1466 | n = rd & 0x80000000; | |
1467 | nz = 1; | |
1468 | } | |
1469 | else | |
1470 | nz = 0; | |
1471 | SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); | |
1472 | goto next; | |
1473 | } | |
1474 | case O (O_EXTS, SW): | |
1475 | rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ | |
1476 | ea = rd & 0x80 ? -256 : 0; | |
1477 | res = rd + ea; | |
1478 | goto log16; | |
1479 | case O (O_EXTS, SL): | |
1480 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1481 | ea = rd & 0x8000 ? -65536 : 0; | |
1482 | res = rd + ea; | |
1483 | goto log32; | |
1484 | case O (O_EXTU, SW): | |
1485 | rd = GET_B_REG (code->src.reg + 8) & 0xff; | |
1486 | ea = 0; | |
1487 | res = rd + ea; | |
1488 | goto log16; | |
1489 | case O (O_EXTU, SL): | |
1490 | rd = GET_W_REG (code->src.reg) & 0xffff; | |
1491 | ea = 0; | |
1492 | res = rd + ea; | |
1493 | goto log32; | |
1494 | ||
1495 | case O (O_NOP, SN): | |
1496 | goto next; | |
1497 | ||
1498 | case O (O_STM, SL): | |
1499 | { | |
1500 | int nregs, firstreg, i; | |
1501 | ||
1502 | nregs = GET_MEMORY_B (pc + 1); | |
1503 | nregs >>= 4; | |
1504 | nregs &= 0xf; | |
1505 | firstreg = GET_MEMORY_B (pc + 3); | |
1506 | firstreg &= 0xf; | |
1507 | for (i = firstreg; i <= firstreg + nregs; i++) | |
1508 | { | |
1509 | cpu.regs[7] -= 4; | |
1510 | SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); | |
1511 | } | |
1512 | } | |
1513 | goto next; | |
1514 | ||
1515 | case O (O_LDM, SL): | |
1516 | { | |
1517 | int nregs, firstreg, i; | |
1518 | ||
1519 | nregs = GET_MEMORY_B (pc + 1); | |
1520 | nregs >>= 4; | |
1521 | nregs &= 0xf; | |
1522 | firstreg = GET_MEMORY_B (pc + 3); | |
1523 | firstreg &= 0xf; | |
1524 | for (i = firstreg; i >= firstreg - nregs; i--) | |
1525 | { | |
1526 | cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); | |
1527 | cpu.regs[7] += 4; | |
1528 | } | |
1529 | } | |
1530 | goto next; | |
1531 | ||
1532 | default: | |
1533 | cpu.state = SIM_STATE_STOPPED; | |
1534 | cpu.exception = SIGILL; | |
1535 | goto end; | |
1536 | ||
1537 | } | |
1538 | abort (); | |
1539 | ||
1540 | setc: | |
1541 | cpu.ccr = res; | |
1542 | GETSR (); | |
1543 | goto next; | |
1544 | ||
1545 | condtrue: | |
1546 | /* When a branch works */ | |
1547 | pc = code->src.literal; | |
1548 | goto end; | |
1549 | ||
1550 | /* Set the cond codes from res */ | |
1551 | bitop: | |
1552 | ||
1553 | /* Set the flags after an 8 bit inc/dec operation */ | |
1554 | just_flags_inc8: | |
1555 | n = res & 0x80; | |
1556 | nz = res & 0xff; | |
1557 | v = (rd & 0x7f) == 0x7f; | |
1558 | goto next; | |
1559 | ||
1560 | ||
1561 | /* Set the flags after an 16 bit inc/dec operation */ | |
1562 | just_flags_inc16: | |
1563 | n = res & 0x8000; | |
1564 | nz = res & 0xffff; | |
1565 | v = (rd & 0x7fff) == 0x7fff; | |
1566 | goto next; | |
1567 | ||
1568 | ||
1569 | /* Set the flags after an 32 bit inc/dec operation */ | |
1570 | just_flags_inc32: | |
1571 | n = res & 0x80000000; | |
1572 | nz = res & 0xffffffff; | |
1573 | v = (rd & 0x7fffffff) == 0x7fffffff; | |
1574 | goto next; | |
1575 | ||
1576 | ||
1577 | shift8: | |
1578 | /* Set flags after an 8 bit shift op, carry,overflow set in insn */ | |
1579 | n = (rd & 0x80); | |
1580 | nz = rd & 0xff; | |
1581 | SET_B_REG (code->src.reg, rd); | |
1582 | goto next; | |
1583 | ||
1584 | shift16: | |
1585 | /* Set flags after an 16 bit shift op, carry,overflow set in insn */ | |
1586 | n = (rd & 0x8000); | |
1587 | nz = rd & 0xffff; | |
1588 | SET_W_REG (code->src.reg, rd); | |
1589 | goto next; | |
1590 | ||
1591 | shift32: | |
1592 | /* Set flags after an 32 bit shift op, carry,overflow set in insn */ | |
1593 | n = (rd & 0x80000000); | |
1594 | nz = rd & 0xffffffff; | |
1595 | SET_L_REG (code->src.reg, rd); | |
1596 | goto next; | |
1597 | ||
1598 | log32: | |
1599 | store (&code->dst, res); | |
1600 | just_flags_log32: | |
1601 | /* flags after a 32bit logical operation */ | |
1602 | n = res & 0x80000000; | |
1603 | nz = res & 0xffffffff; | |
1604 | v = 0; | |
1605 | goto next; | |
1606 | ||
1607 | log16: | |
1608 | store (&code->dst, res); | |
1609 | just_flags_log16: | |
1610 | /* flags after a 16bit logical operation */ | |
1611 | n = res & 0x8000; | |
1612 | nz = res & 0xffff; | |
1613 | v = 0; | |
1614 | goto next; | |
1615 | ||
1616 | ||
1617 | log8: | |
1618 | store (&code->dst, res); | |
1619 | just_flags_log8: | |
1620 | n = res & 0x80; | |
1621 | nz = res & 0xff; | |
1622 | v = 0; | |
1623 | goto next; | |
1624 | ||
1625 | alu8: | |
1626 | SET_B_REG (code->dst.reg, res); | |
1627 | just_flags_alu8: | |
1628 | n = res & 0x80; | |
1629 | nz = res & 0xff; | |
1630 | c = (res & 0x100); | |
1631 | switch (code->opcode / 4) | |
1632 | { | |
1633 | case O_ADD: | |
1634 | v = ((rd & 0x80) == (ea & 0x80) | |
1635 | && (rd & 0x80) != (res & 0x80)); | |
1636 | break; | |
1637 | case O_SUB: | |
1638 | case O_CMP: | |
1639 | v = ((rd & 0x80) != (-ea & 0x80) | |
1640 | && (rd & 0x80) != (res & 0x80)); | |
1641 | break; | |
1642 | case O_NEG: | |
1643 | v = (rd == 0x80); | |
1644 | break; | |
1645 | } | |
1646 | goto next; | |
1647 | ||
1648 | alu16: | |
1649 | SET_W_REG (code->dst.reg, res); | |
1650 | just_flags_alu16: | |
1651 | n = res & 0x8000; | |
1652 | nz = res & 0xffff; | |
1653 | c = (res & 0x10000); | |
1654 | switch (code->opcode / 4) | |
1655 | { | |
1656 | case O_ADD: | |
1657 | v = ((rd & 0x8000) == (ea & 0x8000) | |
1658 | && (rd & 0x8000) != (res & 0x8000)); | |
1659 | break; | |
1660 | case O_SUB: | |
1661 | case O_CMP: | |
1662 | v = ((rd & 0x8000) != (-ea & 0x8000) | |
1663 | && (rd & 0x8000) != (res & 0x8000)); | |
1664 | break; | |
1665 | case O_NEG: | |
1666 | v = (rd == 0x8000); | |
1667 | break; | |
1668 | } | |
1669 | goto next; | |
1670 | ||
1671 | alu32: | |
1672 | SET_L_REG (code->dst.reg, res); | |
1673 | just_flags_alu32: | |
1674 | n = res & 0x80000000; | |
1675 | nz = res & 0xffffffff; | |
1676 | switch (code->opcode / 4) | |
1677 | { | |
1678 | case O_ADD: | |
1679 | v = ((rd & 0x80000000) == (ea & 0x80000000) | |
1680 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1681 | c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); | |
1682 | break; | |
1683 | case O_SUB: | |
1684 | case O_CMP: | |
1685 | v = ((rd & 0x80000000) != (-ea & 0x80000000) | |
1686 | && (rd & 0x80000000) != (res & 0x80000000)); | |
1687 | c = (unsigned) rd < (unsigned) -ea; | |
1688 | break; | |
1689 | case O_NEG: | |
1690 | v = (rd == 0x80000000); | |
1691 | c = res != 0; | |
1692 | break; | |
1693 | } | |
1694 | goto next; | |
1695 | ||
1696 | next:; | |
1697 | pc = code->next_pc; | |
1698 | ||
1699 | end: | |
1700 | ; | |
de9b1892 KH |
1701 | #if 0 |
1702 | if (cpu.regs[8]) | |
1703 | abort (); | |
1704 | #endif | |
c906108c SS |
1705 | |
1706 | if (--poll_count < 0) | |
1707 | { | |
7a292a7a | 1708 | poll_count = POLL_QUIT_INTERVAL; |
c906108c SS |
1709 | if ((*sim_callback->poll_quit) != NULL |
1710 | && (*sim_callback->poll_quit) (sim_callback)) | |
1711 | sim_stop (sd); | |
1712 | } | |
1713 | ||
1714 | } | |
1715 | while (cpu.state == SIM_STATE_RUNNING); | |
1716 | cpu.ticks += get_now () - tick_start; | |
1717 | cpu.cycles += cycles; | |
1718 | cpu.insts += insts; | |
de9b1892 | 1719 | |
c906108c SS |
1720 | cpu.pc = pc; |
1721 | BUILDSR (); | |
1722 | cpu.mask = oldmask; | |
1723 | signal (SIGINT, prev); | |
1724 | } | |
1725 | ||
1726 | int | |
1727 | sim_trace (sd) | |
1728 | SIM_DESC sd; | |
1729 | { | |
2ea716f6 | 1730 | /* FIXME: Unfinished. */ |
c906108c SS |
1731 | abort (); |
1732 | } | |
1733 | ||
1734 | int | |
1735 | sim_write (sd, addr, buffer, size) | |
1736 | SIM_DESC sd; | |
1737 | SIM_ADDR addr; | |
1738 | unsigned char *buffer; | |
1739 | int size; | |
1740 | { | |
1741 | int i; | |
1742 | ||
1743 | init_pointers (); | |
1744 | if (addr < 0) | |
1745 | return 0; | |
1746 | for (i = 0; i < size; i++) | |
1747 | { | |
1748 | if (addr < memory_size) | |
1749 | { | |
1750 | cpu.memory[addr + i] = buffer[i]; | |
1751 | cpu.cache_idx[addr + i] = 0; | |
1752 | } | |
1753 | else | |
1754 | cpu.eightbit[(addr + i) & 0xff] = buffer[i]; | |
1755 | } | |
1756 | return size; | |
1757 | } | |
1758 | ||
1759 | int | |
1760 | sim_read (sd, addr, buffer, size) | |
1761 | SIM_DESC sd; | |
1762 | SIM_ADDR addr; | |
1763 | unsigned char *buffer; | |
1764 | int size; | |
1765 | { | |
1766 | init_pointers (); | |
1767 | if (addr < 0) | |
1768 | return 0; | |
1769 | if (addr < memory_size) | |
1770 | memcpy (buffer, cpu.memory + addr, size); | |
1771 | else | |
1772 | memcpy (buffer, cpu.eightbit + (addr & 0xff), size); | |
1773 | return size; | |
1774 | } | |
1775 | ||
1776 | ||
1777 | #define R0_REGNUM 0 | |
1778 | #define R1_REGNUM 1 | |
1779 | #define R2_REGNUM 2 | |
1780 | #define R3_REGNUM 3 | |
1781 | #define R4_REGNUM 4 | |
1782 | #define R5_REGNUM 5 | |
1783 | #define R6_REGNUM 6 | |
1784 | #define R7_REGNUM 7 | |
1785 | ||
1786 | #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ | |
1787 | #define FP_REGNUM R6_REGNUM /* Contains address of executing | |
2ea716f6 | 1788 | * stack frame */ |
c906108c SS |
1789 | |
1790 | #define CCR_REGNUM 8 /* Contains processor status */ | |
1791 | #define PC_REGNUM 9 /* Contains program counter */ | |
1792 | ||
1793 | #define CYCLE_REGNUM 10 | |
1794 | #define INST_REGNUM 11 | |
1795 | #define TICK_REGNUM 12 | |
1796 | ||
1797 | ||
1798 | int | |
1799 | sim_store_register (sd, rn, value, length) | |
1800 | SIM_DESC sd; | |
1801 | int rn; | |
1802 | unsigned char *value; | |
1803 | int length; | |
1804 | { | |
1805 | int longval; | |
1806 | int shortval; | |
1807 | int intval; | |
1808 | longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; | |
1809 | shortval = (value[0] << 8) | (value[1]); | |
1810 | intval = h8300hmode ? longval : shortval; | |
1811 | ||
1812 | init_pointers (); | |
1813 | switch (rn) | |
1814 | { | |
1815 | case PC_REGNUM: | |
1816 | cpu.pc = intval; | |
1817 | break; | |
1818 | default: | |
1819 | abort (); | |
1820 | case R0_REGNUM: | |
1821 | case R1_REGNUM: | |
1822 | case R2_REGNUM: | |
1823 | case R3_REGNUM: | |
1824 | case R4_REGNUM: | |
1825 | case R5_REGNUM: | |
1826 | case R6_REGNUM: | |
1827 | case R7_REGNUM: | |
1828 | cpu.regs[rn] = intval; | |
1829 | break; | |
1830 | case CCR_REGNUM: | |
1831 | cpu.ccr = intval; | |
1832 | break; | |
1833 | case CYCLE_REGNUM: | |
1834 | cpu.cycles = longval; | |
1835 | break; | |
1836 | ||
1837 | case INST_REGNUM: | |
1838 | cpu.insts = longval; | |
1839 | break; | |
1840 | ||
1841 | case TICK_REGNUM: | |
1842 | cpu.ticks = longval; | |
1843 | break; | |
1844 | } | |
1845 | return -1; | |
1846 | } | |
1847 | ||
1848 | int | |
1849 | sim_fetch_register (sd, rn, buf, length) | |
1850 | SIM_DESC sd; | |
1851 | int rn; | |
1852 | unsigned char *buf; | |
1853 | int length; | |
1854 | { | |
1855 | int v; | |
1856 | int longreg = 0; | |
1857 | ||
1858 | init_pointers (); | |
1859 | ||
1860 | switch (rn) | |
1861 | { | |
1862 | default: | |
1863 | abort (); | |
3b02cf92 | 1864 | case CCR_REGNUM: |
c906108c SS |
1865 | v = cpu.ccr; |
1866 | break; | |
3b02cf92 | 1867 | case PC_REGNUM: |
c906108c SS |
1868 | v = cpu.pc; |
1869 | break; | |
1870 | case R0_REGNUM: | |
1871 | case R1_REGNUM: | |
1872 | case R2_REGNUM: | |
1873 | case R3_REGNUM: | |
1874 | case R4_REGNUM: | |
1875 | case R5_REGNUM: | |
1876 | case R6_REGNUM: | |
1877 | case R7_REGNUM: | |
1878 | v = cpu.regs[rn]; | |
1879 | break; | |
3b02cf92 | 1880 | case CYCLE_REGNUM: |
c906108c SS |
1881 | v = cpu.cycles; |
1882 | longreg = 1; | |
1883 | break; | |
3b02cf92 | 1884 | case TICK_REGNUM: |
c906108c SS |
1885 | v = cpu.ticks; |
1886 | longreg = 1; | |
1887 | break; | |
3b02cf92 | 1888 | case INST_REGNUM: |
c906108c SS |
1889 | v = cpu.insts; |
1890 | longreg = 1; | |
1891 | break; | |
1892 | } | |
1893 | if (h8300hmode || longreg) | |
1894 | { | |
1895 | buf[0] = v >> 24; | |
1896 | buf[1] = v >> 16; | |
1897 | buf[2] = v >> 8; | |
1898 | buf[3] = v >> 0; | |
1899 | } | |
1900 | else | |
1901 | { | |
1902 | buf[0] = v >> 8; | |
1903 | buf[1] = v; | |
1904 | } | |
1905 | return -1; | |
1906 | } | |
1907 | ||
1908 | void | |
1909 | sim_stop_reason (sd, reason, sigrc) | |
1910 | SIM_DESC sd; | |
1911 | enum sim_stop *reason; | |
1912 | int *sigrc; | |
1913 | { | |
1914 | #if 0 /* FIXME: This should work but we can't use it. | |
1915 | grep for SLEEP above. */ | |
1916 | switch (cpu.state) | |
1917 | { | |
1918 | case SIM_STATE_EXITED : *reason = sim_exited; break; | |
1919 | case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; | |
1920 | case SIM_STATE_STOPPED : *reason = sim_stopped; break; | |
1921 | default : abort (); | |
1922 | } | |
1923 | #else | |
1924 | *reason = sim_stopped; | |
1925 | #endif | |
1926 | *sigrc = cpu.exception; | |
1927 | } | |
1928 | ||
1929 | /* FIXME: Rename to sim_set_mem_size. */ | |
1930 | ||
1931 | void | |
1932 | sim_size (n) | |
1933 | int n; | |
1934 | { | |
1935 | /* Memory size is fixed. */ | |
1936 | } | |
1937 | ||
1938 | void | |
1939 | sim_set_simcache_size (n) | |
1940 | { | |
1941 | if (cpu.cache) | |
1942 | free (cpu.cache); | |
1943 | if (n < 2) | |
1944 | n = 2; | |
1945 | cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); | |
1946 | memset (cpu.cache, 0, sizeof (decoded_inst) * n); | |
1947 | cpu.csize = n; | |
1948 | } | |
1949 | ||
1950 | ||
1951 | void | |
1952 | sim_info (sd, verbose) | |
1953 | SIM_DESC sd; | |
1954 | int verbose; | |
1955 | { | |
1956 | double timetaken = (double) cpu.ticks / (double) now_persec (); | |
1957 | double virttime = cpu.cycles / 10.0e6; | |
1958 | ||
1959 | (*sim_callback->printf_filtered) (sim_callback, | |
1960 | "\n\n#instructions executed %10d\n", | |
1961 | cpu.insts); | |
1962 | (*sim_callback->printf_filtered) (sim_callback, | |
1963 | "#cycles (v approximate) %10d\n", | |
1964 | cpu.cycles); | |
1965 | (*sim_callback->printf_filtered) (sim_callback, | |
1966 | "#real time taken %10.4f\n", | |
1967 | timetaken); | |
1968 | (*sim_callback->printf_filtered) (sim_callback, | |
1969 | "#virtual time taked %10.4f\n", | |
1970 | virttime); | |
1971 | if (timetaken != 0.0) | |
1972 | (*sim_callback->printf_filtered) (sim_callback, | |
1973 | "#simulation ratio %10.4f\n", | |
1974 | virttime / timetaken); | |
1975 | (*sim_callback->printf_filtered) (sim_callback, | |
1976 | "#compiles %10d\n", | |
1977 | cpu.compiles); | |
1978 | (*sim_callback->printf_filtered) (sim_callback, | |
1979 | "#cache size %10d\n", | |
1980 | cpu.csize); | |
1981 | ||
1982 | #ifdef ADEBUG | |
1983 | /* This to be conditional on `what' (aka `verbose'), | |
1984 | however it was never passed as non-zero. */ | |
1985 | if (1) | |
1986 | { | |
1987 | int i; | |
1988 | for (i = 0; i < O_LAST; i++) | |
1989 | { | |
1990 | if (cpu.stats[i]) | |
1991 | (*sim_callback->printf_filtered) (sim_callback, | |
1992 | "%d: %d\n", i, cpu.stats[i]); | |
1993 | } | |
1994 | } | |
1995 | #endif | |
1996 | } | |
1997 | ||
2ea716f6 KH |
1998 | /* Indicate whether the cpu is an H8/300 or H8/300H. |
1999 | FLAG is non-zero for the H8/300H. */ | |
c906108c SS |
2000 | |
2001 | void | |
2002 | set_h8300h (flag) | |
2003 | int flag; | |
2004 | { | |
2005 | /* FIXME: Much of the code in sim_load can be moved to sim_open. | |
2006 | This function being replaced by a sim_open:ARGV configuration | |
2ea716f6 | 2007 | option. */ |
c906108c SS |
2008 | h8300hmode = flag; |
2009 | } | |
2010 | ||
2011 | SIM_DESC | |
2012 | sim_open (kind, ptr, abfd, argv) | |
2013 | SIM_OPEN_KIND kind; | |
2014 | struct host_callback_struct *ptr; | |
2015 | struct _bfd *abfd; | |
2016 | char **argv; | |
2017 | { | |
2ea716f6 | 2018 | /* FIXME: Much of the code in sim_load can be moved here. */ |
c906108c SS |
2019 | |
2020 | sim_kind = kind; | |
2021 | myname = argv[0]; | |
2022 | sim_callback = ptr; | |
2ea716f6 | 2023 | /* Fudge our descriptor. */ |
c906108c SS |
2024 | return (SIM_DESC) 1; |
2025 | } | |
2026 | ||
2027 | void | |
2028 | sim_close (sd, quitting) | |
2029 | SIM_DESC sd; | |
2030 | int quitting; | |
2031 | { | |
2ea716f6 | 2032 | /* Nothing to do. */ |
c906108c SS |
2033 | } |
2034 | ||
2035 | /* Called by gdb to load a program into memory. */ | |
2036 | ||
2037 | SIM_RC | |
2038 | sim_load (sd, prog, abfd, from_tty) | |
2039 | SIM_DESC sd; | |
2040 | char *prog; | |
2041 | bfd *abfd; | |
2042 | int from_tty; | |
2043 | { | |
2044 | bfd *prog_bfd; | |
2045 | ||
2ea716f6 KH |
2046 | /* FIXME: The code below that sets a specific variant of the H8/300 |
2047 | being simulated should be moved to sim_open(). */ | |
c906108c | 2048 | |
2ea716f6 | 2049 | /* See if the file is for the H8/300 or H8/300H. */ |
c906108c SS |
2050 | /* ??? This may not be the most efficient way. The z8k simulator |
2051 | does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ | |
2052 | if (abfd != NULL) | |
2053 | prog_bfd = abfd; | |
2054 | else | |
2055 | prog_bfd = bfd_openr (prog, "coff-h8300"); | |
2056 | if (prog_bfd != NULL) | |
2057 | { | |
2058 | /* Set the cpu type. We ignore failure from bfd_check_format | |
2059 | and bfd_openr as sim_load_file checks too. */ | |
de9b1892 | 2060 | if (bfd_check_format (prog_bfd, bfd_object)) |
c906108c SS |
2061 | { |
2062 | unsigned long mach = bfd_get_mach (prog_bfd); | |
2063 | set_h8300h (mach == bfd_mach_h8300h | |
2064 | || mach == bfd_mach_h8300s); | |
2065 | } | |
2066 | } | |
2067 | ||
2068 | /* If we're using gdb attached to the simulator, then we have to | |
2069 | reallocate memory for the simulator. | |
2070 | ||
2071 | When gdb first starts, it calls fetch_registers (among other | |
2072 | functions), which in turn calls init_pointers, which allocates | |
2073 | simulator memory. | |
2074 | ||
2075 | The problem is when we do that, we don't know whether we're | |
2ea716f6 | 2076 | debugging an H8/300 or H8/300H program. |
c906108c SS |
2077 | |
2078 | This is the first point at which we can make that determination, | |
2079 | so we just reallocate memory now; this will also allow us to handle | |
2ea716f6 | 2080 | switching between H8/300 and H8/300H programs without exiting |
c906108c SS |
2081 | gdb. */ |
2082 | if (h8300hmode) | |
2083 | memory_size = H8300H_MSIZE; | |
2084 | else | |
2085 | memory_size = H8300_MSIZE; | |
2086 | ||
2087 | if (cpu.memory) | |
2088 | free (cpu.memory); | |
2089 | if (cpu.cache_idx) | |
2090 | free (cpu.cache_idx); | |
2091 | if (cpu.eightbit) | |
2092 | free (cpu.eightbit); | |
2093 | ||
2094 | cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); | |
2095 | cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); | |
2096 | cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); | |
2097 | ||
2ea716f6 | 2098 | /* `msize' must be a power of two. */ |
c906108c SS |
2099 | if ((memory_size & (memory_size - 1)) != 0) |
2100 | abort (); | |
2101 | cpu.mask = memory_size - 1; | |
2102 | ||
2103 | if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, | |
2104 | sim_kind == SIM_OPEN_DEBUG, | |
2105 | 0, sim_write) | |
2106 | == NULL) | |
2107 | { | |
2108 | /* Close the bfd if we opened it. */ | |
2109 | if (abfd == NULL && prog_bfd != NULL) | |
2110 | bfd_close (prog_bfd); | |
2111 | return SIM_RC_FAIL; | |
2112 | } | |
2113 | ||
2114 | /* Close the bfd if we opened it. */ | |
2115 | if (abfd == NULL && prog_bfd != NULL) | |
2116 | bfd_close (prog_bfd); | |
2117 | return SIM_RC_OK; | |
2118 | } | |
2119 | ||
2120 | SIM_RC | |
2121 | sim_create_inferior (sd, abfd, argv, env) | |
2122 | SIM_DESC sd; | |
2123 | struct _bfd *abfd; | |
2124 | char **argv; | |
2125 | char **env; | |
2126 | { | |
2127 | if (abfd != NULL) | |
2128 | cpu.pc = bfd_get_start_address (abfd); | |
2129 | else | |
2130 | cpu.pc = 0; | |
2131 | return SIM_RC_OK; | |
2132 | } | |
2133 | ||
2134 | void | |
2135 | sim_do_command (sd, cmd) | |
2136 | SIM_DESC sd; | |
2137 | char *cmd; | |
2138 | { | |
2139 | (*sim_callback->printf_filtered) (sim_callback, | |
2140 | "This simulator does not accept any commands.\n"); | |
2141 | } | |
2142 | ||
2143 | void | |
2144 | sim_set_callbacks (ptr) | |
2145 | struct host_callback_struct *ptr; | |
2146 | { | |
2147 | sim_callback = ptr; | |
2148 | } |