]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mips/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* config/tc-i386.c (i386_immediate): Disallow O_big immediates.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
cff3e48b
JM		 1Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
2
3 * mips.igen (MULT): Correct previous mis-applied patch.
4
d4f3574e
SS		 5Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
6
7 * mips.igen (delayslot32): Handle sequence like
8 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
9 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
10 (MULT): Actually pass the third register...
11
121999-09-03 Mark Salter <msalter@cygnus.com>
13
14 * interp.c (sim_open): Added more memory aliases for additional
15 hardware being touched by cygmon on jmr3904 board.
16
17Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
18
19 * configure: Regenerated to track ../common/aclocal.m4 changes.
20
a0b3c4fd
JM		 21Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
22
23 * interp.c (sim_store_register): Handle case where client - GDB -
24 specifies that a 4 byte register is 8 bytes in size.
25 (sim_fetch_register): Ditto.
26
adf40b2e
JM		 271999-07-14 Frank Ch. Eigler <fche@cygnus.com>
28
29 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
30 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
31 (idt_monitor_base): Base address for IDT monitor traps.
32 (pmon_monitor_base): Ditto for PMON.
33 (lsipmon_monitor_base): Ditto for LSI PMON.
34 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
35 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
36 (sim_firmware_command): New function.
37 (mips_option_handler): Call it for OPTION_FIRMWARE.
38 (sim_open): Allocate memory for idt_monitor region. If "--board"
39 option was given, add no monitor by default. Add BREAK hooks only if
40 monitors are also there.
41
43e526b9
JM		 42Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
43
44 * interp.c (sim_monitor): Flush output before reading input.
45
46Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
47
48 * tconfig.in (SIM_HANDLES_LMA): Always define.
49
50Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
51
52 From Mark Salter <msalter@cygnus.com>:
53 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
54 (sim_open): Add setup for BSP board.
55
9846de1b
JM		 56Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
57
58 * mips.igen (MULT, MULTU): Add syntax for two operand version.
59 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
60 them as unimplemented.
61
cd0fc7c3
SS		 621999-05-08 Felix Lee <flee@cygnus.com>
63
64 * configure: Regenerated to track ../common/aclocal.m4 changes.
65
7a292a7a
SS		 661999-04-21 Frank Ch. Eigler <fche@cygnus.com>
67
68 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
69
70Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
71
72 * configure.in: Any mips64vr5*-*-* target should have
73 -DTARGET_ENABLE_FR=1.
74 (default_endian): Any mips64vr*el-*-* target should default to
75 LITTLE_ENDIAN.
76 * configure: Re-generate.
77
781999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
79
80 * mips.igen (ldl): Extend from _16_, not 32.
81
82Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
83
84 * interp.c (sim_store_register): Force registers written to by GDB
85 into an un-interpreted state.
86
c906108c
SS		 871999-02-05 Frank Ch. Eigler <fche@cygnus.com>
88
89 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
90 CPU, start periodic background I/O polls.
91 (tx3904sio_poll): New function: periodic I/O poller.
92
931998-12-30 Frank Ch. Eigler <fche@cygnus.com>
94
95 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
96
97Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
98
99 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
100 case statement.
101
1021998-12-29 Frank Ch. Eigler <fche@cygnus.com>
103
104 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
105 (load_word): Call SIM_CORE_SIGNAL hook on error.
106 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
107 starting. For exception dispatching, pass PC instead of NULL_CIA.
108 (decode_coproc): Use COP0_BADVADDR to store faulting address.
109 * sim-main.h (COP0_BADVADDR): Define.
110 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
111 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
112 (_sim_cpu): Add exc_* fields to store register value snapshots.
113 * mips.igen (*): Replace memory-related SignalException* calls
114 with references to SIM_CORE_SIGNAL hook.
115
116 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
117 fix.
118 * sim-main.c (*): Minor warning cleanups.
119
1201998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
121
122 * m16.igen (DADDIU5): Correct type-o.
123
124Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
125
126 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
127 variables.
128
129Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
130
131 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
132 to include path.
133 (interp.o): Add dependency on itable.h
134 (oengine.c, gencode): Delete remaining references.
135 (BUILT_SRC_FROM_GEN): Clean up.
136
1371998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
138
139 * vr4run.c: New.
140 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
141 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
142 tmp-run-hack) : New.
143 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
144 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
145 Drop the "64" qualifier to get the HACK generator working.
146 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
147 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
148 qualifier to get the hack generator working.
149 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
150 (DSLL): Use do_dsll.
151 (DSLLV): Use do_dsllv.
152 (DSRA): Use do_dsra.
153 (DSRL): Use do_dsrl.
154 (DSRLV): Use do_dsrlv.
155 (BC1): Move *vr4100 to get the HACK generator working.
156 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
157 get the HACK generator working.
158 (MACC) Rename to get the HACK generator working.
159 (DMACC,MACCS,DMACCS): Add the 64.
160
1611998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
162
163 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
164 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
165
1661998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
167
168 * mips/interp.c (DEBUG): Cleanups.
169
1701998-12-10 Frank Ch. Eigler <fche@cygnus.com>
171
172 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
173 (tx3904sio_tickle): fflush after a stdout character output.
174
1751998-12-03 Frank Ch. Eigler <fche@cygnus.com>
176
177 * interp.c (sim_close): Uninstall modules.
178
179Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
180
181 * sim-main.h, interp.c (sim_monitor): Change to global
182 function.
183
184Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
185
186 * configure.in (vr4100): Only include vr4100 instructions in
187 simulator.
188 * configure: Re-generate.
189 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
190
191Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
192
193 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
194 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
195 true alternative.
196
197 * configure.in (sim_default_gen, sim_use_gen): Replace with
198 sim_gen.
199 (--enable-sim-igen): Delete config option. Always using IGEN.
200 * configure: Re-generate.
201
202 * Makefile.in (gencode): Kill, kill, kill.
203 * gencode.c: Ditto.
204
205Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
206
207 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
208 bit mips16 igen simulator.
209 * configure: Re-generate.
210
211 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
212 as part of vr4100 ISA.
213 * vr.igen: Mark all instructions as 64 bit only.
214
215Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
216
217 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
218 Pacify GCC.
219
220Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
221
222 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
223 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
224 * configure: Re-generate.
225
226 * m16.igen (BREAK): Define breakpoint instruction.
227 (JALX32): Mark instruction as mips16 and not r3900.
228 * mips.igen (C.cond.fmt): Fix typo in instruction format.
229
230 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
231
232Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
233
234 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
235 insn as a debug breakpoint.
236
237 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
238 pending.slot_size.
239 (PENDING_SCHED): Clean up trace statement.
240 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
241 (PENDING_FILL): Delay write by only one cycle.
242 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
243
244 * sim-main.c (pending_tick): Clean up trace statements. Add trace
245 of pending writes.
246 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
247 32 & 64.
248 (pending_tick): Move incrementing of index to FOR statement.
249 (pending_tick): Only update PENDING_OUT after a write has occured.
250
251 * configure.in: Add explicit mips-lsi-* target. Use gencode to
252 build simulator.
253 * configure: Re-generate.
254
255 * interp.c (sim_engine_run OLD): Delete explicit call to
256 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
257
258Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
259
260 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
261 interrupt level number to match changed SignalExceptionInterrupt
262 macro.
263
264Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
265
266 * interp.c: #include "itable.h" if WITH_IGEN.
267 (get_insn_name): New function.
268 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
269 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
270
271Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
272
273 * configure: Rebuilt to inhale new common/aclocal.m4.
274
275Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
276
277 * dv-tx3904sio.c: Include sim-assert.h.
278
279Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
280
281 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
282 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
283 Reorganize target-specific sim-hardware checks.
284 * configure: rebuilt.
285 * interp.c (sim_open): For tx39 target boards, set
286 OPERATING_ENVIRONMENT, add tx3904sio devices.
287 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
288 ROM executables. Install dv-sockser into sim-modules list.
289
290 * dv-tx3904irc.c: Compiler warning clean-up.
291 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
292 frequent hw-trace messages.
293
294Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
295
296 * vr.igen (MulAcc): Identify as a vr4100 specific function.
297
298Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
299
300 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
301
302 * vr.igen: New file.
303 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
304 * mips.igen: Define vr4100 model. Include vr.igen.
305Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
306
307 * mips.igen (check_mf_hilo): Correct check.
308
309Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
310
311 * sim-main.h (interrupt_event): Add prototype.
312
313 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
314 register_ptr, register_value.
315 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
316
317 * sim-main.h (tracefh): Make extern.
318
319Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
320
321 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
322 Reduce unnecessarily high timer event frequency.
323 * dv-tx3904cpu.c: Ditto for interrupt event.
324
325Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
326
327 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
328 to allay warnings.
329 (interrupt_event): Made non-static.
330
331 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
332 interchange of configuration values for external vs. internal
333 clock dividers.
334
335Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
336
337 * mips.igen (BREAK): Moved code to here for
338 simulator-reserved break instructions.
339 * gencode.c (build_instruction): Ditto.
340 * interp.c (signal_exception): Code moved from here. Non-
341 reserved instructions now use exception vector, rather
342 than halting sim.
343 * sim-main.h: Moved magic constants to here.
344
345Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
346
347 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
348 register upon non-zero interrupt event level, clear upon zero
349 event value.
350 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
351 by passing zero event value.
352 (*_io_{read,write}_buffer): Endianness fixes.
353 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
354 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
355
356 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
357 serial I/O and timer module at base address 0xFFFF0000.
358
359Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
360
361 * mips.igen (SWC1) : Correct the handling of ReverseEndian
362 and BigEndianCPU.
363
364Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
365
366 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
367 parts.
368 * configure: Update.
369
370Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
371
372 * dv-tx3904tmr.c: New file - implements tx3904 timer.
373 * dv-tx3904{irc,cpu}.c: Mild reformatting.
374 * configure.in: Include tx3904tmr in hw_device list.
375 * configure: Rebuilt.
376 * interp.c (sim_open): Instantiate three timer instances.
377 Fix address typo of tx3904irc instance.
378
379Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
380
381 * interp.c (signal_exception): SystemCall exception now uses
382 the exception vector.
383
384Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
385
386 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
387 to allay warnings.
388
389Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
390
391 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
392
393Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
394
395 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
396
397 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
398 sim-main.h. Declare a struct hw_descriptor instead of struct
399 hw_device_descriptor.
400
401Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
402
403 * mips.igen (do_store_left, do_load_left): Compute nr of left and
404 right bits and then re-align left hand bytes to correct byte
405 lanes. Fix incorrect computation in do_store_left when loading
406 bytes from second word.
407
408Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
409
410 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
411 * interp.c (sim_open): Only create a device tree when HW is
412 enabled.
413
414 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
415 * interp.c (signal_exception): Ditto.
416
417Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
418
419 * gencode.c: Mark BEGEZALL as LIKELY.
420
421Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
422
423 * sim-main.h (ALU32_END): Sign extend 32 bit results.
424 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
425
426Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
427
428 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
429 modules. Recognize TX39 target with "mips*tx39" pattern.
430 * configure: Rebuilt.
431 * sim-main.h (*): Added many macros defining bits in
432 TX39 control registers.
433 (SignalInterrupt): Send actual PC instead of NULL.
434 (SignalNMIReset): New exception type.
435 * interp.c (board): New variable for future use to identify
436 a particular board being simulated.
437 (mips_option_handler,mips_options): Added "--board" option.
438 (interrupt_event): Send actual PC.
439 (sim_open): Make memory layout conditional on board setting.
440 (signal_exception): Initial implementation of hardware interrupt
441 handling. Accept another break instruction variant for simulator
442 exit.
443 (decode_coproc): Implement RFE instruction for TX39.
444 (mips.igen): Decode RFE instruction as such.
445 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
446 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
447 bbegin to implement memory map.
448 * dv-tx3904cpu.c: New file.
449 * dv-tx3904irc.c: New file.
450
451Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
452
453 * mips.igen (check_mt_hilo): Create a separate r3900 version.
454
455Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
456
457 * tx.igen (madd,maddu): Replace calls to check_op_hilo
458 with calls to check_div_hilo.
459
460Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
461
462 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
463 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
464 Add special r3900 version of do_mult_hilo.
465 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
466 with calls to check_mult_hilo.
467 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
468 with calls to check_div_hilo.
469
470Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
471
472 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
473 Document a replacement.
474
475Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
476
477 * interp.c (sim_monitor): Make mon_printf work.
478
479Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
480
481 * sim-main.h (INSN_NAME): New arg `cpu'.
482
483Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
484
485 * configure: Regenerated to track ../common/aclocal.m4 changes.
486
487Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
488
489 * configure: Regenerated to track ../common/aclocal.m4 changes.
490 * config.in: Ditto.
491
492Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
493
494 * acconfig.h: New file.
495 * configure.in: Reverted change of Apr 24; use sinclude again.
496
497Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
498
499 * configure: Regenerated to track ../common/aclocal.m4 changes.
500 * config.in: Ditto.
501
502Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
503
504 * configure.in: Don't call sinclude.
505
506Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
507
508 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
509
510Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
511
512 * mips.igen (ERET): Implement.
513
514 * interp.c (decode_coproc): Return sign-extended EPC.
515
516 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
517
518 * interp.c (signal_exception): Do not ignore Trap.
519 (signal_exception): On TRAP, restart at exception address.
520 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
521 (signal_exception): Update.
522 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
523 so that TRAP instructions are caught.
524
525Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
526
527 * sim-main.h (struct hilo_access, struct hilo_history): Define,
528 contains HI/LO access history.
529 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
530 (HIACCESS, LOACCESS): Delete, replace with
531 (HIHISTORY, LOHISTORY): New macros.
532 (CHECKHILO): Delete all, moved to mips.igen
533
534 * gencode.c (build_instruction): Do not generate checks for
535 correct HI/LO register usage.
536
537 * interp.c (old_engine_run): Delete checks for correct HI/LO
538 register usage.
539
540 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
541 check_mf_cycles): New functions.
542 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
543 do_divu, domultx, do_mult, do_multu): Use.
544
545 * tx.igen ("madd", "maddu"): Use.
546
547Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
548
549 * mips.igen (DSRAV): Use function do_dsrav.
550 (SRAV): Use new function do_srav.
551
552 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
553 (B): Sign extend 11 bit immediate.
554 (EXT-B*): Shift 16 bit immediate left by 1.
555 (ADDIU*): Don't sign extend immediate value.
556
557Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
558
559 * m16run.c (sim_engine_run): Restore CIA after handling an event.
560
561 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
562 functions.
563
564 * mips.igen (delayslot32, nullify_next_insn): New functions.
565 (m16.igen): Always include.
566 (do_*): Add more tracing.
567
568 * m16.igen (delayslot16): Add NIA argument, could be called by a
569 32 bit MIPS16 instruction.
570
571 * interp.c (ifetch16): Move function from here.
572 * sim-main.c (ifetch16): To here.
573
574 * sim-main.c (ifetch16, ifetch32): Update to match current
575 implementations of LH, LW.
576 (signal_exception): Don't print out incorrect hex value of illegal
577 instruction.
578
579Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
580
581 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
582 instruction.
583
584 * m16.igen: Implement MIPS16 instructions.
585
586 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
587 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
588 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
589 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
590 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
591 bodies of corresponding code from 32 bit insn to these. Also used
592 by MIPS16 versions of functions.
593
594 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
595 (IMEM16): Drop NR argument from macro.
596
597Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
598
599 * Makefile.in (SIM_OBJS): Add sim-main.o.
600
601 * sim-main.h (address_translation, load_memory, store_memory,
602 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
603 as INLINE_SIM_MAIN.
604 (pr_addr, pr_uword64): Declare.
605 (sim-main.c): Include when H_REVEALS_MODULE_P.
606
607 * interp.c (address_translation, load_memory, store_memory,
608 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
609 from here.
610 * sim-main.c: To here. Fix compilation problems.
611
612 * configure.in: Enable inlining.
613 * configure: Re-config.
614
615Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
616
617 * configure: Regenerated to track ../common/aclocal.m4 changes.
618
619Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
620
621 * mips.igen: Include tx.igen.
622 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
623 * tx.igen: New file, contains MADD and MADDU.
624
625 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
626 the hardwired constant `7'.
627 (store_memory): Ditto.
628 (LOADDRMASK): Move definition to sim-main.h.
629
630 mips.igen (MTC0): Enable for r3900.
631 (ADDU): Add trace.
632
633 mips.igen (do_load_byte): Delete.
634 (do_load, do_store, do_load_left, do_load_write, do_store_left,
635 do_store_right): New functions.
636 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
637
638 configure.in: Let the tx39 use igen again.
639 configure: Update.
640
641Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
642
643 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
644 not an address sized quantity. Return zero for cache sizes.
645
646Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
647
648 * mips.igen (r3900): r3900 does not support 64 bit integer
649 operations.
650
651Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
652
653 * configure.in (mipstx39*-*-*): Use gencode simulator rather
654 than igen one.
655 * configure : Rebuild.
656
657Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
658
659 * configure: Regenerated to track ../common/aclocal.m4 changes.
660
661Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
662
663 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
664
665Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
666
667 * configure: Regenerated to track ../common/aclocal.m4 changes.
668 * config.in: Regenerated to track ../common/aclocal.m4 changes.
669
670Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
671
672 * configure: Regenerated to track ../common/aclocal.m4 changes.
673
674Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
675
676 * interp.c (Max, Min): Comment out functions. Not yet used.
677
678Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
679
680 * configure: Regenerated to track ../common/aclocal.m4 changes.
681
682Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
683
684 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
685 configurable settings for stand-alone simulator.
686
687 * configure.in: Added X11 search, just in case.
688
689 * configure: Regenerated.
690
691Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
692
693 * interp.c (sim_write, sim_read, load_memory, store_memory):
694 Replace sim_core_*_map with read_map, write_map, exec_map resp.
695
696Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
697
698 * sim-main.h (GETFCC): Return an unsigned value.
699
700Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
701
702 * mips.igen (DIV): Fix check for -1 / MIN_INT.
703 (DADD): Result destination is RD not RT.
704
705Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
706
707 * sim-main.h (HIACCESS, LOACCESS): Always define.
708
709 * mdmx.igen (Maxi, Mini): Rename Max, Min.
710
711 * interp.c (sim_info): Delete.
712
713Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
714
715 * interp.c (DECLARE_OPTION_HANDLER): Use it.
716 (mips_option_handler): New argument `cpu'.
717 (sim_open): Update call to sim_add_option_table.
718
719Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
720
721 * mips.igen (CxC1): Add tracing.
722
723Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
724
725 * sim-main.h (Max, Min): Declare.
726
727 * interp.c (Max, Min): New functions.
728
729 * mips.igen (BC1): Add tracing.
730
731Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
732
733 * interp.c Added memory map for stack in vr4100
734
735Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
736
737 * interp.c (load_memory): Add missing "break"'s.
738
739Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
740
741 * interp.c (sim_store_register, sim_fetch_register): Pass in
742 length parameter. Return -1.
743
744Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
745
746 * interp.c: Added hardware init hook, fixed warnings.
747
748Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
749
750 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
751
752Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * interp.c (ifetch16): New function.
755
756 * sim-main.h (IMEM32): Rename IMEM.
757 (IMEM16_IMMED): Define.
758 (IMEM16): Define.
759 (DELAY_SLOT): Update.
760
761 * m16run.c (sim_engine_run): New file.
762
763 * m16.igen: All instructions except LB.
764 (LB): Call do_load_byte.
765 * mips.igen (do_load_byte): New function.
766 (LB): Call do_load_byte.
767
768 * mips.igen: Move spec for insn bit size and high bit from here.
769 * Makefile.in (tmp-igen, tmp-m16): To here.
770
771 * m16.dc: New file, decode mips16 instructions.
772
773 * Makefile.in (SIM_NO_ALL): Define.
774 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
775
776Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
777
778 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
779 point unit to 32 bit registers.
780 * configure: Re-generate.
781
782Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
783
784 * configure.in (sim_use_gen): Make IGEN the default simulator
785 generator for generic 32 and 64 bit mips targets.
786 * configure: Re-generate.
787
788Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
789
790 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
791 bitsize.
792
793 * interp.c (sim_fetch_register, sim_store_register): Read/write
794 FGR from correct location.
795 (sim_open): Set size of FGR's according to
796 WITH_TARGET_FLOATING_POINT_BITSIZE.
797
798 * sim-main.h (FGR): Store floating point registers in a separate
799 array.
800
801Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
802
803 * configure: Regenerated to track ../common/aclocal.m4 changes.
804
805Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
806
807 * interp.c (ColdReset): Call PENDING_INVALIDATE.
808
809 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
810
811 * interp.c (pending_tick): New function. Deliver pending writes.
812
813 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
814 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
815 it can handle mixed sized quantites and single bits.
816
817Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
818
819 * interp.c (oengine.h): Do not include when building with IGEN.
820 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
821 (sim_info): Ditto for PROCESSOR_64BIT.
822 (sim_monitor): Replace ut_reg with unsigned_word.
823 (*): Ditto for t_reg.
824 (LOADDRMASK): Define.
825 (sim_open): Remove defunct check that host FP is IEEE compliant,
826 using software to emulate floating point.
827 (value_fpr, ...): Always compile, was conditional on HASFPU.
828
829Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
830
831 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
832 size.
833
834 * interp.c (SD, CPU): Define.
835 (mips_option_handler): Set flags in each CPU.
836 (interrupt_event): Assume CPU 0 is the one being iterrupted.
837 (sim_close): Do not clear STATE, deleted anyway.
838 (sim_write, sim_read): Assume CPU zero's vm should be used for
839 data transfers.
840 (sim_create_inferior): Set the PC for all processors.
841 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
842 argument.
843 (mips16_entry): Pass correct nr of args to store_word, load_word.
844 (ColdReset): Cold reset all cpu's.
845 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
846 (sim_monitor, load_memory, store_memory, signal_exception): Use
847 `CPU' instead of STATE_CPU.
848
849
850 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
851 SD or CPU_.
852
853 * sim-main.h (signal_exception): Add sim_cpu arg.
854 (SignalException*): Pass both SD and CPU to signal_exception.
855 * interp.c (signal_exception): Update.
856
857 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
858 Ditto
859 (sync_operation, prefetch, cache_op, store_memory, load_memory,
860 address_translation): Ditto
861 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
862
863Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
864
865 * configure: Regenerated to track ../common/aclocal.m4 changes.
866
867Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
868
869 * interp.c (sim_engine_run): Add `nr_cpus' argument.
870
871 * mips.igen (model): Map processor names onto BFD name.
872
873 * sim-main.h (CPU_CIA): Delete.
874 (SET_CIA, GET_CIA): Define
875
876Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
877
878 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
879 regiser.
880
881 * configure.in (default_endian): Configure a big-endian simulator
882 by default.
883 * configure: Re-generate.
884
885Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
886
887 * configure: Regenerated to track ../common/aclocal.m4 changes.
888
889Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
890
891 * interp.c (sim_monitor): Handle Densan monitor outbyte
892 and inbyte functions.
893
8941997-12-29 Felix Lee <flee@cygnus.com>
895
896 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
897
898Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
899
900 * Makefile.in (tmp-igen): Arrange for $zero to always be
901 reset to zero after every instruction.
902
903Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
904
905 * configure: Regenerated to track ../common/aclocal.m4 changes.
906 * config.in: Ditto.
907
908Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
909
910 * mips.igen (MSUB): Fix to work like MADD.
911 * gencode.c (MSUB): Similarly.
912
913Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
914
915 * configure: Regenerated to track ../common/aclocal.m4 changes.
916
917Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
918
919 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
920
921Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
922
923 * sim-main.h (sim-fpu.h): Include.
924
925 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
926 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
927 using host independant sim_fpu module.
928
929Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
930
931 * interp.c (signal_exception): Report internal errors with SIGABRT
932 not SIGQUIT.
933
934 * sim-main.h (C0_CONFIG): New register.
935 (signal.h): No longer include.
936
937 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
938
939Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
940
941 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
942
943Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
944
945 * mips.igen: Tag vr5000 instructions.
946 (ANDI): Was missing mipsIV model, fix assembler syntax.
947 (do_c_cond_fmt): New function.
948 (C.cond.fmt): Handle mips I-III which do not support CC field
949 separatly.
950 (bc1): Handle mips IV which do not have a delaed FCC separatly.
951 (SDR): Mask paddr when BigEndianMem, not the converse as specified
952 in IV3.2 spec.
953 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
954 vr5000 which saves LO in a GPR separatly.
955
956 * configure.in (enable-sim-igen): For vr5000, select vr5000
957 specific instructions.
958 * configure: Re-generate.
959
960Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
961
962 * Makefile.in (SIM_OBJS): Add sim-fpu module.
963
964 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
965 fmt_uninterpreted_64 bit cases to switch. Convert to
966 fmt_formatted,
967
968 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
969
970 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
971 as specified in IV3.2 spec.
972 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
973
974Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
975
976 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
977 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
978 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
979 PENDING_FILL versions of instructions. Simplify.
980 (X): New function.
981 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
982 instructions.
983 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
984 a signed value.
985 (MTHI, MFHI): Disable code checking HI-LO.
986
987 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
988 global.
989 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
990
991Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
992
993 * gencode.c (build_mips16_operands): Replace IPC with cia.
994
995 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
996 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
997 IPC to `cia'.
998 (UndefinedResult): Replace function with macro/function
999 combination.
1000 (sim_engine_run): Don't save PC in IPC.
1001
1002 * sim-main.h (IPC): Delete.
1003
1004
1005 * interp.c (signal_exception, store_word, load_word,
1006 address_translation, load_memory, store_memory, cache_op,
1007 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1008 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1009 current instruction address - cia - argument.
1010 (sim_read, sim_write): Call address_translation directly.
1011 (sim_engine_run): Rename variable vaddr to cia.
1012 (signal_exception): Pass cia to sim_monitor
1013
1014 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1015 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1016 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1017
1018 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1019 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1020 SIM_ASSERT.
1021
1022 * interp.c (signal_exception): Pass restart address to
1023 sim_engine_restart.
1024
1025 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1026 idecode.o): Add dependency.
1027
1028 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1029 Delete definitions
1030 (DELAY_SLOT): Update NIA not PC with branch address.
1031 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1032
1033 * mips.igen: Use CIA not PC in branch calculations.
1034 (illegal): Call SignalException.
1035 (BEQ, ADDIU): Fix assembler.
1036
1037Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1038
1039 * m16.igen (JALX): Was missing.
1040
1041 * configure.in (enable-sim-igen): New configuration option.
1042 * configure: Re-generate.
1043
1044 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1045
1046 * interp.c (load_memory, store_memory): Delete parameter RAW.
1047 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1048 bypassing {load,store}_memory.
1049
1050 * sim-main.h (ByteSwapMem): Delete definition.
1051
1052 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1053
1054 * interp.c (sim_do_command, sim_commands): Delete mips specific
1055 commands. Handled by module sim-options.
1056
1057 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1058 (WITH_MODULO_MEMORY): Define.
1059
1060 * interp.c (sim_info): Delete code printing memory size.
1061
1062 * interp.c (mips_size): Nee sim_size, delete function.
1063 (power2): Delete.
1064 (monitor, monitor_base, monitor_size): Delete global variables.
1065 (sim_open, sim_close): Delete code creating monitor and other
1066 memory regions. Use sim-memopts module, via sim_do_commandf, to
1067 manage memory regions.
1068 (load_memory, store_memory): Use sim-core for memory model.
1069
1070 * interp.c (address_translation): Delete all memory map code
1071 except line forcing 32 bit addresses.
1072
1073Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1074
1075 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1076 trace options.
1077
1078 * interp.c (logfh, logfile): Delete globals.
1079 (sim_open, sim_close): Delete code opening & closing log file.
1080 (mips_option_handler): Delete -l and -n options.
1081 (OPTION mips_options): Ditto.
1082
1083 * interp.c (OPTION mips_options): Rename option trace to dinero.
1084 (mips_option_handler): Update.
1085
1086Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * interp.c (fetch_str): New function.
1089 (sim_monitor): Rewrite using sim_read & sim_write.
1090 (sim_open): Check magic number.
1091 (sim_open): Write monitor vectors into memory using sim_write.
1092 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1093 (sim_read, sim_write): Simplify - transfer data one byte at a
1094 time.
1095 (load_memory, store_memory): Clarify meaning of parameter RAW.
1096
1097 * sim-main.h (isHOST): Defete definition.
1098 (isTARGET): Mark as depreciated.
1099 (address_translation): Delete parameter HOST.
1100
1101 * interp.c (address_translation): Delete parameter HOST.
1102
1103Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * mips.igen:
1106
1107 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1108 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1109
1110Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1111
1112 * mips.igen: Add model filter field to records.
1113
1114Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1115
1116 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1117
1118 interp.c (sim_engine_run): Do not compile function sim_engine_run
1119 when WITH_IGEN == 1.
1120
1121 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1122 target architecture.
1123
1124 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1125 igen. Replace with configuration variables sim_igen_flags /
1126 sim_m16_flags.
1127
1128 * m16.igen: New file. Copy mips16 insns here.
1129 * mips.igen: From here.
1130
1131Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1132
1133 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1134 to top.
1135 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1136
1137Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1138
1139 * gencode.c (build_instruction): Follow sim_write's lead in using
1140 BigEndianMem instead of !ByteSwapMem.
1141
1142Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1143
1144 * configure.in (sim_gen): Dependent on target, select type of
1145 generator. Always select old style generator.
1146
1147 configure: Re-generate.
1148
1149 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1150 targets.
1151 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1152 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1153 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1154 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1155 SIM_@sim_gen@_*, set by autoconf.
1156
1157Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1158
1159 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1160
1161 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1162 CURRENT_FLOATING_POINT instead.
1163
1164 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1165 (address_translation): Raise exception InstructionFetch when
1166 translation fails and isINSTRUCTION.
1167
1168 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1169 sim_engine_run): Change type of of vaddr and paddr to
1170 address_word.
1171 (address_translation, prefetch, load_memory, store_memory,
1172 cache_op): Change type of vAddr and pAddr to address_word.
1173
1174 * gencode.c (build_instruction): Change type of vaddr and paddr to
1175 address_word.
1176
1177Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1178
1179 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1180 macro to obtain result of ALU op.
1181
1182Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1183
1184 * interp.c (sim_info): Call profile_print.
1185
1186Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1187
1188 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1189
1190 * sim-main.h (WITH_PROFILE): Do not define, defined in
1191 common/sim-config.h. Use sim-profile module.
1192 (simPROFILE): Delete defintion.
1193
1194 * interp.c (PROFILE): Delete definition.
1195 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1196 (sim_close): Delete code writing profile histogram.
1197 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1198 Delete.
1199 (sim_engine_run): Delete code profiling the PC.
1200
1201Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1202
1203 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1204
1205 * interp.c (sim_monitor): Make register pointers of type
1206 unsigned_word*.
1207
1208 * sim-main.h: Make registers of type unsigned_word not
1209 signed_word.
1210
1211Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1212
1213 * interp.c (sync_operation): Rename from SyncOperation, make
1214 global, add SD argument.
1215 (prefetch): Rename from Prefetch, make global, add SD argument.
1216 (decode_coproc): Make global.
1217
1218 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1219
1220 * gencode.c (build_instruction): Generate DecodeCoproc not
1221 decode_coproc calls.
1222
1223 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1224 (SizeFGR): Move to sim-main.h
1225 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1226 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1227 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1228 sim-main.h.
1229 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1230 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1231 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1232 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1233 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1234 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1235
1236 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1237 exception.
1238 (sim-alu.h): Include.
1239 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1240 (sim_cia): Typedef to instruction_address.
1241
1242Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1243
1244 * Makefile.in (interp.o): Rename generated file engine.c to
1245 oengine.c.
1246
1247 * interp.c: Update.
1248
1249Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1250
1251 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1252
1253Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1254
1255 * gencode.c (build_instruction): For "FPSQRT", output correct
1256 number of arguments to Recip.
1257
1258Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1259
1260 * Makefile.in (interp.o): Depends on sim-main.h
1261
1262 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1263
1264 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1265 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1266 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1267 STATE, DSSTATE): Define
1268 (GPR, FGRIDX, ..): Define.
1269
1270 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1271 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1272 (GPR, FGRIDX, ...): Delete macros.
1273
1274 * interp.c: Update names to match defines from sim-main.h
1275
1276Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1277
1278 * interp.c (sim_monitor): Add SD argument.
1279 (sim_warning): Delete. Replace calls with calls to
1280 sim_io_eprintf.
1281 (sim_error): Delete. Replace calls with sim_io_error.
1282 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1283 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1284 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1285 argument.
1286 (mips_size): Rename from sim_size. Add SD argument.
1287
1288 * interp.c (simulator): Delete global variable.
1289 (callback): Delete global variable.
1290 (mips_option_handler, sim_open, sim_write, sim_read,
1291 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1292 sim_size,sim_monitor): Use sim_io_* not callback->*.
1293 (sim_open): ZALLOC simulator struct.
1294 (PROFILE): Do not define.
1295
1296Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297
1298 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1299 support.h with corresponding code.
1300
1301 * sim-main.h (word64, uword64), support.h: Move definition to
1302 sim-main.h.
1303 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1304
1305 * support.h: Delete
1306 * Makefile.in: Update dependencies
1307 * interp.c: Do not include.
1308
1309Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 * interp.c (address_translation, load_memory, store_memory,
1312 cache_op): Rename to from AddressTranslation et.al., make global,
1313 add SD argument
1314
1315 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1316 CacheOp): Define.
1317
1318 * interp.c (SignalException): Rename to signal_exception, make
1319 global.
1320
1321 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1322
1323 * sim-main.h (SignalException, SignalExceptionInterrupt,
1324 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1325 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1326 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1327 Define.
1328
1329 * interp.c, support.h: Use.
1330
1331Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1334 to value_fpr / store_fpr. Add SD argument.
1335 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1336 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1337
1338 * sim-main.h (ValueFPR, StoreFPR): Define.
1339
1340Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1341
1342 * interp.c (sim_engine_run): Check consistency between configure
1343 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1344 and HASFPU.
1345
1346 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1347 (mips_fpu): Configure WITH_FLOATING_POINT.
1348 (mips_endian): Configure WITH_TARGET_ENDIAN.
1349 * configure: Update.
1350
1351Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1352
1353 * configure: Regenerated to track ../common/aclocal.m4 changes.
1354
1355Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1356
1357 * configure: Regenerated.
1358
1359Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1360
1361 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1362
1363Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1364
1365 * gencode.c (print_igen_insn_models): Assume certain architectures
1366 include all mips* instructions.
1367 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1368 instruction.
1369
1370 * Makefile.in (tmp.igen): Add target. Generate igen input from
1371 gencode file.
1372
1373 * gencode.c (FEATURE_IGEN): Define.
1374 (main): Add --igen option. Generate output in igen format.
1375 (process_instructions): Format output according to igen option.
1376 (print_igen_insn_format): New function.
1377 (print_igen_insn_models): New function.
1378 (process_instructions): Only issue warnings and ignore
1379 instructions when no FEATURE_IGEN.
1380
1381Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1382
1383 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1384 MIPS targets.
1385
1386Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1387
1388 * configure: Regenerated to track ../common/aclocal.m4 changes.
1389
1390Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1391
1392 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1393 SIM_RESERVED_BITS): Delete, moved to common.
1394 (SIM_EXTRA_CFLAGS): Update.
1395
1396Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1397
1398 * configure.in: Configure non-strict memory alignment.
1399 * configure: Regenerated to track ../common/aclocal.m4 changes.
1400
1401Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * configure: Regenerated to track ../common/aclocal.m4 changes.
1404
1405Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1406
1407 * gencode.c (SDBBP,DERET): Added (3900) insns.
1408 (RFE): Turn on for 3900.
1409 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1410 (dsstate): Made global.
1411 (SUBTARGET_R3900): Added.
1412 (CANCELDELAYSLOT): New.
1413 (SignalException): Ignore SystemCall rather than ignore and
1414 terminate. Add DebugBreakPoint handling.
1415 (decode_coproc): New insns RFE, DERET; and new registers Debug
1416 and DEPC protected by SUBTARGET_R3900.
1417 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1418 bits explicitly.
1419 * Makefile.in,configure.in: Add mips subtarget option.
1420 * configure: Update.
1421
1422Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1423
1424 * gencode.c: Add r3900 (tx39).
1425
1426
1427Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1428
1429 * gencode.c (build_instruction): Don't need to subtract 4 for
1430 JALR, just 2.
1431
1432Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1433
1434 * interp.c: Correct some HASFPU problems.
1435
1436Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * configure: Regenerated to track ../common/aclocal.m4 changes.
1439
1440Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441
1442 * interp.c (mips_options): Fix samples option short form, should
1443 be `x'.
1444
1445Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * interp.c (sim_info): Enable info code. Was just returning.
1448
1449Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1450
1451 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1452 MFC0.
1453
1454Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1457 constants.
1458 (build_instruction): Ditto for LL.
1459
1460Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1461
1462 * configure: Regenerated to track ../common/aclocal.m4 changes.
1463
1464Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465
1466 * configure: Regenerated to track ../common/aclocal.m4 changes.
1467 * config.in: Ditto.
1468
1469Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1470
1471 * interp.c (sim_open): Add call to sim_analyze_program, update
1472 call to sim_config.
1473
1474Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * interp.c (sim_kill): Delete.
1477 (sim_create_inferior): Add ABFD argument. Set PC from same.
1478 (sim_load): Move code initializing trap handlers from here.
1479 (sim_open): To here.
1480 (sim_load): Delete, use sim-hload.c.
1481
1482 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1483
1484Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1485
1486 * configure: Regenerated to track ../common/aclocal.m4 changes.
1487 * config.in: Ditto.
1488
1489Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 * interp.c (sim_open): Add ABFD argument.
1492 (sim_load): Move call to sim_config from here.
1493 (sim_open): To here. Check return status.
1494
1495Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1496
1497 * gencode.c (build_instruction): Two arg MADD should
1498 not assign result to $0.
1499
1500Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1501
1502 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1503 * sim/mips/configure.in: Regenerate.
1504
1505Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1506
1507 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1508 signed8, unsigned8 et.al. types.
1509
1510 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1511 hosts when selecting subreg.
1512
1513Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1514
1515 * interp.c (sim_engine_run): Reset the ZERO register to zero
1516 regardless of FEATURE_WARN_ZERO.
1517 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1518
1519Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520
1521 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1522 (SignalException): For BreakPoints ignore any mode bits and just
1523 save the PC.
1524 (SignalException): Always set the CAUSE register.
1525
1526Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1527
1528 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1529 exception has been taken.
1530
1531 * interp.c: Implement the ERET and mt/f sr instructions.
1532
1533Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 * interp.c (SignalException): Don't bother restarting an
1536 interrupt.
1537
1538Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539
1540 * interp.c (SignalException): Really take an interrupt.
1541 (interrupt_event): Only deliver interrupts when enabled.
1542
1543Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1544
1545 * interp.c (sim_info): Only print info when verbose.
1546 (sim_info) Use sim_io_printf for output.
1547
1548Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549
1550 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1551 mips architectures.
1552
1553Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1554
1555 * interp.c (sim_do_command): Check for common commands if a
1556 simulator specific command fails.
1557
1558Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1559
1560 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1561 and simBE when DEBUG is defined.
1562
1563Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564
1565 * interp.c (interrupt_event): New function. Pass exception event
1566 onto exception handler.
1567
1568 * configure.in: Check for stdlib.h.
1569 * configure: Regenerate.
1570
1571 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1572 variable declaration.
1573 (build_instruction): Initialize memval1.
1574 (build_instruction): Add UNUSED attribute to byte, bigend,
1575 reverse.
1576 (build_operands): Ditto.
1577
1578 * interp.c: Fix GCC warnings.
1579 (sim_get_quit_code): Delete.
1580
1581 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1582 * Makefile.in: Ditto.
1583 * configure: Re-generate.
1584
1585 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1586
1587Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1588
1589 * interp.c (mips_option_handler): New function parse argumes using
1590 sim-options.
1591 (myname): Replace with STATE_MY_NAME.
1592 (sim_open): Delete check for host endianness - performed by
1593 sim_config.
1594 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1595 (sim_open): Move much of the initialization from here.
1596 (sim_load): To here. After the image has been loaded and
1597 endianness set.
1598 (sim_open): Move ColdReset from here.
1599 (sim_create_inferior): To here.
1600 (sim_open): Make FP check less dependant on host endianness.
1601
1602 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1603 run.
1604 * interp.c (sim_set_callbacks): Delete.
1605
1606 * interp.c (membank, membank_base, membank_size): Replace with
1607 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1608 (sim_open): Remove call to callback->init. gdb/run do this.
1609
1610 * interp.c: Update
1611
1612 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1613
1614 * interp.c (big_endian_p): Delete, replaced by
1615 current_target_byte_order.
1616
1617Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * interp.c (host_read_long, host_read_word, host_swap_word,
1620 host_swap_long): Delete. Using common sim-endian.
1621 (sim_fetch_register, sim_store_register): Use H2T.
1622 (pipeline_ticks): Delete. Handled by sim-events.
1623 (sim_info): Update.
1624 (sim_engine_run): Update.
1625
1626Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1627
1628 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1629 reason from here.
1630 (SignalException): To here. Signal using sim_engine_halt.
1631 (sim_stop_reason): Delete, moved to common.
1632
1633Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1634
1635 * interp.c (sim_open): Add callback argument.
1636 (sim_set_callbacks): Delete SIM_DESC argument.
1637 (sim_size): Ditto.
1638
1639Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * Makefile.in (SIM_OBJS): Add common modules.
1642
1643 * interp.c (sim_set_callbacks): Also set SD callback.
1644 (set_endianness, xfer_*, swap_*): Delete.
1645 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1646 Change to functions using sim-endian macros.
1647 (control_c, sim_stop): Delete, use common version.
1648 (simulate): Convert into.
1649 (sim_engine_run): This function.
1650 (sim_resume): Delete.
1651
1652 * interp.c (simulation): New variable - the simulator object.
1653 (sim_kind): Delete global - merged into simulation.
1654 (sim_load): Cleanup. Move PC assignment from here.
1655 (sim_create_inferior): To here.
1656
1657 * sim-main.h: New file.
1658 * interp.c (sim-main.h): Include.
1659
1660Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1661
1662 * configure: Regenerated to track ../common/aclocal.m4 changes.
1663
1664Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1665
1666 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1667
1668Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1669
1670 * gencode.c (build_instruction): DIV instructions: check
1671 for division by zero and integer overflow before using
1672 host's division operation.
1673
1674Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1675
1676 * Makefile.in (SIM_OBJS): Add sim-load.o.
1677 * interp.c: #include bfd.h.
1678 (target_byte_order): Delete.
1679 (sim_kind, myname, big_endian_p): New static locals.
1680 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1681 after argument parsing. Recognize -E arg, set endianness accordingly.
1682 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1683 load file into simulator. Set PC from bfd.
1684 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1685 (set_endianness): Use big_endian_p instead of target_byte_order.
1686
1687Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1688
1689 * interp.c (sim_size): Delete prototype - conflicts with
1690 definition in remote-sim.h. Correct definition.
1691
1692Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1693
1694 * configure: Regenerated to track ../common/aclocal.m4 changes.
1695 * config.in: Ditto.
1696
1697Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1698
1699 * interp.c (sim_open): New arg `kind'.
1700
1701 * configure: Regenerated to track ../common/aclocal.m4 changes.
1702
1703Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1704
1705 * configure: Regenerated to track ../common/aclocal.m4 changes.
1706
1707Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1708
1709 * interp.c (sim_open): Set optind to 0 before calling getopt.
1710
1711Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1712
1713 * configure: Regenerated to track ../common/aclocal.m4 changes.
1714
1715Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1716
1717 * interp.c : Replace uses of pr_addr with pr_uword64
1718 where the bit length is always 64 independent of SIM_ADDR.
1719 (pr_uword64) : added.
1720
1721Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1722
1723 * configure: Re-generate.
1724
1725Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1726
1727 * configure: Regenerate to track ../common/aclocal.m4 changes.
1728
1729Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1730
1731 * interp.c (sim_open): New SIM_DESC result. Argument is now
1732 in argv form.
1733 (other sim_*): New SIM_DESC argument.
1734
1735Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1736
1737 * interp.c: Fix printing of addresses for non-64-bit targets.
1738 (pr_addr): Add function to print address based on size.
1739
1740Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1741
1742 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1743
1744Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1745
1746 * gencode.c (build_mips16_operands): Correct computation of base
1747 address for extended PC relative instruction.
1748
1749Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1750
1751 * interp.c (mips16_entry): Add support for floating point cases.
1752 (SignalException): Pass floating point cases to mips16_entry.
1753 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1754 registers.
1755 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1756 or fmt_word.
1757 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1758 and then set the state to fmt_uninterpreted.
1759 (COP_SW): Temporarily set the state to fmt_word while calling
1760 ValueFPR.
1761
1762Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1763
1764 * gencode.c (build_instruction): The high order may be set in the
1765 comparison flags at any ISA level, not just ISA 4.
1766
1767Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1768
1769 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1770 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1771 * configure.in: sinclude ../common/aclocal.m4.
1772 * configure: Regenerated.
1773
1774Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1775
1776 * configure: Rebuild after change to aclocal.m4.
1777
1778Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1779
1780 * configure configure.in Makefile.in: Update to new configure
1781 scheme which is more compatible with WinGDB builds.
1782 * configure.in: Improve comment on how to run autoconf.
1783 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1784 * Makefile.in: Use autoconf substitution to install common
1785 makefile fragment.
1786
1787Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1788
1789 * gencode.c (build_instruction): Use BigEndianCPU instead of
1790 ByteSwapMem.
1791
1792Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1793
1794 * interp.c (sim_monitor): Make output to stdout visible in
1795 wingdb's I/O log window.
1796
1797Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1798
1799 * support.h: Undo previous change to SIGTRAP
1800 and SIGQUIT values.
1801
1802Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1803
1804 * interp.c (store_word, load_word): New static functions.
1805 (mips16_entry): New static function.
1806 (SignalException): Look for mips16 entry and exit instructions.
1807 (simulate): Use the correct index when setting fpr_state after
1808 doing a pending move.
1809
1810Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1811
1812 * interp.c: Fix byte-swapping code throughout to work on
1813 both little- and big-endian hosts.
1814
1815Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1816
1817 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1818 with gdb/config/i386/xm-windows.h.
1819
1820Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1821
1822 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1823 that messes up arithmetic shifts.
1824
1825Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1826
1827 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1828 SIGTRAP and SIGQUIT for _WIN32.
1829
1830Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1831
1832 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1833 force a 64 bit multiplication.
1834 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1835 destination register is 0, since that is the default mips16 nop
1836 instruction.
1837
1838Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1839
1840 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1841 (build_endian_shift): Don't check proc64.
1842 (build_instruction): Always set memval to uword64. Cast op2 to
1843 uword64 when shifting it left in memory instructions. Always use
1844 the same code for stores--don't special case proc64.
1845
1846 * gencode.c (build_mips16_operands): Fix base PC value for PC
1847 relative operands.
1848 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1849 jal instruction.
1850 * interp.c (simJALDELAYSLOT): Define.
1851 (JALDELAYSLOT): Define.
1852 (INDELAYSLOT, INJALDELAYSLOT): Define.
1853 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1854
1855Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1856
1857 * interp.c (sim_open): add flush_cache as a PMON routine
1858 (sim_monitor): handle flush_cache by ignoring it
1859
1860Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1861
1862 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1863 BigEndianMem.
1864 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1865 (BigEndianMem): Rename to ByteSwapMem and change sense.
1866 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1867 BigEndianMem references to !ByteSwapMem.
1868 (set_endianness): New function, with prototype.
1869 (sim_open): Call set_endianness.
1870 (sim_info): Use simBE instead of BigEndianMem.
1871 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1872 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1873 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1874 ifdefs, keeping the prototype declaration.
1875 (swap_word): Rewrite correctly.
1876 (ColdReset): Delete references to CONFIG. Delete endianness related
1877 code; moved to set_endianness.
1878
1879Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1880
1881 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1882 * interp.c (CHECKHILO): Define away.
1883 (simSIGINT): New macro.
1884 (membank_size): Increase from 1MB to 2MB.
1885 (control_c): New function.
1886 (sim_resume): Rename parameter signal to signal_number. Add local
1887 variable prev. Call signal before and after simulate.
1888 (sim_stop_reason): Add simSIGINT support.
1889 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1890 functions always.
1891 (sim_warning): Delete call to SignalException. Do call printf_filtered
1892 if logfh is NULL.
1893 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1894 a call to sim_warning.
1895
1896Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1897
1898 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1899 16 bit instructions.
1900
1901Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1902
1903 Add support for mips16 (16 bit MIPS implementation):
1904 * gencode.c (inst_type): Add mips16 instruction encoding types.
1905 (GETDATASIZEINSN): Define.
1906 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1907 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1908 mtlo.
1909 (MIPS16_DECODE): New table, for mips16 instructions.
1910 (bitmap_val): New static function.
1911 (struct mips16_op): Define.
1912 (mips16_op_table): New table, for mips16 operands.
1913 (build_mips16_operands): New static function.
1914 (process_instructions): If PC is odd, decode a mips16
1915 instruction. Break out instruction handling into new
1916 build_instruction function.
1917 (build_instruction): New static function, broken out of
1918 process_instructions. Check modifiers rather than flags for SHIFT
1919 bit count and m[ft]{hi,lo} direction.
1920 (usage): Pass program name to fprintf.
1921 (main): Remove unused variable this_option_optind. Change
1922 ``*loptarg++'' to ``loptarg++''.
1923 (my_strtoul): Parenthesize && within ||.
1924 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1925 (simulate): If PC is odd, fetch a 16 bit instruction, and
1926 increment PC by 2 rather than 4.
1927 * configure.in: Add case for mips16*-*-*.
1928 * configure: Rebuild.
1929
1930Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1931
1932 * interp.c: Allow -t to enable tracing in standalone simulator.
1933 Fix garbage output in trace file and error messages.
1934
1935Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1936
1937 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1938 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1939 * configure.in: Simplify using macros in ../common/aclocal.m4.
1940 * configure: Regenerated.
1941 * tconfig.in: New file.
1942
1943Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1944
1945 * interp.c: Fix bugs in 64-bit port.
1946 Use ansi function declarations for msvc compiler.
1947 Initialize and test file pointer in trace code.
1948 Prevent duplicate definition of LAST_EMED_REGNUM.
1949
1950Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1951
1952 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1953
1954Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1955
1956 * interp.c (SignalException): Check for explicit terminating
1957 breakpoint value.
1958 * gencode.c: Pass instruction value through SignalException()
1959 calls for Trap, Breakpoint and Syscall.
1960
1961Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1962
1963 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1964 only used on those hosts that provide it.
1965 * configure.in: Add sqrt() to list of functions to be checked for.
1966 * config.in: Re-generated.
1967 * configure: Re-generated.
1968
1969Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1970
1971 * gencode.c (process_instructions): Call build_endian_shift when
1972 expanding STORE RIGHT, to fix swr.
1973 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1974 clear the high bits.
1975 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1976 Fix float to int conversions to produce signed values.
1977
1978Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1979
1980 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1981 (process_instructions): Correct handling of nor instruction.
1982 Correct shift count for 32 bit shift instructions. Correct sign
1983 extension for arithmetic shifts to not shift the number of bits in
1984 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1985 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1986 Fix madd.
1987 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1988 It's OK to have a mult follow a mult. What's not OK is to have a
1989 mult follow an mfhi.
1990 (Convert): Comment out incorrect rounding code.
1991
1992Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1993
1994 * interp.c (sim_monitor): Improved monitor printf
1995 simulation. Tidied up simulator warnings, and added "--log" option
1996 for directing warning message output.
1997 * gencode.c: Use sim_warning() rather than WARNING macro.
1998
1999Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2000
2001 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2002 getopt1.o, rather than on gencode.c. Link objects together.
2003 Don't link against -liberty.
2004 (gencode.o, getopt.o, getopt1.o): New targets.
2005 * gencode.c: Include <ctype.h> and "ansidecl.h".
2006 (AND): Undefine after including "ansidecl.h".
2007 (ULONG_MAX): Define if not defined.
2008 (OP_*): Don't define macros; now defined in opcode/mips.h.
2009 (main): Call my_strtoul rather than strtoul.
2010 (my_strtoul): New static function.
2011
2012Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2013
2014 * gencode.c (process_instructions): Generate word64 and uword64
2015 instead of `long long' and `unsigned long long' data types.
2016 * interp.c: #include sysdep.h to get signals, and define default
2017 for SIGBUS.
2018 * (Convert): Work around for Visual-C++ compiler bug with type
2019 conversion.
2020 * support.h: Make things compile under Visual-C++ by using
2021 __int64 instead of `long long'. Change many refs to long long
2022 into word64/uword64 typedefs.
2023
2024Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2025
2026 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2027 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2028 (docdir): Removed.
2029 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2030 (AC_PROG_INSTALL): Added.
2031 (AC_PROG_CC): Moved to before configure.host call.
2032 * configure: Rebuilt.
2033
2034Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2035
2036 * configure.in: Define @SIMCONF@ depending on mips target.
2037 * configure: Rebuild.
2038 * Makefile.in (run): Add @SIMCONF@ to control simulator
2039 construction.
2040 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2041 * interp.c: Remove some debugging, provide more detailed error
2042 messages, update memory accesses to use LOADDRMASK.
2043
2044Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2045
2046 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2047 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2048 stamp-h.
2049 * configure: Rebuild.
2050 * config.in: New file, generated by autoheader.
2051 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2052 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2053 HAVE_ANINT and HAVE_AINT, as appropriate.
2054 * Makefile.in (run): Use @LIBS@ rather than -lm.
2055 (interp.o): Depend upon config.h.
2056 (Makefile): Just rebuild Makefile.
2057 (clean): Remove stamp-h.
2058 (mostlyclean): Make the same as clean, not as distclean.
2059 (config.h, stamp-h): New targets.
2060
2061Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2062
2063 * interp.c (ColdReset): Fix boolean test. Make all simulator
2064 globals static.
2065
2066Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2067
2068 * interp.c (xfer_direct_word, xfer_direct_long,
2069 swap_direct_word, swap_direct_long, xfer_big_word,
2070 xfer_big_long, xfer_little_word, xfer_little_long,
2071 swap_word,swap_long): Added.
2072 * interp.c (ColdReset): Provide function indirection to
2073 host<->simulated_target transfer routines.
2074 * interp.c (sim_store_register, sim_fetch_register): Updated to
2075 make use of indirected transfer routines.
2076
2077Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2078
2079 * gencode.c (process_instructions): Ensure FP ABS instruction
2080 recognised.
2081 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2082 system call support.
2083
2084Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2085
2086 * interp.c (sim_do_command): Complain if callback structure not
2087 initialised.
2088
2089Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2090
2091 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2092 support for Sun hosts.
2093 * Makefile.in (gencode): Ensure the host compiler and libraries
2094 used for cross-hosted build.
2095
2096Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2097
2098 * interp.c, gencode.c: Some more (TODO) tidying.
2099
2100Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2101
2102 * gencode.c, interp.c: Replaced explicit long long references with
2103 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2104 * support.h (SET64LO, SET64HI): Macros added.
2105
2106Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2107
2108 * configure: Regenerate with autoconf 2.7.
2109
2110Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2111
2112 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2113 * support.h: Remove superfluous "1" from #if.
2114 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2115
2116Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2117
2118 * interp.c (StoreFPR): Control UndefinedResult() call on
2119 WARN_RESULT manifest.
2120
2121Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2122
2123 * gencode.c: Tidied instruction decoding, and added FP instruction
2124 support.
2125
2126 * interp.c: Added dineroIII, and BSD profiling support. Also
2127 run-time FP handling.
2128
2129Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2130
2131 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2132 gencode.c, interp.c, support.h: created.
A mirror of the official binutils-gdb repository