]> git.ipfire.org Git - thirdparty/qemu.git/blame - target-sparc/translate.c
projects / thirdparty / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Make likely/unlikely accessible also in hw/.
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
3475187d 28 128-bit float
bd497938 29*/
7a3f1944
FB		 30
31#include <stdarg.h>
32#include <stdlib.h>
33#include <stdio.h>
34#include <string.h>
35#include <inttypes.h>
36
37#include "cpu.h"
38#include "exec-all.h"
39#include "disas.h"
40
41#define DEBUG_DISAS
42
72cbca10
FB		 43#define DYNAMIC_PC 1 /* dynamic pc value */
44#define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
46
7a3f1944 47typedef struct DisasContext {
72cbca10
FB		 48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 51 int is_br;
e8af50a3 52 int mem_idx;
a80dde08 53 int fpu_enabled;
cf495bcf 54 struct TranslationBlock *tb;
7a3f1944
FB		 55} DisasContext;
56
62724a37
BS		 57struct sparc_def_t {
58 const unsigned char *name;
59 target_ulong iu_version;
60 uint32_t fpu_version;
61 uint32_t mmu_version;
62};
63
7a3f1944
FB		 64static uint16_t *gen_opc_ptr;
65static uint32_t *gen_opparam_ptr;
66extern FILE *logfile;
67extern int loglevel;
68
69enum {
70#define DEF(s,n,copy_size) INDEX_op_ ## s,
71#include "opc.h"
72#undef DEF
cf495bcf 73 NB_OPS
7a3f1944
FB		 74};
75
76#include "gen-op.h"
77
3475187d 78// This function uses non-native bit order
7a3f1944
FB		 79#define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
81
3475187d
FB		 82// This function uses the order in the manuals, i.e. bit 0 is 2^0
83#define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
85
86#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 87#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 88
89#ifdef TARGET_SPARC64
90#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
91#else
c185970a 92#define DFPREG(r) (r & 0x1e)
3475187d
FB		 93#endif
94
83469015
FB		 95#ifdef USE_DIRECT_JUMP
96#define TBPARAM(x)
97#else
98#define TBPARAM(x) (long)(x)
99#endif
100
3475187d
FB		 101static int sign_extend(int x, int len)
102{
103 len = 32 - len;
104 return (x << len) >> len;
105}
106
7a3f1944
FB		 107#define IS_IMM (insn & (1<<13))
108
cf495bcf 109static void disas_sparc_insn(DisasContext * dc);
7a3f1944 110
a68156d0 111static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 112 {
113 gen_op_movl_g0_T0,
114 gen_op_movl_g1_T0,
115 gen_op_movl_g2_T0,
116 gen_op_movl_g3_T0,
117 gen_op_movl_g4_T0,
118 gen_op_movl_g5_T0,
119 gen_op_movl_g6_T0,
120 gen_op_movl_g7_T0,
121 gen_op_movl_o0_T0,
122 gen_op_movl_o1_T0,
123 gen_op_movl_o2_T0,
124 gen_op_movl_o3_T0,
125 gen_op_movl_o4_T0,
126 gen_op_movl_o5_T0,
127 gen_op_movl_o6_T0,
128 gen_op_movl_o7_T0,
129 gen_op_movl_l0_T0,
130 gen_op_movl_l1_T0,
131 gen_op_movl_l2_T0,
132 gen_op_movl_l3_T0,
133 gen_op_movl_l4_T0,
134 gen_op_movl_l5_T0,
135 gen_op_movl_l6_T0,
136 gen_op_movl_l7_T0,
137 gen_op_movl_i0_T0,
138 gen_op_movl_i1_T0,
139 gen_op_movl_i2_T0,
140 gen_op_movl_i3_T0,
141 gen_op_movl_i4_T0,
142 gen_op_movl_i5_T0,
143 gen_op_movl_i6_T0,
144 gen_op_movl_i7_T0,
145 },
146 {
147 gen_op_movl_g0_T1,
148 gen_op_movl_g1_T1,
149 gen_op_movl_g2_T1,
150 gen_op_movl_g3_T1,
151 gen_op_movl_g4_T1,
152 gen_op_movl_g5_T1,
153 gen_op_movl_g6_T1,
154 gen_op_movl_g7_T1,
155 gen_op_movl_o0_T1,
156 gen_op_movl_o1_T1,
157 gen_op_movl_o2_T1,
158 gen_op_movl_o3_T1,
159 gen_op_movl_o4_T1,
160 gen_op_movl_o5_T1,
161 gen_op_movl_o6_T1,
162 gen_op_movl_o7_T1,
163 gen_op_movl_l0_T1,
164 gen_op_movl_l1_T1,
165 gen_op_movl_l2_T1,
166 gen_op_movl_l3_T1,
167 gen_op_movl_l4_T1,
168 gen_op_movl_l5_T1,
169 gen_op_movl_l6_T1,
170 gen_op_movl_l7_T1,
171 gen_op_movl_i0_T1,
172 gen_op_movl_i1_T1,
173 gen_op_movl_i2_T1,
174 gen_op_movl_i3_T1,
175 gen_op_movl_i4_T1,
176 gen_op_movl_i5_T1,
177 gen_op_movl_i6_T1,
178 gen_op_movl_i7_T1,
179 }
7a3f1944
FB		 180};
181
a68156d0 182static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 183 {
184 gen_op_movl_T0_g0,
185 gen_op_movl_T0_g1,
186 gen_op_movl_T0_g2,
187 gen_op_movl_T0_g3,
188 gen_op_movl_T0_g4,
189 gen_op_movl_T0_g5,
190 gen_op_movl_T0_g6,
191 gen_op_movl_T0_g7,
192 gen_op_movl_T0_o0,
193 gen_op_movl_T0_o1,
194 gen_op_movl_T0_o2,
195 gen_op_movl_T0_o3,
196 gen_op_movl_T0_o4,
197 gen_op_movl_T0_o5,
198 gen_op_movl_T0_o6,
199 gen_op_movl_T0_o7,
200 gen_op_movl_T0_l0,
201 gen_op_movl_T0_l1,
202 gen_op_movl_T0_l2,
203 gen_op_movl_T0_l3,
204 gen_op_movl_T0_l4,
205 gen_op_movl_T0_l5,
206 gen_op_movl_T0_l6,
207 gen_op_movl_T0_l7,
208 gen_op_movl_T0_i0,
209 gen_op_movl_T0_i1,
210 gen_op_movl_T0_i2,
211 gen_op_movl_T0_i3,
212 gen_op_movl_T0_i4,
213 gen_op_movl_T0_i5,
214 gen_op_movl_T0_i6,
215 gen_op_movl_T0_i7,
216 },
217 {
218 gen_op_movl_T1_g0,
219 gen_op_movl_T1_g1,
220 gen_op_movl_T1_g2,
221 gen_op_movl_T1_g3,
222 gen_op_movl_T1_g4,
223 gen_op_movl_T1_g5,
224 gen_op_movl_T1_g6,
225 gen_op_movl_T1_g7,
226 gen_op_movl_T1_o0,
227 gen_op_movl_T1_o1,
228 gen_op_movl_T1_o2,
229 gen_op_movl_T1_o3,
230 gen_op_movl_T1_o4,
231 gen_op_movl_T1_o5,
232 gen_op_movl_T1_o6,
233 gen_op_movl_T1_o7,
234 gen_op_movl_T1_l0,
235 gen_op_movl_T1_l1,
236 gen_op_movl_T1_l2,
237 gen_op_movl_T1_l3,
238 gen_op_movl_T1_l4,
239 gen_op_movl_T1_l5,
240 gen_op_movl_T1_l6,
241 gen_op_movl_T1_l7,
242 gen_op_movl_T1_i0,
243 gen_op_movl_T1_i1,
244 gen_op_movl_T1_i2,
245 gen_op_movl_T1_i3,
246 gen_op_movl_T1_i4,
247 gen_op_movl_T1_i5,
248 gen_op_movl_T1_i6,
249 gen_op_movl_T1_i7,
250 },
251 {
252 gen_op_movl_T2_g0,
253 gen_op_movl_T2_g1,
254 gen_op_movl_T2_g2,
255 gen_op_movl_T2_g3,
256 gen_op_movl_T2_g4,
257 gen_op_movl_T2_g5,
258 gen_op_movl_T2_g6,
259 gen_op_movl_T2_g7,
260 gen_op_movl_T2_o0,
261 gen_op_movl_T2_o1,
262 gen_op_movl_T2_o2,
263 gen_op_movl_T2_o3,
264 gen_op_movl_T2_o4,
265 gen_op_movl_T2_o5,
266 gen_op_movl_T2_o6,
267 gen_op_movl_T2_o7,
268 gen_op_movl_T2_l0,
269 gen_op_movl_T2_l1,
270 gen_op_movl_T2_l2,
271 gen_op_movl_T2_l3,
272 gen_op_movl_T2_l4,
273 gen_op_movl_T2_l5,
274 gen_op_movl_T2_l6,
275 gen_op_movl_T2_l7,
276 gen_op_movl_T2_i0,
277 gen_op_movl_T2_i1,
278 gen_op_movl_T2_i2,
279 gen_op_movl_T2_i3,
280 gen_op_movl_T2_i4,
281 gen_op_movl_T2_i5,
282 gen_op_movl_T2_i6,
283 gen_op_movl_T2_i7,
284 }
7a3f1944
FB		 285};
286
a68156d0 287static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
cf495bcf
FB		 288 gen_op_movl_T0_im,
289 gen_op_movl_T1_im,
290 gen_op_movl_T2_im
7a3f1944
FB		 291};
292
3475187d
FB		 293// Sign extending version
294static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
295 gen_op_movl_T0_sim,
296 gen_op_movl_T1_sim,
297 gen_op_movl_T2_sim
298};
299
300#ifdef TARGET_SPARC64
301#define GEN32(func, NAME) \
a68156d0 302static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 303NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
315}; \
316static inline void func(int n) \
317{ \
318 NAME ## _table[n](); \
319}
320#else
e8af50a3 321#define GEN32(func, NAME) \
a68156d0 322static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 323NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
331}; \
332static inline void func(int n) \
333{ \
334 NAME ## _table[n](); \
335}
3475187d 336#endif
e8af50a3
FB		 337
338/* floating point registers moves */
339GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 341GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 343
344GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 346GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 348
6ea4a6c8
BS		 349#ifdef ALIGN_7_BUGS_FIXED
350#else
351#ifndef CONFIG_USER_ONLY
352#define gen_op_check_align_T0_7()
353#endif
354#endif
355
3475187d
FB		 356#ifdef TARGET_SPARC64
357// 'a' versions allowed to user depending on asi
358#if defined(CONFIG_USER_ONLY)
359#define supervisor(dc) 0
e9ebed4d 360#define hypervisor(dc) 0
3475187d
FB		 361#define gen_op_ldst(name) gen_op_##name##_raw()
362#define OP_LD_TABLE(width) \
363 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
364 { \
365 int asi, offset; \
366 \
367 if (IS_IMM) { \
368 offset = GET_FIELD(insn, 25, 31); \
369 if (is_ld) \
370 gen_op_ld_asi_reg(offset, size, sign); \
371 else \
372 gen_op_st_asi_reg(offset, size, sign); \
373 return; \
374 } \
375 asi = GET_FIELD(insn, 19, 26); \
376 switch (asi) { \
377 case 0x80: /* Primary address space */ \
378 gen_op_##width##_raw(); \
379 break; \
725cb90b
FB		 380 case 0x82: /* Primary address space, non-faulting load */ \
381 gen_op_##width##_raw(); \
382 break; \
3475187d
FB		 383 default: \
384 break; \
385 } \
386 }
387
388#else
389#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
390#define OP_LD_TABLE(width) \
a68156d0 391 static GenOpFunc * const gen_op_##width[] = { \
3475187d
FB		 392 &gen_op_##width##_user, \
393 &gen_op_##width##_kernel, \
394 }; \
395 \
396 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
397 { \
398 int asi, offset; \
399 \
400 if (IS_IMM) { \
401 offset = GET_FIELD(insn, 25, 31); \
402 if (is_ld) \
403 gen_op_ld_asi_reg(offset, size, sign); \
404 else \
405 gen_op_st_asi_reg(offset, size, sign); \
406 return; \
407 } \
408 asi = GET_FIELD(insn, 19, 26); \
409 if (is_ld) \
410 gen_op_ld_asi(asi, size, sign); \
411 else \
412 gen_op_st_asi(asi, size, sign); \
413 }
414
415#define supervisor(dc) (dc->mem_idx == 1)
e9ebed4d 416#define hypervisor(dc) (dc->mem_idx == 2)
3475187d
FB		 417#endif
418#else
e8af50a3
FB		 419#if defined(CONFIG_USER_ONLY)
420#define gen_op_ldst(name) gen_op_##name##_raw()
0fa85d43 421#define OP_LD_TABLE(width)
e8af50a3
FB		 422#define supervisor(dc) 0
423#else
424#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
425#define OP_LD_TABLE(width) \
a68156d0 426static GenOpFunc * const gen_op_##width[] = { \
e8af50a3
FB		 427 &gen_op_##width##_user, \
428 &gen_op_##width##_kernel, \
429}; \
430 \
431static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
432{ \
433 int asi; \
434 \
435 asi = GET_FIELD(insn, 19, 26); \
436 switch (asi) { \
437 case 10: /* User data access */ \
438 gen_op_##width##_user(); \
439 break; \
440 case 11: /* Supervisor data access */ \
441 gen_op_##width##_kernel(); \
442 break; \
443 case 0x20 ... 0x2f: /* MMU passthrough */ \
444 if (is_ld) \
445 gen_op_ld_asi(asi, size, sign); \
446 else \
447 gen_op_st_asi(asi, size, sign); \
448 break; \
449 default: \
450 if (is_ld) \
451 gen_op_ld_asi(asi, size, sign); \
452 else \
453 gen_op_st_asi(asi, size, sign); \
454 break; \
455 } \
456}
457
458#define supervisor(dc) (dc->mem_idx == 1)
459#endif
3475187d 460#endif
e8af50a3
FB		 461
462OP_LD_TABLE(ld);
463OP_LD_TABLE(st);
464OP_LD_TABLE(ldub);
465OP_LD_TABLE(lduh);
466OP_LD_TABLE(ldsb);
467OP_LD_TABLE(ldsh);
468OP_LD_TABLE(stb);
469OP_LD_TABLE(sth);
470OP_LD_TABLE(std);
471OP_LD_TABLE(ldstub);
472OP_LD_TABLE(swap);
473OP_LD_TABLE(ldd);
474OP_LD_TABLE(stf);
475OP_LD_TABLE(stdf);
476OP_LD_TABLE(ldf);
477OP_LD_TABLE(lddf);
478
3475187d 479#ifdef TARGET_SPARC64
dc011987 480OP_LD_TABLE(lduw);
3475187d
FB		 481OP_LD_TABLE(ldsw);
482OP_LD_TABLE(ldx);
483OP_LD_TABLE(stx);
484OP_LD_TABLE(cas);
485OP_LD_TABLE(casx);
486#endif
487
488static inline void gen_movl_imm_TN(int reg, uint32_t imm)
7a3f1944 489{
83469015 490 gen_op_movl_TN_im[reg](imm);
7a3f1944
FB		 491}
492
3475187d 493static inline void gen_movl_imm_T1(uint32_t val)
7a3f1944 494{
cf495bcf 495 gen_movl_imm_TN(1, val);
7a3f1944
FB		 496}
497
3475187d 498static inline void gen_movl_imm_T0(uint32_t val)
7a3f1944 499{
cf495bcf 500 gen_movl_imm_TN(0, val);
7a3f1944
FB		 501}
502
3475187d
FB		 503static inline void gen_movl_simm_TN(int reg, int32_t imm)
504{
505 gen_op_movl_TN_sim[reg](imm);
506}
507
508static inline void gen_movl_simm_T1(int32_t val)
509{
510 gen_movl_simm_TN(1, val);
511}
512
513static inline void gen_movl_simm_T0(int32_t val)
514{
515 gen_movl_simm_TN(0, val);
516}
517
cf495bcf 518static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 519{
cf495bcf
FB		 520 if (reg)
521 gen_op_movl_reg_TN[t][reg] ();
522 else
523 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 524}
525
cf495bcf 526static inline void gen_movl_reg_T0(int reg)
7a3f1944 527{
cf495bcf 528 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 529}
530
cf495bcf 531static inline void gen_movl_reg_T1(int reg)
7a3f1944 532{
cf495bcf 533 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 534}
535
cf495bcf 536static inline void gen_movl_reg_T2(int reg)
7a3f1944 537{
cf495bcf 538 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 539}
540
cf495bcf 541static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 542{
cf495bcf
FB		 543 if (reg)
544 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 545}
546
cf495bcf 547static inline void gen_movl_T0_reg(int reg)
7a3f1944 548{
cf495bcf 549 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 550}
551
cf495bcf 552static inline void gen_movl_T1_reg(int reg)
7a3f1944 553{
cf495bcf 554 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 555}
556
3475187d
FB		 557static inline void gen_jmp_im(target_ulong pc)
558{
559#ifdef TARGET_SPARC64
560 if (pc == (uint32_t)pc) {
561 gen_op_jmp_im(pc);
562 } else {
563 gen_op_jmp_im64(pc >> 32, pc);
564 }
565#else
566 gen_op_jmp_im(pc);
567#endif
568}
569
570static inline void gen_movl_npc_im(target_ulong npc)
571{
572#ifdef TARGET_SPARC64
573 if (npc == (uint32_t)npc) {
574 gen_op_movl_npc_im(npc);
575 } else {
576 gen_op_movq_npc_im64(npc >> 32, npc);
577 }
578#else
579 gen_op_movl_npc_im(npc);
580#endif
581}
582
5fafdf24 583static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 584 target_ulong pc, target_ulong npc)
585{
586 TranslationBlock *tb;
587
588 tb = s->tb;
589 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
590 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
591 /* jump to same page: we can use a direct jump */
592 if (tb_num == 0)
593 gen_op_goto_tb0(TBPARAM(tb));
594 else
595 gen_op_goto_tb1(TBPARAM(tb));
596 gen_jmp_im(pc);
597 gen_movl_npc_im(npc);
598 gen_op_movl_T0_im((long)tb + tb_num);
599 gen_op_exit_tb();
600 } else {
601 /* jump to another page: currently not optimized */
602 gen_jmp_im(pc);
603 gen_movl_npc_im(npc);
604 gen_op_movl_T0_0();
605 gen_op_exit_tb();
606 }
607}
608
46525e1f
BS		 609static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
610 target_ulong pc2)
83469015
FB		 611{
612 int l1;
613
614 l1 = gen_new_label();
615
616 gen_op_jz_T2_label(l1);
617
6e256c93 618 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 619
620 gen_set_label(l1);
6e256c93 621 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 622}
623
46525e1f
BS		 624static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
625 target_ulong pc2)
83469015
FB		 626{
627 int l1;
628
629 l1 = gen_new_label();
630
631 gen_op_jz_T2_label(l1);
632
6e256c93 633 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 634
635 gen_set_label(l1);
6e256c93 636 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 637}
638
46525e1f
BS		 639static inline void gen_branch(DisasContext *dc, target_ulong pc,
640 target_ulong npc)
83469015 641{
6e256c93 642 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 643}
644
46525e1f 645static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
83469015
FB		 646{
647 int l1, l2;
648
649 l1 = gen_new_label();
650 l2 = gen_new_label();
651 gen_op_jz_T2_label(l1);
652
653 gen_movl_npc_im(npc1);
654 gen_op_jmp_label(l2);
655
656 gen_set_label(l1);
657 gen_movl_npc_im(npc2);
658 gen_set_label(l2);
659}
660
661/* call this function before using T2 as it may have been set for a jump */
662static inline void flush_T2(DisasContext * dc)
663{
664 if (dc->npc == JUMP_PC) {
46525e1f 665 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
83469015
FB		 666 dc->npc = DYNAMIC_PC;
667 }
668}
669
72cbca10
FB		 670static inline void save_npc(DisasContext * dc)
671{
672 if (dc->npc == JUMP_PC) {
46525e1f 673 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 674 dc->npc = DYNAMIC_PC;
675 } else if (dc->npc != DYNAMIC_PC) {
3475187d 676 gen_movl_npc_im(dc->npc);
72cbca10
FB		 677 }
678}
679
680static inline void save_state(DisasContext * dc)
681{
3475187d 682 gen_jmp_im(dc->pc);
72cbca10
FB		 683 save_npc(dc);
684}
685
0bee699e
FB		 686static inline void gen_mov_pc_npc(DisasContext * dc)
687{
688 if (dc->npc == JUMP_PC) {
46525e1f 689 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
0bee699e
FB		 690 gen_op_mov_pc_npc();
691 dc->pc = DYNAMIC_PC;
692 } else if (dc->npc == DYNAMIC_PC) {
693 gen_op_mov_pc_npc();
694 dc->pc = DYNAMIC_PC;
695 } else {
696 dc->pc = dc->npc;
697 }
698}
699
3475187d
FB		 700static GenOpFunc * const gen_cond[2][16] = {
701 {
9bad0425 702 gen_op_eval_bn,
3475187d
FB		 703 gen_op_eval_be,
704 gen_op_eval_ble,
705 gen_op_eval_bl,
706 gen_op_eval_bleu,
707 gen_op_eval_bcs,
708 gen_op_eval_bneg,
709 gen_op_eval_bvs,
9bad0425 710 gen_op_eval_ba,
3475187d
FB		 711 gen_op_eval_bne,
712 gen_op_eval_bg,
713 gen_op_eval_bge,
714 gen_op_eval_bgu,
715 gen_op_eval_bcc,
716 gen_op_eval_bpos,
717 gen_op_eval_bvc,
718 },
719 {
720#ifdef TARGET_SPARC64
9bad0425 721 gen_op_eval_bn,
3475187d
FB		 722 gen_op_eval_xbe,
723 gen_op_eval_xble,
724 gen_op_eval_xbl,
725 gen_op_eval_xbleu,
726 gen_op_eval_xbcs,
727 gen_op_eval_xbneg,
728 gen_op_eval_xbvs,
9bad0425 729 gen_op_eval_ba,
3475187d
FB		 730 gen_op_eval_xbne,
731 gen_op_eval_xbg,
732 gen_op_eval_xbge,
733 gen_op_eval_xbgu,
734 gen_op_eval_xbcc,
735 gen_op_eval_xbpos,
736 gen_op_eval_xbvc,
737#endif
738 },
739};
740
741static GenOpFunc * const gen_fcond[4][16] = {
742 {
9bad0425 743 gen_op_eval_bn,
3475187d
FB		 744 gen_op_eval_fbne,
745 gen_op_eval_fblg,
746 gen_op_eval_fbul,
747 gen_op_eval_fbl,
748 gen_op_eval_fbug,
749 gen_op_eval_fbg,
750 gen_op_eval_fbu,
9bad0425 751 gen_op_eval_ba,
3475187d
FB		 752 gen_op_eval_fbe,
753 gen_op_eval_fbue,
754 gen_op_eval_fbge,
755 gen_op_eval_fbuge,
756 gen_op_eval_fble,
757 gen_op_eval_fbule,
758 gen_op_eval_fbo,
759 },
760#ifdef TARGET_SPARC64
761 {
9bad0425 762 gen_op_eval_bn,
3475187d
FB		 763 gen_op_eval_fbne_fcc1,
764 gen_op_eval_fblg_fcc1,
765 gen_op_eval_fbul_fcc1,
766 gen_op_eval_fbl_fcc1,
767 gen_op_eval_fbug_fcc1,
768 gen_op_eval_fbg_fcc1,
769 gen_op_eval_fbu_fcc1,
9bad0425 770 gen_op_eval_ba,
3475187d
FB		 771 gen_op_eval_fbe_fcc1,
772 gen_op_eval_fbue_fcc1,
773 gen_op_eval_fbge_fcc1,
774 gen_op_eval_fbuge_fcc1,
775 gen_op_eval_fble_fcc1,
776 gen_op_eval_fbule_fcc1,
777 gen_op_eval_fbo_fcc1,
778 },
779 {
9bad0425 780 gen_op_eval_bn,
3475187d
FB		 781 gen_op_eval_fbne_fcc2,
782 gen_op_eval_fblg_fcc2,
783 gen_op_eval_fbul_fcc2,
784 gen_op_eval_fbl_fcc2,
785 gen_op_eval_fbug_fcc2,
786 gen_op_eval_fbg_fcc2,
787 gen_op_eval_fbu_fcc2,
9bad0425 788 gen_op_eval_ba,
3475187d
FB		 789 gen_op_eval_fbe_fcc2,
790 gen_op_eval_fbue_fcc2,
791 gen_op_eval_fbge_fcc2,
792 gen_op_eval_fbuge_fcc2,
793 gen_op_eval_fble_fcc2,
794 gen_op_eval_fbule_fcc2,
795 gen_op_eval_fbo_fcc2,
796 },
797 {
9bad0425 798 gen_op_eval_bn,
3475187d
FB		 799 gen_op_eval_fbne_fcc3,
800 gen_op_eval_fblg_fcc3,
801 gen_op_eval_fbul_fcc3,
802 gen_op_eval_fbl_fcc3,
803 gen_op_eval_fbug_fcc3,
804 gen_op_eval_fbg_fcc3,
805 gen_op_eval_fbu_fcc3,
9bad0425 806 gen_op_eval_ba,
3475187d
FB		 807 gen_op_eval_fbe_fcc3,
808 gen_op_eval_fbue_fcc3,
809 gen_op_eval_fbge_fcc3,
810 gen_op_eval_fbuge_fcc3,
811 gen_op_eval_fble_fcc3,
812 gen_op_eval_fbule_fcc3,
813 gen_op_eval_fbo_fcc3,
814 },
815#else
816 {}, {}, {},
817#endif
818};
7a3f1944 819
3475187d
FB		 820#ifdef TARGET_SPARC64
821static void gen_cond_reg(int cond)
e8af50a3
FB		 822{
823 switch (cond) {
e8af50a3 824 case 0x1:
3475187d 825 gen_op_eval_brz();
e8af50a3
FB		 826 break;
827 case 0x2:
3475187d 828 gen_op_eval_brlez();
e8af50a3
FB		 829 break;
830 case 0x3:
3475187d 831 gen_op_eval_brlz();
e8af50a3
FB		 832 break;
833 case 0x5:
3475187d 834 gen_op_eval_brnz();
e8af50a3
FB		 835 break;
836 case 0x6:
3475187d 837 gen_op_eval_brgz();
e8af50a3
FB		 838 break;
839 default:
3475187d
FB		 840 case 0x7:
841 gen_op_eval_brgez();
e8af50a3
FB		 842 break;
843 }
844}
3475187d 845#endif
cf495bcf 846
0bee699e 847/* XXX: potentially incorrect if dynamic npc */
3475187d 848static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 849{
cf495bcf 850 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 851 target_ulong target = dc->pc + offset;
5fafdf24 852
cf495bcf
FB		 853 if (cond == 0x0) {
854 /* unconditional not taken */
855 if (a) {
5fafdf24 856 dc->pc = dc->npc + 4;
cf495bcf
FB		 857 dc->npc = dc->pc + 4;
858 } else {
859 dc->pc = dc->npc;
860 dc->npc = dc->pc + 4;
861 }
862 } else if (cond == 0x8) {
863 /* unconditional taken */
864 if (a) {
72cbca10 865 dc->pc = target;
cf495bcf
FB		 866 dc->npc = dc->pc + 4;
867 } else {
868 dc->pc = dc->npc;
72cbca10 869 dc->npc = target;
cf495bcf
FB		 870 }
871 } else {
72cbca10 872 flush_T2(dc);
3475187d 873 gen_cond[cc][cond]();
cf495bcf 874 if (a) {
46525e1f 875 gen_branch_a(dc, target, dc->npc);
cf495bcf 876 dc->is_br = 1;
cf495bcf
FB		 877 } else {
878 dc->pc = dc->npc;
72cbca10
FB		 879 dc->jump_pc[0] = target;
880 dc->jump_pc[1] = dc->npc + 4;
881 dc->npc = JUMP_PC;
cf495bcf
FB		 882 }
883 }
7a3f1944
FB		 884}
885
0bee699e 886/* XXX: potentially incorrect if dynamic npc */
3475187d 887static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 888{
889 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 890 target_ulong target = dc->pc + offset;
891
e8af50a3
FB		 892 if (cond == 0x0) {
893 /* unconditional not taken */
894 if (a) {
895 dc->pc = dc->npc + 4;
896 dc->npc = dc->pc + 4;
897 } else {
898 dc->pc = dc->npc;
899 dc->npc = dc->pc + 4;
900 }
901 } else if (cond == 0x8) {
902 /* unconditional taken */
903 if (a) {
904 dc->pc = target;
905 dc->npc = dc->pc + 4;
906 } else {
907 dc->pc = dc->npc;
908 dc->npc = target;
909 }
910 } else {
911 flush_T2(dc);
3475187d 912 gen_fcond[cc][cond]();
e8af50a3 913 if (a) {
46525e1f 914 gen_branch_a(dc, target, dc->npc);
e8af50a3
FB		 915 dc->is_br = 1;
916 } else {
917 dc->pc = dc->npc;
918 dc->jump_pc[0] = target;
919 dc->jump_pc[1] = dc->npc + 4;
920 dc->npc = JUMP_PC;
921 }
922 }
923}
924
3475187d
FB		 925#ifdef TARGET_SPARC64
926/* XXX: potentially incorrect if dynamic npc */
927static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 928{
3475187d
FB		 929 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
930 target_ulong target = dc->pc + offset;
931
932 flush_T2(dc);
933 gen_cond_reg(cond);
934 if (a) {
46525e1f 935 gen_branch_a(dc, target, dc->npc);
3475187d
FB		 936 dc->is_br = 1;
937 } else {
938 dc->pc = dc->npc;
939 dc->jump_pc[0] = target;
940 dc->jump_pc[1] = dc->npc + 4;
941 dc->npc = JUMP_PC;
942 }
7a3f1944
FB		 943}
944
3475187d
FB		 945static GenOpFunc * const gen_fcmps[4] = {
946 gen_op_fcmps,
947 gen_op_fcmps_fcc1,
948 gen_op_fcmps_fcc2,
949 gen_op_fcmps_fcc3,
950};
951
952static GenOpFunc * const gen_fcmpd[4] = {
953 gen_op_fcmpd,
954 gen_op_fcmpd_fcc1,
955 gen_op_fcmpd_fcc2,
956 gen_op_fcmpd_fcc3,
957};
417454b0
BS		 958
959static GenOpFunc * const gen_fcmpes[4] = {
960 gen_op_fcmpes,
961 gen_op_fcmpes_fcc1,
962 gen_op_fcmpes_fcc2,
963 gen_op_fcmpes_fcc3,
964};
965
966static GenOpFunc * const gen_fcmped[4] = {
967 gen_op_fcmped,
968 gen_op_fcmped_fcc1,
969 gen_op_fcmped_fcc2,
970 gen_op_fcmped_fcc3,
971};
972
3475187d
FB		 973#endif
974
a80dde08
FB		 975static int gen_trap_ifnofpu(DisasContext * dc)
976{
977#if !defined(CONFIG_USER_ONLY)
978 if (!dc->fpu_enabled) {
979 save_state(dc);
980 gen_op_exception(TT_NFPU_INSN);
981 dc->is_br = 1;
982 return 1;
983 }
984#endif
985 return 0;
986}
987
0bee699e 988/* before an instruction, dc->pc must be static */
cf495bcf
FB		 989static void disas_sparc_insn(DisasContext * dc)
990{
991 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 992
0fa85d43 993 insn = ldl_code(dc->pc);
cf495bcf 994 opc = GET_FIELD(insn, 0, 1);
7a3f1944 995
cf495bcf
FB		 996 rd = GET_FIELD(insn, 2, 6);
997 switch (opc) {
998 case 0: /* branches/sethi */
999 {
1000 unsigned int xop = GET_FIELD(insn, 7, 9);
af7bf89b 1001 int32_t target;
cf495bcf 1002 switch (xop) {
3475187d 1003#ifdef TARGET_SPARC64
af7bf89b 1004 case 0x1: /* V9 BPcc */
3475187d
FB		 1005 {
1006 int cc;
1007
1008 target = GET_FIELD_SP(insn, 0, 18);
3475187d 1009 target = sign_extend(target, 18);
ee6c0b51 1010 target <<= 2;
3475187d
FB		 1011 cc = GET_FIELD_SP(insn, 20, 21);
1012 if (cc == 0)
1013 do_branch(dc, target, insn, 0);
1014 else if (cc == 2)
1015 do_branch(dc, target, insn, 1);
1016 else
1017 goto illegal_insn;
1018 goto jmp_insn;
1019 }
af7bf89b 1020 case 0x3: /* V9 BPr */
3475187d 1021 {
5fafdf24 1022 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1023 (GET_FIELD_SP(insn, 20, 21) << 14);
3475187d 1024 target = sign_extend(target, 16);
ee6c0b51 1025 target <<= 2;
3475187d 1026 rs1 = GET_FIELD(insn, 13, 17);
83469015 1027 gen_movl_reg_T0(rs1);
3475187d
FB		 1028 do_branch_reg(dc, target, insn);
1029 goto jmp_insn;
1030 }
af7bf89b 1031 case 0x5: /* V9 FBPcc */
3475187d
FB		 1032 {
1033 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1034 if (gen_trap_ifnofpu(dc))
1035 goto jmp_insn;
3475187d 1036 target = GET_FIELD_SP(insn, 0, 18);
3475187d 1037 target = sign_extend(target, 19);
ee6c0b51 1038 target <<= 2;
3475187d
FB		 1039 do_fbranch(dc, target, insn, cc);
1040 goto jmp_insn;
1041 }
a4d17f19
BS		 1042#else
1043 case 0x7: /* CBN+x */
1044 {
1045 goto ncp_insn;
1046 }
3475187d 1047#endif
cf495bcf 1048 case 0x2: /* BN+x */
7a3f1944 1049 {
3475187d 1050 target = GET_FIELD(insn, 10, 31);
cf495bcf 1051 target = sign_extend(target, 22);
ee6c0b51 1052 target <<= 2;
3475187d 1053 do_branch(dc, target, insn, 0);
cf495bcf 1054 goto jmp_insn;
7a3f1944 1055 }
e8af50a3
FB		 1056 case 0x6: /* FBN+x */
1057 {
a80dde08
FB		 1058 if (gen_trap_ifnofpu(dc))
1059 goto jmp_insn;
3475187d 1060 target = GET_FIELD(insn, 10, 31);
e8af50a3 1061 target = sign_extend(target, 22);
ee6c0b51 1062 target <<= 2;
3475187d 1063 do_fbranch(dc, target, insn, 0);
e8af50a3
FB		 1064 goto jmp_insn;
1065 }
cf495bcf 1066 case 0x4: /* SETHI */
e80cfcfc
FB		 1067#define OPTIM
1068#if defined(OPTIM)
1069 if (rd) { // nop
1070#endif
3475187d
FB		 1071 uint32_t value = GET_FIELD(insn, 10, 31);
1072 gen_movl_imm_T0(value << 10);
e80cfcfc
FB		 1073 gen_movl_T0_reg(rd);
1074#if defined(OPTIM)
1075 }
1076#endif
cf495bcf 1077 break;
3475187d
FB		 1078 case 0x0: /* UNIMPL */
1079 default:
1080 goto illegal_insn;
cf495bcf
FB		 1081 }
1082 break;
1083 }
af7bf89b 1084 break;
cf495bcf
FB		 1085 case 1:
1086 /*CALL*/ {
af7bf89b 1087 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1088
83469015
FB		 1089#ifdef TARGET_SPARC64
1090 if (dc->pc == (uint32_t)dc->pc) {
1091 gen_op_movl_T0_im(dc->pc);
1092 } else {
1093 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1094 }
1095#else
af7bf89b 1096 gen_op_movl_T0_im(dc->pc);
83469015 1097#endif
cf495bcf 1098 gen_movl_T0_reg(15);
af7bf89b 1099 target += dc->pc;
0bee699e 1100 gen_mov_pc_npc(dc);
72cbca10 1101 dc->npc = target;
cf495bcf
FB		 1102 }
1103 goto jmp_insn;
1104 case 2: /* FPU & Logical Operations */
1105 {
1106 unsigned int xop = GET_FIELD(insn, 7, 12);
1107 if (xop == 0x3a) { /* generate trap */
1108 int cond;
3475187d 1109
cf495bcf
FB		 1110 rs1 = GET_FIELD(insn, 13, 17);
1111 gen_movl_reg_T0(rs1);
1112 if (IS_IMM) {
e8af50a3 1113 rs2 = GET_FIELD(insn, 25, 31);
e80cfcfc 1114#if defined(OPTIM)
e8af50a3 1115 if (rs2 != 0) {
e80cfcfc 1116#endif
3475187d 1117 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1118 gen_op_add_T1_T0();
1119#if defined(OPTIM)
e8af50a3 1120 }
e80cfcfc 1121#endif
cf495bcf
FB		 1122 } else {
1123 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 1124#if defined(OPTIM)
1125 if (rs2 != 0) {
1126#endif
1127 gen_movl_reg_T1(rs2);
1128 gen_op_add_T1_T0();
1129#if defined(OPTIM)
1130 }
1131#endif
cf495bcf 1132 }
cf495bcf
FB		 1133 cond = GET_FIELD(insn, 3, 6);
1134 if (cond == 0x8) {
a80dde08 1135 save_state(dc);
cf495bcf 1136 gen_op_trap_T0();
af7bf89b 1137 } else if (cond != 0) {
3475187d
FB		 1138#ifdef TARGET_SPARC64
1139 /* V9 icc/xcc */
1140 int cc = GET_FIELD_SP(insn, 11, 12);
a80dde08
FB		 1141 flush_T2(dc);
1142 save_state(dc);
3475187d
FB		 1143 if (cc == 0)
1144 gen_cond[0][cond]();
1145 else if (cc == 2)
1146 gen_cond[1][cond]();
1147 else
1148 goto illegal_insn;
1149#else
a80dde08
FB		 1150 flush_T2(dc);
1151 save_state(dc);
3475187d
FB		 1152 gen_cond[0][cond]();
1153#endif
cf495bcf
FB		 1154 gen_op_trapcc_T0();
1155 }
a80dde08
FB		 1156 gen_op_next_insn();
1157 gen_op_movl_T0_0();
1158 gen_op_exit_tb();
1159 dc->is_br = 1;
1160 goto jmp_insn;
cf495bcf
FB		 1161 } else if (xop == 0x28) {
1162 rs1 = GET_FIELD(insn, 13, 17);
1163 switch(rs1) {
1164 case 0: /* rdy */
65fe7b09
BS		 1165#ifndef TARGET_SPARC64
1166 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1167 manual, rdy on the microSPARC
1168 II */
1169 case 0x0f: /* stbar in the SPARCv8 manual,
1170 rdy on the microSPARC II */
1171 case 0x10 ... 0x1f: /* implementation-dependent in the
1172 SPARCv8 manual, rdy on the
1173 microSPARC II */
1174#endif
1175 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1176 gen_movl_T0_reg(rd);
1177 break;
3475187d 1178#ifdef TARGET_SPARC64
af7bf89b 1179 case 0x2: /* V9 rdccr */
3475187d
FB		 1180 gen_op_rdccr();
1181 gen_movl_T0_reg(rd);
1182 break;
af7bf89b 1183 case 0x3: /* V9 rdasi */
3475187d
FB		 1184 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1185 gen_movl_T0_reg(rd);
1186 break;
af7bf89b 1187 case 0x4: /* V9 rdtick */
3475187d
FB		 1188 gen_op_rdtick();
1189 gen_movl_T0_reg(rd);
1190 break;
af7bf89b 1191 case 0x5: /* V9 rdpc */
ded3ab80
PB		 1192 if (dc->pc == (uint32_t)dc->pc) {
1193 gen_op_movl_T0_im(dc->pc);
1194 } else {
1195 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1196 }
3475187d
FB		 1197 gen_movl_T0_reg(rd);
1198 break;
af7bf89b 1199 case 0x6: /* V9 rdfprs */
3475187d
FB		 1200 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1201 gen_movl_T0_reg(rd);
1202 break;
65fe7b09
BS		 1203 case 0xf: /* V9 membar */
1204 break; /* no effect */
725cb90b
FB		 1205 case 0x13: /* Graphics Status */
1206 if (gen_trap_ifnofpu(dc))
1207 goto jmp_insn;
1208 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1209 gen_movl_T0_reg(rd);
1210 break;
83469015
FB		 1211 case 0x17: /* Tick compare */
1212 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1213 gen_movl_T0_reg(rd);
1214 break;
1215 case 0x18: /* System tick */
20c9f095 1216 gen_op_rdstick();
83469015
FB		 1217 gen_movl_T0_reg(rd);
1218 break;
1219 case 0x19: /* System tick compare */
1220 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1221 gen_movl_T0_reg(rd);
1222 break;
1223 case 0x10: /* Performance Control */
1224 case 0x11: /* Performance Instrumentation Counter */
1225 case 0x12: /* Dispatch Control */
83469015
FB		 1226 case 0x14: /* Softint set, WO */
1227 case 0x15: /* Softint clear, WO */
1228 case 0x16: /* Softint write */
3475187d
FB		 1229#endif
1230 default:
cf495bcf
FB		 1231 goto illegal_insn;
1232 }
e8af50a3 1233#if !defined(CONFIG_USER_ONLY)
e9ebed4d 1234 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 1235#ifndef TARGET_SPARC64
e8af50a3
FB		 1236 if (!supervisor(dc))
1237 goto priv_insn;
1238 gen_op_rdpsr();
e9ebed4d
BS		 1239#else
1240 if (!hypervisor(dc))
1241 goto priv_insn;
1242 rs1 = GET_FIELD(insn, 13, 17);
1243 switch (rs1) {
1244 case 0: // hpstate
1245 // gen_op_rdhpstate();
1246 break;
1247 case 1: // htstate
1248 // gen_op_rdhtstate();
1249 break;
1250 case 3: // hintp
1251 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1252 break;
1253 case 5: // htba
1254 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1255 break;
1256 case 6: // hver
1257 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1258 break;
1259 case 31: // hstick_cmpr
1260 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1261 break;
1262 default:
1263 goto illegal_insn;
1264 }
1265#endif
e8af50a3
FB		 1266 gen_movl_T0_reg(rd);
1267 break;
3475187d 1268 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
e8af50a3
FB		 1269 if (!supervisor(dc))
1270 goto priv_insn;
3475187d
FB		 1271#ifdef TARGET_SPARC64
1272 rs1 = GET_FIELD(insn, 13, 17);
1273 switch (rs1) {
1274 case 0: // tpc
1275 gen_op_rdtpc();
1276 break;
1277 case 1: // tnpc
1278 gen_op_rdtnpc();
1279 break;
1280 case 2: // tstate
1281 gen_op_rdtstate();
1282 break;
1283 case 3: // tt
1284 gen_op_rdtt();
1285 break;
1286 case 4: // tick
1287 gen_op_rdtick();
1288 break;
1289 case 5: // tba
1290 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1291 break;
1292 case 6: // pstate
1293 gen_op_rdpstate();
1294 break;
1295 case 7: // tl
1296 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1297 break;
1298 case 8: // pil
1299 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1300 break;
1301 case 9: // cwp
1302 gen_op_rdcwp();
1303 break;
1304 case 10: // cansave
1305 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1306 break;
1307 case 11: // canrestore
1308 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1309 break;
1310 case 12: // cleanwin
1311 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1312 break;
1313 case 13: // otherwin
1314 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1315 break;
1316 case 14: // wstate
1317 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1318 break;
e9ebed4d
BS		 1319 case 16: // UA2005 gl
1320 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1321 break;
1322 case 26: // UA2005 strand status
1323 if (!hypervisor(dc))
1324 goto priv_insn;
1325 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1326 break;
3475187d
FB		 1327 case 31: // ver
1328 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1329 break;
1330 case 15: // fq
1331 default:
1332 goto illegal_insn;
1333 }
1334#else
1335 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1336#endif
e8af50a3
FB		 1337 gen_movl_T0_reg(rd);
1338 break;
3475187d
FB		 1339 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1340#ifdef TARGET_SPARC64
1341 gen_op_flushw();
1342#else
e8af50a3
FB		 1343 if (!supervisor(dc))
1344 goto priv_insn;
3475187d 1345 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1346 gen_movl_T0_reg(rd);
3475187d 1347#endif
e8af50a3
FB		 1348 break;
1349#endif
e80cfcfc 1350 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 1351 if (gen_trap_ifnofpu(dc))
1352 goto jmp_insn;
417454b0 1353 gen_op_clear_ieee_excp_and_FTT();
e8af50a3
FB		 1354 rs1 = GET_FIELD(insn, 13, 17);
1355 rs2 = GET_FIELD(insn, 27, 31);
1356 xop = GET_FIELD(insn, 18, 26);
1357 switch (xop) {
1358 case 0x1: /* fmovs */
1359 gen_op_load_fpr_FT0(rs2);
1360 gen_op_store_FT0_fpr(rd);
1361 break;
1362 case 0x5: /* fnegs */
1363 gen_op_load_fpr_FT1(rs2);
1364 gen_op_fnegs();
1365 gen_op_store_FT0_fpr(rd);
1366 break;
1367 case 0x9: /* fabss */
1368 gen_op_load_fpr_FT1(rs2);
1369 gen_op_fabss();
1370 gen_op_store_FT0_fpr(rd);
1371 break;
1372 case 0x29: /* fsqrts */
1373 gen_op_load_fpr_FT1(rs2);
1374 gen_op_fsqrts();
1375 gen_op_store_FT0_fpr(rd);
1376 break;
1377 case 0x2a: /* fsqrtd */
3475187d 1378 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1379 gen_op_fsqrtd();
3475187d 1380 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1381 break;
e80cfcfc
FB		 1382 case 0x2b: /* fsqrtq */
1383 goto nfpu_insn;
e8af50a3
FB		 1384 case 0x41:
1385 gen_op_load_fpr_FT0(rs1);
1386 gen_op_load_fpr_FT1(rs2);
1387 gen_op_fadds();
1388 gen_op_store_FT0_fpr(rd);
1389 break;
1390 case 0x42:
3475187d
FB		 1391 gen_op_load_fpr_DT0(DFPREG(rs1));
1392 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1393 gen_op_faddd();
3475187d 1394 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1395 break;
e80cfcfc
FB		 1396 case 0x43: /* faddq */
1397 goto nfpu_insn;
e8af50a3
FB		 1398 case 0x45:
1399 gen_op_load_fpr_FT0(rs1);
1400 gen_op_load_fpr_FT1(rs2);
1401 gen_op_fsubs();
1402 gen_op_store_FT0_fpr(rd);
1403 break;
1404 case 0x46:
3475187d
FB		 1405 gen_op_load_fpr_DT0(DFPREG(rs1));
1406 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1407 gen_op_fsubd();
3475187d 1408 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1409 break;
e80cfcfc
FB		 1410 case 0x47: /* fsubq */
1411 goto nfpu_insn;
e8af50a3
FB		 1412 case 0x49:
1413 gen_op_load_fpr_FT0(rs1);
1414 gen_op_load_fpr_FT1(rs2);
1415 gen_op_fmuls();
1416 gen_op_store_FT0_fpr(rd);
1417 break;
1418 case 0x4a:
3475187d
FB		 1419 gen_op_load_fpr_DT0(DFPREG(rs1));
1420 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1421 gen_op_fmuld();
1422 gen_op_store_DT0_fpr(rd);
1423 break;
e80cfcfc
FB		 1424 case 0x4b: /* fmulq */
1425 goto nfpu_insn;
e8af50a3
FB		 1426 case 0x4d:
1427 gen_op_load_fpr_FT0(rs1);
1428 gen_op_load_fpr_FT1(rs2);
1429 gen_op_fdivs();
1430 gen_op_store_FT0_fpr(rd);
1431 break;
1432 case 0x4e:
3475187d
FB		 1433 gen_op_load_fpr_DT0(DFPREG(rs1));
1434 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3 1435 gen_op_fdivd();
3475187d 1436 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1437 break;
e80cfcfc
FB		 1438 case 0x4f: /* fdivq */
1439 goto nfpu_insn;
e8af50a3
FB		 1440 case 0x69:
1441 gen_op_load_fpr_FT0(rs1);
1442 gen_op_load_fpr_FT1(rs2);
1443 gen_op_fsmuld();
3475187d 1444 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1445 break;
e80cfcfc
FB		 1446 case 0x6e: /* fdmulq */
1447 goto nfpu_insn;
e8af50a3
FB		 1448 case 0xc4:
1449 gen_op_load_fpr_FT1(rs2);
1450 gen_op_fitos();
1451 gen_op_store_FT0_fpr(rd);
1452 break;
1453 case 0xc6:
3475187d 1454 gen_op_load_fpr_DT1(DFPREG(rs2));
e8af50a3
FB		 1455 gen_op_fdtos();
1456 gen_op_store_FT0_fpr(rd);
1457 break;
e80cfcfc
FB		 1458 case 0xc7: /* fqtos */
1459 goto nfpu_insn;
e8af50a3
FB		 1460 case 0xc8:
1461 gen_op_load_fpr_FT1(rs2);
1462 gen_op_fitod();
3475187d 1463 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3
FB		 1464 break;
1465 case 0xc9:
1466 gen_op_load_fpr_FT1(rs2);
1467 gen_op_fstod();
3475187d 1468 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 1469 break;
e80cfcfc
FB		 1470 case 0xcb: /* fqtod */
1471 goto nfpu_insn;
1472 case 0xcc: /* fitoq */
1473 goto nfpu_insn;
1474 case 0xcd: /* fstoq */
1475 goto nfpu_insn;
1476 case 0xce: /* fdtoq */
1477 goto nfpu_insn;
e8af50a3
FB		 1478 case 0xd1:
1479 gen_op_load_fpr_FT1(rs2);
1480 gen_op_fstoi();
1481 gen_op_store_FT0_fpr(rd);
1482 break;
1483 case 0xd2:
1484 gen_op_load_fpr_DT1(rs2);
1485 gen_op_fdtoi();
1486 gen_op_store_FT0_fpr(rd);
1487 break;
e80cfcfc
FB		 1488 case 0xd3: /* fqtoi */
1489 goto nfpu_insn;
3475187d 1490#ifdef TARGET_SPARC64
af7bf89b 1491 case 0x2: /* V9 fmovd */
3475187d
FB		 1492 gen_op_load_fpr_DT0(DFPREG(rs2));
1493 gen_op_store_DT0_fpr(DFPREG(rd));
1494 break;
af7bf89b 1495 case 0x6: /* V9 fnegd */
3475187d
FB		 1496 gen_op_load_fpr_DT1(DFPREG(rs2));
1497 gen_op_fnegd();
1498 gen_op_store_DT0_fpr(DFPREG(rd));
1499 break;
af7bf89b 1500 case 0xa: /* V9 fabsd */
3475187d
FB		 1501 gen_op_load_fpr_DT1(DFPREG(rs2));
1502 gen_op_fabsd();
1503 gen_op_store_DT0_fpr(DFPREG(rd));
1504 break;
af7bf89b 1505 case 0x81: /* V9 fstox */
3475187d
FB		 1506 gen_op_load_fpr_FT1(rs2);
1507 gen_op_fstox();
1508 gen_op_store_DT0_fpr(DFPREG(rd));
1509 break;
af7bf89b 1510 case 0x82: /* V9 fdtox */
3475187d
FB		 1511 gen_op_load_fpr_DT1(DFPREG(rs2));
1512 gen_op_fdtox();
1513 gen_op_store_DT0_fpr(DFPREG(rd));
1514 break;
af7bf89b 1515 case 0x84: /* V9 fxtos */
3475187d
FB		 1516 gen_op_load_fpr_DT1(DFPREG(rs2));
1517 gen_op_fxtos();
1518 gen_op_store_FT0_fpr(rd);
1519 break;
af7bf89b 1520 case 0x88: /* V9 fxtod */
3475187d
FB		 1521 gen_op_load_fpr_DT1(DFPREG(rs2));
1522 gen_op_fxtod();
1523 gen_op_store_DT0_fpr(DFPREG(rd));
1524 break;
af7bf89b
FB		 1525 case 0x3: /* V9 fmovq */
1526 case 0x7: /* V9 fnegq */
1527 case 0xb: /* V9 fabsq */
1528 case 0x83: /* V9 fqtox */
1529 case 0x8c: /* V9 fxtoq */
3475187d
FB		 1530 goto nfpu_insn;
1531#endif
1532 default:
e8af50a3
FB		 1533 goto illegal_insn;
1534 }
e80cfcfc 1535 } else if (xop == 0x35) { /* FPU Operations */
3475187d
FB		 1536#ifdef TARGET_SPARC64
1537 int cond;
1538#endif
a80dde08
FB		 1539 if (gen_trap_ifnofpu(dc))
1540 goto jmp_insn;
417454b0 1541 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 1542 rs1 = GET_FIELD(insn, 13, 17);
e80cfcfc
FB		 1543 rs2 = GET_FIELD(insn, 27, 31);
1544 xop = GET_FIELD(insn, 18, 26);
3475187d
FB		 1545#ifdef TARGET_SPARC64
1546 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1547 cond = GET_FIELD_SP(insn, 14, 17);
1548 gen_op_load_fpr_FT0(rd);
1549 gen_op_load_fpr_FT1(rs2);
1550 rs1 = GET_FIELD(insn, 13, 17);
1551 gen_movl_reg_T0(rs1);
1552 flush_T2(dc);
1553 gen_cond_reg(cond);
1554 gen_op_fmovs_cc();
1555 gen_op_store_FT0_fpr(rd);
1556 break;
1557 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1558 cond = GET_FIELD_SP(insn, 14, 17);
1559 gen_op_load_fpr_DT0(rd);
1560 gen_op_load_fpr_DT1(rs2);
1561 flush_T2(dc);
1562 rs1 = GET_FIELD(insn, 13, 17);
1563 gen_movl_reg_T0(rs1);
1564 gen_cond_reg(cond);
1565 gen_op_fmovs_cc();
1566 gen_op_store_DT0_fpr(rd);
1567 break;
1568 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1569 goto nfpu_insn;
1570 }
1571#endif
e80cfcfc 1572 switch (xop) {
3475187d
FB		 1573#ifdef TARGET_SPARC64
1574 case 0x001: /* V9 fmovscc %fcc0 */
1575 cond = GET_FIELD_SP(insn, 14, 17);
1576 gen_op_load_fpr_FT0(rd);
1577 gen_op_load_fpr_FT1(rs2);
1578 flush_T2(dc);
1579 gen_fcond[0][cond]();
1580 gen_op_fmovs_cc();
1581 gen_op_store_FT0_fpr(rd);
1582 break;
1583 case 0x002: /* V9 fmovdcc %fcc0 */
1584 cond = GET_FIELD_SP(insn, 14, 17);
1585 gen_op_load_fpr_DT0(rd);
1586 gen_op_load_fpr_DT1(rs2);
1587 flush_T2(dc);
1588 gen_fcond[0][cond]();
1589 gen_op_fmovd_cc();
1590 gen_op_store_DT0_fpr(rd);
1591 break;
1592 case 0x003: /* V9 fmovqcc %fcc0 */
1593 goto nfpu_insn;
1594 case 0x041: /* V9 fmovscc %fcc1 */
1595 cond = GET_FIELD_SP(insn, 14, 17);
1596 gen_op_load_fpr_FT0(rd);
1597 gen_op_load_fpr_FT1(rs2);
1598 flush_T2(dc);
1599 gen_fcond[1][cond]();
1600 gen_op_fmovs_cc();
1601 gen_op_store_FT0_fpr(rd);
1602 break;
1603 case 0x042: /* V9 fmovdcc %fcc1 */
1604 cond = GET_FIELD_SP(insn, 14, 17);
1605 gen_op_load_fpr_DT0(rd);
1606 gen_op_load_fpr_DT1(rs2);
1607 flush_T2(dc);
1608 gen_fcond[1][cond]();
1609 gen_op_fmovd_cc();
1610 gen_op_store_DT0_fpr(rd);
1611 break;
1612 case 0x043: /* V9 fmovqcc %fcc1 */
1613 goto nfpu_insn;
1614 case 0x081: /* V9 fmovscc %fcc2 */
1615 cond = GET_FIELD_SP(insn, 14, 17);
1616 gen_op_load_fpr_FT0(rd);
1617 gen_op_load_fpr_FT1(rs2);
1618 flush_T2(dc);
1619 gen_fcond[2][cond]();
1620 gen_op_fmovs_cc();
1621 gen_op_store_FT0_fpr(rd);
1622 break;
1623 case 0x082: /* V9 fmovdcc %fcc2 */
1624 cond = GET_FIELD_SP(insn, 14, 17);
1625 gen_op_load_fpr_DT0(rd);
1626 gen_op_load_fpr_DT1(rs2);
1627 flush_T2(dc);
1628 gen_fcond[2][cond]();
1629 gen_op_fmovd_cc();
1630 gen_op_store_DT0_fpr(rd);
1631 break;
1632 case 0x083: /* V9 fmovqcc %fcc2 */
1633 goto nfpu_insn;
1634 case 0x0c1: /* V9 fmovscc %fcc3 */
1635 cond = GET_FIELD_SP(insn, 14, 17);
1636 gen_op_load_fpr_FT0(rd);
1637 gen_op_load_fpr_FT1(rs2);
1638 flush_T2(dc);
1639 gen_fcond[3][cond]();
1640 gen_op_fmovs_cc();
1641 gen_op_store_FT0_fpr(rd);
1642 break;
1643 case 0x0c2: /* V9 fmovdcc %fcc3 */
1644 cond = GET_FIELD_SP(insn, 14, 17);
1645 gen_op_load_fpr_DT0(rd);
1646 gen_op_load_fpr_DT1(rs2);
1647 flush_T2(dc);
1648 gen_fcond[3][cond]();
1649 gen_op_fmovd_cc();
1650 gen_op_store_DT0_fpr(rd);
1651 break;
1652 case 0x0c3: /* V9 fmovqcc %fcc3 */
1653 goto nfpu_insn;
1654 case 0x101: /* V9 fmovscc %icc */
1655 cond = GET_FIELD_SP(insn, 14, 17);
1656 gen_op_load_fpr_FT0(rd);
1657 gen_op_load_fpr_FT1(rs2);
1658 flush_T2(dc);
1659 gen_cond[0][cond]();
1660 gen_op_fmovs_cc();
1661 gen_op_store_FT0_fpr(rd);
1662 break;
1663 case 0x102: /* V9 fmovdcc %icc */
1664 cond = GET_FIELD_SP(insn, 14, 17);
1665 gen_op_load_fpr_DT0(rd);
1666 gen_op_load_fpr_DT1(rs2);
1667 flush_T2(dc);
1668 gen_cond[0][cond]();
1669 gen_op_fmovd_cc();
1670 gen_op_store_DT0_fpr(rd);
1671 break;
1672 case 0x103: /* V9 fmovqcc %icc */
1673 goto nfpu_insn;
1674 case 0x181: /* V9 fmovscc %xcc */
1675 cond = GET_FIELD_SP(insn, 14, 17);
1676 gen_op_load_fpr_FT0(rd);
1677 gen_op_load_fpr_FT1(rs2);
1678 flush_T2(dc);
1679 gen_cond[1][cond]();
1680 gen_op_fmovs_cc();
1681 gen_op_store_FT0_fpr(rd);
1682 break;
1683 case 0x182: /* V9 fmovdcc %xcc */
1684 cond = GET_FIELD_SP(insn, 14, 17);
1685 gen_op_load_fpr_DT0(rd);
1686 gen_op_load_fpr_DT1(rs2);
1687 flush_T2(dc);
1688 gen_cond[1][cond]();
1689 gen_op_fmovd_cc();
1690 gen_op_store_DT0_fpr(rd);
1691 break;
1692 case 0x183: /* V9 fmovqcc %xcc */
1693 goto nfpu_insn;
1694#endif
1695 case 0x51: /* V9 %fcc */
e80cfcfc
FB		 1696 gen_op_load_fpr_FT0(rs1);
1697 gen_op_load_fpr_FT1(rs2);
3475187d
FB		 1698#ifdef TARGET_SPARC64
1699 gen_fcmps[rd & 3]();
1700#else
e80cfcfc 1701 gen_op_fcmps();
3475187d 1702#endif
e80cfcfc 1703 break;
3475187d
FB		 1704 case 0x52: /* V9 %fcc */
1705 gen_op_load_fpr_DT0(DFPREG(rs1));
1706 gen_op_load_fpr_DT1(DFPREG(rs2));
1707#ifdef TARGET_SPARC64
1708 gen_fcmpd[rd & 3]();
1709#else
e80cfcfc 1710 gen_op_fcmpd();
3475187d 1711#endif
e80cfcfc
FB		 1712 break;
1713 case 0x53: /* fcmpq */
1714 goto nfpu_insn;
3475187d 1715 case 0x55: /* fcmpes, V9 %fcc */
e80cfcfc
FB		 1716 gen_op_load_fpr_FT0(rs1);
1717 gen_op_load_fpr_FT1(rs2);
3475187d 1718#ifdef TARGET_SPARC64
417454b0 1719 gen_fcmpes[rd & 3]();
3475187d 1720#else
417454b0 1721 gen_op_fcmpes();
3475187d 1722#endif
e80cfcfc 1723 break;
3475187d
FB		 1724 case 0x56: /* fcmped, V9 %fcc */
1725 gen_op_load_fpr_DT0(DFPREG(rs1));
1726 gen_op_load_fpr_DT1(DFPREG(rs2));
1727#ifdef TARGET_SPARC64
417454b0 1728 gen_fcmped[rd & 3]();
3475187d 1729#else
417454b0 1730 gen_op_fcmped();
3475187d 1731#endif
e80cfcfc
FB		 1732 break;
1733 case 0x57: /* fcmpeq */
1734 goto nfpu_insn;
1735 default:
1736 goto illegal_insn;
1737 }
1738#if defined(OPTIM)
1739 } else if (xop == 0x2) {
1740 // clr/mov shortcut
1741
1742 rs1 = GET_FIELD(insn, 13, 17);
1743 if (rs1 == 0) {
1744 // or %g0, x, y -> mov T1, x; mov y, T1
1745 if (IS_IMM) { /* immediate */
1746 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1747 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1748 } else { /* register */
1749 rs2 = GET_FIELD(insn, 27, 31);
1750 gen_movl_reg_T1(rs2);
1751 }
1752 gen_movl_T1_reg(rd);
1753 } else {
1754 gen_movl_reg_T0(rs1);
1755 if (IS_IMM) { /* immediate */
1756 // or x, #0, y -> mov T1, x; mov y, T1
1757 rs2 = GET_FIELDs(insn, 19, 31);
1758 if (rs2 != 0) {
3475187d 1759 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 1760 gen_op_or_T1_T0();
1761 }
1762 } else { /* register */
1763 // or x, %g0, y -> mov T1, x; mov y, T1
1764 rs2 = GET_FIELD(insn, 27, 31);
1765 if (rs2 != 0) {
1766 gen_movl_reg_T1(rs2);
1767 gen_op_or_T1_T0();
1768 }
1769 }
1770 gen_movl_T0_reg(rd);
1771 }
83469015
FB		 1772#endif
1773#ifdef TARGET_SPARC64
8a08f9a8 1774 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015
FB		 1775 rs1 = GET_FIELD(insn, 13, 17);
1776 gen_movl_reg_T0(rs1);
1777 if (IS_IMM) { /* immediate */
1778 rs2 = GET_FIELDs(insn, 20, 31);
1779 gen_movl_simm_T1(rs2);
1780 } else { /* register */
1781 rs2 = GET_FIELD(insn, 27, 31);
1782 gen_movl_reg_T1(rs2);
1783 }
8a08f9a8
BS		 1784 if (insn & (1 << 12))
1785 gen_op_sllx();
1786 else
1787 gen_op_sll();
83469015
FB		 1788 gen_movl_T0_reg(rd);
1789 } else if (xop == 0x26) { /* srl, V9 srlx */
1790 rs1 = GET_FIELD(insn, 13, 17);
1791 gen_movl_reg_T0(rs1);
1792 if (IS_IMM) { /* immediate */
1793 rs2 = GET_FIELDs(insn, 20, 31);
1794 gen_movl_simm_T1(rs2);
1795 } else { /* register */
1796 rs2 = GET_FIELD(insn, 27, 31);
1797 gen_movl_reg_T1(rs2);
1798 }
1799 if (insn & (1 << 12))
1800 gen_op_srlx();
1801 else
1802 gen_op_srl();
1803 gen_movl_T0_reg(rd);
1804 } else if (xop == 0x27) { /* sra, V9 srax */
1805 rs1 = GET_FIELD(insn, 13, 17);
1806 gen_movl_reg_T0(rs1);
1807 if (IS_IMM) { /* immediate */
1808 rs2 = GET_FIELDs(insn, 20, 31);
1809 gen_movl_simm_T1(rs2);
1810 } else { /* register */
1811 rs2 = GET_FIELD(insn, 27, 31);
1812 gen_movl_reg_T1(rs2);
1813 }
1814 if (insn & (1 << 12))
1815 gen_op_srax();
1816 else
1817 gen_op_sra();
1818 gen_movl_T0_reg(rd);
e80cfcfc 1819#endif
fcc72045 1820 } else if (xop < 0x36) {
e80cfcfc
FB		 1821 rs1 = GET_FIELD(insn, 13, 17);
1822 gen_movl_reg_T0(rs1);
1823 if (IS_IMM) { /* immediate */
cf495bcf 1824 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 1825 gen_movl_simm_T1(rs2);
cf495bcf
FB		 1826 } else { /* register */
1827 rs2 = GET_FIELD(insn, 27, 31);
1828 gen_movl_reg_T1(rs2);
1829 }
1830 if (xop < 0x20) {
1831 switch (xop & ~0x10) {
1832 case 0x0:
1833 if (xop & 0x10)
1834 gen_op_add_T1_T0_cc();
1835 else
1836 gen_op_add_T1_T0();
1837 break;
1838 case 0x1:
1839 gen_op_and_T1_T0();
1840 if (xop & 0x10)
1841 gen_op_logic_T0_cc();
1842 break;
1843 case 0x2:
e80cfcfc
FB		 1844 gen_op_or_T1_T0();
1845 if (xop & 0x10)
1846 gen_op_logic_T0_cc();
1847 break;
cf495bcf
FB		 1848 case 0x3:
1849 gen_op_xor_T1_T0();
1850 if (xop & 0x10)
1851 gen_op_logic_T0_cc();
1852 break;
1853 case 0x4:
1854 if (xop & 0x10)
1855 gen_op_sub_T1_T0_cc();
1856 else
1857 gen_op_sub_T1_T0();
1858 break;
1859 case 0x5:
1860 gen_op_andn_T1_T0();
1861 if (xop & 0x10)
1862 gen_op_logic_T0_cc();
1863 break;
1864 case 0x6:
1865 gen_op_orn_T1_T0();
1866 if (xop & 0x10)
1867 gen_op_logic_T0_cc();
1868 break;
1869 case 0x7:
1870 gen_op_xnor_T1_T0();
1871 if (xop & 0x10)
1872 gen_op_logic_T0_cc();
1873 break;
1874 case 0x8:
cf495bcf 1875 if (xop & 0x10)
af7bf89b
FB		 1876 gen_op_addx_T1_T0_cc();
1877 else
1878 gen_op_addx_T1_T0();
cf495bcf 1879 break;
ded3ab80
PB		 1880#ifdef TARGET_SPARC64
1881 case 0x9: /* V9 mulx */
1882 gen_op_mulx_T1_T0();
1883 break;
1884#endif
cf495bcf
FB		 1885 case 0xa:
1886 gen_op_umul_T1_T0();
1887 if (xop & 0x10)
1888 gen_op_logic_T0_cc();
1889 break;
1890 case 0xb:
1891 gen_op_smul_T1_T0();
1892 if (xop & 0x10)
1893 gen_op_logic_T0_cc();
1894 break;
1895 case 0xc:
cf495bcf 1896 if (xop & 0x10)
af7bf89b
FB		 1897 gen_op_subx_T1_T0_cc();
1898 else
1899 gen_op_subx_T1_T0();
cf495bcf 1900 break;
ded3ab80
PB		 1901#ifdef TARGET_SPARC64
1902 case 0xd: /* V9 udivx */
1903 gen_op_udivx_T1_T0();
1904 break;
1905#endif
cf495bcf
FB		 1906 case 0xe:
1907 gen_op_udiv_T1_T0();
1908 if (xop & 0x10)
1909 gen_op_div_cc();
1910 break;
1911 case 0xf:
1912 gen_op_sdiv_T1_T0();
1913 if (xop & 0x10)
1914 gen_op_div_cc();
1915 break;
1916 default:
1917 goto illegal_insn;
1918 }
e80cfcfc 1919 gen_movl_T0_reg(rd);
cf495bcf
FB		 1920 } else {
1921 switch (xop) {
e80cfcfc 1922 case 0x20: /* taddcc */
e32f879d
BS		 1923 gen_op_tadd_T1_T0_cc();
1924 gen_movl_T0_reg(rd);
1925 break;
e80cfcfc 1926 case 0x21: /* tsubcc */
e32f879d
BS		 1927 gen_op_tsub_T1_T0_cc();
1928 gen_movl_T0_reg(rd);
1929 break;
e80cfcfc 1930 case 0x22: /* taddcctv */
e32f879d
BS		 1931 gen_op_tadd_T1_T0_ccTV();
1932 gen_movl_T0_reg(rd);
1933 break;
e80cfcfc 1934 case 0x23: /* tsubcctv */
e32f879d
BS		 1935 gen_op_tsub_T1_T0_ccTV();
1936 gen_movl_T0_reg(rd);
1937 break;
cf495bcf
FB		 1938 case 0x24: /* mulscc */
1939 gen_op_mulscc_T1_T0();
1940 gen_movl_T0_reg(rd);
1941 break;
83469015
FB		 1942#ifndef TARGET_SPARC64
1943 case 0x25: /* sll */
3475187d 1944 gen_op_sll();
cf495bcf
FB		 1945 gen_movl_T0_reg(rd);
1946 break;
83469015 1947 case 0x26: /* srl */
3475187d 1948 gen_op_srl();
cf495bcf
FB		 1949 gen_movl_T0_reg(rd);
1950 break;
83469015 1951 case 0x27: /* sra */
3475187d 1952 gen_op_sra();
cf495bcf
FB		 1953 gen_movl_T0_reg(rd);
1954 break;
83469015 1955#endif
cf495bcf
FB		 1956 case 0x30:
1957 {
cf495bcf 1958 switch(rd) {
3475187d
FB		 1959 case 0: /* wry */
1960 gen_op_xor_T1_T0();
1961 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 1962 break;
65fe7b09
BS		 1963#ifndef TARGET_SPARC64
1964 case 0x01 ... 0x0f: /* undefined in the
1965 SPARCv8 manual, nop
1966 on the microSPARC
1967 II */
1968 case 0x10 ... 0x1f: /* implementation-dependent
1969 in the SPARCv8
1970 manual, nop on the
1971 microSPARC II */
1972 break;
1973#else
af7bf89b 1974 case 0x2: /* V9 wrccr */
3475187d
FB		 1975 gen_op_wrccr();
1976 break;
af7bf89b 1977 case 0x3: /* V9 wrasi */
3475187d
FB		 1978 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1979 break;
af7bf89b 1980 case 0x6: /* V9 wrfprs */
3299908c 1981 gen_op_xor_T1_T0();
3475187d 1982 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 1983 save_state(dc);
1984 gen_op_next_insn();
1985 gen_op_movl_T0_0();
1986 gen_op_exit_tb();
1987 dc->is_br = 1;
3475187d
FB		 1988 break;
1989 case 0xf: /* V9 sir, nop if user */
1990#if !defined(CONFIG_USER_ONLY)
1991 if (supervisor(dc))
1992 gen_op_sir();
1993#endif
1994 break;
725cb90b
FB		 1995 case 0x13: /* Graphics Status */
1996 if (gen_trap_ifnofpu(dc))
1997 goto jmp_insn;
1998 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
1999 break;
83469015
FB		 2000 case 0x17: /* Tick compare */
2001#if !defined(CONFIG_USER_ONLY)
2002 if (!supervisor(dc))
2003 goto illegal_insn;
2004#endif
20c9f095
BS		 2005 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2006 gen_op_wrtick_cmpr();
83469015
FB		 2007 break;
2008 case 0x18: /* System tick */
2009#if !defined(CONFIG_USER_ONLY)
2010 if (!supervisor(dc))
2011 goto illegal_insn;
2012#endif
20c9f095 2013 gen_op_wrstick();
83469015
FB		 2014 break;
2015 case 0x19: /* System tick compare */
2016#if !defined(CONFIG_USER_ONLY)
2017 if (!supervisor(dc))
2018 goto illegal_insn;
3475187d 2019#endif
20c9f095
BS		 2020 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2021 gen_op_wrstick_cmpr();
83469015
FB		 2022 break;
2023
3475187d
FB		 2024 case 0x10: /* Performance Control */
2025 case 0x11: /* Performance Instrumentation Counter */
2026 case 0x12: /* Dispatch Control */
3475187d
FB		 2027 case 0x14: /* Softint set */
2028 case 0x15: /* Softint clear */
2029 case 0x16: /* Softint write */
83469015 2030#endif
3475187d 2031 default:
cf495bcf
FB		 2032 goto illegal_insn;
2033 }
2034 }
2035 break;
e8af50a3 2036#if !defined(CONFIG_USER_ONLY)
af7bf89b 2037 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3
FB		 2038 {
2039 if (!supervisor(dc))
2040 goto priv_insn;
3475187d
FB		 2041#ifdef TARGET_SPARC64
2042 switch (rd) {
2043 case 0:
2044 gen_op_saved();
2045 break;
2046 case 1:
2047 gen_op_restored();
2048 break;
e9ebed4d
BS		 2049 case 2: /* UA2005 allclean */
2050 case 3: /* UA2005 otherw */
2051 case 4: /* UA2005 normalw */
2052 case 5: /* UA2005 invalw */
2053 // XXX
3475187d
FB		 2054 default:
2055 goto illegal_insn;
2056 }
2057#else
e8af50a3
FB		 2058 gen_op_xor_T1_T0();
2059 gen_op_wrpsr();
9e61bde5
FB		 2060 save_state(dc);
2061 gen_op_next_insn();
2062 gen_op_movl_T0_0();
2063 gen_op_exit_tb();
2064 dc->is_br = 1;
3475187d 2065#endif
e8af50a3
FB		 2066 }
2067 break;
af7bf89b 2068 case 0x32: /* wrwim, V9 wrpr */
e8af50a3
FB		 2069 {
2070 if (!supervisor(dc))
2071 goto priv_insn;
2072 gen_op_xor_T1_T0();
3475187d
FB		 2073#ifdef TARGET_SPARC64
2074 switch (rd) {
2075 case 0: // tpc
2076 gen_op_wrtpc();
2077 break;
2078 case 1: // tnpc
2079 gen_op_wrtnpc();
2080 break;
2081 case 2: // tstate
2082 gen_op_wrtstate();
2083 break;
2084 case 3: // tt
2085 gen_op_wrtt();
2086 break;
2087 case 4: // tick
2088 gen_op_wrtick();
2089 break;
2090 case 5: // tba
83469015 2091 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3475187d
FB		 2092 break;
2093 case 6: // pstate
2094 gen_op_wrpstate();
ded3ab80
PB		 2095 save_state(dc);
2096 gen_op_next_insn();
2097 gen_op_movl_T0_0();
2098 gen_op_exit_tb();
2099 dc->is_br = 1;
3475187d
FB		 2100 break;
2101 case 7: // tl
2102 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2103 break;
2104 case 8: // pil
2105 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2106 break;
2107 case 9: // cwp
2108 gen_op_wrcwp();
2109 break;
2110 case 10: // cansave
2111 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2112 break;
2113 case 11: // canrestore
2114 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2115 break;
2116 case 12: // cleanwin
2117 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2118 break;
2119 case 13: // otherwin
2120 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2121 break;
2122 case 14: // wstate
2123 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2124 break;
e9ebed4d
BS		 2125 case 16: // UA2005 gl
2126 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2127 break;
2128 case 26: // UA2005 strand status
2129 if (!hypervisor(dc))
2130 goto priv_insn;
2131 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2132 break;
3475187d
FB		 2133 default:
2134 goto illegal_insn;
2135 }
2136#else
c688a6eb 2137 gen_op_wrwim();
3475187d 2138#endif
e8af50a3
FB		 2139 }
2140 break;
e9ebed4d 2141 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 2142 {
e9ebed4d 2143#ifndef TARGET_SPARC64
e8af50a3
FB		 2144 if (!supervisor(dc))
2145 goto priv_insn;
2146 gen_op_xor_T1_T0();
e9ebed4d
BS		 2147 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2148#else
2149 if (!hypervisor(dc))
2150 goto priv_insn;
2151 gen_op_xor_T1_T0();
2152 switch (rd) {
2153 case 0: // hpstate
2154 // XXX gen_op_wrhpstate();
2155 save_state(dc);
2156 gen_op_next_insn();
2157 gen_op_movl_T0_0();
2158 gen_op_exit_tb();
2159 dc->is_br = 1;
2160 break;
2161 case 1: // htstate
2162 // XXX gen_op_wrhtstate();
2163 break;
2164 case 3: // hintp
2165 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2166 break;
2167 case 5: // htba
2168 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2169 break;
2170 case 31: // hstick_cmpr
20c9f095
BS		 2171 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2172 gen_op_wrhstick_cmpr();
e9ebed4d
BS		 2173 break;
2174 case 6: // hver readonly
2175 default:
2176 goto illegal_insn;
2177 }
2178#endif
e8af50a3
FB		 2179 }
2180 break;
2181#endif
3475187d 2182#ifdef TARGET_SPARC64
af7bf89b 2183 case 0x2c: /* V9 movcc */
3475187d
FB		 2184 {
2185 int cc = GET_FIELD_SP(insn, 11, 12);
2186 int cond = GET_FIELD_SP(insn, 14, 17);
2187 if (IS_IMM) { /* immediate */
2188 rs2 = GET_FIELD_SPs(insn, 0, 10);
2189 gen_movl_simm_T1(rs2);
2190 }
2191 else {
2192 rs2 = GET_FIELD_SP(insn, 0, 4);
2193 gen_movl_reg_T1(rs2);
2194 }
2195 gen_movl_reg_T0(rd);
2196 flush_T2(dc);
2197 if (insn & (1 << 18)) {
2198 if (cc == 0)
2199 gen_cond[0][cond]();
2200 else if (cc == 2)
2201 gen_cond[1][cond]();
2202 else
2203 goto illegal_insn;
2204 } else {
2205 gen_fcond[cc][cond]();
2206 }
2207 gen_op_mov_cc();
2208 gen_movl_T0_reg(rd);
2209 break;
2210 }
af7bf89b 2211 case 0x2d: /* V9 sdivx */
3475187d
FB		 2212 gen_op_sdivx_T1_T0();
2213 gen_movl_T0_reg(rd);
2214 break;
af7bf89b 2215 case 0x2e: /* V9 popc */
3475187d
FB		 2216 {
2217 if (IS_IMM) { /* immediate */
2218 rs2 = GET_FIELD_SPs(insn, 0, 12);
2219 gen_movl_simm_T1(rs2);
2220 // XXX optimize: popc(constant)
2221 }
2222 else {
2223 rs2 = GET_FIELD_SP(insn, 0, 4);
2224 gen_movl_reg_T1(rs2);
2225 }
2226 gen_op_popc();
2227 gen_movl_T0_reg(rd);
2228 }
af7bf89b 2229 case 0x2f: /* V9 movr */
3475187d
FB		 2230 {
2231 int cond = GET_FIELD_SP(insn, 10, 12);
2232 rs1 = GET_FIELD(insn, 13, 17);
2233 flush_T2(dc);
2234 gen_movl_reg_T0(rs1);
2235 gen_cond_reg(cond);
2236 if (IS_IMM) { /* immediate */
46d38ba8 2237 rs2 = GET_FIELD_SPs(insn, 0, 9);
3475187d
FB		 2238 gen_movl_simm_T1(rs2);
2239 }
2240 else {
2241 rs2 = GET_FIELD_SP(insn, 0, 4);
2242 gen_movl_reg_T1(rs2);
2243 }
2244 gen_movl_reg_T0(rd);
2245 gen_op_mov_cc();
2246 gen_movl_T0_reg(rd);
2247 break;
2248 }
3475187d
FB		 2249#endif
2250 default:
e80cfcfc
FB		 2251 goto illegal_insn;
2252 }
2253 }
3299908c
BS		 2254 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2255#ifdef TARGET_SPARC64
2256 int opf = GET_FIELD_SP(insn, 5, 13);
2257 rs1 = GET_FIELD(insn, 13, 17);
2258 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 2259 if (gen_trap_ifnofpu(dc))
2260 goto jmp_insn;
3299908c
BS		 2261
2262 switch (opf) {
e9ebed4d
BS		 2263 case 0x000: /* VIS I edge8cc */
2264 case 0x001: /* VIS II edge8n */
2265 case 0x002: /* VIS I edge8lcc */
2266 case 0x003: /* VIS II edge8ln */
2267 case 0x004: /* VIS I edge16cc */
2268 case 0x005: /* VIS II edge16n */
2269 case 0x006: /* VIS I edge16lcc */
2270 case 0x007: /* VIS II edge16ln */
2271 case 0x008: /* VIS I edge32cc */
2272 case 0x009: /* VIS II edge32n */
2273 case 0x00a: /* VIS I edge32lcc */
2274 case 0x00b: /* VIS II edge32ln */
2275 // XXX
2276 goto illegal_insn;
2277 case 0x010: /* VIS I array8 */
2278 gen_movl_reg_T0(rs1);
2279 gen_movl_reg_T1(rs2);
2280 gen_op_array8();
2281 gen_movl_T0_reg(rd);
2282 break;
2283 case 0x012: /* VIS I array16 */
2284 gen_movl_reg_T0(rs1);
2285 gen_movl_reg_T1(rs2);
2286 gen_op_array16();
2287 gen_movl_T0_reg(rd);
2288 break;
2289 case 0x014: /* VIS I array32 */
2290 gen_movl_reg_T0(rs1);
2291 gen_movl_reg_T1(rs2);
2292 gen_op_array32();
2293 gen_movl_T0_reg(rd);
2294 break;
3299908c 2295 case 0x018: /* VIS I alignaddr */
3299908c
BS		 2296 gen_movl_reg_T0(rs1);
2297 gen_movl_reg_T1(rs2);
2298 gen_op_alignaddr();
2299 gen_movl_T0_reg(rd);
2300 break;
e9ebed4d 2301 case 0x019: /* VIS II bmask */
3299908c 2302 case 0x01a: /* VIS I alignaddrl */
3299908c 2303 // XXX
e9ebed4d
BS		 2304 goto illegal_insn;
2305 case 0x020: /* VIS I fcmple16 */
2306 gen_op_load_fpr_DT0(rs1);
2307 gen_op_load_fpr_DT1(rs2);
2308 gen_op_fcmple16();
2309 gen_op_store_DT0_fpr(rd);
2310 break;
2311 case 0x022: /* VIS I fcmpne16 */
2312 gen_op_load_fpr_DT0(rs1);
2313 gen_op_load_fpr_DT1(rs2);
2314 gen_op_fcmpne16();
2315 gen_op_store_DT0_fpr(rd);
3299908c 2316 break;
e9ebed4d
BS		 2317 case 0x024: /* VIS I fcmple32 */
2318 gen_op_load_fpr_DT0(rs1);
2319 gen_op_load_fpr_DT1(rs2);
2320 gen_op_fcmple32();
2321 gen_op_store_DT0_fpr(rd);
2322 break;
2323 case 0x026: /* VIS I fcmpne32 */
2324 gen_op_load_fpr_DT0(rs1);
2325 gen_op_load_fpr_DT1(rs2);
2326 gen_op_fcmpne32();
2327 gen_op_store_DT0_fpr(rd);
2328 break;
2329 case 0x028: /* VIS I fcmpgt16 */
2330 gen_op_load_fpr_DT0(rs1);
2331 gen_op_load_fpr_DT1(rs2);
2332 gen_op_fcmpgt16();
2333 gen_op_store_DT0_fpr(rd);
2334 break;
2335 case 0x02a: /* VIS I fcmpeq16 */
2336 gen_op_load_fpr_DT0(rs1);
2337 gen_op_load_fpr_DT1(rs2);
2338 gen_op_fcmpeq16();
2339 gen_op_store_DT0_fpr(rd);
2340 break;
2341 case 0x02c: /* VIS I fcmpgt32 */
2342 gen_op_load_fpr_DT0(rs1);
2343 gen_op_load_fpr_DT1(rs2);
2344 gen_op_fcmpgt32();
2345 gen_op_store_DT0_fpr(rd);
2346 break;
2347 case 0x02e: /* VIS I fcmpeq32 */
2348 gen_op_load_fpr_DT0(rs1);
2349 gen_op_load_fpr_DT1(rs2);
2350 gen_op_fcmpeq32();
2351 gen_op_store_DT0_fpr(rd);
2352 break;
2353 case 0x031: /* VIS I fmul8x16 */
2354 gen_op_load_fpr_DT0(rs1);
2355 gen_op_load_fpr_DT1(rs2);
2356 gen_op_fmul8x16();
2357 gen_op_store_DT0_fpr(rd);
2358 break;
2359 case 0x033: /* VIS I fmul8x16au */
2360 gen_op_load_fpr_DT0(rs1);
2361 gen_op_load_fpr_DT1(rs2);
2362 gen_op_fmul8x16au();
2363 gen_op_store_DT0_fpr(rd);
2364 break;
2365 case 0x035: /* VIS I fmul8x16al */
2366 gen_op_load_fpr_DT0(rs1);
2367 gen_op_load_fpr_DT1(rs2);
2368 gen_op_fmul8x16al();
2369 gen_op_store_DT0_fpr(rd);
2370 break;
2371 case 0x036: /* VIS I fmul8sux16 */
2372 gen_op_load_fpr_DT0(rs1);
2373 gen_op_load_fpr_DT1(rs2);
2374 gen_op_fmul8sux16();
2375 gen_op_store_DT0_fpr(rd);
2376 break;
2377 case 0x037: /* VIS I fmul8ulx16 */
2378 gen_op_load_fpr_DT0(rs1);
2379 gen_op_load_fpr_DT1(rs2);
2380 gen_op_fmul8ulx16();
2381 gen_op_store_DT0_fpr(rd);
2382 break;
2383 case 0x038: /* VIS I fmuld8sux16 */
2384 gen_op_load_fpr_DT0(rs1);
2385 gen_op_load_fpr_DT1(rs2);
2386 gen_op_fmuld8sux16();
2387 gen_op_store_DT0_fpr(rd);
2388 break;
2389 case 0x039: /* VIS I fmuld8ulx16 */
2390 gen_op_load_fpr_DT0(rs1);
2391 gen_op_load_fpr_DT1(rs2);
2392 gen_op_fmuld8ulx16();
2393 gen_op_store_DT0_fpr(rd);
2394 break;
2395 case 0x03a: /* VIS I fpack32 */
2396 case 0x03b: /* VIS I fpack16 */
2397 case 0x03d: /* VIS I fpackfix */
2398 case 0x03e: /* VIS I pdist */
2399 // XXX
2400 goto illegal_insn;
3299908c 2401 case 0x048: /* VIS I faligndata */
3299908c
BS		 2402 gen_op_load_fpr_DT0(rs1);
2403 gen_op_load_fpr_DT1(rs2);
2404 gen_op_faligndata();
2405 gen_op_store_DT0_fpr(rd);
2406 break;
e9ebed4d
BS		 2407 case 0x04b: /* VIS I fpmerge */
2408 gen_op_load_fpr_DT0(rs1);
2409 gen_op_load_fpr_DT1(rs2);
2410 gen_op_fpmerge();
2411 gen_op_store_DT0_fpr(rd);
2412 break;
2413 case 0x04c: /* VIS II bshuffle */
2414 // XXX
2415 goto illegal_insn;
2416 case 0x04d: /* VIS I fexpand */
2417 gen_op_load_fpr_DT0(rs1);
2418 gen_op_load_fpr_DT1(rs2);
2419 gen_op_fexpand();
2420 gen_op_store_DT0_fpr(rd);
2421 break;
2422 case 0x050: /* VIS I fpadd16 */
2423 gen_op_load_fpr_DT0(rs1);
2424 gen_op_load_fpr_DT1(rs2);
2425 gen_op_fpadd16();
2426 gen_op_store_DT0_fpr(rd);
2427 break;
2428 case 0x051: /* VIS I fpadd16s */
2429 gen_op_load_fpr_FT0(rs1);
2430 gen_op_load_fpr_FT1(rs2);
2431 gen_op_fpadd16s();
2432 gen_op_store_FT0_fpr(rd);
2433 break;
2434 case 0x052: /* VIS I fpadd32 */
2435 gen_op_load_fpr_DT0(rs1);
2436 gen_op_load_fpr_DT1(rs2);
2437 gen_op_fpadd32();
2438 gen_op_store_DT0_fpr(rd);
2439 break;
2440 case 0x053: /* VIS I fpadd32s */
2441 gen_op_load_fpr_FT0(rs1);
2442 gen_op_load_fpr_FT1(rs2);
2443 gen_op_fpadd32s();
2444 gen_op_store_FT0_fpr(rd);
2445 break;
2446 case 0x054: /* VIS I fpsub16 */
2447 gen_op_load_fpr_DT0(rs1);
2448 gen_op_load_fpr_DT1(rs2);
2449 gen_op_fpsub16();
2450 gen_op_store_DT0_fpr(rd);
2451 break;
2452 case 0x055: /* VIS I fpsub16s */
2453 gen_op_load_fpr_FT0(rs1);
2454 gen_op_load_fpr_FT1(rs2);
2455 gen_op_fpsub16s();
2456 gen_op_store_FT0_fpr(rd);
2457 break;
2458 case 0x056: /* VIS I fpsub32 */
2459 gen_op_load_fpr_DT0(rs1);
2460 gen_op_load_fpr_DT1(rs2);
2461 gen_op_fpadd32();
2462 gen_op_store_DT0_fpr(rd);
2463 break;
2464 case 0x057: /* VIS I fpsub32s */
2465 gen_op_load_fpr_FT0(rs1);
2466 gen_op_load_fpr_FT1(rs2);
2467 gen_op_fpsub32s();
2468 gen_op_store_FT0_fpr(rd);
2469 break;
3299908c 2470 case 0x060: /* VIS I fzero */
3299908c
BS		 2471 gen_op_movl_DT0_0();
2472 gen_op_store_DT0_fpr(rd);
2473 break;
2474 case 0x061: /* VIS I fzeros */
3299908c
BS		 2475 gen_op_movl_FT0_0();
2476 gen_op_store_FT0_fpr(rd);
2477 break;
e9ebed4d
BS		 2478 case 0x062: /* VIS I fnor */
2479 gen_op_load_fpr_DT0(rs1);
2480 gen_op_load_fpr_DT1(rs2);
2481 gen_op_fnor();
2482 gen_op_store_DT0_fpr(rd);
2483 break;
2484 case 0x063: /* VIS I fnors */
2485 gen_op_load_fpr_FT0(rs1);
2486 gen_op_load_fpr_FT1(rs2);
2487 gen_op_fnors();
2488 gen_op_store_FT0_fpr(rd);
2489 break;
2490 case 0x064: /* VIS I fandnot2 */
2491 gen_op_load_fpr_DT1(rs1);
2492 gen_op_load_fpr_DT0(rs2);
2493 gen_op_fandnot();
2494 gen_op_store_DT0_fpr(rd);
2495 break;
2496 case 0x065: /* VIS I fandnot2s */
2497 gen_op_load_fpr_FT1(rs1);
2498 gen_op_load_fpr_FT0(rs2);
2499 gen_op_fandnots();
2500 gen_op_store_FT0_fpr(rd);
2501 break;
2502 case 0x066: /* VIS I fnot2 */
2503 gen_op_load_fpr_DT1(rs2);
2504 gen_op_fnot();
2505 gen_op_store_DT0_fpr(rd);
2506 break;
2507 case 0x067: /* VIS I fnot2s */
2508 gen_op_load_fpr_FT1(rs2);
2509 gen_op_fnot();
2510 gen_op_store_FT0_fpr(rd);
2511 break;
2512 case 0x068: /* VIS I fandnot1 */
2513 gen_op_load_fpr_DT0(rs1);
2514 gen_op_load_fpr_DT1(rs2);
2515 gen_op_fandnot();
2516 gen_op_store_DT0_fpr(rd);
2517 break;
2518 case 0x069: /* VIS I fandnot1s */
2519 gen_op_load_fpr_FT0(rs1);
2520 gen_op_load_fpr_FT1(rs2);
2521 gen_op_fandnots();
2522 gen_op_store_FT0_fpr(rd);
2523 break;
2524 case 0x06a: /* VIS I fnot1 */
2525 gen_op_load_fpr_DT1(rs1);
2526 gen_op_fnot();
2527 gen_op_store_DT0_fpr(rd);
2528 break;
2529 case 0x06b: /* VIS I fnot1s */
2530 gen_op_load_fpr_FT1(rs1);
2531 gen_op_fnot();
2532 gen_op_store_FT0_fpr(rd);
2533 break;
2534 case 0x06c: /* VIS I fxor */
2535 gen_op_load_fpr_DT0(rs1);
2536 gen_op_load_fpr_DT1(rs2);
2537 gen_op_fxor();
2538 gen_op_store_DT0_fpr(rd);
2539 break;
2540 case 0x06d: /* VIS I fxors */
2541 gen_op_load_fpr_FT0(rs1);
2542 gen_op_load_fpr_FT1(rs2);
2543 gen_op_fxors();
2544 gen_op_store_FT0_fpr(rd);
2545 break;
2546 case 0x06e: /* VIS I fnand */
2547 gen_op_load_fpr_DT0(rs1);
2548 gen_op_load_fpr_DT1(rs2);
2549 gen_op_fnand();
2550 gen_op_store_DT0_fpr(rd);
2551 break;
2552 case 0x06f: /* VIS I fnands */
2553 gen_op_load_fpr_FT0(rs1);
2554 gen_op_load_fpr_FT1(rs2);
2555 gen_op_fnands();
2556 gen_op_store_FT0_fpr(rd);
2557 break;
2558 case 0x070: /* VIS I fand */
2559 gen_op_load_fpr_DT0(rs1);
2560 gen_op_load_fpr_DT1(rs2);
2561 gen_op_fand();
2562 gen_op_store_DT0_fpr(rd);
2563 break;
2564 case 0x071: /* VIS I fands */
2565 gen_op_load_fpr_FT0(rs1);
2566 gen_op_load_fpr_FT1(rs2);
2567 gen_op_fands();
2568 gen_op_store_FT0_fpr(rd);
2569 break;
2570 case 0x072: /* VIS I fxnor */
2571 gen_op_load_fpr_DT0(rs1);
2572 gen_op_load_fpr_DT1(rs2);
2573 gen_op_fxnor();
2574 gen_op_store_DT0_fpr(rd);
2575 break;
2576 case 0x073: /* VIS I fxnors */
2577 gen_op_load_fpr_FT0(rs1);
2578 gen_op_load_fpr_FT1(rs2);
2579 gen_op_fxnors();
2580 gen_op_store_FT0_fpr(rd);
2581 break;
3299908c 2582 case 0x074: /* VIS I fsrc1 */
3299908c
BS		 2583 gen_op_load_fpr_DT0(rs1);
2584 gen_op_store_DT0_fpr(rd);
2585 break;
2586 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 2587 gen_op_load_fpr_FT0(rs1);
2588 gen_op_store_FT0_fpr(rd);
2589 break;
e9ebed4d
BS		 2590 case 0x076: /* VIS I fornot2 */
2591 gen_op_load_fpr_DT1(rs1);
2592 gen_op_load_fpr_DT0(rs2);
2593 gen_op_fornot();
2594 gen_op_store_DT0_fpr(rd);
2595 break;
2596 case 0x077: /* VIS I fornot2s */
2597 gen_op_load_fpr_FT1(rs1);
2598 gen_op_load_fpr_FT0(rs2);
2599 gen_op_fornots();
2600 gen_op_store_FT0_fpr(rd);
2601 break;
3299908c 2602 case 0x078: /* VIS I fsrc2 */
3299908c
BS		 2603 gen_op_load_fpr_DT0(rs2);
2604 gen_op_store_DT0_fpr(rd);
2605 break;
2606 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 2607 gen_op_load_fpr_FT0(rs2);
2608 gen_op_store_FT0_fpr(rd);
2609 break;
e9ebed4d
BS		 2610 case 0x07a: /* VIS I fornot1 */
2611 gen_op_load_fpr_DT0(rs1);
2612 gen_op_load_fpr_DT1(rs2);
2613 gen_op_fornot();
2614 gen_op_store_DT0_fpr(rd);
2615 break;
2616 case 0x07b: /* VIS I fornot1s */
2617 gen_op_load_fpr_FT0(rs1);
2618 gen_op_load_fpr_FT1(rs2);
2619 gen_op_fornots();
2620 gen_op_store_FT0_fpr(rd);
2621 break;
2622 case 0x07c: /* VIS I for */
2623 gen_op_load_fpr_DT0(rs1);
2624 gen_op_load_fpr_DT1(rs2);
2625 gen_op_for();
2626 gen_op_store_DT0_fpr(rd);
2627 break;
2628 case 0x07d: /* VIS I fors */
2629 gen_op_load_fpr_FT0(rs1);
2630 gen_op_load_fpr_FT1(rs2);
2631 gen_op_fors();
2632 gen_op_store_FT0_fpr(rd);
2633 break;
3299908c 2634 case 0x07e: /* VIS I fone */
3299908c
BS		 2635 gen_op_movl_DT0_1();
2636 gen_op_store_DT0_fpr(rd);
2637 break;
2638 case 0x07f: /* VIS I fones */
3299908c
BS		 2639 gen_op_movl_FT0_1();
2640 gen_op_store_FT0_fpr(rd);
2641 break;
e9ebed4d
BS		 2642 case 0x080: /* VIS I shutdown */
2643 case 0x081: /* VIS II siam */
2644 // XXX
2645 goto illegal_insn;
3299908c
BS		 2646 default:
2647 goto illegal_insn;
2648 }
2649#else
2650 goto ncp_insn;
2651#endif
2652 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045
BS		 2653#ifdef TARGET_SPARC64
2654 goto illegal_insn;
2655#else
2656 goto ncp_insn;
2657#endif
3475187d
FB		 2658#ifdef TARGET_SPARC64
2659 } else if (xop == 0x39) { /* V9 return */
3475187d 2660 rs1 = GET_FIELD(insn, 13, 17);
1ad21e69 2661 save_state(dc);
3475187d
FB		 2662 gen_movl_reg_T0(rs1);
2663 if (IS_IMM) { /* immediate */
2664 rs2 = GET_FIELDs(insn, 19, 31);
2665#if defined(OPTIM)
2666 if (rs2) {
2667#endif
2668 gen_movl_simm_T1(rs2);
2669 gen_op_add_T1_T0();
2670#if defined(OPTIM)
2671 }
2672#endif
2673 } else { /* register */
2674 rs2 = GET_FIELD(insn, 27, 31);
2675#if defined(OPTIM)
2676 if (rs2) {
2677#endif
2678 gen_movl_reg_T1(rs2);
2679 gen_op_add_T1_T0();
2680#if defined(OPTIM)
2681 }
2682#endif
2683 }
83469015 2684 gen_op_restore();
3475187d 2685 gen_mov_pc_npc(dc);
6ea4a6c8 2686 gen_op_check_align_T0_3();
3475187d
FB		 2687 gen_op_movl_npc_T0();
2688 dc->npc = DYNAMIC_PC;
2689 goto jmp_insn;
2690#endif
e80cfcfc
FB		 2691 } else {
2692 rs1 = GET_FIELD(insn, 13, 17);
2693 gen_movl_reg_T0(rs1);
2694 if (IS_IMM) { /* immediate */
2695 rs2 = GET_FIELDs(insn, 19, 31);
2696#if defined(OPTIM)
2697 if (rs2) {
e8af50a3 2698#endif
3475187d 2699 gen_movl_simm_T1(rs2);
e80cfcfc
FB		 2700 gen_op_add_T1_T0();
2701#if defined(OPTIM)
2702 }
e8af50a3 2703#endif
e80cfcfc
FB		 2704 } else { /* register */
2705 rs2 = GET_FIELD(insn, 27, 31);
2706#if defined(OPTIM)
2707 if (rs2) {
2708#endif
2709 gen_movl_reg_T1(rs2);
2710 gen_op_add_T1_T0();
2711#if defined(OPTIM)
2712 }
e8af50a3 2713#endif
cf495bcf 2714 }
e80cfcfc
FB		 2715 switch (xop) {
2716 case 0x38: /* jmpl */
2717 {
e80cfcfc 2718 if (rd != 0) {
ded3ab80
PB		 2719#ifdef TARGET_SPARC64
2720 if (dc->pc == (uint32_t)dc->pc) {
2721 gen_op_movl_T1_im(dc->pc);
2722 } else {
2723 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2724 }
2725#else
0bee699e 2726 gen_op_movl_T1_im(dc->pc);
ded3ab80 2727#endif
0bee699e 2728 gen_movl_T1_reg(rd);
e80cfcfc 2729 }
0bee699e 2730 gen_mov_pc_npc(dc);
6ea4a6c8 2731 gen_op_check_align_T0_3();
0bee699e 2732 gen_op_movl_npc_T0();
e80cfcfc
FB		 2733 dc->npc = DYNAMIC_PC;
2734 }
2735 goto jmp_insn;
3475187d 2736#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
af7bf89b 2737 case 0x39: /* rett, V9 return */
e80cfcfc
FB		 2738 {
2739 if (!supervisor(dc))
2740 goto priv_insn;
0bee699e 2741 gen_mov_pc_npc(dc);
6ea4a6c8 2742 gen_op_check_align_T0_3();
e80cfcfc 2743 gen_op_movl_npc_T0();
0bee699e 2744 dc->npc = DYNAMIC_PC;
e80cfcfc
FB		 2745 gen_op_rett();
2746 }
0bee699e 2747 goto jmp_insn;
e80cfcfc
FB		 2748#endif
2749 case 0x3b: /* flush */
2750 gen_op_flush_T0();
2751 break;
2752 case 0x3c: /* save */
2753 save_state(dc);
2754 gen_op_save();
2755 gen_movl_T0_reg(rd);
2756 break;
2757 case 0x3d: /* restore */
2758 save_state(dc);
2759 gen_op_restore();
2760 gen_movl_T0_reg(rd);
2761 break;
3475187d 2762#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
af7bf89b 2763 case 0x3e: /* V9 done/retry */
3475187d
FB		 2764 {
2765 switch (rd) {
2766 case 0:
2767 if (!supervisor(dc))
2768 goto priv_insn;
83469015
FB		 2769 dc->npc = DYNAMIC_PC;
2770 dc->pc = DYNAMIC_PC;
3475187d 2771 gen_op_done();
83469015 2772 goto jmp_insn;
3475187d
FB		 2773 case 1:
2774 if (!supervisor(dc))
2775 goto priv_insn;
83469015
FB		 2776 dc->npc = DYNAMIC_PC;
2777 dc->pc = DYNAMIC_PC;
3475187d 2778 gen_op_retry();
83469015 2779 goto jmp_insn;
3475187d
FB		 2780 default:
2781 goto illegal_insn;
2782 }
2783 }
2784 break;
2785#endif
2786 default:
e80cfcfc
FB		 2787 goto illegal_insn;
2788 }
cf495bcf
FB		 2789 }
2790 break;
2791 }
af7bf89b 2792 break;
cf495bcf
FB		 2793 case 3: /* load/store instructions */
2794 {
2795 unsigned int xop = GET_FIELD(insn, 7, 12);
2796 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 2797 save_state(dc);
cf495bcf
FB		 2798 gen_movl_reg_T0(rs1);
2799 if (IS_IMM) { /* immediate */
2800 rs2 = GET_FIELDs(insn, 19, 31);
e80cfcfc 2801#if defined(OPTIM)
e8af50a3 2802 if (rs2 != 0) {
e80cfcfc 2803#endif
3475187d 2804 gen_movl_simm_T1(rs2);
e8af50a3 2805 gen_op_add_T1_T0();
e80cfcfc 2806#if defined(OPTIM)
e8af50a3 2807 }
e80cfcfc 2808#endif
cf495bcf
FB		 2809 } else { /* register */
2810 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc
FB		 2811#if defined(OPTIM)
2812 if (rs2 != 0) {
2813#endif
2814 gen_movl_reg_T1(rs2);
2815 gen_op_add_T1_T0();
2816#if defined(OPTIM)
2817 }
2818#endif
cf495bcf 2819 }
2f2ecb83
BS		 2820 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
2821 (xop > 0x17 && xop <= 0x1d ) ||
2822 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
cf495bcf
FB		 2823 switch (xop) {
2824 case 0x0: /* load word */
6ea4a6c8
BS		 2825#ifdef CONFIG_USER_ONLY
2826 gen_op_check_align_T0_3();
2827#endif
dc011987 2828#ifndef TARGET_SPARC64
e8af50a3 2829 gen_op_ldst(ld);
dc011987
BS		 2830#else
2831 gen_op_ldst(lduw);
2832#endif
cf495bcf
FB		 2833 break;
2834 case 0x1: /* load unsigned byte */
e8af50a3 2835 gen_op_ldst(ldub);
cf495bcf
FB		 2836 break;
2837 case 0x2: /* load unsigned halfword */
6ea4a6c8
BS		 2838#ifdef CONFIG_USER_ONLY
2839 gen_op_check_align_T0_1();
2840#endif
e8af50a3 2841 gen_op_ldst(lduh);
cf495bcf
FB		 2842 break;
2843 case 0x3: /* load double word */
6ea4a6c8 2844 gen_op_check_align_T0_7();
d4218d99
BS		 2845 if (rd & 1)
2846 goto illegal_insn;
e8af50a3 2847 gen_op_ldst(ldd);
cf495bcf
FB		 2848 gen_movl_T0_reg(rd + 1);
2849 break;
2850 case 0x9: /* load signed byte */
e8af50a3 2851 gen_op_ldst(ldsb);
cf495bcf
FB		 2852 break;
2853 case 0xa: /* load signed halfword */
6ea4a6c8
BS		 2854#ifdef CONFIG_USER_ONLY
2855 gen_op_check_align_T0_1();
2856#endif
e8af50a3 2857 gen_op_ldst(ldsh);
cf495bcf
FB		 2858 break;
2859 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 2860 gen_op_ldst(ldstub);
cf495bcf
FB		 2861 break;
2862 case 0x0f: /* swap register with memory. Also atomically */
6ea4a6c8
BS		 2863#ifdef CONFIG_USER_ONLY
2864 gen_op_check_align_T0_3();
2865#endif
e80cfcfc 2866 gen_movl_reg_T1(rd);
e8af50a3
FB		 2867 gen_op_ldst(swap);
2868 break;
3475187d 2869#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 2870 case 0x10: /* load word alternate */
3475187d 2871#ifndef TARGET_SPARC64
d4218d99
BS		 2872 if (IS_IMM)
2873 goto illegal_insn;
e8af50a3
FB		 2874 if (!supervisor(dc))
2875 goto priv_insn;
6ea4a6c8
BS		 2876#ifdef CONFIG_USER_ONLY
2877 gen_op_check_align_T0_3();
2878#endif
e8af50a3 2879 gen_op_lda(insn, 1, 4, 0);
dc011987 2880#else
6ea4a6c8
BS		 2881#ifdef CONFIG_USER_ONLY
2882 gen_op_check_align_T0_3();
2883#endif
dc011987
BS		 2884 gen_op_lduwa(insn, 1, 4, 0);
2885#endif
e8af50a3
FB		 2886 break;
2887 case 0x11: /* load unsigned byte alternate */
3475187d 2888#ifndef TARGET_SPARC64
d4218d99
BS		 2889 if (IS_IMM)
2890 goto illegal_insn;
e8af50a3
FB		 2891 if (!supervisor(dc))
2892 goto priv_insn;
3475187d 2893#endif
e8af50a3
FB		 2894 gen_op_lduba(insn, 1, 1, 0);
2895 break;
2896 case 0x12: /* load unsigned halfword alternate */
3475187d 2897#ifndef TARGET_SPARC64
d4218d99
BS		 2898 if (IS_IMM)
2899 goto illegal_insn;
e8af50a3
FB		 2900 if (!supervisor(dc))
2901 goto priv_insn;
6ea4a6c8
BS		 2902#endif
2903#ifdef CONFIG_USER_ONLY
2904 gen_op_check_align_T0_1();
3475187d 2905#endif
e8af50a3
FB		 2906 gen_op_lduha(insn, 1, 2, 0);
2907 break;
2908 case 0x13: /* load double word alternate */
3475187d 2909#ifndef TARGET_SPARC64
d4218d99
BS		 2910 if (IS_IMM)
2911 goto illegal_insn;
e8af50a3
FB		 2912 if (!supervisor(dc))
2913 goto priv_insn;
3475187d 2914#endif
d4218d99
BS		 2915 if (rd & 1)
2916 goto illegal_insn;
6ea4a6c8 2917 gen_op_check_align_T0_7();
e8af50a3
FB		 2918 gen_op_ldda(insn, 1, 8, 0);
2919 gen_movl_T0_reg(rd + 1);
2920 break;
2921 case 0x19: /* load signed byte alternate */
3475187d 2922#ifndef TARGET_SPARC64
d4218d99
BS		 2923 if (IS_IMM)
2924 goto illegal_insn;
e8af50a3
FB		 2925 if (!supervisor(dc))
2926 goto priv_insn;
3475187d 2927#endif
e8af50a3
FB		 2928 gen_op_ldsba(insn, 1, 1, 1);
2929 break;
2930 case 0x1a: /* load signed halfword alternate */
3475187d 2931#ifndef TARGET_SPARC64
d4218d99
BS		 2932 if (IS_IMM)
2933 goto illegal_insn;
e8af50a3
FB		 2934 if (!supervisor(dc))
2935 goto priv_insn;
6ea4a6c8
BS		 2936#endif
2937#ifdef CONFIG_USER_ONLY
2938 gen_op_check_align_T0_1();
3475187d 2939#endif
e8af50a3
FB		 2940 gen_op_ldsha(insn, 1, 2 ,1);
2941 break;
2942 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 2943#ifndef TARGET_SPARC64
d4218d99
BS		 2944 if (IS_IMM)
2945 goto illegal_insn;
e8af50a3
FB		 2946 if (!supervisor(dc))
2947 goto priv_insn;
3475187d 2948#endif
e8af50a3
FB		 2949 gen_op_ldstuba(insn, 1, 1, 0);
2950 break;
2951 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 2952#ifndef TARGET_SPARC64
d4218d99
BS		 2953 if (IS_IMM)
2954 goto illegal_insn;
e8af50a3
FB		 2955 if (!supervisor(dc))
2956 goto priv_insn;
3475187d 2957#endif
e80cfcfc 2958 gen_movl_reg_T1(rd);
6ea4a6c8
BS		 2959#ifdef CONFIG_USER_ONLY
2960 gen_op_check_align_T0_3();
2961#endif
e8af50a3 2962 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 2963 break;
3475187d
FB		 2964
2965#ifndef TARGET_SPARC64
fcc72045
BS		 2966 case 0x30: /* ldc */
2967 case 0x31: /* ldcsr */
2968 case 0x33: /* lddc */
fcc72045 2969 goto ncp_insn;
0fa85d43
FB		 2970 /* avoid warnings */
2971 (void) &gen_op_stfa;
2972 (void) &gen_op_stdfa;
2973 (void) &gen_op_ldfa;
2974 (void) &gen_op_lddfa;
3475187d 2975#else
dc011987 2976 (void) &gen_op_lda;
3475187d
FB		 2977#if !defined(CONFIG_USER_ONLY)
2978 (void) &gen_op_cas;
2979 (void) &gen_op_casx;
e80cfcfc 2980#endif
3475187d
FB		 2981#endif
2982#endif
2983#ifdef TARGET_SPARC64
af7bf89b 2984 case 0x08: /* V9 ldsw */
6ea4a6c8
BS		 2985#ifdef CONFIG_USER_ONLY
2986 gen_op_check_align_T0_3();
2987#endif
3475187d
FB		 2988 gen_op_ldst(ldsw);
2989 break;
af7bf89b 2990 case 0x0b: /* V9 ldx */
6ea4a6c8 2991 gen_op_check_align_T0_7();
3475187d
FB		 2992 gen_op_ldst(ldx);
2993 break;
af7bf89b 2994 case 0x18: /* V9 ldswa */
6ea4a6c8
BS		 2995#ifdef CONFIG_USER_ONLY
2996 gen_op_check_align_T0_3();
2997#endif
3475187d
FB		 2998 gen_op_ldswa(insn, 1, 4, 1);
2999 break;
af7bf89b 3000 case 0x1b: /* V9 ldxa */
6ea4a6c8 3001 gen_op_check_align_T0_7();
3475187d
FB		 3002 gen_op_ldxa(insn, 1, 8, 0);
3003 break;
3004 case 0x2d: /* V9 prefetch, no effect */
3005 goto skip_move;
af7bf89b 3006 case 0x30: /* V9 ldfa */
6ea4a6c8
BS		 3007#ifdef CONFIG_USER_ONLY
3008 gen_op_check_align_T0_3();
3009#endif
3475187d
FB		 3010 gen_op_ldfa(insn, 1, 8, 0); // XXX
3011 break;
af7bf89b 3012 case 0x33: /* V9 lddfa */
6ea4a6c8 3013 gen_op_check_align_T0_7();
3475187d 3014 gen_op_lddfa(insn, 1, 8, 0); // XXX
af7bf89b 3015
3475187d
FB		 3016 break;
3017 case 0x3d: /* V9 prefetcha, no effect */
3018 goto skip_move;
af7bf89b 3019 case 0x32: /* V9 ldqfa */
3475187d
FB		 3020 goto nfpu_insn;
3021#endif
3022 default:
e80cfcfc 3023 goto illegal_insn;
7a3f1944 3024 }
cf495bcf 3025 gen_movl_T1_reg(rd);
3475187d
FB		 3026#ifdef TARGET_SPARC64
3027 skip_move: ;
3028#endif
e8af50a3 3029 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 3030 if (gen_trap_ifnofpu(dc))
3031 goto jmp_insn;
e8af50a3
FB		 3032 switch (xop) {
3033 case 0x20: /* load fpreg */
6ea4a6c8
BS		 3034#ifdef CONFIG_USER_ONLY
3035 gen_op_check_align_T0_3();
3036#endif
e8af50a3
FB		 3037 gen_op_ldst(ldf);
3038 gen_op_store_FT0_fpr(rd);
3039 break;
3040 case 0x21: /* load fsr */
6ea4a6c8
BS		 3041#ifdef CONFIG_USER_ONLY
3042 gen_op_check_align_T0_3();
3043#endif
9e61bde5 3044 gen_op_ldst(ldf);
e8af50a3
FB		 3045 gen_op_ldfsr();
3046 break;
af7bf89b
FB		 3047 case 0x22: /* load quad fpreg */
3048 goto nfpu_insn;
e8af50a3 3049 case 0x23: /* load double fpreg */
6ea4a6c8 3050 gen_op_check_align_T0_7();
e8af50a3 3051 gen_op_ldst(lddf);
3475187d 3052 gen_op_store_DT0_fpr(DFPREG(rd));
e8af50a3 3053 break;
e80cfcfc
FB		 3054 default:
3055 goto illegal_insn;
e8af50a3 3056 }
3475187d
FB		 3057 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3058 xop == 0xe || xop == 0x1e) {
cf495bcf
FB		 3059 gen_movl_reg_T1(rd);
3060 switch (xop) {
3061 case 0x4:
6ea4a6c8
BS		 3062#ifdef CONFIG_USER_ONLY
3063 gen_op_check_align_T0_3();
3064#endif
e8af50a3 3065 gen_op_ldst(st);
cf495bcf
FB		 3066 break;
3067 case 0x5:
e8af50a3 3068 gen_op_ldst(stb);
cf495bcf
FB		 3069 break;
3070 case 0x6:
6ea4a6c8
BS		 3071#ifdef CONFIG_USER_ONLY
3072 gen_op_check_align_T0_1();
3073#endif
e8af50a3 3074 gen_op_ldst(sth);
cf495bcf
FB		 3075 break;
3076 case 0x7:
d4218d99
BS		 3077 if (rd & 1)
3078 goto illegal_insn;
6ea4a6c8 3079 gen_op_check_align_T0_7();
72cbca10 3080 flush_T2(dc);
cf495bcf 3081 gen_movl_reg_T2(rd + 1);
e8af50a3
FB		 3082 gen_op_ldst(std);
3083 break;
3475187d 3084#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
e8af50a3 3085 case 0x14:
3475187d 3086#ifndef TARGET_SPARC64
d4218d99
BS		 3087 if (IS_IMM)
3088 goto illegal_insn;
e8af50a3
FB		 3089 if (!supervisor(dc))
3090 goto priv_insn;
6ea4a6c8
BS		 3091#endif
3092#ifdef CONFIG_USER_ONLY
3093 gen_op_check_align_T0_3();
3475187d 3094#endif
e8af50a3 3095 gen_op_sta(insn, 0, 4, 0);
d39c0b99 3096 break;
e8af50a3 3097 case 0x15:
3475187d 3098#ifndef TARGET_SPARC64
d4218d99
BS		 3099 if (IS_IMM)
3100 goto illegal_insn;
e8af50a3
FB		 3101 if (!supervisor(dc))
3102 goto priv_insn;
3475187d 3103#endif
e8af50a3 3104 gen_op_stba(insn, 0, 1, 0);
d39c0b99 3105 break;
e8af50a3 3106 case 0x16:
3475187d 3107#ifndef TARGET_SPARC64
d4218d99
BS		 3108 if (IS_IMM)
3109 goto illegal_insn;
e8af50a3
FB		 3110 if (!supervisor(dc))
3111 goto priv_insn;
6ea4a6c8
BS		 3112#endif
3113#ifdef CONFIG_USER_ONLY
3114 gen_op_check_align_T0_1();
3475187d 3115#endif
e8af50a3 3116 gen_op_stha(insn, 0, 2, 0);
d39c0b99 3117 break;
e8af50a3 3118 case 0x17:
3475187d 3119#ifndef TARGET_SPARC64
d4218d99
BS		 3120 if (IS_IMM)
3121 goto illegal_insn;
e8af50a3
FB		 3122 if (!supervisor(dc))
3123 goto priv_insn;
3475187d 3124#endif
d4218d99
BS		 3125 if (rd & 1)
3126 goto illegal_insn;
6ea4a6c8 3127 gen_op_check_align_T0_7();
e8af50a3
FB		 3128 flush_T2(dc);
3129 gen_movl_reg_T2(rd + 1);
3130 gen_op_stda(insn, 0, 8, 0);
d39c0b99 3131 break;
e80cfcfc 3132#endif
3475187d 3133#ifdef TARGET_SPARC64
af7bf89b 3134 case 0x0e: /* V9 stx */
6ea4a6c8 3135 gen_op_check_align_T0_7();
3475187d
FB		 3136 gen_op_ldst(stx);
3137 break;
af7bf89b 3138 case 0x1e: /* V9 stxa */
6ea4a6c8 3139 gen_op_check_align_T0_7();
3475187d
FB		 3140 gen_op_stxa(insn, 0, 8, 0); // XXX
3141 break;
3142#endif
3143 default:
e80cfcfc 3144 goto illegal_insn;
7a3f1944 3145 }
e8af50a3 3146 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 3147 if (gen_trap_ifnofpu(dc))
3148 goto jmp_insn;
e8af50a3
FB		 3149 switch (xop) {
3150 case 0x24:
6ea4a6c8
BS		 3151#ifdef CONFIG_USER_ONLY
3152 gen_op_check_align_T0_3();
3153#endif
e8af50a3
FB		 3154 gen_op_load_fpr_FT0(rd);
3155 gen_op_ldst(stf);
3156 break;
af7bf89b 3157 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8
BS		 3158#ifdef CONFIG_USER_ONLY
3159 gen_op_check_align_T0_3();
3160#endif
e8af50a3 3161 gen_op_stfsr();
9e61bde5 3162 gen_op_ldst(stf);
e8af50a3 3163 break;
9143e598 3164#if !defined(CONFIG_USER_ONLY)
af7bf89b 3165 case 0x26: /* stdfq */
9143e598
BS		 3166 if (!supervisor(dc))
3167 goto priv_insn;
3168 if (gen_trap_ifnofpu(dc))
3169 goto jmp_insn;
3170 goto nfq_insn;
3171#endif
e8af50a3 3172 case 0x27:
6ea4a6c8 3173 gen_op_check_align_T0_7();
3475187d 3174 gen_op_load_fpr_DT0(DFPREG(rd));
e8af50a3
FB		 3175 gen_op_ldst(stdf);
3176 break;
e80cfcfc 3177 default:
3475187d
FB		 3178 goto illegal_insn;
3179 }
3180 } else if (xop > 0x33 && xop < 0x3f) {
3475187d 3181 switch (xop) {
a4d17f19 3182#ifdef TARGET_SPARC64
af7bf89b 3183 case 0x34: /* V9 stfa */
6ea4a6c8
BS		 3184#ifdef CONFIG_USER_ONLY
3185 gen_op_check_align_T0_3();
3186#endif
3475187d
FB		 3187 gen_op_stfa(insn, 0, 0, 0); // XXX
3188 break;
af7bf89b 3189 case 0x37: /* V9 stdfa */
6ea4a6c8 3190 gen_op_check_align_T0_7();
3475187d
FB		 3191 gen_op_stdfa(insn, 0, 0, 0); // XXX
3192 break;
af7bf89b 3193 case 0x3c: /* V9 casa */
6ea4a6c8
BS		 3194#ifdef CONFIG_USER_ONLY
3195 gen_op_check_align_T0_3();
3196#endif
3475187d
FB		 3197 gen_op_casa(insn, 0, 4, 0); // XXX
3198 break;
af7bf89b 3199 case 0x3e: /* V9 casxa */
6ea4a6c8 3200 gen_op_check_align_T0_7();
3475187d
FB		 3201 gen_op_casxa(insn, 0, 8, 0); // XXX
3202 break;
af7bf89b 3203 case 0x36: /* V9 stqfa */
3475187d 3204 goto nfpu_insn;
a4d17f19
BS		 3205#else
3206 case 0x34: /* stc */
3207 case 0x35: /* stcsr */
3208 case 0x36: /* stdcq */
3209 case 0x37: /* stdc */
3210 goto ncp_insn;
3211#endif
3475187d 3212 default:
e80cfcfc 3213 goto illegal_insn;
e8af50a3 3214 }
e8af50a3 3215 }
e80cfcfc
FB		 3216 else
3217 goto illegal_insn;
7a3f1944 3218 }
af7bf89b 3219 break;
cf495bcf
FB		 3220 }
3221 /* default case for non jump instructions */
72cbca10
FB		 3222 if (dc->npc == DYNAMIC_PC) {
3223 dc->pc = DYNAMIC_PC;
3224 gen_op_next_insn();
3225 } else if (dc->npc == JUMP_PC) {
3226 /* we can do a static jump */
46525e1f 3227 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 3228 dc->is_br = 1;
3229 } else {
cf495bcf
FB		 3230 dc->pc = dc->npc;
3231 dc->npc = dc->npc + 4;
cf495bcf 3232 }
e80cfcfc 3233 jmp_insn:
cf495bcf
FB		 3234 return;
3235 illegal_insn:
72cbca10 3236 save_state(dc);
cf495bcf
FB		 3237 gen_op_exception(TT_ILL_INSN);
3238 dc->is_br = 1;
e8af50a3 3239 return;
e80cfcfc 3240#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 3241 priv_insn:
3242 save_state(dc);
3243 gen_op_exception(TT_PRIV_INSN);
3244 dc->is_br = 1;
e80cfcfc
FB		 3245 return;
3246#endif
3247 nfpu_insn:
3248 save_state(dc);
3249 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3250 dc->is_br = 1;
fcc72045 3251 return;
9143e598
BS		 3252#if !defined(CONFIG_USER_ONLY)
3253 nfq_insn:
3254 save_state(dc);
3255 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3256 dc->is_br = 1;
3257 return;
3258#endif
fcc72045
BS		 3259#ifndef TARGET_SPARC64
3260 ncp_insn:
3261 save_state(dc);
3262 gen_op_exception(TT_NCP_INSN);
3263 dc->is_br = 1;
3264 return;
3265#endif
7a3f1944
FB		 3266}
3267
cf495bcf 3268static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 3269 int spc, CPUSPARCState *env)
7a3f1944 3270{
72cbca10 3271 target_ulong pc_start, last_pc;
cf495bcf
FB		 3272 uint16_t *gen_opc_end;
3273 DisasContext dc1, *dc = &dc1;
e8af50a3 3274 int j, lj = -1;
cf495bcf
FB		 3275
3276 memset(dc, 0, sizeof(DisasContext));
cf495bcf 3277 dc->tb = tb;
72cbca10 3278 pc_start = tb->pc;
cf495bcf 3279 dc->pc = pc_start;
e80cfcfc 3280 last_pc = dc->pc;
72cbca10 3281 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 3282#if defined(CONFIG_USER_ONLY)
3283 dc->mem_idx = 0;
a80dde08 3284 dc->fpu_enabled = 1;
e8af50a3
FB		 3285#else
3286 dc->mem_idx = ((env->psrs) != 0);
a80dde08
FB		 3287#ifdef TARGET_SPARC64
3288 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3289#else
3290 dc->fpu_enabled = ((env->psref) != 0);
3291#endif
e8af50a3 3292#endif
cf495bcf
FB		 3293 gen_opc_ptr = gen_opc_buf;
3294 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3295 gen_opparam_ptr = gen_opparam_buf;
83469015 3296 nb_gen_labels = 0;
cf495bcf
FB		 3297
3298 do {
e8af50a3
FB		 3299 if (env->nb_breakpoints > 0) {
3300 for(j = 0; j < env->nb_breakpoints; j++) {
3301 if (env->breakpoints[j] == dc->pc) {
e80cfcfc
FB		 3302 if (dc->pc != pc_start)
3303 save_state(dc);
3304 gen_op_debug();
3305 gen_op_movl_T0_0();
3306 gen_op_exit_tb();
3307 dc->is_br = 1;
3308 goto exit_gen_loop;
e8af50a3
FB		 3309 }
3310 }
3311 }
3312 if (spc) {
3313 if (loglevel > 0)
3314 fprintf(logfile, "Search PC...\n");
3315 j = gen_opc_ptr - gen_opc_buf;
3316 if (lj < j) {
3317 lj++;
3318 while (lj < j)
3319 gen_opc_instr_start[lj++] = 0;
3320 gen_opc_pc[lj] = dc->pc;
3321 gen_opc_npc[lj] = dc->npc;
3322 gen_opc_instr_start[lj] = 1;
3323 }
3324 }
cf495bcf
FB		 3325 last_pc = dc->pc;
3326 disas_sparc_insn(dc);
3475187d 3327
cf495bcf
FB		 3328 if (dc->is_br)
3329 break;
3330 /* if the next PC is different, we abort now */
3331 if (dc->pc != (last_pc + 4))
3332 break;
d39c0b99
FB		 3333 /* if we reach a page boundary, we stop generation so that the
3334 PC of a TT_TFAULT exception is always in the right page */
3335 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3336 break;
e80cfcfc
FB		 3337 /* if single step mode, we generate only one instruction and
3338 generate an exception */
3339 if (env->singlestep_enabled) {
3475187d 3340 gen_jmp_im(dc->pc);
e80cfcfc
FB		 3341 gen_op_movl_T0_0();
3342 gen_op_exit_tb();
3343 break;
3344 }
cf495bcf
FB		 3345 } while ((gen_opc_ptr < gen_opc_end) &&
3346 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 3347
3348 exit_gen_loop:
72cbca10 3349 if (!dc->is_br) {
5fafdf24 3350 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 3351 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3352 /* static PC and NPC: we can use direct chaining */
46525e1f 3353 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 3354 } else {
3355 if (dc->pc != DYNAMIC_PC)
3475187d 3356 gen_jmp_im(dc->pc);
72cbca10
FB		 3357 save_npc(dc);
3358 gen_op_movl_T0_0();
3359 gen_op_exit_tb();
3360 }
3361 }
cf495bcf 3362 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 3363 if (spc) {
3364 j = gen_opc_ptr - gen_opc_buf;
3365 lj++;
3366 while (lj <= j)
3367 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 3368#if 0
3369 if (loglevel > 0) {
3370 page_dump(logfile);
3371 }
3372#endif
c3278b7b
FB		 3373 gen_opc_jump_pc[0] = dc->jump_pc[0];
3374 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 3375 } else {
e80cfcfc 3376 tb->size = last_pc + 4 - pc_start;
e8af50a3 3377 }
7a3f1944 3378#ifdef DEBUG_DISAS
e19e89a5 3379 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 3380 fprintf(logfile, "--------------\n");
0fa85d43
FB		 3381 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3382 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
cf495bcf 3383 fprintf(logfile, "\n");
e19e89a5
FB		 3384 if (loglevel & CPU_LOG_TB_OP) {
3385 fprintf(logfile, "OP:\n");
3386 dump_ops(gen_opc_buf, gen_opparam_buf);
3387 fprintf(logfile, "\n");
3388 }
cf495bcf 3389 }
7a3f1944 3390#endif
cf495bcf 3391 return 0;
7a3f1944
FB		 3392}
3393
cf495bcf 3394int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3395{
e8af50a3 3396 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 3397}
3398
cf495bcf 3399int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3400{
e8af50a3 3401 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 3402}
3403
e80cfcfc 3404extern int ram_size;
cf495bcf 3405
e80cfcfc
FB		 3406void cpu_reset(CPUSPARCState *env)
3407{
bb05683b 3408 tlb_flush(env, 1);
cf495bcf
FB		 3409 env->cwp = 0;
3410 env->wim = 1;
3411 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 3412#if defined(CONFIG_USER_ONLY)
cf495bcf 3413 env->user_mode_only = 1;
5ef54116 3414#ifdef TARGET_SPARC64
6ef905f6
BS		 3415 env->cleanwin = NWINDOWS - 2;
3416 env->cansave = NWINDOWS - 2;
3417 env->pstate = PS_RMO | PS_PEF | PS_IE;
3418 env->asi = 0x82; // Primary no-fault
5ef54116 3419#endif
e8af50a3 3420#else
32af58f9 3421 env->psret = 0;
e8af50a3 3422 env->psrs = 1;
0bee699e 3423 env->psrps = 1;
3475187d 3424#ifdef TARGET_SPARC64
83469015 3425 env->pstate = PS_PRIV;
83469015 3426 env->pc = 0x1fff0000000ULL;
3475187d 3427#else
83469015 3428 env->pc = 0xffd00000;
32af58f9 3429 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3475187d 3430#endif
83469015 3431 env->npc = env->pc + 4;
e8af50a3 3432#endif
e80cfcfc
FB		 3433}
3434
3435CPUSPARCState *cpu_sparc_init(void)
3436{
3437 CPUSPARCState *env;
3438
c68ea704
FB		 3439 env = qemu_mallocz(sizeof(CPUSPARCState));
3440 if (!env)
3441 return NULL;
3442 cpu_exec_init(env);
e80cfcfc 3443 cpu_reset(env);
cf495bcf 3444 return (env);
7a3f1944
FB		 3445}
3446
62724a37
BS		 3447static const sparc_def_t sparc_defs[] = {
3448#ifdef TARGET_SPARC64
3449 {
3450 .name = "TI UltraSparc II",
3451 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3452 | (MAXTL << 8) | (NWINDOWS - 1)),
3453 .fpu_version = 0x00000000,
3454 .mmu_version = 0,
3455 },
3456#else
3457 {
3458 .name = "Fujitsu MB86904",
3459 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3460 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3461 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3462 },
e0353fe2 3463 {
5ef62c5c
BS		 3464 .name = "Fujitsu MB86907",
3465 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3466 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3467 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3468 },
3469 {
3470 .name = "TI MicroSparc I",
3471 .iu_version = 0x41000000,
3472 .fpu_version = 4 << 17,
3473 .mmu_version = 0x41000000,
3474 },
3475 {
e0353fe2
BS		 3476 .name = "TI SuperSparc II",
3477 .iu_version = 0x40000000,
5ef62c5c
BS		 3478 .fpu_version = 0 << 17,
3479 .mmu_version = 0x04000000,
3480 },
3481 {
3482 .name = "Ross RT620",
3483 .iu_version = 0x1e000000,
3484 .fpu_version = 1 << 17,
3485 .mmu_version = 0x17000000,
e0353fe2 3486 },
62724a37
BS		 3487#endif
3488};
3489
3490int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3491{
3492 int ret;
3493 unsigned int i;
3494
3495 ret = -1;
3496 *def = NULL;
3497 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3498 if (strcasecmp(name, sparc_defs[i].name) == 0) {
3499 *def = &sparc_defs[i];
3500 ret = 0;
3501 break;
3502 }
3503 }
3504
3505 return ret;
3506}
3507
3508void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3509{
3510 unsigned int i;
3511
3512 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3513 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3514 sparc_defs[i].name,
3515 sparc_defs[i].iu_version,
3516 sparc_defs[i].fpu_version,
3517 sparc_defs[i].mmu_version);
3518 }
3519}
3520
3521int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3522{
3523 env->version = def->iu_version;
3524 env->fsr = def->fpu_version;
3525#if !defined(TARGET_SPARC64)
3526 env->mmuregs[0] = def->mmu_version;
3527#endif
3528 return 0;
3529}
3530
7a3f1944
FB		 3531#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3532
5fafdf24 3533void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 3534 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3535 int flags)
7a3f1944 3536{
cf495bcf
FB		 3537 int i, x;
3538
af7bf89b 3539 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 3540 cpu_fprintf(f, "General Registers:\n");
cf495bcf 3541 for (i = 0; i < 4; i++)
af7bf89b 3542 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 3543 cpu_fprintf(f, "\n");
cf495bcf 3544 for (; i < 8; i++)
af7bf89b 3545 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 3546 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB		 3547 for (x = 0; x < 3; x++) {
3548 for (i = 0; i < 4; i++)
af7bf89b 3549 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 3550 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3551 env->regwptr[i + x * 8]);
7fe48483 3552 cpu_fprintf(f, "\n");
cf495bcf 3553 for (; i < 8; i++)
af7bf89b 3554 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
cf495bcf
FB		 3555 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3556 env->regwptr[i + x * 8]);
7fe48483 3557 cpu_fprintf(f, "\n");
cf495bcf 3558 }
7fe48483 3559 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 3560 for (i = 0; i < 32; i++) {
3561 if ((i & 3) == 0)
7fe48483
FB		 3562 cpu_fprintf(f, "%%f%02d:", i);
3563 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 3564 if ((i & 3) == 3)
7fe48483 3565 cpu_fprintf(f, "\n");
e8af50a3 3566 }
ded3ab80 3567#ifdef TARGET_SPARC64
3299908c
BS		 3568 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3569 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80
PB		 3570 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3571 env->cansave, env->canrestore, env->otherwin, env->wstate,
3572 env->cleanwin, NWINDOWS - 1 - env->cwp);
3573#else
7fe48483 3574 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB		 3575 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3576 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
5fafdf24 3577 env->psrs?'S':'-', env->psrps?'P':'-',
e8af50a3 3578 env->psret?'E':'-', env->wim);
ded3ab80 3579#endif
3475187d 3580 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 3581}
edfcbd99 3582
e80cfcfc 3583#if defined(CONFIG_USER_ONLY)
9b3c35e0 3584target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 3585{
3586 return addr;
3587}
658138bc 3588
e80cfcfc 3589#else
af7bf89b
FB		 3590extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3591 int *access_index, target_ulong address, int rw,
0fa85d43
FB		 3592 int is_user);
3593
9b3c35e0 3594target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 3595{
af7bf89b 3596 target_phys_addr_t phys_addr;
e80cfcfc
FB		 3597 int prot, access_index;
3598
3599 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
6b1575b7
FB		 3600 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3601 return -1;
6c36d3fa
BS		 3602 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3603 return -1;
e80cfcfc
FB		 3604 return phys_addr;
3605}
3606#endif
3607
658138bc
FB		 3608void helper_flush(target_ulong addr)
3609{
3610 addr &= ~7;
3611 tb_invalidate_page_range(addr, addr + 8);
3612}
Mirror of https://git.qemu.org/git/qemu.git