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18a00dfd 1/*
f905432c 2 * Voipac PXA270 Support
18a00dfd 3 *
f905432c 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
18a00dfd 5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
18a00dfd
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7 */
8
9#include <common.h>
10#include <asm/arch/hardware.h>
5d877f42 11#include <asm/arch/regs-mmc.h>
4438a45f 12#include <asm/arch/pxa.h>
c7e61334 13#include <netdev.h>
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14#include <serial.h>
15#include <asm/io.h>
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16
17DECLARE_GLOBAL_DATA_PTR;
18
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19/*
20 * Miscelaneous platform dependent initialisations
21 */
f905432c 22int board_init(void)
18a00dfd 23{
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24 /* We have RAM, disable cache */
25 dcache_disable();
26 icache_disable();
27
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28 /* memory and cpu-speed are setup before relocation */
29 /* so we do _nothing_ here */
30
f905432c 31 /* Arch number of vpac270 */
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32 gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
33
34 /* adress of boot parameters */
35 gd->bd->bi_boot_params = 0xa0000100;
36
37 return 0;
38}
39
f905432c 40int dram_init(void)
6ef6eb91 41{
411b9eaf 42#ifndef CONFIG_ONENAND
f68d2a22 43 pxa2xx_dram_init();
411b9eaf 44#endif
6ef6eb91 45 gd->ram_size = PHYS_SDRAM_1_SIZE;
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46 return 0;
47}
48
49void dram_init_banksize(void)
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50{
51 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
18a00dfd 52 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
18a00dfd 53
f97e9c65 54#ifdef CONFIG_RAM_256M
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55 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
56 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
57#endif
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58}
59
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60#ifdef CONFIG_CMD_MMC
61int board_mmc_init(bd_t *bis)
62{
63 pxa_mmc_register(0);
64 return 0;
65}
66#endif
67
f905432c 68#ifdef CONFIG_CMD_USB
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69int usb_board_init(void)
70{
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71 writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
72 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
73 UHCHR);
18a00dfd 74
3ba8bf7c 75 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
18a00dfd 76
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77 while (readl(UHCHR) & UHCHR_FSBIR)
78 ;
18a00dfd 79
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80 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
81 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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82
83 /* Clear any OTG Pin Hold */
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84 if (readl(PSSR) & PSSR_OTGPH)
85 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
18a00dfd 86
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87 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
88 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
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89
90 /* Set port power control mask bits, only 3 ports. */
3ba8bf7c 91 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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92
93 /* enable port 2 */
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94 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
95 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
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96
97 return 0;
98}
99
100void usb_board_init_fail(void)
101{
102 return;
103}
104
105void usb_board_stop(void)
106{
3ba8bf7c 107 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
18a00dfd 108 udelay(11);
3ba8bf7c 109 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
18a00dfd 110
3ba8bf7c 111 writel(readl(UHCCOMS) | 1, UHCCOMS);
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112 udelay(10);
113
3ba8bf7c 114 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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115
116 return;
117}
f905432c 118#endif
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119
120#ifdef CONFIG_DRIVER_DM9000
121int board_eth_init(bd_t *bis)
122{
123 return dm9000_initialize(bis);
124}
125#endif