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2e8cf49e NC |
1 | /* cpustate.h -- Prototypes for AArch64 simulator functions. |
2 | ||
3666a048 | 3 | Copyright (C) 2015-2021 Free Software Foundation, Inc. |
2e8cf49e NC |
4 | |
5 | Contributed by Red Hat. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include <stdio.h> | |
c0386d4d | 23 | #include <math.h> |
2e8cf49e NC |
24 | |
25 | #include "sim-main.h" | |
26 | #include "cpustate.h" | |
27 | #include "simulator.h" | |
cd5b6074 | 28 | #include "libiberty.h" |
2e8cf49e NC |
29 | |
30 | /* Some operands are allowed to access the stack pointer (reg 31). | |
31 | For others a read from r31 always returns 0, and a write to r31 is ignored. */ | |
32 | #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg)) | |
33 | ||
34 | void | |
35 | aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val) | |
36 | { | |
37 | if (reg == R31 && ! r31_is_sp) | |
38 | { | |
e101a78b | 39 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); |
2e8cf49e NC |
40 | return; |
41 | } | |
42 | ||
43 | if (val != cpu->gr[reg].u64) | |
44 | TRACE_REGISTER (cpu, | |
e101a78b | 45 | "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64, |
2e8cf49e NC |
46 | reg, cpu->gr[reg].u64, val); |
47 | ||
48 | cpu->gr[reg].u64 = val; | |
49 | } | |
50 | ||
51 | void | |
52 | aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val) | |
53 | { | |
54 | if (reg == R31 && ! r31_is_sp) | |
55 | { | |
e101a78b | 56 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); |
2e8cf49e NC |
57 | return; |
58 | } | |
59 | ||
60 | if (val != cpu->gr[reg].s64) | |
61 | TRACE_REGISTER (cpu, | |
e101a78b | 62 | "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64, |
2e8cf49e NC |
63 | reg, cpu->gr[reg].s64, val); |
64 | ||
65 | cpu->gr[reg].s64 = val; | |
66 | } | |
67 | ||
68 | uint64_t | |
69 | aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
70 | { | |
71 | return cpu->gr[reg_num(reg)].u64; | |
72 | } | |
73 | ||
74 | int64_t | |
75 | aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
76 | { | |
77 | return cpu->gr[reg_num(reg)].s64; | |
78 | } | |
79 | ||
80 | uint32_t | |
81 | aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
82 | { | |
83 | return cpu->gr[reg_num(reg)].u32; | |
84 | } | |
85 | ||
86 | int32_t | |
87 | aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
88 | { | |
89 | return cpu->gr[reg_num(reg)].s32; | |
90 | } | |
91 | ||
7517e550 NC |
92 | void |
93 | aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val) | |
94 | { | |
95 | if (reg == R31 && ! r31_is_sp) | |
96 | { | |
97 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); | |
98 | return; | |
99 | } | |
100 | ||
101 | if (val != cpu->gr[reg].s32) | |
102 | TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x", | |
103 | reg, cpu->gr[reg].s32, val); | |
104 | ||
105 | /* The ARM ARM states that (C1.2.4): | |
106 | When the data size is 32 bits, the lower 32 bits of the | |
107 | register are used and the upper 32 bits are ignored on | |
108 | a read and cleared to zero on a write. | |
109 | We simulate this by first clearing the whole 64-bits and | |
110 | then writing to the 32-bit value in the GRegister union. */ | |
111 | cpu->gr[reg].s64 = 0; | |
112 | cpu->gr[reg].s32 = val; | |
113 | } | |
114 | ||
115 | void | |
116 | aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val) | |
117 | { | |
118 | if (reg == R31 && ! r31_is_sp) | |
119 | { | |
120 | TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!"); | |
121 | return; | |
122 | } | |
123 | ||
124 | if (val != cpu->gr[reg].u32) | |
125 | TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x", | |
126 | reg, cpu->gr[reg].u32, val); | |
127 | ||
128 | cpu->gr[reg].u64 = 0; | |
129 | cpu->gr[reg].u32 = val; | |
130 | } | |
131 | ||
2e8cf49e NC |
132 | uint32_t |
133 | aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
134 | { | |
135 | return cpu->gr[reg_num(reg)].u16; | |
136 | } | |
137 | ||
138 | int32_t | |
139 | aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
140 | { | |
141 | return cpu->gr[reg_num(reg)].s16; | |
142 | } | |
143 | ||
144 | uint32_t | |
145 | aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
146 | { | |
147 | return cpu->gr[reg_num(reg)].u8; | |
148 | } | |
149 | ||
150 | int32_t | |
151 | aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp) | |
152 | { | |
153 | return cpu->gr[reg_num(reg)].s8; | |
154 | } | |
155 | ||
156 | uint64_t | |
157 | aarch64_get_PC (sim_cpu *cpu) | |
158 | { | |
159 | return cpu->pc; | |
160 | } | |
161 | ||
162 | uint64_t | |
163 | aarch64_get_next_PC (sim_cpu *cpu) | |
164 | { | |
165 | return cpu->nextpc; | |
166 | } | |
167 | ||
168 | void | |
169 | aarch64_set_next_PC (sim_cpu *cpu, uint64_t next) | |
170 | { | |
171 | if (next != cpu->nextpc + 4) | |
172 | TRACE_REGISTER (cpu, | |
e101a78b | 173 | "NextPC changes from %16" PRIx64 " to %16" PRIx64, |
2e8cf49e NC |
174 | cpu->nextpc, next); |
175 | ||
176 | cpu->nextpc = next; | |
177 | } | |
178 | ||
179 | void | |
180 | aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset) | |
181 | { | |
182 | if (cpu->pc + offset != cpu->nextpc + 4) | |
183 | TRACE_REGISTER (cpu, | |
e101a78b | 184 | "NextPC changes from %16" PRIx64 " to %16" PRIx64, |
2e8cf49e NC |
185 | cpu->nextpc, cpu->pc + offset); |
186 | ||
187 | cpu->nextpc = cpu->pc + offset; | |
188 | } | |
189 | ||
190 | /* Install nextpc as current pc. */ | |
191 | void | |
192 | aarch64_update_PC (sim_cpu *cpu) | |
193 | { | |
194 | cpu->pc = cpu->nextpc; | |
195 | /* Rezero the register we hand out when asked for ZR just in case it | |
196 | was used as the destination for a write by the previous | |
197 | instruction. */ | |
198 | cpu->gr[32].u64 = 0UL; | |
199 | } | |
200 | ||
201 | /* This instruction can be used to save the next PC to LR | |
202 | just before installing a branch PC. */ | |
203 | void | |
204 | aarch64_save_LR (sim_cpu *cpu) | |
205 | { | |
206 | if (cpu->gr[LR].u64 != cpu->nextpc) | |
207 | TRACE_REGISTER (cpu, | |
e101a78b | 208 | "LR changes from %16" PRIx64 " to %16" PRIx64, |
2e8cf49e NC |
209 | cpu->gr[LR].u64, cpu->nextpc); |
210 | ||
211 | cpu->gr[LR].u64 = cpu->nextpc; | |
212 | } | |
213 | ||
214 | static const char * | |
215 | decode_cpsr (FlagMask flags) | |
216 | { | |
217 | switch (flags & CPSR_ALL_FLAGS) | |
218 | { | |
219 | default: | |
220 | case 0: return "----"; | |
221 | case 1: return "---V"; | |
222 | case 2: return "--C-"; | |
223 | case 3: return "--CV"; | |
224 | case 4: return "-Z--"; | |
225 | case 5: return "-Z-V"; | |
226 | case 6: return "-ZC-"; | |
227 | case 7: return "-ZCV"; | |
228 | case 8: return "N---"; | |
229 | case 9: return "N--V"; | |
230 | case 10: return "N-C-"; | |
231 | case 11: return "N-CV"; | |
232 | case 12: return "NZ--"; | |
233 | case 13: return "NZ-V"; | |
234 | case 14: return "NZC-"; | |
235 | case 15: return "NZCV"; | |
236 | } | |
237 | } | |
238 | ||
239 | /* Retrieve the CPSR register as an int. */ | |
240 | uint32_t | |
241 | aarch64_get_CPSR (sim_cpu *cpu) | |
242 | { | |
243 | return cpu->CPSR; | |
244 | } | |
245 | ||
246 | /* Set the CPSR register as an int. */ | |
247 | void | |
248 | aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags) | |
249 | { | |
250 | if (TRACE_REGISTER_P (cpu)) | |
251 | { | |
252 | if (cpu->CPSR != new_flags) | |
253 | TRACE_REGISTER (cpu, | |
e101a78b | 254 | "CPSR changes from %s to %s", |
2e8cf49e NC |
255 | decode_cpsr (cpu->CPSR), decode_cpsr (new_flags)); |
256 | else | |
257 | TRACE_REGISTER (cpu, | |
e101a78b | 258 | "CPSR stays at %s", decode_cpsr (cpu->CPSR)); |
2e8cf49e NC |
259 | } |
260 | ||
261 | cpu->CPSR = new_flags & CPSR_ALL_FLAGS; | |
262 | } | |
263 | ||
264 | /* Read a specific subset of the CPSR as a bit pattern. */ | |
265 | uint32_t | |
266 | aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask) | |
267 | { | |
268 | return cpu->CPSR & mask; | |
269 | } | |
270 | ||
271 | /* Assign a specific subset of the CPSR as a bit pattern. */ | |
272 | void | |
273 | aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value) | |
274 | { | |
275 | uint32_t old_flags = cpu->CPSR; | |
276 | ||
277 | mask &= CPSR_ALL_FLAGS; | |
278 | cpu->CPSR &= ~ mask; | |
279 | cpu->CPSR |= (value & mask); | |
280 | ||
281 | if (old_flags != cpu->CPSR) | |
282 | TRACE_REGISTER (cpu, | |
e101a78b | 283 | "CPSR changes from %s to %s", |
2e8cf49e NC |
284 | decode_cpsr (old_flags), decode_cpsr (cpu->CPSR)); |
285 | } | |
286 | ||
287 | /* Test the value of a single CPSR returned as non-zero or zero. */ | |
288 | uint32_t | |
289 | aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
290 | { | |
291 | return cpu->CPSR & bit; | |
292 | } | |
293 | ||
294 | /* Set a single flag in the CPSR. */ | |
295 | void | |
296 | aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
297 | { | |
298 | uint32_t old_flags = cpu->CPSR; | |
299 | ||
300 | cpu->CPSR |= (bit & CPSR_ALL_FLAGS); | |
301 | ||
302 | if (old_flags != cpu->CPSR) | |
303 | TRACE_REGISTER (cpu, | |
e101a78b | 304 | "CPSR changes from %s to %s", |
2e8cf49e NC |
305 | decode_cpsr (old_flags), decode_cpsr (cpu->CPSR)); |
306 | } | |
307 | ||
308 | /* Clear a single flag in the CPSR. */ | |
309 | void | |
310 | aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit) | |
311 | { | |
312 | uint32_t old_flags = cpu->CPSR; | |
313 | ||
314 | cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS); | |
315 | ||
316 | if (old_flags != cpu->CPSR) | |
317 | TRACE_REGISTER (cpu, | |
e101a78b | 318 | "CPSR changes from %s to %s", |
2e8cf49e NC |
319 | decode_cpsr (old_flags), decode_cpsr (cpu->CPSR)); |
320 | } | |
321 | ||
5ab6d79e NC |
322 | float |
323 | aarch64_get_FP_half (sim_cpu *cpu, VReg reg) | |
324 | { | |
325 | union | |
326 | { | |
327 | uint16_t h[2]; | |
328 | float f; | |
329 | } u; | |
330 | ||
7517e550 NC |
331 | u.h[0] = 0; |
332 | u.h[1] = cpu->fr[reg].h[0]; | |
5ab6d79e NC |
333 | return u.f; |
334 | } | |
335 | ||
336 | ||
2e8cf49e NC |
337 | float |
338 | aarch64_get_FP_float (sim_cpu *cpu, VReg reg) | |
339 | { | |
340 | return cpu->fr[reg].s; | |
341 | } | |
342 | ||
343 | double | |
344 | aarch64_get_FP_double (sim_cpu *cpu, VReg reg) | |
345 | { | |
346 | return cpu->fr[reg].d; | |
347 | } | |
348 | ||
349 | void | |
350 | aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a) | |
351 | { | |
352 | a->v[0] = cpu->fr[reg].v[0]; | |
353 | a->v[1] = cpu->fr[reg].v[1]; | |
354 | } | |
355 | ||
5ab6d79e NC |
356 | void |
357 | aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val) | |
358 | { | |
359 | union | |
360 | { | |
361 | uint16_t h[2]; | |
362 | float f; | |
363 | } u; | |
364 | ||
365 | u.f = val; | |
7517e550 | 366 | cpu->fr[reg].h[0] = u.h[1]; |
5ab6d79e NC |
367 | cpu->fr[reg].h[1] = 0; |
368 | } | |
369 | ||
370 | ||
2e8cf49e NC |
371 | void |
372 | aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) | |
373 | { | |
c0386d4d JW |
374 | if (val != cpu->fr[reg].s |
375 | /* Handle +/- zero. */ | |
376 | || signbit (val) != signbit (cpu->fr[reg].s)) | |
e101a78b NC |
377 | { |
378 | FRegister v; | |
379 | ||
380 | v.s = val; | |
381 | TRACE_REGISTER (cpu, | |
f1ca3215 | 382 | "FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]", |
e101a78b NC |
383 | reg, cpu->fr[reg].s, val, v.v[0]); |
384 | } | |
2e8cf49e NC |
385 | |
386 | cpu->fr[reg].s = val; | |
387 | } | |
388 | ||
389 | void | |
390 | aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val) | |
391 | { | |
c0386d4d JW |
392 | if (val != cpu->fr[reg].d |
393 | /* Handle +/- zero. */ | |
394 | || signbit (val) != signbit (cpu->fr[reg].d)) | |
e101a78b NC |
395 | { |
396 | FRegister v; | |
2e8cf49e | 397 | |
e101a78b NC |
398 | v.d = val; |
399 | TRACE_REGISTER (cpu, | |
f1ca3215 | 400 | "FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]", |
e101a78b NC |
401 | reg, cpu->fr[reg].d, val, v.v[0]); |
402 | } | |
2e8cf49e NC |
403 | cpu->fr[reg].d = val; |
404 | } | |
405 | ||
406 | void | |
407 | aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a) | |
408 | { | |
409 | if (cpu->fr[reg].v[0] != a.v[0] | |
410 | || cpu->fr[reg].v[1] != a.v[1]) | |
411 | TRACE_REGISTER (cpu, | |
f1ca3215 MF |
412 | "FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0" |
413 | PRIx64 " %0" PRIx64 "] ", | |
2e8cf49e NC |
414 | reg, |
415 | cpu->fr[reg].v[0], cpu->fr[reg].v[1], | |
416 | a.v[0], a.v[1]); | |
417 | ||
418 | cpu->fr[reg].v[0] = a.v[0]; | |
419 | cpu->fr[reg].v[1] = a.v[1]; | |
420 | } | |
421 | ||
e101a78b NC |
422 | #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \ |
423 | do \ | |
424 | { \ | |
87bba7a5 | 425 | if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \ |
e101a78b NC |
426 | { \ |
427 | TRACE_REGISTER (cpu, \ | |
428 | "Internal SIM error: invalid element number: %d ",\ | |
429 | ELEMENT); \ | |
430 | sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \ | |
431 | sim_stopped, SIM_SIGBUS); \ | |
432 | } \ | |
433 | return cpu->fr[REG].FIELD [ELEMENT]; \ | |
434 | } \ | |
435 | while (0) | |
436 | ||
2e8cf49e NC |
437 | uint64_t |
438 | aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element) | |
439 | { | |
e101a78b | 440 | GET_VEC_ELEMENT (reg, element, v); |
2e8cf49e NC |
441 | } |
442 | ||
443 | uint32_t | |
e101a78b | 444 | aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element) |
2e8cf49e | 445 | { |
e101a78b | 446 | GET_VEC_ELEMENT (reg, element, w); |
2e8cf49e NC |
447 | } |
448 | ||
449 | uint16_t | |
e101a78b | 450 | aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element) |
2e8cf49e | 451 | { |
e101a78b | 452 | GET_VEC_ELEMENT (reg, element, h); |
2e8cf49e NC |
453 | } |
454 | ||
455 | uint8_t | |
e101a78b | 456 | aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element) |
2e8cf49e | 457 | { |
e101a78b | 458 | GET_VEC_ELEMENT (reg, element, b); |
2e8cf49e NC |
459 | } |
460 | ||
e101a78b NC |
461 | int64_t |
462 | aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 463 | { |
e101a78b | 464 | GET_VEC_ELEMENT (reg, element, V); |
2e8cf49e NC |
465 | } |
466 | ||
e101a78b NC |
467 | int32_t |
468 | aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 469 | { |
e101a78b | 470 | GET_VEC_ELEMENT (reg, element, W); |
2e8cf49e NC |
471 | } |
472 | ||
e101a78b NC |
473 | int16_t |
474 | aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 475 | { |
e101a78b | 476 | GET_VEC_ELEMENT (reg, element, H); |
2e8cf49e NC |
477 | } |
478 | ||
e101a78b NC |
479 | int8_t |
480 | aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 481 | { |
e101a78b | 482 | GET_VEC_ELEMENT (reg, element, B); |
2e8cf49e NC |
483 | } |
484 | ||
e101a78b NC |
485 | float |
486 | aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element) | |
2e8cf49e | 487 | { |
e101a78b | 488 | GET_VEC_ELEMENT (reg, element, S); |
2e8cf49e NC |
489 | } |
490 | ||
e101a78b NC |
491 | double |
492 | aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element) | |
493 | { | |
494 | GET_VEC_ELEMENT (reg, element, D); | |
495 | } | |
496 | ||
497 | ||
7517e550 NC |
498 | #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \ |
499 | do \ | |
500 | { \ | |
4c0ca98e | 501 | if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \ |
e101a78b | 502 | { \ |
7517e550 | 503 | TRACE_REGISTER (cpu, \ |
e101a78b NC |
504 | "Internal SIM error: invalid element number: %d ",\ |
505 | ELEMENT); \ | |
506 | sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \ | |
507 | sim_stopped, SIM_SIGBUS); \ | |
508 | } \ | |
509 | if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \ | |
510 | TRACE_REGISTER (cpu, \ | |
511 | "VR[%2d]." #FIELD " [%d] changes from " PRINTER \ | |
512 | " to " PRINTER , REG, \ | |
513 | ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \ | |
7517e550 NC |
514 | \ |
515 | cpu->fr[REG].FIELD [ELEMENT] = VAL; \ | |
516 | } \ | |
e101a78b | 517 | while (0) |
2e8cf49e NC |
518 | |
519 | void | |
ef0d8ffc | 520 | aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val) |
2e8cf49e | 521 | { |
f1ca3215 | 522 | SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64); |
2e8cf49e NC |
523 | } |
524 | ||
e101a78b | 525 | void |
ef0d8ffc | 526 | aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val) |
2e8cf49e | 527 | { |
e101a78b | 528 | SET_VEC_ELEMENT (reg, element, val, w, "%8x"); |
2e8cf49e NC |
529 | } |
530 | ||
e101a78b | 531 | void |
ef0d8ffc | 532 | aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val) |
2e8cf49e | 533 | { |
e101a78b | 534 | SET_VEC_ELEMENT (reg, element, val, h, "%4x"); |
2e8cf49e NC |
535 | } |
536 | ||
e101a78b | 537 | void |
ef0d8ffc | 538 | aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val) |
2e8cf49e | 539 | { |
e101a78b | 540 | SET_VEC_ELEMENT (reg, element, val, b, "%x"); |
2e8cf49e NC |
541 | } |
542 | ||
543 | void | |
e101a78b | 544 | aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val) |
2e8cf49e | 545 | { |
f1ca3215 | 546 | SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64); |
2e8cf49e NC |
547 | } |
548 | ||
549 | void | |
e101a78b | 550 | aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val) |
2e8cf49e | 551 | { |
e101a78b | 552 | SET_VEC_ELEMENT (reg, element, val, W, "%8x"); |
2e8cf49e NC |
553 | } |
554 | ||
e101a78b NC |
555 | void |
556 | aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val) | |
2e8cf49e | 557 | { |
e101a78b | 558 | SET_VEC_ELEMENT (reg, element, val, H, "%4x"); |
2e8cf49e NC |
559 | } |
560 | ||
e101a78b NC |
561 | void |
562 | aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val) | |
2e8cf49e | 563 | { |
e101a78b | 564 | SET_VEC_ELEMENT (reg, element, val, B, "%x"); |
2e8cf49e NC |
565 | } |
566 | ||
e101a78b NC |
567 | void |
568 | aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val) | |
2e8cf49e | 569 | { |
e101a78b | 570 | SET_VEC_ELEMENT (reg, element, val, S, "%f"); |
2e8cf49e NC |
571 | } |
572 | ||
e101a78b NC |
573 | void |
574 | aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val) | |
2e8cf49e | 575 | { |
e101a78b | 576 | SET_VEC_ELEMENT (reg, element, val, D, "%f"); |
2e8cf49e NC |
577 | } |
578 | ||
579 | void | |
e101a78b | 580 | aarch64_set_FPSR (sim_cpu *cpu, uint32_t value) |
2e8cf49e | 581 | { |
e101a78b | 582 | if (cpu->FPSR != value) |
2e8cf49e | 583 | TRACE_REGISTER (cpu, |
e101a78b | 584 | "FPSR changes from %x to %x", cpu->FPSR, value); |
2e8cf49e | 585 | |
e101a78b | 586 | cpu->FPSR = value & FPSR_ALL_FPSRS; |
2e8cf49e NC |
587 | } |
588 | ||
e101a78b NC |
589 | uint32_t |
590 | aarch64_get_FPSR (sim_cpu *cpu) | |
2e8cf49e | 591 | { |
e101a78b | 592 | return cpu->FPSR; |
2e8cf49e NC |
593 | } |
594 | ||
595 | void | |
e101a78b | 596 | aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value) |
2e8cf49e | 597 | { |
e101a78b NC |
598 | uint32_t old_FPSR = cpu->FPSR; |
599 | ||
600 | mask &= FPSR_ALL_FPSRS; | |
601 | cpu->FPSR &= ~mask; | |
602 | cpu->FPSR |= (value & mask); | |
2e8cf49e | 603 | |
e101a78b NC |
604 | if (cpu->FPSR != old_FPSR) |
605 | TRACE_REGISTER (cpu, | |
606 | "FPSR changes from %x to %x", old_FPSR, cpu->FPSR); | |
2e8cf49e NC |
607 | } |
608 | ||
e101a78b NC |
609 | uint32_t |
610 | aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask) | |
2e8cf49e | 611 | { |
e101a78b NC |
612 | mask &= FPSR_ALL_FPSRS; |
613 | return cpu->FPSR & mask; | |
614 | } | |
2e8cf49e | 615 | |
e101a78b NC |
616 | int |
617 | aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag) | |
618 | { | |
619 | return cpu->FPSR & flag; | |
2e8cf49e | 620 | } |
5ab6d79e NC |
621 | |
622 | uint64_t | |
ef0d8ffc | 623 | aarch64_get_thread_id (sim_cpu *cpu) |
5ab6d79e NC |
624 | { |
625 | return cpu->tpidr; | |
626 | } | |
627 | ||
628 | uint32_t | |
ef0d8ffc | 629 | aarch64_get_FPCR (sim_cpu *cpu) |
5ab6d79e NC |
630 | { |
631 | return cpu->FPCR; | |
632 | } | |
633 | ||
634 | void | |
ef0d8ffc | 635 | aarch64_set_FPCR (sim_cpu *cpu, uint32_t val) |
5ab6d79e NC |
636 | { |
637 | if (cpu->FPCR != val) | |
638 | TRACE_REGISTER (cpu, | |
639 | "FPCR changes from %x to %x", cpu->FPCR, val); | |
640 | cpu->FPCR = val; | |
641 | } |