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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
4ce44c66
JM		 11999-11-11 Andrew Haley <aph@cygnus.com>
2
3 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
4 instructions.
5
cff3e48b
JM		 6Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
7
8 * mips.igen (MULT): Correct previous mis-applied patch.
9
d4f3574e
SS		 10Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
11
12 * mips.igen (delayslot32): Handle sequence like
13 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
14 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
15 (MULT): Actually pass the third register...
16
171999-09-03 Mark Salter <msalter@cygnus.com>
18
19 * interp.c (sim_open): Added more memory aliases for additional
20 hardware being touched by cygmon on jmr3904 board.
21
22Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
23
24 * configure: Regenerated to track ../common/aclocal.m4 changes.
25
a0b3c4fd
JM		 26Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
27
28 * interp.c (sim_store_register): Handle case where client - GDB -
29 specifies that a 4 byte register is 8 bytes in size.
30 (sim_fetch_register): Ditto.
31
adf40b2e
JM		 321999-07-14 Frank Ch. Eigler <fche@cygnus.com>
33
34 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
35 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
36 (idt_monitor_base): Base address for IDT monitor traps.
37 (pmon_monitor_base): Ditto for PMON.
38 (lsipmon_monitor_base): Ditto for LSI PMON.
39 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
40 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
41 (sim_firmware_command): New function.
42 (mips_option_handler): Call it for OPTION_FIRMWARE.
43 (sim_open): Allocate memory for idt_monitor region. If "--board"
44 option was given, add no monitor by default. Add BREAK hooks only if
45 monitors are also there.
46
43e526b9
JM		 47Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
48
49 * interp.c (sim_monitor): Flush output before reading input.
50
51Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
52
53 * tconfig.in (SIM_HANDLES_LMA): Always define.
54
55Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
56
57 From Mark Salter <msalter@cygnus.com>:
58 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
59 (sim_open): Add setup for BSP board.
60
9846de1b
JM		 61Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
62
63 * mips.igen (MULT, MULTU): Add syntax for two operand version.
64 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
65 them as unimplemented.
66
cd0fc7c3
SS		 671999-05-08 Felix Lee <flee@cygnus.com>
68
69 * configure: Regenerated to track ../common/aclocal.m4 changes.
70
7a292a7a
SS		 711999-04-21 Frank Ch. Eigler <fche@cygnus.com>
72
73 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
74
75Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
76
77 * configure.in: Any mips64vr5*-*-* target should have
78 -DTARGET_ENABLE_FR=1.
79 (default_endian): Any mips64vr*el-*-* target should default to
80 LITTLE_ENDIAN.
81 * configure: Re-generate.
82
831999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
84
85 * mips.igen (ldl): Extend from _16_, not 32.
86
87Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
88
89 * interp.c (sim_store_register): Force registers written to by GDB
90 into an un-interpreted state.
91
c906108c
SS		 921999-02-05 Frank Ch. Eigler <fche@cygnus.com>
93
94 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
95 CPU, start periodic background I/O polls.
96 (tx3904sio_poll): New function: periodic I/O poller.
97
981998-12-30 Frank Ch. Eigler <fche@cygnus.com>
99
100 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
101
102Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
103
104 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
105 case statement.
106
1071998-12-29 Frank Ch. Eigler <fche@cygnus.com>
108
109 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
110 (load_word): Call SIM_CORE_SIGNAL hook on error.
111 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
112 starting. For exception dispatching, pass PC instead of NULL_CIA.
113 (decode_coproc): Use COP0_BADVADDR to store faulting address.
114 * sim-main.h (COP0_BADVADDR): Define.
115 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
116 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
117 (_sim_cpu): Add exc_* fields to store register value snapshots.
118 * mips.igen (*): Replace memory-related SignalException* calls
119 with references to SIM_CORE_SIGNAL hook.
120
121 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
122 fix.
123 * sim-main.c (*): Minor warning cleanups.
124
1251998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
126
127 * m16.igen (DADDIU5): Correct type-o.
128
129Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
130
131 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
132 variables.
133
134Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
135
136 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
137 to include path.
138 (interp.o): Add dependency on itable.h
139 (oengine.c, gencode): Delete remaining references.
140 (BUILT_SRC_FROM_GEN): Clean up.
141
1421998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
143
144 * vr4run.c: New.
145 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
146 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
147 tmp-run-hack) : New.
148 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
149 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
150 Drop the "64" qualifier to get the HACK generator working.
151 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
152 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
153 qualifier to get the hack generator working.
154 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
155 (DSLL): Use do_dsll.
156 (DSLLV): Use do_dsllv.
157 (DSRA): Use do_dsra.
158 (DSRL): Use do_dsrl.
159 (DSRLV): Use do_dsrlv.
160 (BC1): Move *vr4100 to get the HACK generator working.
161 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
162 get the HACK generator working.
163 (MACC) Rename to get the HACK generator working.
164 (DMACC,MACCS,DMACCS): Add the 64.
165
1661998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
167
168 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
169 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
170
1711998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
172
173 * mips/interp.c (DEBUG): Cleanups.
174
1751998-12-10 Frank Ch. Eigler <fche@cygnus.com>
176
177 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
178 (tx3904sio_tickle): fflush after a stdout character output.
179
1801998-12-03 Frank Ch. Eigler <fche@cygnus.com>
181
182 * interp.c (sim_close): Uninstall modules.
183
184Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
185
186 * sim-main.h, interp.c (sim_monitor): Change to global
187 function.
188
189Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
190
191 * configure.in (vr4100): Only include vr4100 instructions in
192 simulator.
193 * configure: Re-generate.
194 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
195
196Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
197
198 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
199 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
200 true alternative.
201
202 * configure.in (sim_default_gen, sim_use_gen): Replace with
203 sim_gen.
204 (--enable-sim-igen): Delete config option. Always using IGEN.
205 * configure: Re-generate.
206
207 * Makefile.in (gencode): Kill, kill, kill.
208 * gencode.c: Ditto.
209
210Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
211
212 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
213 bit mips16 igen simulator.
214 * configure: Re-generate.
215
216 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
217 as part of vr4100 ISA.
218 * vr.igen: Mark all instructions as 64 bit only.
219
220Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
221
222 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
223 Pacify GCC.
224
225Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
226
227 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
228 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
229 * configure: Re-generate.
230
231 * m16.igen (BREAK): Define breakpoint instruction.
232 (JALX32): Mark instruction as mips16 and not r3900.
233 * mips.igen (C.cond.fmt): Fix typo in instruction format.
234
235 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
236
237Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
238
239 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
240 insn as a debug breakpoint.
241
242 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
243 pending.slot_size.
244 (PENDING_SCHED): Clean up trace statement.
245 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
246 (PENDING_FILL): Delay write by only one cycle.
247 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
248
249 * sim-main.c (pending_tick): Clean up trace statements. Add trace
250 of pending writes.
251 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
252 32 & 64.
253 (pending_tick): Move incrementing of index to FOR statement.
254 (pending_tick): Only update PENDING_OUT after a write has occured.
255
256 * configure.in: Add explicit mips-lsi-* target. Use gencode to
257 build simulator.
258 * configure: Re-generate.
259
260 * interp.c (sim_engine_run OLD): Delete explicit call to
261 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
262
263Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
264
265 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
266 interrupt level number to match changed SignalExceptionInterrupt
267 macro.
268
269Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
270
271 * interp.c: #include "itable.h" if WITH_IGEN.
272 (get_insn_name): New function.
273 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
274 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
275
276Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
277
278 * configure: Rebuilt to inhale new common/aclocal.m4.
279
280Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
281
282 * dv-tx3904sio.c: Include sim-assert.h.
283
284Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
285
286 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
287 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
288 Reorganize target-specific sim-hardware checks.
289 * configure: rebuilt.
290 * interp.c (sim_open): For tx39 target boards, set
291 OPERATING_ENVIRONMENT, add tx3904sio devices.
292 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
293 ROM executables. Install dv-sockser into sim-modules list.
294
295 * dv-tx3904irc.c: Compiler warning clean-up.
296 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
297 frequent hw-trace messages.
298
299Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
300
301 * vr.igen (MulAcc): Identify as a vr4100 specific function.
302
303Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
304
305 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
306
307 * vr.igen: New file.
308 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
309 * mips.igen: Define vr4100 model. Include vr.igen.
310Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
311
312 * mips.igen (check_mf_hilo): Correct check.
313
314Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
315
316 * sim-main.h (interrupt_event): Add prototype.
317
318 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
319 register_ptr, register_value.
320 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
321
322 * sim-main.h (tracefh): Make extern.
323
324Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
325
326 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
327 Reduce unnecessarily high timer event frequency.
328 * dv-tx3904cpu.c: Ditto for interrupt event.
329
330Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
331
332 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
333 to allay warnings.
334 (interrupt_event): Made non-static.
335
336 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
337 interchange of configuration values for external vs. internal
338 clock dividers.
339
340Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
341
342 * mips.igen (BREAK): Moved code to here for
343 simulator-reserved break instructions.
344 * gencode.c (build_instruction): Ditto.
345 * interp.c (signal_exception): Code moved from here. Non-
346 reserved instructions now use exception vector, rather
347 than halting sim.
348 * sim-main.h: Moved magic constants to here.
349
350Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
351
352 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
353 register upon non-zero interrupt event level, clear upon zero
354 event value.
355 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
356 by passing zero event value.
357 (*_io_{read,write}_buffer): Endianness fixes.
358 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
359 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
360
361 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
362 serial I/O and timer module at base address 0xFFFF0000.
363
364Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
365
366 * mips.igen (SWC1) : Correct the handling of ReverseEndian
367 and BigEndianCPU.
368
369Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
370
371 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
372 parts.
373 * configure: Update.
374
375Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
376
377 * dv-tx3904tmr.c: New file - implements tx3904 timer.
378 * dv-tx3904{irc,cpu}.c: Mild reformatting.
379 * configure.in: Include tx3904tmr in hw_device list.
380 * configure: Rebuilt.
381 * interp.c (sim_open): Instantiate three timer instances.
382 Fix address typo of tx3904irc instance.
383
384Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
385
386 * interp.c (signal_exception): SystemCall exception now uses
387 the exception vector.
388
389Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
390
391 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
392 to allay warnings.
393
394Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
395
396 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
397
398Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
399
400 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
401
402 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
403 sim-main.h. Declare a struct hw_descriptor instead of struct
404 hw_device_descriptor.
405
406Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
407
408 * mips.igen (do_store_left, do_load_left): Compute nr of left and
409 right bits and then re-align left hand bytes to correct byte
410 lanes. Fix incorrect computation in do_store_left when loading
411 bytes from second word.
412
413Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
414
415 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
416 * interp.c (sim_open): Only create a device tree when HW is
417 enabled.
418
419 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
420 * interp.c (signal_exception): Ditto.
421
422Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
423
424 * gencode.c: Mark BEGEZALL as LIKELY.
425
426Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
427
428 * sim-main.h (ALU32_END): Sign extend 32 bit results.
429 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
430
431Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
432
433 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
434 modules. Recognize TX39 target with "mips*tx39" pattern.
435 * configure: Rebuilt.
436 * sim-main.h (*): Added many macros defining bits in
437 TX39 control registers.
438 (SignalInterrupt): Send actual PC instead of NULL.
439 (SignalNMIReset): New exception type.
440 * interp.c (board): New variable for future use to identify
441 a particular board being simulated.
442 (mips_option_handler,mips_options): Added "--board" option.
443 (interrupt_event): Send actual PC.
444 (sim_open): Make memory layout conditional on board setting.
445 (signal_exception): Initial implementation of hardware interrupt
446 handling. Accept another break instruction variant for simulator
447 exit.
448 (decode_coproc): Implement RFE instruction for TX39.
449 (mips.igen): Decode RFE instruction as such.
450 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
451 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
452 bbegin to implement memory map.
453 * dv-tx3904cpu.c: New file.
454 * dv-tx3904irc.c: New file.
455
456Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
457
458 * mips.igen (check_mt_hilo): Create a separate r3900 version.
459
460Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
461
462 * tx.igen (madd,maddu): Replace calls to check_op_hilo
463 with calls to check_div_hilo.
464
465Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
466
467 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
468 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
469 Add special r3900 version of do_mult_hilo.
470 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
471 with calls to check_mult_hilo.
472 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
473 with calls to check_div_hilo.
474
475Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
476
477 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
478 Document a replacement.
479
480Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
481
482 * interp.c (sim_monitor): Make mon_printf work.
483
484Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
485
486 * sim-main.h (INSN_NAME): New arg `cpu'.
487
488Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
489
490 * configure: Regenerated to track ../common/aclocal.m4 changes.
491
492Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
493
494 * configure: Regenerated to track ../common/aclocal.m4 changes.
495 * config.in: Ditto.
496
497Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
498
499 * acconfig.h: New file.
500 * configure.in: Reverted change of Apr 24; use sinclude again.
501
502Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
503
504 * configure: Regenerated to track ../common/aclocal.m4 changes.
505 * config.in: Ditto.
506
507Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
508
509 * configure.in: Don't call sinclude.
510
511Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
512
513 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
514
515Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
516
517 * mips.igen (ERET): Implement.
518
519 * interp.c (decode_coproc): Return sign-extended EPC.
520
521 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
522
523 * interp.c (signal_exception): Do not ignore Trap.
524 (signal_exception): On TRAP, restart at exception address.
525 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
526 (signal_exception): Update.
527 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
528 so that TRAP instructions are caught.
529
530Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
531
532 * sim-main.h (struct hilo_access, struct hilo_history): Define,
533 contains HI/LO access history.
534 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
535 (HIACCESS, LOACCESS): Delete, replace with
536 (HIHISTORY, LOHISTORY): New macros.
537 (CHECKHILO): Delete all, moved to mips.igen
538
539 * gencode.c (build_instruction): Do not generate checks for
540 correct HI/LO register usage.
541
542 * interp.c (old_engine_run): Delete checks for correct HI/LO
543 register usage.
544
545 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
546 check_mf_cycles): New functions.
547 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
548 do_divu, domultx, do_mult, do_multu): Use.
549
550 * tx.igen ("madd", "maddu"): Use.
551
552Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
553
554 * mips.igen (DSRAV): Use function do_dsrav.
555 (SRAV): Use new function do_srav.
556
557 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
558 (B): Sign extend 11 bit immediate.
559 (EXT-B*): Shift 16 bit immediate left by 1.
560 (ADDIU*): Don't sign extend immediate value.
561
562Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
563
564 * m16run.c (sim_engine_run): Restore CIA after handling an event.
565
566 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
567 functions.
568
569 * mips.igen (delayslot32, nullify_next_insn): New functions.
570 (m16.igen): Always include.
571 (do_*): Add more tracing.
572
573 * m16.igen (delayslot16): Add NIA argument, could be called by a
574 32 bit MIPS16 instruction.
575
576 * interp.c (ifetch16): Move function from here.
577 * sim-main.c (ifetch16): To here.
578
579 * sim-main.c (ifetch16, ifetch32): Update to match current
580 implementations of LH, LW.
581 (signal_exception): Don't print out incorrect hex value of illegal
582 instruction.
583
584Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
585
586 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
587 instruction.
588
589 * m16.igen: Implement MIPS16 instructions.
590
591 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
592 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
593 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
594 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
595 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
596 bodies of corresponding code from 32 bit insn to these. Also used
597 by MIPS16 versions of functions.
598
599 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
600 (IMEM16): Drop NR argument from macro.
601
602Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
603
604 * Makefile.in (SIM_OBJS): Add sim-main.o.
605
606 * sim-main.h (address_translation, load_memory, store_memory,
607 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
608 as INLINE_SIM_MAIN.
609 (pr_addr, pr_uword64): Declare.
610 (sim-main.c): Include when H_REVEALS_MODULE_P.
611
612 * interp.c (address_translation, load_memory, store_memory,
613 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
614 from here.
615 * sim-main.c: To here. Fix compilation problems.
616
617 * configure.in: Enable inlining.
618 * configure: Re-config.
619
620Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
621
622 * configure: Regenerated to track ../common/aclocal.m4 changes.
623
624Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
625
626 * mips.igen: Include tx.igen.
627 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
628 * tx.igen: New file, contains MADD and MADDU.
629
630 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
631 the hardwired constant `7'.
632 (store_memory): Ditto.
633 (LOADDRMASK): Move definition to sim-main.h.
634
635 mips.igen (MTC0): Enable for r3900.
636 (ADDU): Add trace.
637
638 mips.igen (do_load_byte): Delete.
639 (do_load, do_store, do_load_left, do_load_write, do_store_left,
640 do_store_right): New functions.
641 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
642
643 configure.in: Let the tx39 use igen again.
644 configure: Update.
645
646Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
647
648 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
649 not an address sized quantity. Return zero for cache sizes.
650
651Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
652
653 * mips.igen (r3900): r3900 does not support 64 bit integer
654 operations.
655
656Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
657
658 * configure.in (mipstx39*-*-*): Use gencode simulator rather
659 than igen one.
660 * configure : Rebuild.
661
662Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
663
664 * configure: Regenerated to track ../common/aclocal.m4 changes.
665
666Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
667
668 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
669
670Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
671
672 * configure: Regenerated to track ../common/aclocal.m4 changes.
673 * config.in: Regenerated to track ../common/aclocal.m4 changes.
674
675Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
676
677 * configure: Regenerated to track ../common/aclocal.m4 changes.
678
679Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
680
681 * interp.c (Max, Min): Comment out functions. Not yet used.
682
683Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
684
685 * configure: Regenerated to track ../common/aclocal.m4 changes.
686
687Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
688
689 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
690 configurable settings for stand-alone simulator.
691
692 * configure.in: Added X11 search, just in case.
693
694 * configure: Regenerated.
695
696Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
697
698 * interp.c (sim_write, sim_read, load_memory, store_memory):
699 Replace sim_core_*_map with read_map, write_map, exec_map resp.
700
701Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
702
703 * sim-main.h (GETFCC): Return an unsigned value.
704
705Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
706
707 * mips.igen (DIV): Fix check for -1 / MIN_INT.
708 (DADD): Result destination is RD not RT.
709
710Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
711
712 * sim-main.h (HIACCESS, LOACCESS): Always define.
713
714 * mdmx.igen (Maxi, Mini): Rename Max, Min.
715
716 * interp.c (sim_info): Delete.
717
718Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
719
720 * interp.c (DECLARE_OPTION_HANDLER): Use it.
721 (mips_option_handler): New argument `cpu'.
722 (sim_open): Update call to sim_add_option_table.
723
724Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
725
726 * mips.igen (CxC1): Add tracing.
727
728Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * sim-main.h (Max, Min): Declare.
731
732 * interp.c (Max, Min): New functions.
733
734 * mips.igen (BC1): Add tracing.
735
736Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
737
738 * interp.c Added memory map for stack in vr4100
739
740Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
741
742 * interp.c (load_memory): Add missing "break"'s.
743
744Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
745
746 * interp.c (sim_store_register, sim_fetch_register): Pass in
747 length parameter. Return -1.
748
749Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
750
751 * interp.c: Added hardware init hook, fixed warnings.
752
753Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
754
755 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
756
757Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
758
759 * interp.c (ifetch16): New function.
760
761 * sim-main.h (IMEM32): Rename IMEM.
762 (IMEM16_IMMED): Define.
763 (IMEM16): Define.
764 (DELAY_SLOT): Update.
765
766 * m16run.c (sim_engine_run): New file.
767
768 * m16.igen: All instructions except LB.
769 (LB): Call do_load_byte.
770 * mips.igen (do_load_byte): New function.
771 (LB): Call do_load_byte.
772
773 * mips.igen: Move spec for insn bit size and high bit from here.
774 * Makefile.in (tmp-igen, tmp-m16): To here.
775
776 * m16.dc: New file, decode mips16 instructions.
777
778 * Makefile.in (SIM_NO_ALL): Define.
779 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
780
781Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
782
783 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
784 point unit to 32 bit registers.
785 * configure: Re-generate.
786
787Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
788
789 * configure.in (sim_use_gen): Make IGEN the default simulator
790 generator for generic 32 and 64 bit mips targets.
791 * configure: Re-generate.
792
793Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
794
795 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
796 bitsize.
797
798 * interp.c (sim_fetch_register, sim_store_register): Read/write
799 FGR from correct location.
800 (sim_open): Set size of FGR's according to
801 WITH_TARGET_FLOATING_POINT_BITSIZE.
802
803 * sim-main.h (FGR): Store floating point registers in a separate
804 array.
805
806Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
807
808 * configure: Regenerated to track ../common/aclocal.m4 changes.
809
810Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
811
812 * interp.c (ColdReset): Call PENDING_INVALIDATE.
813
814 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
815
816 * interp.c (pending_tick): New function. Deliver pending writes.
817
818 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
819 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
820 it can handle mixed sized quantites and single bits.
821
822Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
823
824 * interp.c (oengine.h): Do not include when building with IGEN.
825 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
826 (sim_info): Ditto for PROCESSOR_64BIT.
827 (sim_monitor): Replace ut_reg with unsigned_word.
828 (*): Ditto for t_reg.
829 (LOADDRMASK): Define.
830 (sim_open): Remove defunct check that host FP is IEEE compliant,
831 using software to emulate floating point.
832 (value_fpr, ...): Always compile, was conditional on HASFPU.
833
834Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
835
836 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
837 size.
838
839 * interp.c (SD, CPU): Define.
840 (mips_option_handler): Set flags in each CPU.
841 (interrupt_event): Assume CPU 0 is the one being iterrupted.
842 (sim_close): Do not clear STATE, deleted anyway.
843 (sim_write, sim_read): Assume CPU zero's vm should be used for
844 data transfers.
845 (sim_create_inferior): Set the PC for all processors.
846 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
847 argument.
848 (mips16_entry): Pass correct nr of args to store_word, load_word.
849 (ColdReset): Cold reset all cpu's.
850 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
851 (sim_monitor, load_memory, store_memory, signal_exception): Use
852 `CPU' instead of STATE_CPU.
853
854
855 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
856 SD or CPU_.
857
858 * sim-main.h (signal_exception): Add sim_cpu arg.
859 (SignalException*): Pass both SD and CPU to signal_exception.
860 * interp.c (signal_exception): Update.
861
862 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
863 Ditto
864 (sync_operation, prefetch, cache_op, store_memory, load_memory,
865 address_translation): Ditto
866 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
867
868Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
869
870 * configure: Regenerated to track ../common/aclocal.m4 changes.
871
872Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
873
874 * interp.c (sim_engine_run): Add `nr_cpus' argument.
875
876 * mips.igen (model): Map processor names onto BFD name.
877
878 * sim-main.h (CPU_CIA): Delete.
879 (SET_CIA, GET_CIA): Define
880
881Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
882
883 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
884 regiser.
885
886 * configure.in (default_endian): Configure a big-endian simulator
887 by default.
888 * configure: Re-generate.
889
890Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
891
892 * configure: Regenerated to track ../common/aclocal.m4 changes.
893
894Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
895
896 * interp.c (sim_monitor): Handle Densan monitor outbyte
897 and inbyte functions.
898
8991997-12-29 Felix Lee <flee@cygnus.com>
900
901 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
902
903Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
904
905 * Makefile.in (tmp-igen): Arrange for $zero to always be
906 reset to zero after every instruction.
907
908Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
909
910 * configure: Regenerated to track ../common/aclocal.m4 changes.
911 * config.in: Ditto.
912
913Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
914
915 * mips.igen (MSUB): Fix to work like MADD.
916 * gencode.c (MSUB): Similarly.
917
918Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
919
920 * configure: Regenerated to track ../common/aclocal.m4 changes.
921
922Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
923
924 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
925
926Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
927
928 * sim-main.h (sim-fpu.h): Include.
929
930 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
931 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
932 using host independant sim_fpu module.
933
934Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
935
936 * interp.c (signal_exception): Report internal errors with SIGABRT
937 not SIGQUIT.
938
939 * sim-main.h (C0_CONFIG): New register.
940 (signal.h): No longer include.
941
942 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
943
944Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
945
946 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
947
948Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
949
950 * mips.igen: Tag vr5000 instructions.
951 (ANDI): Was missing mipsIV model, fix assembler syntax.
952 (do_c_cond_fmt): New function.
953 (C.cond.fmt): Handle mips I-III which do not support CC field
954 separatly.
955 (bc1): Handle mips IV which do not have a delaed FCC separatly.
956 (SDR): Mask paddr when BigEndianMem, not the converse as specified
957 in IV3.2 spec.
958 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
959 vr5000 which saves LO in a GPR separatly.
960
961 * configure.in (enable-sim-igen): For vr5000, select vr5000
962 specific instructions.
963 * configure: Re-generate.
964
965Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
966
967 * Makefile.in (SIM_OBJS): Add sim-fpu module.
968
969 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
970 fmt_uninterpreted_64 bit cases to switch. Convert to
971 fmt_formatted,
972
973 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
974
975 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
976 as specified in IV3.2 spec.
977 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
978
979Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
980
981 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
982 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
983 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
984 PENDING_FILL versions of instructions. Simplify.
985 (X): New function.
986 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
987 instructions.
988 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
989 a signed value.
990 (MTHI, MFHI): Disable code checking HI-LO.
991
992 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
993 global.
994 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
995
996Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
997
998 * gencode.c (build_mips16_operands): Replace IPC with cia.
999
1000 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1001 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1002 IPC to `cia'.
1003 (UndefinedResult): Replace function with macro/function
1004 combination.
1005 (sim_engine_run): Don't save PC in IPC.
1006
1007 * sim-main.h (IPC): Delete.
1008
1009
1010 * interp.c (signal_exception, store_word, load_word,
1011 address_translation, load_memory, store_memory, cache_op,
1012 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1013 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1014 current instruction address - cia - argument.
1015 (sim_read, sim_write): Call address_translation directly.
1016 (sim_engine_run): Rename variable vaddr to cia.
1017 (signal_exception): Pass cia to sim_monitor
1018
1019 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1020 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1021 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1022
1023 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1024 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1025 SIM_ASSERT.
1026
1027 * interp.c (signal_exception): Pass restart address to
1028 sim_engine_restart.
1029
1030 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1031 idecode.o): Add dependency.
1032
1033 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1034 Delete definitions
1035 (DELAY_SLOT): Update NIA not PC with branch address.
1036 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1037
1038 * mips.igen: Use CIA not PC in branch calculations.
1039 (illegal): Call SignalException.
1040 (BEQ, ADDIU): Fix assembler.
1041
1042Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1043
1044 * m16.igen (JALX): Was missing.
1045
1046 * configure.in (enable-sim-igen): New configuration option.
1047 * configure: Re-generate.
1048
1049 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1050
1051 * interp.c (load_memory, store_memory): Delete parameter RAW.
1052 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1053 bypassing {load,store}_memory.
1054
1055 * sim-main.h (ByteSwapMem): Delete definition.
1056
1057 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1058
1059 * interp.c (sim_do_command, sim_commands): Delete mips specific
1060 commands. Handled by module sim-options.
1061
1062 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1063 (WITH_MODULO_MEMORY): Define.
1064
1065 * interp.c (sim_info): Delete code printing memory size.
1066
1067 * interp.c (mips_size): Nee sim_size, delete function.
1068 (power2): Delete.
1069 (monitor, monitor_base, monitor_size): Delete global variables.
1070 (sim_open, sim_close): Delete code creating monitor and other
1071 memory regions. Use sim-memopts module, via sim_do_commandf, to
1072 manage memory regions.
1073 (load_memory, store_memory): Use sim-core for memory model.
1074
1075 * interp.c (address_translation): Delete all memory map code
1076 except line forcing 32 bit addresses.
1077
1078Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1079
1080 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1081 trace options.
1082
1083 * interp.c (logfh, logfile): Delete globals.
1084 (sim_open, sim_close): Delete code opening & closing log file.
1085 (mips_option_handler): Delete -l and -n options.
1086 (OPTION mips_options): Ditto.
1087
1088 * interp.c (OPTION mips_options): Rename option trace to dinero.
1089 (mips_option_handler): Update.
1090
1091Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1092
1093 * interp.c (fetch_str): New function.
1094 (sim_monitor): Rewrite using sim_read & sim_write.
1095 (sim_open): Check magic number.
1096 (sim_open): Write monitor vectors into memory using sim_write.
1097 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1098 (sim_read, sim_write): Simplify - transfer data one byte at a
1099 time.
1100 (load_memory, store_memory): Clarify meaning of parameter RAW.
1101
1102 * sim-main.h (isHOST): Defete definition.
1103 (isTARGET): Mark as depreciated.
1104 (address_translation): Delete parameter HOST.
1105
1106 * interp.c (address_translation): Delete parameter HOST.
1107
1108Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1109
1110 * mips.igen:
1111
1112 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1113 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1114
1115Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1116
1117 * mips.igen: Add model filter field to records.
1118
1119Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1120
1121 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1122
1123 interp.c (sim_engine_run): Do not compile function sim_engine_run
1124 when WITH_IGEN == 1.
1125
1126 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1127 target architecture.
1128
1129 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1130 igen. Replace with configuration variables sim_igen_flags /
1131 sim_m16_flags.
1132
1133 * m16.igen: New file. Copy mips16 insns here.
1134 * mips.igen: From here.
1135
1136Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1137
1138 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1139 to top.
1140 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1141
1142Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1143
1144 * gencode.c (build_instruction): Follow sim_write's lead in using
1145 BigEndianMem instead of !ByteSwapMem.
1146
1147Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1148
1149 * configure.in (sim_gen): Dependent on target, select type of
1150 generator. Always select old style generator.
1151
1152 configure: Re-generate.
1153
1154 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1155 targets.
1156 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1157 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1158 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1159 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1160 SIM_@sim_gen@_*, set by autoconf.
1161
1162Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1163
1164 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1165
1166 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1167 CURRENT_FLOATING_POINT instead.
1168
1169 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1170 (address_translation): Raise exception InstructionFetch when
1171 translation fails and isINSTRUCTION.
1172
1173 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1174 sim_engine_run): Change type of of vaddr and paddr to
1175 address_word.
1176 (address_translation, prefetch, load_memory, store_memory,
1177 cache_op): Change type of vAddr and pAddr to address_word.
1178
1179 * gencode.c (build_instruction): Change type of vaddr and paddr to
1180 address_word.
1181
1182Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1183
1184 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1185 macro to obtain result of ALU op.
1186
1187Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1188
1189 * interp.c (sim_info): Call profile_print.
1190
1191Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1192
1193 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1194
1195 * sim-main.h (WITH_PROFILE): Do not define, defined in
1196 common/sim-config.h. Use sim-profile module.
1197 (simPROFILE): Delete defintion.
1198
1199 * interp.c (PROFILE): Delete definition.
1200 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1201 (sim_close): Delete code writing profile histogram.
1202 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1203 Delete.
1204 (sim_engine_run): Delete code profiling the PC.
1205
1206Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1207
1208 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1209
1210 * interp.c (sim_monitor): Make register pointers of type
1211 unsigned_word*.
1212
1213 * sim-main.h: Make registers of type unsigned_word not
1214 signed_word.
1215
1216Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * interp.c (sync_operation): Rename from SyncOperation, make
1219 global, add SD argument.
1220 (prefetch): Rename from Prefetch, make global, add SD argument.
1221 (decode_coproc): Make global.
1222
1223 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1224
1225 * gencode.c (build_instruction): Generate DecodeCoproc not
1226 decode_coproc calls.
1227
1228 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1229 (SizeFGR): Move to sim-main.h
1230 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1231 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1232 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1233 sim-main.h.
1234 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1235 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1236 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1237 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1238 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1239 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1240
1241 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1242 exception.
1243 (sim-alu.h): Include.
1244 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1245 (sim_cia): Typedef to instruction_address.
1246
1247Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1248
1249 * Makefile.in (interp.o): Rename generated file engine.c to
1250 oengine.c.
1251
1252 * interp.c: Update.
1253
1254Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1255
1256 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1257
1258Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1259
1260 * gencode.c (build_instruction): For "FPSQRT", output correct
1261 number of arguments to Recip.
1262
1263Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1264
1265 * Makefile.in (interp.o): Depends on sim-main.h
1266
1267 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1268
1269 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1270 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1271 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1272 STATE, DSSTATE): Define
1273 (GPR, FGRIDX, ..): Define.
1274
1275 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1276 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1277 (GPR, FGRIDX, ...): Delete macros.
1278
1279 * interp.c: Update names to match defines from sim-main.h
1280
1281Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * interp.c (sim_monitor): Add SD argument.
1284 (sim_warning): Delete. Replace calls with calls to
1285 sim_io_eprintf.
1286 (sim_error): Delete. Replace calls with sim_io_error.
1287 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1288 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1289 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1290 argument.
1291 (mips_size): Rename from sim_size. Add SD argument.
1292
1293 * interp.c (simulator): Delete global variable.
1294 (callback): Delete global variable.
1295 (mips_option_handler, sim_open, sim_write, sim_read,
1296 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1297 sim_size,sim_monitor): Use sim_io_* not callback->*.
1298 (sim_open): ZALLOC simulator struct.
1299 (PROFILE): Do not define.
1300
1301Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1302
1303 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1304 support.h with corresponding code.
1305
1306 * sim-main.h (word64, uword64), support.h: Move definition to
1307 sim-main.h.
1308 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1309
1310 * support.h: Delete
1311 * Makefile.in: Update dependencies
1312 * interp.c: Do not include.
1313
1314Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * interp.c (address_translation, load_memory, store_memory,
1317 cache_op): Rename to from AddressTranslation et.al., make global,
1318 add SD argument
1319
1320 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1321 CacheOp): Define.
1322
1323 * interp.c (SignalException): Rename to signal_exception, make
1324 global.
1325
1326 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1327
1328 * sim-main.h (SignalException, SignalExceptionInterrupt,
1329 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1330 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1331 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1332 Define.
1333
1334 * interp.c, support.h: Use.
1335
1336Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1337
1338 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1339 to value_fpr / store_fpr. Add SD argument.
1340 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1341 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1342
1343 * sim-main.h (ValueFPR, StoreFPR): Define.
1344
1345Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1346
1347 * interp.c (sim_engine_run): Check consistency between configure
1348 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1349 and HASFPU.
1350
1351 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1352 (mips_fpu): Configure WITH_FLOATING_POINT.
1353 (mips_endian): Configure WITH_TARGET_ENDIAN.
1354 * configure: Update.
1355
1356Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * configure: Regenerated to track ../common/aclocal.m4 changes.
1359
1360Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1361
1362 * configure: Regenerated.
1363
1364Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1365
1366 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1367
1368Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1369
1370 * gencode.c (print_igen_insn_models): Assume certain architectures
1371 include all mips* instructions.
1372 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1373 instruction.
1374
1375 * Makefile.in (tmp.igen): Add target. Generate igen input from
1376 gencode file.
1377
1378 * gencode.c (FEATURE_IGEN): Define.
1379 (main): Add --igen option. Generate output in igen format.
1380 (process_instructions): Format output according to igen option.
1381 (print_igen_insn_format): New function.
1382 (print_igen_insn_models): New function.
1383 (process_instructions): Only issue warnings and ignore
1384 instructions when no FEATURE_IGEN.
1385
1386Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1387
1388 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1389 MIPS targets.
1390
1391Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1392
1393 * configure: Regenerated to track ../common/aclocal.m4 changes.
1394
1395Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1396
1397 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1398 SIM_RESERVED_BITS): Delete, moved to common.
1399 (SIM_EXTRA_CFLAGS): Update.
1400
1401Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * configure.in: Configure non-strict memory alignment.
1404 * configure: Regenerated to track ../common/aclocal.m4 changes.
1405
1406Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1407
1408 * configure: Regenerated to track ../common/aclocal.m4 changes.
1409
1410Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1411
1412 * gencode.c (SDBBP,DERET): Added (3900) insns.
1413 (RFE): Turn on for 3900.
1414 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1415 (dsstate): Made global.
1416 (SUBTARGET_R3900): Added.
1417 (CANCELDELAYSLOT): New.
1418 (SignalException): Ignore SystemCall rather than ignore and
1419 terminate. Add DebugBreakPoint handling.
1420 (decode_coproc): New insns RFE, DERET; and new registers Debug
1421 and DEPC protected by SUBTARGET_R3900.
1422 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1423 bits explicitly.
1424 * Makefile.in,configure.in: Add mips subtarget option.
1425 * configure: Update.
1426
1427Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1428
1429 * gencode.c: Add r3900 (tx39).
1430
1431
1432Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1433
1434 * gencode.c (build_instruction): Don't need to subtract 4 for
1435 JALR, just 2.
1436
1437Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1438
1439 * interp.c: Correct some HASFPU problems.
1440
1441Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1442
1443 * configure: Regenerated to track ../common/aclocal.m4 changes.
1444
1445Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * interp.c (mips_options): Fix samples option short form, should
1448 be `x'.
1449
1450Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * interp.c (sim_info): Enable info code. Was just returning.
1453
1454Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1457 MFC0.
1458
1459Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1462 constants.
1463 (build_instruction): Ditto for LL.
1464
1465Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1466
1467 * configure: Regenerated to track ../common/aclocal.m4 changes.
1468
1469Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1470
1471 * configure: Regenerated to track ../common/aclocal.m4 changes.
1472 * config.in: Ditto.
1473
1474Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1475
1476 * interp.c (sim_open): Add call to sim_analyze_program, update
1477 call to sim_config.
1478
1479Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1480
1481 * interp.c (sim_kill): Delete.
1482 (sim_create_inferior): Add ABFD argument. Set PC from same.
1483 (sim_load): Move code initializing trap handlers from here.
1484 (sim_open): To here.
1485 (sim_load): Delete, use sim-hload.c.
1486
1487 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1488
1489Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 * configure: Regenerated to track ../common/aclocal.m4 changes.
1492 * config.in: Ditto.
1493
1494Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * interp.c (sim_open): Add ABFD argument.
1497 (sim_load): Move call to sim_config from here.
1498 (sim_open): To here. Check return status.
1499
1500Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1501
1502 * gencode.c (build_instruction): Two arg MADD should
1503 not assign result to $0.
1504
1505Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1506
1507 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1508 * sim/mips/configure.in: Regenerate.
1509
1510Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1511
1512 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1513 signed8, unsigned8 et.al. types.
1514
1515 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1516 hosts when selecting subreg.
1517
1518Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1519
1520 * interp.c (sim_engine_run): Reset the ZERO register to zero
1521 regardless of FEATURE_WARN_ZERO.
1522 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1523
1524Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1527 (SignalException): For BreakPoints ignore any mode bits and just
1528 save the PC.
1529 (SignalException): Always set the CAUSE register.
1530
1531Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1532
1533 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1534 exception has been taken.
1535
1536 * interp.c: Implement the ERET and mt/f sr instructions.
1537
1538Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539
1540 * interp.c (SignalException): Don't bother restarting an
1541 interrupt.
1542
1543Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1544
1545 * interp.c (SignalException): Really take an interrupt.
1546 (interrupt_event): Only deliver interrupts when enabled.
1547
1548Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1549
1550 * interp.c (sim_info): Only print info when verbose.
1551 (sim_info) Use sim_io_printf for output.
1552
1553Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1554
1555 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1556 mips architectures.
1557
1558Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * interp.c (sim_do_command): Check for common commands if a
1561 simulator specific command fails.
1562
1563Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1564
1565 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1566 and simBE when DEBUG is defined.
1567
1568Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569
1570 * interp.c (interrupt_event): New function. Pass exception event
1571 onto exception handler.
1572
1573 * configure.in: Check for stdlib.h.
1574 * configure: Regenerate.
1575
1576 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1577 variable declaration.
1578 (build_instruction): Initialize memval1.
1579 (build_instruction): Add UNUSED attribute to byte, bigend,
1580 reverse.
1581 (build_operands): Ditto.
1582
1583 * interp.c: Fix GCC warnings.
1584 (sim_get_quit_code): Delete.
1585
1586 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1587 * Makefile.in: Ditto.
1588 * configure: Re-generate.
1589
1590 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1591
1592Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1593
1594 * interp.c (mips_option_handler): New function parse argumes using
1595 sim-options.
1596 (myname): Replace with STATE_MY_NAME.
1597 (sim_open): Delete check for host endianness - performed by
1598 sim_config.
1599 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1600 (sim_open): Move much of the initialization from here.
1601 (sim_load): To here. After the image has been loaded and
1602 endianness set.
1603 (sim_open): Move ColdReset from here.
1604 (sim_create_inferior): To here.
1605 (sim_open): Make FP check less dependant on host endianness.
1606
1607 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1608 run.
1609 * interp.c (sim_set_callbacks): Delete.
1610
1611 * interp.c (membank, membank_base, membank_size): Replace with
1612 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1613 (sim_open): Remove call to callback->init. gdb/run do this.
1614
1615 * interp.c: Update
1616
1617 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1618
1619 * interp.c (big_endian_p): Delete, replaced by
1620 current_target_byte_order.
1621
1622Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623
1624 * interp.c (host_read_long, host_read_word, host_swap_word,
1625 host_swap_long): Delete. Using common sim-endian.
1626 (sim_fetch_register, sim_store_register): Use H2T.
1627 (pipeline_ticks): Delete. Handled by sim-events.
1628 (sim_info): Update.
1629 (sim_engine_run): Update.
1630
1631Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1634 reason from here.
1635 (SignalException): To here. Signal using sim_engine_halt.
1636 (sim_stop_reason): Delete, moved to common.
1637
1638Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1639
1640 * interp.c (sim_open): Add callback argument.
1641 (sim_set_callbacks): Delete SIM_DESC argument.
1642 (sim_size): Ditto.
1643
1644Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645
1646 * Makefile.in (SIM_OBJS): Add common modules.
1647
1648 * interp.c (sim_set_callbacks): Also set SD callback.
1649 (set_endianness, xfer_*, swap_*): Delete.
1650 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1651 Change to functions using sim-endian macros.
1652 (control_c, sim_stop): Delete, use common version.
1653 (simulate): Convert into.
1654 (sim_engine_run): This function.
1655 (sim_resume): Delete.
1656
1657 * interp.c (simulation): New variable - the simulator object.
1658 (sim_kind): Delete global - merged into simulation.
1659 (sim_load): Cleanup. Move PC assignment from here.
1660 (sim_create_inferior): To here.
1661
1662 * sim-main.h: New file.
1663 * interp.c (sim-main.h): Include.
1664
1665Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1666
1667 * configure: Regenerated to track ../common/aclocal.m4 changes.
1668
1669Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1670
1671 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1672
1673Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1674
1675 * gencode.c (build_instruction): DIV instructions: check
1676 for division by zero and integer overflow before using
1677 host's division operation.
1678
1679Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1680
1681 * Makefile.in (SIM_OBJS): Add sim-load.o.
1682 * interp.c: #include bfd.h.
1683 (target_byte_order): Delete.
1684 (sim_kind, myname, big_endian_p): New static locals.
1685 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1686 after argument parsing. Recognize -E arg, set endianness accordingly.
1687 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1688 load file into simulator. Set PC from bfd.
1689 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1690 (set_endianness): Use big_endian_p instead of target_byte_order.
1691
1692Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1693
1694 * interp.c (sim_size): Delete prototype - conflicts with
1695 definition in remote-sim.h. Correct definition.
1696
1697Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1698
1699 * configure: Regenerated to track ../common/aclocal.m4 changes.
1700 * config.in: Ditto.
1701
1702Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1703
1704 * interp.c (sim_open): New arg `kind'.
1705
1706 * configure: Regenerated to track ../common/aclocal.m4 changes.
1707
1708Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1709
1710 * configure: Regenerated to track ../common/aclocal.m4 changes.
1711
1712Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1713
1714 * interp.c (sim_open): Set optind to 0 before calling getopt.
1715
1716Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1717
1718 * configure: Regenerated to track ../common/aclocal.m4 changes.
1719
1720Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1721
1722 * interp.c : Replace uses of pr_addr with pr_uword64
1723 where the bit length is always 64 independent of SIM_ADDR.
1724 (pr_uword64) : added.
1725
1726Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1727
1728 * configure: Re-generate.
1729
1730Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1731
1732 * configure: Regenerate to track ../common/aclocal.m4 changes.
1733
1734Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1735
1736 * interp.c (sim_open): New SIM_DESC result. Argument is now
1737 in argv form.
1738 (other sim_*): New SIM_DESC argument.
1739
1740Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1741
1742 * interp.c: Fix printing of addresses for non-64-bit targets.
1743 (pr_addr): Add function to print address based on size.
1744
1745Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1746
1747 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1748
1749Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1750
1751 * gencode.c (build_mips16_operands): Correct computation of base
1752 address for extended PC relative instruction.
1753
1754Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1755
1756 * interp.c (mips16_entry): Add support for floating point cases.
1757 (SignalException): Pass floating point cases to mips16_entry.
1758 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1759 registers.
1760 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1761 or fmt_word.
1762 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1763 and then set the state to fmt_uninterpreted.
1764 (COP_SW): Temporarily set the state to fmt_word while calling
1765 ValueFPR.
1766
1767Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1768
1769 * gencode.c (build_instruction): The high order may be set in the
1770 comparison flags at any ISA level, not just ISA 4.
1771
1772Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1773
1774 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1775 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1776 * configure.in: sinclude ../common/aclocal.m4.
1777 * configure: Regenerated.
1778
1779Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1780
1781 * configure: Rebuild after change to aclocal.m4.
1782
1783Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1784
1785 * configure configure.in Makefile.in: Update to new configure
1786 scheme which is more compatible with WinGDB builds.
1787 * configure.in: Improve comment on how to run autoconf.
1788 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1789 * Makefile.in: Use autoconf substitution to install common
1790 makefile fragment.
1791
1792Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1793
1794 * gencode.c (build_instruction): Use BigEndianCPU instead of
1795 ByteSwapMem.
1796
1797Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1798
1799 * interp.c (sim_monitor): Make output to stdout visible in
1800 wingdb's I/O log window.
1801
1802Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1803
1804 * support.h: Undo previous change to SIGTRAP
1805 and SIGQUIT values.
1806
1807Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1808
1809 * interp.c (store_word, load_word): New static functions.
1810 (mips16_entry): New static function.
1811 (SignalException): Look for mips16 entry and exit instructions.
1812 (simulate): Use the correct index when setting fpr_state after
1813 doing a pending move.
1814
1815Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1816
1817 * interp.c: Fix byte-swapping code throughout to work on
1818 both little- and big-endian hosts.
1819
1820Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1821
1822 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1823 with gdb/config/i386/xm-windows.h.
1824
1825Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1826
1827 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1828 that messes up arithmetic shifts.
1829
1830Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1831
1832 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1833 SIGTRAP and SIGQUIT for _WIN32.
1834
1835Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1836
1837 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1838 force a 64 bit multiplication.
1839 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1840 destination register is 0, since that is the default mips16 nop
1841 instruction.
1842
1843Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1844
1845 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1846 (build_endian_shift): Don't check proc64.
1847 (build_instruction): Always set memval to uword64. Cast op2 to
1848 uword64 when shifting it left in memory instructions. Always use
1849 the same code for stores--don't special case proc64.
1850
1851 * gencode.c (build_mips16_operands): Fix base PC value for PC
1852 relative operands.
1853 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1854 jal instruction.
1855 * interp.c (simJALDELAYSLOT): Define.
1856 (JALDELAYSLOT): Define.
1857 (INDELAYSLOT, INJALDELAYSLOT): Define.
1858 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1859
1860Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1861
1862 * interp.c (sim_open): add flush_cache as a PMON routine
1863 (sim_monitor): handle flush_cache by ignoring it
1864
1865Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1866
1867 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1868 BigEndianMem.
1869 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1870 (BigEndianMem): Rename to ByteSwapMem and change sense.
1871 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1872 BigEndianMem references to !ByteSwapMem.
1873 (set_endianness): New function, with prototype.
1874 (sim_open): Call set_endianness.
1875 (sim_info): Use simBE instead of BigEndianMem.
1876 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1877 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1878 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1879 ifdefs, keeping the prototype declaration.
1880 (swap_word): Rewrite correctly.
1881 (ColdReset): Delete references to CONFIG. Delete endianness related
1882 code; moved to set_endianness.
1883
1884Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1885
1886 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1887 * interp.c (CHECKHILO): Define away.
1888 (simSIGINT): New macro.
1889 (membank_size): Increase from 1MB to 2MB.
1890 (control_c): New function.
1891 (sim_resume): Rename parameter signal to signal_number. Add local
1892 variable prev. Call signal before and after simulate.
1893 (sim_stop_reason): Add simSIGINT support.
1894 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1895 functions always.
1896 (sim_warning): Delete call to SignalException. Do call printf_filtered
1897 if logfh is NULL.
1898 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1899 a call to sim_warning.
1900
1901Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1902
1903 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1904 16 bit instructions.
1905
1906Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1907
1908 Add support for mips16 (16 bit MIPS implementation):
1909 * gencode.c (inst_type): Add mips16 instruction encoding types.
1910 (GETDATASIZEINSN): Define.
1911 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1912 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1913 mtlo.
1914 (MIPS16_DECODE): New table, for mips16 instructions.
1915 (bitmap_val): New static function.
1916 (struct mips16_op): Define.
1917 (mips16_op_table): New table, for mips16 operands.
1918 (build_mips16_operands): New static function.
1919 (process_instructions): If PC is odd, decode a mips16
1920 instruction. Break out instruction handling into new
1921 build_instruction function.
1922 (build_instruction): New static function, broken out of
1923 process_instructions. Check modifiers rather than flags for SHIFT
1924 bit count and m[ft]{hi,lo} direction.
1925 (usage): Pass program name to fprintf.
1926 (main): Remove unused variable this_option_optind. Change
1927 ``*loptarg++'' to ``loptarg++''.
1928 (my_strtoul): Parenthesize && within ||.
1929 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1930 (simulate): If PC is odd, fetch a 16 bit instruction, and
1931 increment PC by 2 rather than 4.
1932 * configure.in: Add case for mips16*-*-*.
1933 * configure: Rebuild.
1934
1935Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1936
1937 * interp.c: Allow -t to enable tracing in standalone simulator.
1938 Fix garbage output in trace file and error messages.
1939
1940Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1941
1942 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1943 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1944 * configure.in: Simplify using macros in ../common/aclocal.m4.
1945 * configure: Regenerated.
1946 * tconfig.in: New file.
1947
1948Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1949
1950 * interp.c: Fix bugs in 64-bit port.
1951 Use ansi function declarations for msvc compiler.
1952 Initialize and test file pointer in trace code.
1953 Prevent duplicate definition of LAST_EMED_REGNUM.
1954
1955Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1956
1957 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1958
1959Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1960
1961 * interp.c (SignalException): Check for explicit terminating
1962 breakpoint value.
1963 * gencode.c: Pass instruction value through SignalException()
1964 calls for Trap, Breakpoint and Syscall.
1965
1966Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1967
1968 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1969 only used on those hosts that provide it.
1970 * configure.in: Add sqrt() to list of functions to be checked for.
1971 * config.in: Re-generated.
1972 * configure: Re-generated.
1973
1974Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1975
1976 * gencode.c (process_instructions): Call build_endian_shift when
1977 expanding STORE RIGHT, to fix swr.
1978 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1979 clear the high bits.
1980 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1981 Fix float to int conversions to produce signed values.
1982
1983Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1984
1985 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1986 (process_instructions): Correct handling of nor instruction.
1987 Correct shift count for 32 bit shift instructions. Correct sign
1988 extension for arithmetic shifts to not shift the number of bits in
1989 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1990 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1991 Fix madd.
1992 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1993 It's OK to have a mult follow a mult. What's not OK is to have a
1994 mult follow an mfhi.
1995 (Convert): Comment out incorrect rounding code.
1996
1997Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1998
1999 * interp.c (sim_monitor): Improved monitor printf
2000 simulation. Tidied up simulator warnings, and added "--log" option
2001 for directing warning message output.
2002 * gencode.c: Use sim_warning() rather than WARNING macro.
2003
2004Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2005
2006 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2007 getopt1.o, rather than on gencode.c. Link objects together.
2008 Don't link against -liberty.
2009 (gencode.o, getopt.o, getopt1.o): New targets.
2010 * gencode.c: Include <ctype.h> and "ansidecl.h".
2011 (AND): Undefine after including "ansidecl.h".
2012 (ULONG_MAX): Define if not defined.
2013 (OP_*): Don't define macros; now defined in opcode/mips.h.
2014 (main): Call my_strtoul rather than strtoul.
2015 (my_strtoul): New static function.
2016
2017Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2018
2019 * gencode.c (process_instructions): Generate word64 and uword64
2020 instead of `long long' and `unsigned long long' data types.
2021 * interp.c: #include sysdep.h to get signals, and define default
2022 for SIGBUS.
2023 * (Convert): Work around for Visual-C++ compiler bug with type
2024 conversion.
2025 * support.h: Make things compile under Visual-C++ by using
2026 __int64 instead of `long long'. Change many refs to long long
2027 into word64/uword64 typedefs.
2028
2029Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2030
2031 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2032 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2033 (docdir): Removed.
2034 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2035 (AC_PROG_INSTALL): Added.
2036 (AC_PROG_CC): Moved to before configure.host call.
2037 * configure: Rebuilt.
2038
2039Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2040
2041 * configure.in: Define @SIMCONF@ depending on mips target.
2042 * configure: Rebuild.
2043 * Makefile.in (run): Add @SIMCONF@ to control simulator
2044 construction.
2045 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2046 * interp.c: Remove some debugging, provide more detailed error
2047 messages, update memory accesses to use LOADDRMASK.
2048
2049Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2050
2051 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2052 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2053 stamp-h.
2054 * configure: Rebuild.
2055 * config.in: New file, generated by autoheader.
2056 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2057 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2058 HAVE_ANINT and HAVE_AINT, as appropriate.
2059 * Makefile.in (run): Use @LIBS@ rather than -lm.
2060 (interp.o): Depend upon config.h.
2061 (Makefile): Just rebuild Makefile.
2062 (clean): Remove stamp-h.
2063 (mostlyclean): Make the same as clean, not as distclean.
2064 (config.h, stamp-h): New targets.
2065
2066Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2067
2068 * interp.c (ColdReset): Fix boolean test. Make all simulator
2069 globals static.
2070
2071Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2072
2073 * interp.c (xfer_direct_word, xfer_direct_long,
2074 swap_direct_word, swap_direct_long, xfer_big_word,
2075 xfer_big_long, xfer_little_word, xfer_little_long,
2076 swap_word,swap_long): Added.
2077 * interp.c (ColdReset): Provide function indirection to
2078 host<->simulated_target transfer routines.
2079 * interp.c (sim_store_register, sim_fetch_register): Updated to
2080 make use of indirected transfer routines.
2081
2082Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2083
2084 * gencode.c (process_instructions): Ensure FP ABS instruction
2085 recognised.
2086 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2087 system call support.
2088
2089Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2090
2091 * interp.c (sim_do_command): Complain if callback structure not
2092 initialised.
2093
2094Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2095
2096 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2097 support for Sun hosts.
2098 * Makefile.in (gencode): Ensure the host compiler and libraries
2099 used for cross-hosted build.
2100
2101Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2102
2103 * interp.c, gencode.c: Some more (TODO) tidying.
2104
2105Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2106
2107 * gencode.c, interp.c: Replaced explicit long long references with
2108 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2109 * support.h (SET64LO, SET64HI): Macros added.
2110
2111Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2112
2113 * configure: Regenerate with autoconf 2.7.
2114
2115Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2116
2117 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2118 * support.h: Remove superfluous "1" from #if.
2119 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2120
2121Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2122
2123 * interp.c (StoreFPR): Control UndefinedResult() call on
2124 WARN_RESULT manifest.
2125
2126Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2127
2128 * gencode.c: Tidied instruction decoding, and added FP instruction
2129 support.
2130
2131 * interp.c: Added dineroIII, and BSD profiling support. Also
2132 run-time FP handling.
2133
2134Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2135
2136 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2137 gencode.c, interp.c, support.h: created.
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