sim/bfin/dv-bfin_evt.c

   1 /* Blackfin Event Vector Table (EVT) model.
   2
   3    Copyright (C) 2010-2021 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "devices.h"
  26 #include "dv-bfin_cec.h"
  27 #include "dv-bfin_evt.h"
  28
  29 struct bfin_evt
  30 {
  31   bu32 base;
  32
  33   /* Order after here is important -- matches hardware MMR layout.  */
  34   bu32 evt[16];
  35 };
  36 #define mmr_base()      offsetof(struct bfin_evt, evt[0])
  37 #define mmr_offset(mmr) (offsetof(struct bfin_evt, mmr) - mmr_base())
  38
  39 static const char * const mmr_names[] =
  40 {
  41   "EVT0", "EVT1", "EVT2", "EVT3", "EVT4", "EVT5", "EVT6", "EVT7", "EVT8",
  42   "EVT9", "EVT10", "EVT11", "EVT12", "EVT13", "EVT14", "EVT15",
  43 };
  44 #define mmr_name(off) mmr_names[(off) / 4]
  45
  46 static unsigned
  47 bfin_evt_io_write_buffer (struct hw *me, const void *source,
  48                           int space, address_word addr, unsigned nr_bytes)
  49 {
  50   struct bfin_evt *evt = hw_data (me);
  51   bu32 mmr_off;
  52   bu32 value;
  53
  54   /* Invalid access mode is higher priority than missing register.  */
  55   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
  56     return 0;
  57
  58   value = dv_load_4 (source);
  59   mmr_off = addr - evt->base;
  60
  61   HW_TRACE_WRITE ();
  62
  63   evt->evt[mmr_off / 4] = value;
  64
  65   return nr_bytes;
  66 }
  67
  68 static unsigned
  69 bfin_evt_io_read_buffer (struct hw *me, void *dest,
  70                          int space, address_word addr, unsigned nr_bytes)
  71 {
  72   struct bfin_evt *evt = hw_data (me);
  73   bu32 mmr_off;
  74   bu32 value;
  75
  76   /* Invalid access mode is higher priority than missing register.  */
  77   if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
  78     return 0;
  79
  80   mmr_off = addr - evt->base;
  81
  82   HW_TRACE_READ ();
  83
  84   value = evt->evt[mmr_off / 4];
  85
  86   dv_store_4 (dest, value);
  87
  88   return nr_bytes;
  89 }
  90
  91 static void
  92 attach_bfin_evt_regs (struct hw *me, struct bfin_evt *evt)
  93 {
  94   address_word attach_address;
  95   int attach_space;
  96   unsigned attach_size;
  97   reg_property_spec reg;
  98
  99   if (hw_find_property (me, "reg") == NULL)
 100     hw_abort (me, "Missing \"reg\" property");
 101
 102   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 103     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 104
 105   hw_unit_address_to_attach_address (hw_parent (me),
 106                                      &reg.address,
 107                                      &attach_space, &attach_address, me);
 108   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 109
 110   if (attach_size != BFIN_COREMMR_EVT_SIZE)
 111     hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_EVT_SIZE);
 112
 113   hw_attach_address (hw_parent (me),
 114                      0, attach_space, attach_address, attach_size, me);
 115
 116   evt->base = attach_address;
 117 }
 118
 119 static void
 120 bfin_evt_finish (struct hw *me)
 121 {
 122   struct bfin_evt *evt;
 123
 124   evt = HW_ZALLOC (me, struct bfin_evt);
 125
 126   set_hw_data (me, evt);
 127   set_hw_io_read_buffer (me, bfin_evt_io_read_buffer);
 128   set_hw_io_write_buffer (me, bfin_evt_io_write_buffer);
 129
 130   attach_bfin_evt_regs (me, evt);
 131 }
 132
 133 const struct hw_descriptor dv_bfin_evt_descriptor[] =
 134 {
 135   {"bfin_evt", bfin_evt_finish,},
 136   {NULL, NULL},
 137 };
 138
 139 #define EVT_STATE(cpu) DV_STATE_CACHED (cpu, evt)
 140
 141 void
 142 cec_set_evt (SIM_CPU *cpu, int ivg, bu32 handler_addr)
 143 {
 144   if (ivg > IVG15 || ivg < 0)
 145     sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
 146
 147   EVT_STATE (cpu)->evt[ivg] = handler_addr;
 148 }
 149
 150 bu32
 151 cec_get_evt (SIM_CPU *cpu, int ivg)
 152 {
 153   if (ivg > IVG15 || ivg < 0)
 154     sim_io_error (CPU_STATE (cpu), "%s: ivg %i out of range !", __func__, ivg);
 155
 156   return EVT_STATE (cpu)->evt[ivg];
 157 }
 158
 159 bu32
 160 cec_get_reset_evt (SIM_CPU *cpu)
 161 {
 162   /* XXX: This should tail into the model to get via BMODE pins.  */
 163   return 0xef000000;
 164 }