sim/v850/interp.c

   1 /* This must come before any other includes.  */
   2 #include "defs.h"
   3
   4 #include "sim-main.h"
   5 #include "sim-options.h"
   6 #include "v850_sim.h"
   7 #include "sim-assert.h"
   8 #include "itable.h"
   9
  10 #include <stdlib.h>
  11 #include <string.h>
  12
  13 #include "bfd.h"
  14
  15 static const char * get_insn_name (sim_cpu *, int);
  16
  17 /* For compatibility.  */
  18 SIM_DESC simulator;
  19
  20 /* V850 interrupt model.  */
  21
  22 enum interrupt_type
  23 {
  24   int_reset,
  25   int_nmi,
  26   int_intov1,
  27   int_intp10,
  28   int_intp11,
  29   int_intp12,
  30   int_intp13,
  31   int_intcm4,
  32   num_int_types
  33 };
  34
  35 const char *interrupt_names[] =
  36 {
  37   "reset",
  38   "nmi",
  39   "intov1",
  40   "intp10",
  41   "intp11",
  42   "intp12",
  43   "intp13",
  44   "intcm4",
  45   NULL
  46 };
  47
  48 static void
  49 do_interrupt (SIM_DESC sd, void *data)
  50 {
  51   const char **interrupt_name = (const char**)data;
  52   enum interrupt_type inttype;
  53   inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
  54
  55   /* For a hardware reset, drop everything and jump to the start
  56      address */
  57   if (inttype == int_reset)
  58     {
  59       PC = 0;
  60       PSW = 0x20;
  61       ECR = 0;
  62       sim_engine_restart (sd, NULL, NULL, NULL_CIA);
  63     }
  64
  65   /* Deliver an NMI when allowed */
  66   if (inttype == int_nmi)
  67     {
  68       if (PSW & PSW_NP)
  69         {
  70           /* We're already working on an NMI, so this one must wait
  71              around until the previous one is done.  The processor
  72              ignores subsequent NMIs, so we don't need to count them.
  73              Just keep re-scheduling a single NMI until it manages to
  74              be delivered */
  75           if (STATE_CPU (sd, 0)->pending_nmi != NULL)
  76             sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
  77           STATE_CPU (sd, 0)->pending_nmi =
  78             sim_events_schedule (sd, 1, do_interrupt, data);
  79           return;
  80         }
  81       else
  82         {
  83           /* NMI can be delivered.  Do not deschedule pending_nmi as
  84              that, if still in the event queue, is a second NMI that
  85              needs to be delivered later. */
  86           FEPC = PC;
  87           FEPSW = PSW;
  88           /* Set the FECC part of the ECR. */
  89           ECR &= 0x0000ffff;
  90           ECR |= 0x10;
  91           PSW |= PSW_NP;
  92           PSW &= ~PSW_EP;
  93           PSW |= PSW_ID;
  94           PC = 0x10;
  95           sim_engine_restart (sd, NULL, NULL, NULL_CIA);
  96         }
  97     }
  98
  99   /* deliver maskable interrupt when allowed */
 100   if (inttype > int_nmi && inttype < num_int_types)
 101     {
 102       if ((PSW & PSW_NP) || (PSW & PSW_ID))
 103         {
 104           /* Can't deliver this interrupt, reschedule it for later */
 105           sim_events_schedule (sd, 1, do_interrupt, data);
 106           return;
 107         }
 108       else
 109         {
 110           /* save context */
 111           EIPC = PC;
 112           EIPSW = PSW;
 113           /* Disable further interrupts.  */
 114           PSW |= PSW_ID;
 115           /* Indicate that we're doing interrupt not exception processing.  */
 116           PSW &= ~PSW_EP;
 117           /* Clear the EICC part of the ECR, will set below. */
 118           ECR &= 0xffff0000;
 119           switch (inttype)
 120             {
 121             case int_intov1:
 122               PC = 0x80;
 123               ECR |= 0x80;
 124               break;
 125             case int_intp10:
 126               PC = 0x90;
 127               ECR |= 0x90;
 128               break;
 129             case int_intp11:
 130               PC = 0xa0;
 131               ECR |= 0xa0;
 132               break;
 133             case int_intp12:
 134               PC = 0xb0;
 135               ECR |= 0xb0;
 136               break;
 137             case int_intp13:
 138               PC = 0xc0;
 139               ECR |= 0xc0;
 140               break;
 141             case int_intcm4:
 142               PC = 0xd0;
 143               ECR |= 0xd0;
 144               break;
 145             default:
 146               /* Should never be possible.  */
 147               sim_engine_abort (sd, NULL, NULL_CIA,
 148                                 "do_interrupt - internal error - bad switch");
 149               break;
 150             }
 151         }
 152       sim_engine_restart (sd, NULL, NULL, NULL_CIA);
 153     }
 154
 155   /* some other interrupt? */
 156   sim_engine_abort (sd, NULL, NULL_CIA,
 157                     "do_interrupt - internal error - interrupt %d unknown",
 158                     inttype);
 159 }
 160
 161 /* Return name of an insn, used by insn profiling.  */
 162
 163 static const char *
 164 get_insn_name (sim_cpu *cpu, int i)
 165 {
 166   return itable[i].name;
 167 }
 168
 169 /* These default values correspond to expected usage for the chip.  */
 170
 171 uint32 OP[4];
 172
 173 static sim_cia
 174 v850_pc_get (sim_cpu *cpu)
 175 {
 176   return PC;
 177 }
 178
 179 static void
 180 v850_pc_set (sim_cpu *cpu, sim_cia pc)
 181 {
 182   PC = pc;
 183 }
 184
 185 static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
 186 static int v850_reg_store (SIM_CPU *, int, unsigned char *, int);
 187
 188 SIM_DESC
 189 sim_open (SIM_OPEN_KIND    kind,
 190           host_callback *  cb,
 191           struct bfd *     abfd,
 192           char * const *   argv)
 193 {
 194   int i;
 195   SIM_DESC sd = sim_state_alloc (kind, cb);
 196   int mach;
 197
 198   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 199
 200   /* Set default options before parsing user options.  */
 201   current_target_byte_order = BFD_ENDIAN_LITTLE;
 202
 203   /* The cpu data is kept in a separately allocated chunk of memory.  */
 204   if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
 205     return 0;
 206
 207   /* for compatibility */
 208   simulator = sd;
 209
 210   /* FIXME: should be better way of setting up interrupts */
 211   STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
 212   STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
 213
 214   /* Initialize the mechanism for doing insn profiling.  */
 215   CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
 216   CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
 217
 218   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 219     return 0;
 220
 221   /* Allocate core managed memory */
 222
 223   /* "Mirror" the ROM addresses below 1MB. */
 224   sim_do_commandf (sd, "memory region 0,0x100000,0x%x", V850_ROM_SIZE);
 225   /* Chunk of ram adjacent to rom */
 226   sim_do_commandf (sd, "memory region 0x100000,0x%x", V850_LOW_END-0x100000);
 227   /* peripheral I/O region - mirror 1K across 4k (0x1000) */
 228   sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
 229   /* similarly if in the internal RAM region */
 230   sim_do_command (sd, "memory region 0xffe000,0x1000,1024");
 231
 232   /* The parser will print an error message for us, so we silently return.  */
 233   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 234     {
 235       /* Uninstall the modules to avoid memory leaks,
 236          file descriptor leaks, etc.  */
 237       sim_module_uninstall (sd);
 238       return 0;
 239     }
 240
 241   /* check for/establish the a reference program image */
 242   if (sim_analyze_program (sd,
 243                            (STATE_PROG_ARGV (sd) != NULL
 244                             ? *STATE_PROG_ARGV (sd)
 245                             : NULL),
 246                            abfd) != SIM_RC_OK)
 247     {
 248       sim_module_uninstall (sd);
 249       return 0;
 250     }
 251
 252   /* establish any remaining configuration options */
 253   if (sim_config (sd) != SIM_RC_OK)
 254     {
 255       sim_module_uninstall (sd);
 256       return 0;
 257     }
 258
 259   if (sim_post_argv_init (sd) != SIM_RC_OK)
 260     {
 261       /* Uninstall the modules to avoid memory leaks,
 262          file descriptor leaks, etc.  */
 263       sim_module_uninstall (sd);
 264       return 0;
 265     }
 266
 267
 268   /* determine the machine type */
 269   if (STATE_ARCHITECTURE (sd) != NULL
 270       && (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
 271           || STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
 272     mach = STATE_ARCHITECTURE (sd)->mach;
 273   else
 274     mach = bfd_mach_v850; /* default */
 275
 276   /* set machine specific configuration */
 277   switch (mach)
 278     {
 279     case bfd_mach_v850:
 280     case bfd_mach_v850e:
 281     case bfd_mach_v850e1:
 282     case bfd_mach_v850e2:
 283     case bfd_mach_v850e2v3:
 284     case bfd_mach_v850e3v5:
 285       STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
 286                                      | PSW_CY | PSW_OV | PSW_S | PSW_Z);
 287       break;
 288     }
 289
 290   /* CPU specific initialization.  */
 291   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 292     {
 293       SIM_CPU *cpu = STATE_CPU (sd, i);
 294
 295       CPU_REG_FETCH (cpu) = v850_reg_fetch;
 296       CPU_REG_STORE (cpu) = v850_reg_store;
 297       CPU_PC_FETCH (cpu) = v850_pc_get;
 298       CPU_PC_STORE (cpu) = v850_pc_set;
 299     }
 300
 301   return sd;
 302 }
 303
 304 SIM_RC
 305 sim_create_inferior (SIM_DESC      sd,
 306                      struct bfd *  prog_bfd,
 307                      char * const *argv,
 308                      char * const *env)
 309 {
 310   memset (&State, 0, sizeof (State));
 311   if (prog_bfd != NULL)
 312     PC = bfd_get_start_address (prog_bfd);
 313   return SIM_RC_OK;
 314 }
 315
 316 static int
 317 v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 318 {
 319   *(unsigned32*)memory = H2T_4 (State.regs[rn]);
 320   return -1;
 321 }
 322
 323 static int
 324 v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 325 {
 326   State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
 327   return length;
 328 }