[thirdparty/qemu.git] / hw / isa / vt82c686.c

/*
 * VT82C686B south bridge support
 *
 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "hw/isa/vt82c686.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
#include "hw/isa/superio.h"
#include "migration/vmstate.h"
#include "hw/isa/apm.h"
#include "hw/acpi/acpi.h"
#include "hw/i2c/pm_smbus.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/range.h"
#include "qemu/timer.h"
#include "exec/address-spaces.h"
#include "trace.h"

OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)

struct VT686PMState {
    PCIDevice dev;
    MemoryRegion io;
    ACPIREGS ar;
    APMState apm;
    PMSMBus smb;
};

static void pm_io_space_update(VT686PMState *s)
{
    uint32_t pm_io_base;

    pm_io_base = pci_get_long(s->dev.config + 0x40);
    pm_io_base &= 0xffc0;

    memory_region_transaction_begin();
    memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
    memory_region_set_address(&s->io, pm_io_base);
    memory_region_transaction_commit();
}

static void smb_io_space_update(VT686PMState *s)
{
    uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL;

    memory_region_transaction_begin();
    memory_region_set_address(&s->smb.io, smbase);
    memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0));
    memory_region_transaction_commit();
}

static int vmstate_acpi_post_load(void *opaque, int version_id)
{
    VT686PMState *s = opaque;

    pm_io_space_update(s);
    smb_io_space_update(s);
    return 0;
}

static const VMStateDescription vmstate_acpi = {
    .name = "vt82c686b_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = vmstate_acpi_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, VT686PMState),
        VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
        VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
        VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
        VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
        VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
        VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
        VMSTATE_END_OF_LIST()
    }
};

static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
{
    VT686PMState *s = VT82C686B_PM(d);

    trace_via_pm_write(addr, val, len);
    pci_default_write_config(d, addr, val, len);
    if (ranges_overlap(addr, len, 0x90, 4)) {
        uint32_t v = pci_get_long(s->dev.config + 0x90);
        pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1);
    }
    if (range_covers_byte(addr, len, 0xd2)) {
        s->dev.config[0xd2] &= 0xf;
        smb_io_space_update(s);
    }
}

static void pm_update_sci(VT686PMState *s)
{
    int sci_level, pmsts;

    pmsts = acpi_pm1_evt_get_sts(&s->ar);
    sci_level = (((pmsts & s->ar.pm1.evt.en) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
    pci_set_irq(&s->dev, sci_level);
    /* schedule a timer interruption if needed */
    acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
                       !(pmsts & ACPI_BITMASK_TIMER_STATUS));
}

static void pm_tmr_timer(ACPIREGS *ar)
{
    VT686PMState *s = container_of(ar, VT686PMState, ar);
    pm_update_sci(s);
}

static void vt82c686b_pm_reset(DeviceState *d)
{
    VT686PMState *s = VT82C686B_PM(d);

    /* SMBus IO base */
    pci_set_long(s->dev.config + 0x90, 1);
    s->dev.config[0xd2] = 0;

    smb_io_space_update(s);
}

static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp)
{
    VT686PMState *s = VT82C686B_PM(dev);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_set_word(pci_conf + PCI_COMMAND, 0);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
                 PCI_STATUS_DEVSEL_MEDIUM);

    /* 0x48-0x4B is Power Management I/O Base */
    pci_set_long(pci_conf + 0x48, 0x00000001);

    pm_smbus_init(DEVICE(s), &s->smb, false);
    memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io);
    memory_region_set_enabled(&s->smb.io, false);

    apm_init(dev, &s->apm, NULL, s);

    memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
    memory_region_set_enabled(&s->io, false);
    memory_region_add_subregion(get_system_io(), 0, &s->io);

    acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
    acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
    acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
}

static void via_pm_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = vt82c686b_pm_realize;
    k->config_write = pm_write_config;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_ACPI;
    k->class_id = PCI_CLASS_BRIDGE_OTHER;
    k->revision = 0x40;
    dc->reset = vt82c686b_pm_reset;
    dc->desc = "PM";
    dc->vmsd = &vmstate_acpi;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo via_pm_info = {
    .name          = TYPE_VT82C686B_PM,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(VT686PMState),
    .class_init    = via_pm_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};


typedef struct SuperIOConfig {
    uint8_t regs[0x100];
    uint8_t index;
    MemoryRegion io;
} SuperIOConfig;

static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
                              unsigned size)
{
    SuperIOConfig *sc = opaque;

    if (addr == 0x3f0) { /* config index register */
        sc->index = data & 0xff;
    } else {
        bool can_write = true;
        /* 0x3f1, config data register */
        trace_via_superio_write(sc->index, data & 0xff);
        switch (sc->index) {
        case 0x00 ... 0xdf:
        case 0xe4:
        case 0xe5:
        case 0xe9 ... 0xed:
        case 0xf3:
        case 0xf5:
        case 0xf7:
        case 0xf9 ... 0xfb:
        case 0xfd ... 0xff:
            can_write = false;
            break;
        /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
        default:
            break;

        }
        if (can_write) {
            sc->regs[sc->index] = data & 0xff;
        }
    }
}

static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
{
    SuperIOConfig *sc = opaque;
    uint8_t val = sc->regs[sc->index];

    trace_via_superio_read(sc->index, val);
    return val;
}

static const MemoryRegionOps superio_cfg_ops = {
    .read = superio_cfg_read,
    .write = superio_cfg_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
};


OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)

struct VT82C686BISAState {
    PCIDevice dev;
    SuperIOConfig superio_cfg;
};

static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
                                   uint32_t val, int len)
{
    VT82C686BISAState *s = VT82C686B_ISA(d);

    trace_via_isa_write(addr, val, len);
    pci_default_write_config(d, addr, val, len);
    if (addr == 0x85) {
        /* BIT(1): enable or disable superio config io ports */
        memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
    }
}

static const VMStateDescription vmstate_via = {
    .name = "vt82c686b",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
        VMSTATE_END_OF_LIST()
    }
};

static void vt82c686b_isa_reset(DeviceState *dev)
{
    VT82C686BISAState *s = VT82C686B_ISA(dev);
    uint8_t *pci_conf = s->dev.config;

    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
                 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);

    pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
    pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
    pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
    pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
    pci_conf[0x59] = 0x04;
    pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
    pci_conf[0x5f] = 0x04;
    pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */

    s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
    s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
    s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
    s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
    s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
    s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
}

static void vt82c686b_realize(PCIDevice *d, Error **errp)
{
    VT82C686BISAState *s = VT82C686B_ISA(d);
    uint8_t *pci_conf;
    ISABus *isa_bus;
    uint8_t *wmask;
    int i;

    isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
                          pci_address_space_io(d), errp);
    if (!isa_bus) {
        return;
    }

    pci_conf = d->config;
    pci_config_set_prog_interface(pci_conf, 0x0);

    wmask = d->wmask;
    for (i = 0x00; i < 0xff; i++) {
        if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) {
            wmask[i] = 0x00;
        }
    }

    memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
                          &s->superio_cfg, "superio_cfg", 2);
    memory_region_set_enabled(&s->superio_cfg.io, false);
    /*
     * The floppy also uses 0x3f0 and 0x3f1.
     * But we do not emulate a floppy, so just set it here.
     */
    memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
                                &s->superio_cfg.io);
}

static void via_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = vt82c686b_realize;
    k->config_write = vt82c686b_write_config;
    k->vendor_id = PCI_VENDOR_ID_VIA;
    k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
    k->class_id = PCI_CLASS_BRIDGE_ISA;
    k->revision = 0x40;
    dc->reset = vt82c686b_isa_reset;
    dc->desc = "ISA bridge";
    dc->vmsd = &vmstate_via;
    /*
     * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
     * e.g. by mips_fuloong2e_init()
     */
    dc->user_creatable = false;
}

static const TypeInfo via_info = {
    .name          = TYPE_VT82C686B_ISA,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(VT82C686BISAState),
    .class_init    = via_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};


static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
{
    ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);

    sc->serial.count = 2;
    sc->parallel.count = 1;
    sc->ide.count = 0;
    sc->floppy.count = 1;
}

static const TypeInfo via_superio_info = {
    .name          = TYPE_VT82C686B_SUPERIO,
    .parent        = TYPE_ISA_SUPERIO,
    .instance_size = sizeof(ISASuperIODevice),
    .class_size    = sizeof(ISASuperIOClass),
    .class_init    = vt82c686b_superio_class_init,
};


static void vt82c686b_register_types(void)
{
    type_register_static(&via_pm_info);
    type_register_static(&via_info);
    type_register_static(&via_superio_info);
}

type_init(vt82c686b_register_types)
Commit	Line	Data
edf79e66 HC	1	/*
	2	* VT82C686B south bridge support
	3	*
	4	* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
	5	* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
	6	* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
	7	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
edf79e66 HC	11	*/
edf79e66 HC	12
0430891c	13	#include "qemu/osdep.h"
0d09e41a	14	#include "hw/isa/vt82c686.h"
83c9f4ca	15	#include "hw/pci/pci.h"
a27bd6c7	16	#include "hw/qdev-properties.h"
0d09e41a	17	#include "hw/isa/isa.h"
98cf824b	18	#include "hw/isa/superio.h"
d6454270	19	#include "migration/vmstate.h"
0d09e41a PB	20	#include "hw/isa/apm.h"
	21	#include "hw/acpi/acpi.h"
	22	#include "hw/i2c/pm_smbus.h"
9307d06d	23	#include "qapi/error.h"
0b8fa32f	24	#include "qemu/module.h"
911629e6	25	#include "qemu/range.h"
1de7afc9	26	#include "qemu/timer.h"
022c62cb	27	#include "exec/address-spaces.h"
ff413a1f	28	#include "trace.h"
edf79e66	29
94349bff	30	OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM)
edf79e66	31
db1015e9	32	struct VT686PMState {
edf79e66	33	PCIDevice dev;
a2902821	34	MemoryRegion io;
355bf2e5	35	ACPIREGS ar;
edf79e66	36	APMState apm;
edf79e66	37	PMSMBus smb;
db1015e9	38	};
edf79e66	39
edf79e66 HC	40	static void pm_io_space_update(VT686PMState *s)
	41	{
	42	uint32_t pm_io_base;
	43
a2902821 GH	44	pm_io_base = pci_get_long(s->dev.config + 0x40);
a2902821 GH	45	pm_io_base &= 0xffc0;
edf79e66	46
a2902821 GH	47	memory_region_transaction_begin();
	48	memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
	49	memory_region_set_address(&s->io, pm_io_base);
	50	memory_region_transaction_commit();
edf79e66 HC	51	}
edf79e66 HC	52
911629e6 BZ	53	static void smb_io_space_update(VT686PMState *s)
	54	{
	55	uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL;
	56
	57	memory_region_transaction_begin();
	58	memory_region_set_address(&s->smb.io, smbase);
	59	memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0));
	60	memory_region_transaction_commit();
	61	}
	62
edf79e66 HC	63	static int vmstate_acpi_post_load(void *opaque, int version_id)
	64	{
	65	VT686PMState *s = opaque;
	66
	67	pm_io_space_update(s);
911629e6	68	smb_io_space_update(s);
edf79e66 HC	69	return 0;
	70	}
	71
	72	static const VMStateDescription vmstate_acpi = {
	73	.name = "vt82c686b_pm",
	74	.version_id = 1,
	75	.minimum_version_id = 1,
edf79e66	76	.post_load = vmstate_acpi_post_load,
d49805ae	77	.fields = (VMStateField[]) {
edf79e66	78	VMSTATE_PCI_DEVICE(dev, VT686PMState),
355bf2e5 GH	79	VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
	80	VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
	81	VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
edf79e66	82	VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
e720677e	83	VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState),
355bf2e5	84	VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
edf79e66 HC	85	VMSTATE_END_OF_LIST()
	86	}
	87	};
	88
94349bff BZ	89	static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len)
94349bff BZ	90	{
911629e6 BZ	91	VT686PMState *s = VT82C686B_PM(d);
911629e6 BZ	92
94349bff BZ	93	trace_via_pm_write(addr, val, len);
94349bff BZ	94	pci_default_write_config(d, addr, val, len);
911629e6 BZ	95	if (ranges_overlap(addr, len, 0x90, 4)) {
	96	uint32_t v = pci_get_long(s->dev.config + 0x90);
	97	pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) \| 1);
	98	}
	99	if (range_covers_byte(addr, len, 0xd2)) {
	100	s->dev.config[0xd2] &= 0xf;
	101	smb_io_space_update(s);
	102	}
94349bff BZ	103	}
	104
	105	static void pm_update_sci(VT686PMState *s)
	106	{
	107	int sci_level, pmsts;
	108
	109	pmsts = acpi_pm1_evt_get_sts(&s->ar);
	110	sci_level = (((pmsts & s->ar.pm1.evt.en) &
	111	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	112	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	113	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
	114	ACPI_BITMASK_TIMER_ENABLE)) != 0);
	115	pci_set_irq(&s->dev, sci_level);
	116	/* schedule a timer interruption if needed */
	117	acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
	118	!(pmsts & ACPI_BITMASK_TIMER_STATUS));
	119	}
	120
	121	static void pm_tmr_timer(ACPIREGS *ar)
	122	{
	123	VT686PMState *s = container_of(ar, VT686PMState, ar);
	124	pm_update_sci(s);
	125	}
	126
911629e6 BZ	127	static void vt82c686b_pm_reset(DeviceState *d)
	128	{
	129	VT686PMState *s = VT82C686B_PM(d);
	130
	131	/* SMBus IO base */
	132	pci_set_long(s->dev.config + 0x90, 1);
	133	s->dev.config[0xd2] = 0;
	134
	135	smb_io_space_update(s);
	136	}
	137
9af21dbe	138	static void vt82c686b_pm_realize(PCIDevice dev, Error *errp)
edf79e66	139	{
e6340505	140	VT686PMState *s = VT82C686B_PM(dev);
edf79e66 HC	141	uint8_t *pci_conf;
	142
	143	pci_conf = s->dev.config;
edf79e66 HC	144	pci_set_word(pci_conf + PCI_COMMAND, 0);
	145	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK \|
	146	PCI_STATUS_DEVSEL_MEDIUM);
	147
	148	/* 0x48-0x4B is Power Management I/O Base */
	149	pci_set_long(pci_conf + 0x48, 0x00000001);
	150
a30c34d2	151	pm_smbus_init(DEVICE(s), &s->smb, false);
911629e6 BZ	152	memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io);
911629e6 BZ	153	memory_region_set_enabled(&s->smb.io, false);
edf79e66	154
42d8a3cf	155	apm_init(dev, &s->apm, NULL, s);
edf79e66	156
1437c94b	157	memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
a2902821 GH	158	memory_region_set_enabled(&s->io, false);
a2902821 GH	159	memory_region_add_subregion(get_system_io(), 0, &s->io);
edf79e66	160
77d58b1e	161	acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
b5a7c024	162	acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
9a10bbb4	163	acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2);
edf79e66 HC	164	}
edf79e66 HC	165
40021f08 AL	166	static void via_pm_class_init(ObjectClass klass, void data)
40021f08 AL	167	{
39bffca2	168	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	169	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	170
9af21dbe	171	k->realize = vt82c686b_pm_realize;
40021f08 AL	172	k->config_write = pm_write_config;
	173	k->vendor_id = PCI_VENDOR_ID_VIA;
	174	k->device_id = PCI_DEVICE_ID_VIA_ACPI;
	175	k->class_id = PCI_CLASS_BRIDGE_OTHER;
	176	k->revision = 0x40;
911629e6	177	dc->reset = vt82c686b_pm_reset;
39bffca2 AL	178	dc->desc = "PM";
39bffca2 AL	179	dc->vmsd = &vmstate_acpi;
125ee0ed	180	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
40021f08 AL	181	}
40021f08 AL	182
8c43a6f0	183	static const TypeInfo via_pm_info = {
e6340505	184	.name = TYPE_VT82C686B_PM,
39bffca2 AL	185	.parent = TYPE_PCI_DEVICE,
	186	.instance_size = sizeof(VT686PMState),
	187	.class_init = via_pm_class_init,
fd3b02c8 EH	188	.interfaces = (InterfaceInfo[]) {
	189	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	190	{ },
	191	},
edf79e66 HC	192	};
edf79e66 HC	193
94349bff BZ	194
	195	typedef struct SuperIOConfig {
	196	uint8_t regs[0x100];
	197	uint8_t index;
	198	MemoryRegion io;
	199	} SuperIOConfig;
	200
	201	static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
	202	unsigned size)
	203	{
	204	SuperIOConfig *sc = opaque;
	205
	206	if (addr == 0x3f0) { /* config index register */
	207	sc->index = data & 0xff;
	208	} else {
	209	bool can_write = true;
	210	/* 0x3f1, config data register */
	211	trace_via_superio_write(sc->index, data & 0xff);
	212	switch (sc->index) {
	213	case 0x00 ... 0xdf:
	214	case 0xe4:
	215	case 0xe5:
	216	case 0xe9 ... 0xed:
	217	case 0xf3:
	218	case 0xf5:
	219	case 0xf7:
	220	case 0xf9 ... 0xfb:
	221	case 0xfd ... 0xff:
	222	can_write = false;
	223	break;
	224	/* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
	225	default:
	226	break;
	227
	228	}
	229	if (can_write) {
	230	sc->regs[sc->index] = data & 0xff;
	231	}
	232	}
	233	}
	234
	235	static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
	236	{
	237	SuperIOConfig *sc = opaque;
	238	uint8_t val = sc->regs[sc->index];
	239
	240	trace_via_superio_read(sc->index, val);
	241	return val;
	242	}
	243
	244	static const MemoryRegionOps superio_cfg_ops = {
	245	.read = superio_cfg_read,
	246	.write = superio_cfg_write,
	247	.endianness = DEVICE_NATIVE_ENDIAN,
	248	.impl = {
	249	.min_access_size = 1,
	250	.max_access_size = 1,
	251	},
	252	};
	253
	254
	255	OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
	256
	257	struct VT82C686BISAState {
258	PCIDevice dev;
259	SuperIOConfig superio_cfg;
260	};
261
262	static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
263	uint32_t val, int len)
264	{
265	VT82C686BISAState *s = VT82C686B_ISA(d);
266
267	trace_via_isa_write(addr, val, len);
268	pci_default_write_config(d, addr, val, len);
269	if (addr == 0x85) {
270	/* BIT(1): enable or disable superio config io ports */
271	memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
272	}
273	}
274
edf79e66 HC	275	static const VMStateDescription vmstate_via = {
	276	.name = "vt82c686b",
	277	.version_id = 1,
	278	.minimum_version_id = 1,
d49805ae	279	.fields = (VMStateField[]) {
0f798461	280	VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
edf79e66 HC	281	VMSTATE_END_OF_LIST()
	282	}
	283	};
	284
94349bff BZ	285	static void vt82c686b_isa_reset(DeviceState *dev)
	286	{
	287	VT82C686BISAState *s = VT82C686B_ISA(dev);
	288	uint8_t *pci_conf = s->dev.config;
	289
	290	pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
	291	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \|
	292	PCI_COMMAND_MASTER \| PCI_COMMAND_SPECIAL);
	293	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
	294
	295	pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
	296	pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
	297	pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
	298	pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
	299	pci_conf[0x59] = 0x04;
	300	pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
	301	pci_conf[0x5f] = 0x04;
	302	pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
	303
	304	s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
	305	s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
	306	s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
	307	s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
	308	s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
	309	s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
	310	}
	311
9af21dbe	312	static void vt82c686b_realize(PCIDevice d, Error *errp)
edf79e66	313	{
007b3103	314	VT82C686BISAState *s = VT82C686B_ISA(d);
edf79e66	315	uint8_t *pci_conf;
bcc37e24	316	ISABus *isa_bus;
edf79e66 HC	317	uint8_t *wmask;
	318	int i;
	319
bb2ed009	320	isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
d10e5432 MA	321	pci_address_space_io(d), errp);
	322	if (!isa_bus) {
	323	return;
	324	}
edf79e66 HC	325
edf79e66 HC	326	pci_conf = d->config;
edf79e66	327	pci_config_set_prog_interface(pci_conf, 0x0);
edf79e66 HC	328
	329	wmask = d->wmask;
	330	for (i = 0x00; i < 0xff; i++) {
f3db354c FB	331	if (i <= 0x03 \|\| (i >= 0x08 && i <= 0x3f)) {
	332	wmask[i] = 0x00;
	333	}
edf79e66 HC	334	}
edf79e66 HC	335
6be6e4bc BZ	336	memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
	337	&s->superio_cfg, "superio_cfg", 2);
	338	memory_region_set_enabled(&s->superio_cfg.io, false);
f3db354c FB	339	/*
	340	* The floppy also uses 0x3f0 and 0x3f1.
	341	* But we do not emulate a floppy, so just set it here.
	342	*/
bcc37e24	343	memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
6be6e4bc	344	&s->superio_cfg.io);
edf79e66 HC	345	}
edf79e66 HC	346
40021f08 AL	347	static void via_class_init(ObjectClass klass, void data)
40021f08 AL	348	{
39bffca2	349	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	350	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	351
9af21dbe	352	k->realize = vt82c686b_realize;
40021f08 AL	353	k->config_write = vt82c686b_write_config;
	354	k->vendor_id = PCI_VENDOR_ID_VIA;
	355	k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
	356	k->class_id = PCI_CLASS_BRIDGE_ISA;
	357	k->revision = 0x40;
9dc1a769	358	dc->reset = vt82c686b_isa_reset;
39bffca2	359	dc->desc = "ISA bridge";
39bffca2	360	dc->vmsd = &vmstate_via;
04916ee9 MA	361	/*
04916ee9 MA	362	* Reason: part of VIA VT82C686 southbridge, needs to be wired up,
c3a09ff6	363	* e.g. by mips_fuloong2e_init()
04916ee9	364	*/
e90f2a8c	365	dc->user_creatable = false;
40021f08 AL	366	}
40021f08 AL	367
8c43a6f0	368	static const TypeInfo via_info = {
0f798461	369	.name = TYPE_VT82C686B_ISA,
39bffca2	370	.parent = TYPE_PCI_DEVICE,
0f798461	371	.instance_size = sizeof(VT82C686BISAState),
39bffca2	372	.class_init = via_class_init,
fd3b02c8 EH	373	.interfaces = (InterfaceInfo[]) {
	374	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	375	{ },
	376	},
edf79e66 HC	377	};
edf79e66 HC	378
94349bff	379
98cf824b PMD	380	static void vt82c686b_superio_class_init(ObjectClass klass, void data)
	381	{
	382	ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
	383
	384	sc->serial.count = 2;
	385	sc->parallel.count = 1;
	386	sc->ide.count = 0;
	387	sc->floppy.count = 1;
	388	}
	389
	390	static const TypeInfo via_superio_info = {
	391	.name = TYPE_VT82C686B_SUPERIO,
	392	.parent = TYPE_ISA_SUPERIO,
	393	.instance_size = sizeof(ISASuperIODevice),
	394	.class_size = sizeof(ISASuperIOClass),
	395	.class_init = vt82c686b_superio_class_init,
	396	};
	397
94349bff	398
83f7d43a	399	static void vt82c686b_register_types(void)
edf79e66	400	{
83f7d43a	401	type_register_static(&via_pm_info);
39bffca2	402	type_register_static(&via_info);
94349bff	403	type_register_static(&via_superio_info);
edf79e66	404	}
83f7d43a AF	405
83f7d43a AF	406	type_init(vt82c686b_register_types)