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d7dfca08 IM |
1 | /* |
2 | * SD Association Host Standard Specification v2.0 controller emulation | |
3 | * | |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
5 | * Mitsyanko Igor <i.mitsyanko@samsung.com> | |
6 | * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> | |
7 | * | |
8 | * Based on MMC controller for Samsung S5PC1xx-based board emulation | |
9 | * by Alexey Merkulov and Vladimir Monakhov. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
19 | * See the GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
0430891c | 25 | #include "qemu/osdep.h" |
b635d98c | 26 | #include "qapi/error.h" |
83c9f4ca | 27 | #include "hw/hw.h" |
fa1d36df | 28 | #include "sysemu/block-backend.h" |
d7dfca08 IM |
29 | #include "sysemu/blockdev.h" |
30 | #include "sysemu/dma.h" | |
31 | #include "qemu/timer.h" | |
d7dfca08 | 32 | #include "qemu/bitops.h" |
f82a0f44 | 33 | #include "hw/sd/sdhci.h" |
637d23be | 34 | #include "sdhci-internal.h" |
03dd024f | 35 | #include "qemu/log.h" |
d7dfca08 IM |
36 | |
37 | /* host controller debug messages */ | |
38 | #ifndef SDHC_DEBUG | |
39 | #define SDHC_DEBUG 0 | |
40 | #endif | |
41 | ||
7af0fc99 SPB |
42 | #define DPRINT_L1(fmt, args...) \ |
43 | do { \ | |
44 | if (SDHC_DEBUG) { \ | |
45 | fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ | |
46 | } \ | |
47 | } while (0) | |
48 | #define DPRINT_L2(fmt, args...) \ | |
49 | do { \ | |
50 | if (SDHC_DEBUG > 1) { \ | |
51 | fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ | |
52 | } \ | |
53 | } while (0) | |
54 | #define ERRPRINT(fmt, args...) \ | |
55 | do { \ | |
56 | if (SDHC_DEBUG) { \ | |
57 | fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \ | |
58 | } \ | |
59 | } while (0) | |
d7dfca08 | 60 | |
40bbc194 PM |
61 | #define TYPE_SDHCI_BUS "sdhci-bus" |
62 | #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) | |
63 | ||
d7dfca08 IM |
64 | /* Default SD/MMC host controller features information, which will be |
65 | * presented in CAPABILITIES register of generic SD host controller at reset. | |
66 | * If not stated otherwise: | |
67 | * 0 - not supported, 1 - supported, other - prohibited. | |
68 | */ | |
69 | #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ | |
70 | #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ | |
71 | #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ | |
72 | #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ | |
73 | #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ | |
74 | #define SDHC_CAPAB_SDMA 1ul /* SDMA support */ | |
75 | #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ | |
76 | #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ | |
77 | #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ | |
78 | /* Maximum host controller R/W buffers size | |
79 | * Possible values: 512, 1024, 2048 bytes */ | |
80 | #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul | |
81 | /* Maximum clock frequency for SDclock in MHz | |
82 | * value in range 10-63 MHz, 0 - not defined */ | |
c7ff8daa | 83 | #define SDHC_CAPAB_BASECLKFREQ 52ul |
d7dfca08 IM |
84 | #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ |
85 | /* Timeout clock frequency 1-63, 0 - not defined */ | |
c7ff8daa | 86 | #define SDHC_CAPAB_TOCLKFREQ 52ul |
d7dfca08 IM |
87 | |
88 | /* Now check all parameters and calculate CAPABILITIES REGISTER value */ | |
89 | #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ | |
90 | SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ | |
91 | SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ | |
92 | SDHC_CAPAB_TOUNIT > 1 | |
93 | #error Capabilities features can have value 0 or 1 only! | |
94 | #endif | |
95 | ||
96 | #if SDHC_CAPAB_MAXBLOCKLENGTH == 512 | |
97 | #define MAX_BLOCK_LENGTH 0ul | |
98 | #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 | |
99 | #define MAX_BLOCK_LENGTH 1ul | |
100 | #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 | |
101 | #define MAX_BLOCK_LENGTH 2ul | |
102 | #else | |
103 | #error Max host controller block size can have value 512, 1024 or 2048 only! | |
104 | #endif | |
105 | ||
106 | #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ | |
107 | SDHC_CAPAB_BASECLKFREQ > 63 | |
108 | #error SDclock frequency can have value in range 0, 10-63 only! | |
109 | #endif | |
110 | ||
111 | #if SDHC_CAPAB_TOCLKFREQ > 63 | |
112 | #error Timeout clock frequency can have value in range 0-63 only! | |
113 | #endif | |
114 | ||
115 | #define SDHC_CAPAB_REG_DEFAULT \ | |
116 | ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ | |
117 | (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ | |
118 | (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ | |
119 | (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ | |
120 | (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ | |
121 | (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ | |
122 | (SDHC_CAPAB_TOCLKFREQ)) | |
123 | ||
8b20aefa | 124 | #define MASK_TRNMOD 0x0037 |
d7dfca08 IM |
125 | #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) |
126 | ||
127 | static uint8_t sdhci_slotint(SDHCIState *s) | |
128 | { | |
129 | return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || | |
130 | ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || | |
131 | ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); | |
132 | } | |
133 | ||
134 | static inline void sdhci_update_irq(SDHCIState *s) | |
135 | { | |
136 | qemu_set_irq(s->irq, sdhci_slotint(s)); | |
137 | } | |
138 | ||
139 | static void sdhci_raise_insertion_irq(void *opaque) | |
140 | { | |
141 | SDHCIState *s = (SDHCIState *)opaque; | |
142 | ||
143 | if (s->norintsts & SDHC_NIS_REMOVE) { | |
bc72ad67 AB |
144 | timer_mod(s->insert_timer, |
145 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); | |
d7dfca08 IM |
146 | } else { |
147 | s->prnsts = 0x1ff0000; | |
148 | if (s->norintstsen & SDHC_NISEN_INSERT) { | |
149 | s->norintsts |= SDHC_NIS_INSERT; | |
150 | } | |
151 | sdhci_update_irq(s); | |
152 | } | |
153 | } | |
154 | ||
40bbc194 | 155 | static void sdhci_set_inserted(DeviceState *dev, bool level) |
d7dfca08 | 156 | { |
40bbc194 | 157 | SDHCIState *s = (SDHCIState *)dev; |
d7dfca08 IM |
158 | DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); |
159 | ||
160 | if ((s->norintsts & SDHC_NIS_REMOVE) && level) { | |
161 | /* Give target some time to notice card ejection */ | |
bc72ad67 AB |
162 | timer_mod(s->insert_timer, |
163 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); | |
d7dfca08 IM |
164 | } else { |
165 | if (level) { | |
166 | s->prnsts = 0x1ff0000; | |
167 | if (s->norintstsen & SDHC_NISEN_INSERT) { | |
168 | s->norintsts |= SDHC_NIS_INSERT; | |
169 | } | |
170 | } else { | |
171 | s->prnsts = 0x1fa0000; | |
172 | s->pwrcon &= ~SDHC_POWER_ON; | |
173 | s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; | |
174 | if (s->norintstsen & SDHC_NISEN_REMOVE) { | |
175 | s->norintsts |= SDHC_NIS_REMOVE; | |
176 | } | |
177 | } | |
178 | sdhci_update_irq(s); | |
179 | } | |
180 | } | |
181 | ||
40bbc194 | 182 | static void sdhci_set_readonly(DeviceState *dev, bool level) |
d7dfca08 | 183 | { |
40bbc194 | 184 | SDHCIState *s = (SDHCIState *)dev; |
d7dfca08 IM |
185 | |
186 | if (level) { | |
187 | s->prnsts &= ~SDHC_WRITE_PROTECT; | |
188 | } else { | |
189 | /* Write enabled */ | |
190 | s->prnsts |= SDHC_WRITE_PROTECT; | |
191 | } | |
192 | } | |
193 | ||
194 | static void sdhci_reset(SDHCIState *s) | |
195 | { | |
40bbc194 PM |
196 | DeviceState *dev = DEVICE(s); |
197 | ||
bc72ad67 AB |
198 | timer_del(s->insert_timer); |
199 | timer_del(s->transfer_timer); | |
d7dfca08 IM |
200 | /* Set all registers to 0. Capabilities registers are not cleared |
201 | * and assumed to always preserve their value, given to them during | |
202 | * initialization */ | |
203 | memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); | |
204 | ||
5c1bc9a2 AB |
205 | /* Reset other state based on current card insertion/readonly status */ |
206 | sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); | |
207 | sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); | |
40bbc194 | 208 | |
d7dfca08 IM |
209 | s->data_count = 0; |
210 | s->stopped_state = sdhc_not_stopped; | |
0a7ac9f9 | 211 | s->pending_insert_state = false; |
d7dfca08 IM |
212 | } |
213 | ||
8b41c305 PM |
214 | static void sdhci_poweron_reset(DeviceState *dev) |
215 | { | |
216 | /* QOM (ie power-on) reset. This is identical to reset | |
217 | * commanded via device register apart from handling of the | |
218 | * 'pending insert on powerup' quirk. | |
219 | */ | |
220 | SDHCIState *s = (SDHCIState *)dev; | |
221 | ||
222 | sdhci_reset(s); | |
223 | ||
224 | if (s->pending_insert_quirk) { | |
225 | s->pending_insert_state = true; | |
226 | } | |
227 | } | |
228 | ||
d368ba43 | 229 | static void sdhci_data_transfer(void *opaque); |
d7dfca08 IM |
230 | |
231 | static void sdhci_send_command(SDHCIState *s) | |
232 | { | |
233 | SDRequest request; | |
234 | uint8_t response[16]; | |
235 | int rlen; | |
236 | ||
237 | s->errintsts = 0; | |
238 | s->acmd12errsts = 0; | |
239 | request.cmd = s->cmdreg >> 8; | |
240 | request.arg = s->argument; | |
241 | DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); | |
40bbc194 | 242 | rlen = sdbus_do_command(&s->sdbus, &request, response); |
d7dfca08 IM |
243 | |
244 | if (s->cmdreg & SDHC_CMD_RESPONSE) { | |
245 | if (rlen == 4) { | |
246 | s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | | |
247 | (response[2] << 8) | response[3]; | |
248 | s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; | |
249 | DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); | |
250 | } else if (rlen == 16) { | |
251 | s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | | |
252 | (response[13] << 8) | response[14]; | |
253 | s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | | |
254 | (response[9] << 8) | response[10]; | |
255 | s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | | |
256 | (response[5] << 8) | response[6]; | |
257 | s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | | |
258 | response[2]; | |
259 | DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." | |
260 | "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", | |
261 | s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); | |
262 | } else { | |
263 | ERRPRINT("Timeout waiting for command response\n"); | |
264 | if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { | |
265 | s->errintsts |= SDHC_EIS_CMDTIMEOUT; | |
266 | s->norintsts |= SDHC_NIS_ERR; | |
267 | } | |
268 | } | |
269 | ||
270 | if ((s->norintstsen & SDHC_NISEN_TRSCMP) && | |
271 | (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { | |
272 | s->norintsts |= SDHC_NIS_TRSCMP; | |
273 | } | |
d7dfca08 IM |
274 | } |
275 | ||
276 | if (s->norintstsen & SDHC_NISEN_CMDCMP) { | |
277 | s->norintsts |= SDHC_NIS_CMDCMP; | |
278 | } | |
279 | ||
280 | sdhci_update_irq(s); | |
281 | ||
282 | if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { | |
656f416c | 283 | s->data_count = 0; |
d368ba43 | 284 | sdhci_data_transfer(s); |
d7dfca08 IM |
285 | } |
286 | } | |
287 | ||
288 | static void sdhci_end_transfer(SDHCIState *s) | |
289 | { | |
290 | /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ | |
291 | if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { | |
292 | SDRequest request; | |
293 | uint8_t response[16]; | |
294 | ||
295 | request.cmd = 0x0C; | |
296 | request.arg = 0; | |
297 | DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); | |
40bbc194 | 298 | sdbus_do_command(&s->sdbus, &request, response); |
d7dfca08 IM |
299 | /* Auto CMD12 response goes to the upper Response register */ |
300 | s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | | |
301 | (response[2] << 8) | response[3]; | |
302 | } | |
303 | ||
304 | s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | | |
305 | SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | | |
306 | SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); | |
307 | ||
308 | if (s->norintstsen & SDHC_NISEN_TRSCMP) { | |
309 | s->norintsts |= SDHC_NIS_TRSCMP; | |
310 | } | |
311 | ||
312 | sdhci_update_irq(s); | |
313 | } | |
314 | ||
315 | /* | |
316 | * Programmed i/o data transfer | |
317 | */ | |
318 | ||
319 | /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ | |
320 | static void sdhci_read_block_from_card(SDHCIState *s) | |
321 | { | |
322 | int index = 0; | |
323 | ||
324 | if ((s->trnmod & SDHC_TRNS_MULTI) && | |
325 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { | |
326 | return; | |
327 | } | |
328 | ||
329 | for (index = 0; index < (s->blksize & 0x0fff); index++) { | |
40bbc194 | 330 | s->fifo_buffer[index] = sdbus_read_data(&s->sdbus); |
d7dfca08 IM |
331 | } |
332 | ||
333 | /* New data now available for READ through Buffer Port Register */ | |
334 | s->prnsts |= SDHC_DATA_AVAILABLE; | |
335 | if (s->norintstsen & SDHC_NISEN_RBUFRDY) { | |
336 | s->norintsts |= SDHC_NIS_RBUFRDY; | |
337 | } | |
338 | ||
339 | /* Clear DAT line active status if that was the last block */ | |
340 | if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || | |
341 | ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { | |
342 | s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; | |
343 | } | |
344 | ||
345 | /* If stop at block gap request was set and it's not the last block of | |
346 | * data - generate Block Event interrupt */ | |
347 | if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && | |
348 | s->blkcnt != 1) { | |
349 | s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; | |
350 | if (s->norintstsen & SDHC_EISEN_BLKGAP) { | |
351 | s->norintsts |= SDHC_EIS_BLKGAP; | |
352 | } | |
353 | } | |
354 | ||
355 | sdhci_update_irq(s); | |
356 | } | |
357 | ||
358 | /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ | |
359 | static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) | |
360 | { | |
361 | uint32_t value = 0; | |
362 | int i; | |
363 | ||
364 | /* first check that a valid data exists in host controller input buffer */ | |
365 | if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { | |
366 | ERRPRINT("Trying to read from empty buffer\n"); | |
367 | return 0; | |
368 | } | |
369 | ||
370 | for (i = 0; i < size; i++) { | |
371 | value |= s->fifo_buffer[s->data_count] << i * 8; | |
372 | s->data_count++; | |
373 | /* check if we've read all valid data (blksize bytes) from buffer */ | |
374 | if ((s->data_count) >= (s->blksize & 0x0fff)) { | |
375 | DPRINT_L2("All %u bytes of data have been read from input buffer\n", | |
376 | s->data_count); | |
377 | s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ | |
378 | s->data_count = 0; /* next buff read must start at position [0] */ | |
379 | ||
380 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { | |
381 | s->blkcnt--; | |
382 | } | |
383 | ||
384 | /* if that was the last block of data */ | |
385 | if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || | |
386 | ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || | |
387 | /* stop at gap request */ | |
388 | (s->stopped_state == sdhc_gap_read && | |
389 | !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { | |
d368ba43 | 390 | sdhci_end_transfer(s); |
d7dfca08 | 391 | } else { /* if there are more data, read next block from card */ |
d368ba43 | 392 | sdhci_read_block_from_card(s); |
d7dfca08 IM |
393 | } |
394 | break; | |
395 | } | |
396 | } | |
397 | ||
398 | return value; | |
399 | } | |
400 | ||
401 | /* Write data from host controller FIFO to card */ | |
402 | static void sdhci_write_block_to_card(SDHCIState *s) | |
403 | { | |
404 | int index = 0; | |
405 | ||
406 | if (s->prnsts & SDHC_SPACE_AVAILABLE) { | |
407 | if (s->norintstsen & SDHC_NISEN_WBUFRDY) { | |
408 | s->norintsts |= SDHC_NIS_WBUFRDY; | |
409 | } | |
410 | sdhci_update_irq(s); | |
411 | return; | |
412 | } | |
413 | ||
414 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { | |
415 | if (s->blkcnt == 0) { | |
416 | return; | |
417 | } else { | |
418 | s->blkcnt--; | |
419 | } | |
420 | } | |
421 | ||
422 | for (index = 0; index < (s->blksize & 0x0fff); index++) { | |
40bbc194 | 423 | sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); |
d7dfca08 IM |
424 | } |
425 | ||
426 | /* Next data can be written through BUFFER DATORT register */ | |
427 | s->prnsts |= SDHC_SPACE_AVAILABLE; | |
d7dfca08 IM |
428 | |
429 | /* Finish transfer if that was the last block of data */ | |
430 | if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || | |
431 | ((s->trnmod & SDHC_TRNS_MULTI) && | |
432 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { | |
d368ba43 | 433 | sdhci_end_transfer(s); |
dcdb4cd8 PC |
434 | } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { |
435 | s->norintsts |= SDHC_NIS_WBUFRDY; | |
d7dfca08 IM |
436 | } |
437 | ||
438 | /* Generate Block Gap Event if requested and if not the last block */ | |
439 | if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && | |
440 | s->blkcnt > 0) { | |
441 | s->prnsts &= ~SDHC_DOING_WRITE; | |
442 | if (s->norintstsen & SDHC_EISEN_BLKGAP) { | |
443 | s->norintsts |= SDHC_EIS_BLKGAP; | |
444 | } | |
d368ba43 | 445 | sdhci_end_transfer(s); |
d7dfca08 IM |
446 | } |
447 | ||
448 | sdhci_update_irq(s); | |
449 | } | |
450 | ||
451 | /* Write @size bytes of @value data to host controller @s Buffer Data Port | |
452 | * register */ | |
453 | static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) | |
454 | { | |
455 | unsigned i; | |
456 | ||
457 | /* Check that there is free space left in a buffer */ | |
458 | if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { | |
459 | ERRPRINT("Can't write to data buffer: buffer full\n"); | |
460 | return; | |
461 | } | |
462 | ||
463 | for (i = 0; i < size; i++) { | |
464 | s->fifo_buffer[s->data_count] = value & 0xFF; | |
465 | s->data_count++; | |
466 | value >>= 8; | |
467 | if (s->data_count >= (s->blksize & 0x0fff)) { | |
468 | DPRINT_L2("write buffer filled with %u bytes of data\n", | |
469 | s->data_count); | |
470 | s->data_count = 0; | |
471 | s->prnsts &= ~SDHC_SPACE_AVAILABLE; | |
472 | if (s->prnsts & SDHC_DOING_WRITE) { | |
d368ba43 | 473 | sdhci_write_block_to_card(s); |
d7dfca08 IM |
474 | } |
475 | } | |
476 | } | |
477 | } | |
478 | ||
479 | /* | |
480 | * Single DMA data transfer | |
481 | */ | |
482 | ||
483 | /* Multi block SDMA transfer */ | |
484 | static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) | |
485 | { | |
486 | bool page_aligned = false; | |
487 | unsigned int n, begin; | |
488 | const uint16_t block_size = s->blksize & 0x0fff; | |
489 | uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); | |
490 | uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); | |
491 | ||
6e86d903 PP |
492 | if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { |
493 | qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); | |
494 | return; | |
495 | } | |
496 | ||
d7dfca08 IM |
497 | /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for |
498 | * possible stop at page boundary if initial address is not page aligned, | |
499 | * allow them to work properly */ | |
500 | if ((s->sdmasysad % boundary_chk) == 0) { | |
501 | page_aligned = true; | |
502 | } | |
503 | ||
504 | if (s->trnmod & SDHC_TRNS_READ) { | |
505 | s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | | |
506 | SDHC_DAT_LINE_ACTIVE; | |
507 | while (s->blkcnt) { | |
508 | if (s->data_count == 0) { | |
509 | for (n = 0; n < block_size; n++) { | |
40bbc194 | 510 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); |
d7dfca08 IM |
511 | } |
512 | } | |
513 | begin = s->data_count; | |
514 | if (((boundary_count + begin) < block_size) && page_aligned) { | |
515 | s->data_count = boundary_count + begin; | |
516 | boundary_count = 0; | |
517 | } else { | |
518 | s->data_count = block_size; | |
519 | boundary_count -= block_size - begin; | |
520 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { | |
521 | s->blkcnt--; | |
522 | } | |
523 | } | |
df32fd1c | 524 | dma_memory_write(&address_space_memory, s->sdmasysad, |
d7dfca08 IM |
525 | &s->fifo_buffer[begin], s->data_count - begin); |
526 | s->sdmasysad += s->data_count - begin; | |
527 | if (s->data_count == block_size) { | |
528 | s->data_count = 0; | |
529 | } | |
530 | if (page_aligned && boundary_count == 0) { | |
531 | break; | |
532 | } | |
533 | } | |
534 | } else { | |
535 | s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | | |
536 | SDHC_DAT_LINE_ACTIVE; | |
537 | while (s->blkcnt) { | |
538 | begin = s->data_count; | |
539 | if (((boundary_count + begin) < block_size) && page_aligned) { | |
540 | s->data_count = boundary_count + begin; | |
541 | boundary_count = 0; | |
542 | } else { | |
543 | s->data_count = block_size; | |
544 | boundary_count -= block_size - begin; | |
545 | } | |
df32fd1c | 546 | dma_memory_read(&address_space_memory, s->sdmasysad, |
42922105 | 547 | &s->fifo_buffer[begin], s->data_count - begin); |
d7dfca08 IM |
548 | s->sdmasysad += s->data_count - begin; |
549 | if (s->data_count == block_size) { | |
550 | for (n = 0; n < block_size; n++) { | |
40bbc194 | 551 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); |
d7dfca08 IM |
552 | } |
553 | s->data_count = 0; | |
554 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { | |
555 | s->blkcnt--; | |
556 | } | |
557 | } | |
558 | if (page_aligned && boundary_count == 0) { | |
559 | break; | |
560 | } | |
561 | } | |
562 | } | |
563 | ||
564 | if (s->blkcnt == 0) { | |
d368ba43 | 565 | sdhci_end_transfer(s); |
d7dfca08 IM |
566 | } else { |
567 | if (s->norintstsen & SDHC_NISEN_DMA) { | |
568 | s->norintsts |= SDHC_NIS_DMA; | |
569 | } | |
570 | sdhci_update_irq(s); | |
571 | } | |
572 | } | |
573 | ||
574 | /* single block SDMA transfer */ | |
d7dfca08 IM |
575 | static void sdhci_sdma_transfer_single_block(SDHCIState *s) |
576 | { | |
577 | int n; | |
578 | uint32_t datacnt = s->blksize & 0x0fff; | |
579 | ||
580 | if (s->trnmod & SDHC_TRNS_READ) { | |
581 | for (n = 0; n < datacnt; n++) { | |
40bbc194 | 582 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); |
d7dfca08 | 583 | } |
df32fd1c | 584 | dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, |
d7dfca08 IM |
585 | datacnt); |
586 | } else { | |
df32fd1c | 587 | dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, |
d7dfca08 IM |
588 | datacnt); |
589 | for (n = 0; n < datacnt; n++) { | |
40bbc194 | 590 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); |
d7dfca08 IM |
591 | } |
592 | } | |
241999bf | 593 | s->blkcnt--; |
d7dfca08 | 594 | |
d368ba43 | 595 | sdhci_end_transfer(s); |
d7dfca08 IM |
596 | } |
597 | ||
598 | typedef struct ADMADescr { | |
599 | hwaddr addr; | |
600 | uint16_t length; | |
601 | uint8_t attr; | |
602 | uint8_t incr; | |
603 | } ADMADescr; | |
604 | ||
605 | static void get_adma_description(SDHCIState *s, ADMADescr *dscr) | |
606 | { | |
607 | uint32_t adma1 = 0; | |
608 | uint64_t adma2 = 0; | |
609 | hwaddr entry_addr = (hwaddr)s->admasysaddr; | |
610 | switch (SDHC_DMA_TYPE(s->hostctl)) { | |
611 | case SDHC_CTRL_ADMA2_32: | |
df32fd1c | 612 | dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, |
d7dfca08 IM |
613 | sizeof(adma2)); |
614 | adma2 = le64_to_cpu(adma2); | |
615 | /* The spec does not specify endianness of descriptor table. | |
616 | * We currently assume that it is LE. | |
617 | */ | |
618 | dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; | |
619 | dscr->length = (uint16_t)extract64(adma2, 16, 16); | |
620 | dscr->attr = (uint8_t)extract64(adma2, 0, 7); | |
621 | dscr->incr = 8; | |
622 | break; | |
623 | case SDHC_CTRL_ADMA1_32: | |
df32fd1c | 624 | dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, |
d7dfca08 IM |
625 | sizeof(adma1)); |
626 | adma1 = le32_to_cpu(adma1); | |
627 | dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); | |
628 | dscr->attr = (uint8_t)extract32(adma1, 0, 7); | |
629 | dscr->incr = 4; | |
630 | if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { | |
631 | dscr->length = (uint16_t)extract32(adma1, 12, 16); | |
632 | } else { | |
633 | dscr->length = 4096; | |
634 | } | |
635 | break; | |
636 | case SDHC_CTRL_ADMA2_64: | |
df32fd1c | 637 | dma_memory_read(&address_space_memory, entry_addr, |
d7dfca08 | 638 | (uint8_t *)(&dscr->attr), 1); |
df32fd1c | 639 | dma_memory_read(&address_space_memory, entry_addr + 2, |
d7dfca08 IM |
640 | (uint8_t *)(&dscr->length), 2); |
641 | dscr->length = le16_to_cpu(dscr->length); | |
df32fd1c | 642 | dma_memory_read(&address_space_memory, entry_addr + 4, |
d7dfca08 IM |
643 | (uint8_t *)(&dscr->addr), 8); |
644 | dscr->attr = le64_to_cpu(dscr->attr); | |
645 | dscr->attr &= 0xfffffff8; | |
646 | dscr->incr = 12; | |
647 | break; | |
648 | } | |
649 | } | |
650 | ||
651 | /* Advanced DMA data transfer */ | |
652 | ||
653 | static void sdhci_do_adma(SDHCIState *s) | |
654 | { | |
655 | unsigned int n, begin, length; | |
656 | const uint16_t block_size = s->blksize & 0x0fff; | |
657 | ADMADescr dscr; | |
658 | int i; | |
659 | ||
660 | for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { | |
661 | s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; | |
662 | ||
663 | get_adma_description(s, &dscr); | |
664 | DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", | |
665 | dscr.addr, dscr.length, dscr.attr); | |
666 | ||
667 | if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { | |
668 | /* Indicate that error occurred in ST_FDS state */ | |
669 | s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; | |
670 | s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; | |
671 | ||
672 | /* Generate ADMA error interrupt */ | |
673 | if (s->errintstsen & SDHC_EISEN_ADMAERR) { | |
674 | s->errintsts |= SDHC_EIS_ADMAERR; | |
675 | s->norintsts |= SDHC_NIS_ERR; | |
676 | } | |
677 | ||
678 | sdhci_update_irq(s); | |
679 | return; | |
680 | } | |
681 | ||
682 | length = dscr.length ? dscr.length : 65536; | |
683 | ||
684 | switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { | |
685 | case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ | |
686 | ||
687 | if (s->trnmod & SDHC_TRNS_READ) { | |
688 | while (length) { | |
689 | if (s->data_count == 0) { | |
690 | for (n = 0; n < block_size; n++) { | |
40bbc194 | 691 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); |
d7dfca08 IM |
692 | } |
693 | } | |
694 | begin = s->data_count; | |
695 | if ((length + begin) < block_size) { | |
696 | s->data_count = length + begin; | |
697 | length = 0; | |
698 | } else { | |
699 | s->data_count = block_size; | |
700 | length -= block_size - begin; | |
701 | } | |
df32fd1c | 702 | dma_memory_write(&address_space_memory, dscr.addr, |
d7dfca08 IM |
703 | &s->fifo_buffer[begin], |
704 | s->data_count - begin); | |
705 | dscr.addr += s->data_count - begin; | |
706 | if (s->data_count == block_size) { | |
707 | s->data_count = 0; | |
708 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { | |
709 | s->blkcnt--; | |
710 | if (s->blkcnt == 0) { | |
711 | break; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | } else { | |
717 | while (length) { | |
718 | begin = s->data_count; | |
719 | if ((length + begin) < block_size) { | |
720 | s->data_count = length + begin; | |
721 | length = 0; | |
722 | } else { | |
723 | s->data_count = block_size; | |
724 | length -= block_size - begin; | |
725 | } | |
df32fd1c | 726 | dma_memory_read(&address_space_memory, dscr.addr, |
9db11cef PC |
727 | &s->fifo_buffer[begin], |
728 | s->data_count - begin); | |
d7dfca08 IM |
729 | dscr.addr += s->data_count - begin; |
730 | if (s->data_count == block_size) { | |
731 | for (n = 0; n < block_size; n++) { | |
40bbc194 | 732 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); |
d7dfca08 IM |
733 | } |
734 | s->data_count = 0; | |
735 | if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { | |
736 | s->blkcnt--; | |
737 | if (s->blkcnt == 0) { | |
738 | break; | |
739 | } | |
740 | } | |
741 | } | |
742 | } | |
743 | } | |
744 | s->admasysaddr += dscr.incr; | |
745 | break; | |
746 | case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ | |
747 | s->admasysaddr = dscr.addr; | |
be9c5dde SPB |
748 | DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n", |
749 | s->admasysaddr); | |
d7dfca08 IM |
750 | break; |
751 | default: | |
752 | s->admasysaddr += dscr.incr; | |
753 | break; | |
754 | } | |
755 | ||
1d32c26f | 756 | if (dscr.attr & SDHC_ADMA_ATTR_INT) { |
be9c5dde SPB |
757 | DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n", |
758 | s->admasysaddr); | |
1d32c26f PC |
759 | if (s->norintstsen & SDHC_NISEN_DMA) { |
760 | s->norintsts |= SDHC_NIS_DMA; | |
761 | } | |
762 | ||
763 | sdhci_update_irq(s); | |
764 | } | |
765 | ||
d7dfca08 IM |
766 | /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ |
767 | if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && | |
768 | (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { | |
769 | DPRINT_L2("ADMA transfer completed\n"); | |
770 | if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && | |
771 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && | |
772 | s->blkcnt != 0)) { | |
773 | ERRPRINT("SD/MMC host ADMA length mismatch\n"); | |
774 | s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | | |
775 | SDHC_ADMAERR_STATE_ST_TFR; | |
776 | if (s->errintstsen & SDHC_EISEN_ADMAERR) { | |
777 | ERRPRINT("Set ADMA error flag\n"); | |
778 | s->errintsts |= SDHC_EIS_ADMAERR; | |
779 | s->norintsts |= SDHC_NIS_ERR; | |
780 | } | |
781 | ||
782 | sdhci_update_irq(s); | |
783 | } | |
d368ba43 | 784 | sdhci_end_transfer(s); |
d7dfca08 IM |
785 | return; |
786 | } | |
787 | ||
d7dfca08 IM |
788 | } |
789 | ||
085d8134 | 790 | /* we have unfinished business - reschedule to continue ADMA */ |
bc72ad67 AB |
791 | timer_mod(s->transfer_timer, |
792 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); | |
d7dfca08 IM |
793 | } |
794 | ||
795 | /* Perform data transfer according to controller configuration */ | |
796 | ||
d368ba43 | 797 | static void sdhci_data_transfer(void *opaque) |
d7dfca08 | 798 | { |
d368ba43 | 799 | SDHCIState *s = (SDHCIState *)opaque; |
d7dfca08 IM |
800 | |
801 | if (s->trnmod & SDHC_TRNS_DMA) { | |
802 | switch (SDHC_DMA_TYPE(s->hostctl)) { | |
803 | case SDHC_CTRL_SDMA: | |
d7dfca08 | 804 | if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { |
d368ba43 | 805 | sdhci_sdma_transfer_single_block(s); |
d7dfca08 | 806 | } else { |
d368ba43 | 807 | sdhci_sdma_transfer_multi_blocks(s); |
d7dfca08 IM |
808 | } |
809 | ||
810 | break; | |
811 | case SDHC_CTRL_ADMA1_32: | |
812 | if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { | |
813 | ERRPRINT("ADMA1 not supported\n"); | |
814 | break; | |
815 | } | |
816 | ||
d368ba43 | 817 | sdhci_do_adma(s); |
d7dfca08 IM |
818 | break; |
819 | case SDHC_CTRL_ADMA2_32: | |
820 | if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { | |
821 | ERRPRINT("ADMA2 not supported\n"); | |
822 | break; | |
823 | } | |
824 | ||
d368ba43 | 825 | sdhci_do_adma(s); |
d7dfca08 IM |
826 | break; |
827 | case SDHC_CTRL_ADMA2_64: | |
828 | if (!(s->capareg & SDHC_CAN_DO_ADMA2) || | |
829 | !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { | |
830 | ERRPRINT("64 bit ADMA not supported\n"); | |
831 | break; | |
832 | } | |
833 | ||
d368ba43 | 834 | sdhci_do_adma(s); |
d7dfca08 IM |
835 | break; |
836 | default: | |
837 | ERRPRINT("Unsupported DMA type\n"); | |
838 | break; | |
839 | } | |
840 | } else { | |
40bbc194 | 841 | if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { |
d7dfca08 IM |
842 | s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | |
843 | SDHC_DAT_LINE_ACTIVE; | |
d368ba43 | 844 | sdhci_read_block_from_card(s); |
d7dfca08 IM |
845 | } else { |
846 | s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | | |
847 | SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; | |
d368ba43 | 848 | sdhci_write_block_to_card(s); |
d7dfca08 IM |
849 | } |
850 | } | |
851 | } | |
852 | ||
853 | static bool sdhci_can_issue_command(SDHCIState *s) | |
854 | { | |
6890a695 | 855 | if (!SDHC_CLOCK_IS_ON(s->clkcon) || |
d7dfca08 IM |
856 | (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && |
857 | ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || | |
858 | ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && | |
859 | !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { | |
860 | return false; | |
861 | } | |
862 | ||
863 | return true; | |
864 | } | |
865 | ||
866 | /* The Buffer Data Port register must be accessed in sequential and | |
867 | * continuous manner */ | |
868 | static inline bool | |
869 | sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) | |
870 | { | |
871 | if ((s->data_count & 0x3) != byte_num) { | |
872 | ERRPRINT("Non-sequential access to Buffer Data Port register" | |
873 | "is prohibited\n"); | |
874 | return false; | |
875 | } | |
876 | return true; | |
877 | } | |
878 | ||
d368ba43 | 879 | static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) |
d7dfca08 | 880 | { |
d368ba43 | 881 | SDHCIState *s = (SDHCIState *)opaque; |
d7dfca08 IM |
882 | uint32_t ret = 0; |
883 | ||
884 | switch (offset & ~0x3) { | |
885 | case SDHC_SYSAD: | |
886 | ret = s->sdmasysad; | |
887 | break; | |
888 | case SDHC_BLKSIZE: | |
889 | ret = s->blksize | (s->blkcnt << 16); | |
890 | break; | |
891 | case SDHC_ARGUMENT: | |
892 | ret = s->argument; | |
893 | break; | |
894 | case SDHC_TRNMOD: | |
895 | ret = s->trnmod | (s->cmdreg << 16); | |
896 | break; | |
897 | case SDHC_RSPREG0 ... SDHC_RSPREG3: | |
898 | ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; | |
899 | break; | |
900 | case SDHC_BDATA: | |
901 | if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { | |
d368ba43 KC |
902 | ret = sdhci_read_dataport(s, size); |
903 | DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, | |
677ff2ae | 904 | ret, ret); |
d7dfca08 IM |
905 | return ret; |
906 | } | |
907 | break; | |
908 | case SDHC_PRNSTS: | |
909 | ret = s->prnsts; | |
910 | break; | |
911 | case SDHC_HOSTCTL: | |
912 | ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | | |
913 | (s->wakcon << 24); | |
914 | break; | |
915 | case SDHC_CLKCON: | |
916 | ret = s->clkcon | (s->timeoutcon << 16); | |
917 | break; | |
918 | case SDHC_NORINTSTS: | |
919 | ret = s->norintsts | (s->errintsts << 16); | |
920 | break; | |
921 | case SDHC_NORINTSTSEN: | |
922 | ret = s->norintstsen | (s->errintstsen << 16); | |
923 | break; | |
924 | case SDHC_NORINTSIGEN: | |
925 | ret = s->norintsigen | (s->errintsigen << 16); | |
926 | break; | |
927 | case SDHC_ACMD12ERRSTS: | |
928 | ret = s->acmd12errsts; | |
929 | break; | |
930 | case SDHC_CAPAREG: | |
931 | ret = s->capareg; | |
932 | break; | |
933 | case SDHC_MAXCURR: | |
934 | ret = s->maxcurr; | |
935 | break; | |
936 | case SDHC_ADMAERR: | |
937 | ret = s->admaerr; | |
938 | break; | |
939 | case SDHC_ADMASYSADDR: | |
940 | ret = (uint32_t)s->admasysaddr; | |
941 | break; | |
942 | case SDHC_ADMASYSADDR + 4: | |
943 | ret = (uint32_t)(s->admasysaddr >> 32); | |
944 | break; | |
945 | case SDHC_SLOT_INT_STATUS: | |
946 | ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); | |
947 | break; | |
948 | default: | |
d368ba43 | 949 | ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset); |
d7dfca08 IM |
950 | break; |
951 | } | |
952 | ||
953 | ret >>= (offset & 0x3) * 8; | |
954 | ret &= (1ULL << (size * 8)) - 1; | |
d368ba43 | 955 | DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret); |
d7dfca08 IM |
956 | return ret; |
957 | } | |
958 | ||
959 | static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) | |
960 | { | |
961 | if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { | |
962 | return; | |
963 | } | |
964 | s->blkgap = value & SDHC_STOP_AT_GAP_REQ; | |
965 | ||
966 | if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && | |
967 | (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { | |
968 | if (s->stopped_state == sdhc_gap_read) { | |
969 | s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; | |
d368ba43 | 970 | sdhci_read_block_from_card(s); |
d7dfca08 IM |
971 | } else { |
972 | s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; | |
d368ba43 | 973 | sdhci_write_block_to_card(s); |
d7dfca08 IM |
974 | } |
975 | s->stopped_state = sdhc_not_stopped; | |
976 | } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { | |
977 | if (s->prnsts & SDHC_DOING_READ) { | |
978 | s->stopped_state = sdhc_gap_read; | |
979 | } else if (s->prnsts & SDHC_DOING_WRITE) { | |
980 | s->stopped_state = sdhc_gap_write; | |
981 | } | |
982 | } | |
983 | } | |
984 | ||
985 | static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) | |
986 | { | |
987 | switch (value) { | |
988 | case SDHC_RESET_ALL: | |
d368ba43 | 989 | sdhci_reset(s); |
d7dfca08 IM |
990 | break; |
991 | case SDHC_RESET_CMD: | |
992 | s->prnsts &= ~SDHC_CMD_INHIBIT; | |
993 | s->norintsts &= ~SDHC_NIS_CMDCMP; | |
994 | break; | |
995 | case SDHC_RESET_DATA: | |
996 | s->data_count = 0; | |
997 | s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | | |
998 | SDHC_DOING_READ | SDHC_DOING_WRITE | | |
999 | SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); | |
1000 | s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); | |
1001 | s->stopped_state = sdhc_not_stopped; | |
1002 | s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | | |
1003 | SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); | |
1004 | break; | |
1005 | } | |
1006 | } | |
1007 | ||
1008 | static void | |
d368ba43 | 1009 | sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) |
d7dfca08 | 1010 | { |
d368ba43 | 1011 | SDHCIState *s = (SDHCIState *)opaque; |
d7dfca08 IM |
1012 | unsigned shift = 8 * (offset & 0x3); |
1013 | uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); | |
d368ba43 | 1014 | uint32_t value = val; |
d7dfca08 IM |
1015 | value <<= shift; |
1016 | ||
1017 | switch (offset & ~0x3) { | |
1018 | case SDHC_SYSAD: | |
1019 | s->sdmasysad = (s->sdmasysad & mask) | value; | |
1020 | MASKED_WRITE(s->sdmasysad, mask, value); | |
1021 | /* Writing to last byte of sdmasysad might trigger transfer */ | |
1022 | if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && | |
1023 | s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { | |
45ba9f76 PP |
1024 | if (s->trnmod & SDHC_TRNS_MULTI) { |
1025 | sdhci_sdma_transfer_multi_blocks(s); | |
1026 | } else { | |
1027 | sdhci_sdma_transfer_single_block(s); | |
1028 | } | |
d7dfca08 IM |
1029 | } |
1030 | break; | |
1031 | case SDHC_BLKSIZE: | |
1032 | if (!TRANSFERRING_DATA(s->prnsts)) { | |
1033 | MASKED_WRITE(s->blksize, mask, value); | |
1034 | MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); | |
1035 | } | |
9201bb9a AF |
1036 | |
1037 | /* Limit block size to the maximum buffer size */ | |
1038 | if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { | |
1039 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ | |
1040 | "the maximum buffer 0x%x", __func__, s->blksize, | |
1041 | s->buf_maxsz); | |
1042 | ||
1043 | s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); | |
1044 | } | |
1045 | ||
d7dfca08 IM |
1046 | break; |
1047 | case SDHC_ARGUMENT: | |
1048 | MASKED_WRITE(s->argument, mask, value); | |
1049 | break; | |
1050 | case SDHC_TRNMOD: | |
1051 | /* DMA can be enabled only if it is supported as indicated by | |
1052 | * capabilities register */ | |
1053 | if (!(s->capareg & SDHC_CAN_DO_DMA)) { | |
1054 | value &= ~SDHC_TRNS_DMA; | |
1055 | } | |
8b20aefa | 1056 | MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD); |
d7dfca08 IM |
1057 | MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); |
1058 | ||
1059 | /* Writing to the upper byte of CMDREG triggers SD command generation */ | |
d368ba43 | 1060 | if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { |
d7dfca08 IM |
1061 | break; |
1062 | } | |
1063 | ||
d368ba43 | 1064 | sdhci_send_command(s); |
d7dfca08 IM |
1065 | break; |
1066 | case SDHC_BDATA: | |
1067 | if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { | |
d368ba43 | 1068 | sdhci_write_dataport(s, value >> shift, size); |
d7dfca08 IM |
1069 | } |
1070 | break; | |
1071 | case SDHC_HOSTCTL: | |
1072 | if (!(mask & 0xFF0000)) { | |
1073 | sdhci_blkgap_write(s, value >> 16); | |
1074 | } | |
1075 | MASKED_WRITE(s->hostctl, mask, value); | |
1076 | MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); | |
1077 | MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); | |
1078 | if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || | |
1079 | !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { | |
1080 | s->pwrcon &= ~SDHC_POWER_ON; | |
1081 | } | |
1082 | break; | |
1083 | case SDHC_CLKCON: | |
1084 | if (!(mask & 0xFF000000)) { | |
1085 | sdhci_reset_write(s, value >> 24); | |
1086 | } | |
1087 | MASKED_WRITE(s->clkcon, mask, value); | |
1088 | MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); | |
1089 | if (s->clkcon & SDHC_CLOCK_INT_EN) { | |
1090 | s->clkcon |= SDHC_CLOCK_INT_STABLE; | |
1091 | } else { | |
1092 | s->clkcon &= ~SDHC_CLOCK_INT_STABLE; | |
1093 | } | |
1094 | break; | |
1095 | case SDHC_NORINTSTS: | |
1096 | if (s->norintstsen & SDHC_NISEN_CARDINT) { | |
1097 | value &= ~SDHC_NIS_CARDINT; | |
1098 | } | |
1099 | s->norintsts &= mask | ~value; | |
1100 | s->errintsts &= (mask >> 16) | ~(value >> 16); | |
1101 | if (s->errintsts) { | |
1102 | s->norintsts |= SDHC_NIS_ERR; | |
1103 | } else { | |
1104 | s->norintsts &= ~SDHC_NIS_ERR; | |
1105 | } | |
1106 | sdhci_update_irq(s); | |
1107 | break; | |
1108 | case SDHC_NORINTSTSEN: | |
1109 | MASKED_WRITE(s->norintstsen, mask, value); | |
1110 | MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); | |
1111 | s->norintsts &= s->norintstsen; | |
1112 | s->errintsts &= s->errintstsen; | |
1113 | if (s->errintsts) { | |
1114 | s->norintsts |= SDHC_NIS_ERR; | |
1115 | } else { | |
1116 | s->norintsts &= ~SDHC_NIS_ERR; | |
1117 | } | |
0a7ac9f9 AB |
1118 | /* Quirk for Raspberry Pi: pending card insert interrupt |
1119 | * appears when first enabled after power on */ | |
1120 | if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { | |
1121 | assert(s->pending_insert_quirk); | |
1122 | s->norintsts |= SDHC_NIS_INSERT; | |
1123 | s->pending_insert_state = false; | |
1124 | } | |
d7dfca08 IM |
1125 | sdhci_update_irq(s); |
1126 | break; | |
1127 | case SDHC_NORINTSIGEN: | |
1128 | MASKED_WRITE(s->norintsigen, mask, value); | |
1129 | MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); | |
1130 | sdhci_update_irq(s); | |
1131 | break; | |
1132 | case SDHC_ADMAERR: | |
1133 | MASKED_WRITE(s->admaerr, mask, value); | |
1134 | break; | |
1135 | case SDHC_ADMASYSADDR: | |
1136 | s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | | |
1137 | (uint64_t)mask)) | (uint64_t)value; | |
1138 | break; | |
1139 | case SDHC_ADMASYSADDR + 4: | |
1140 | s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | | |
1141 | ((uint64_t)mask << 32))) | ((uint64_t)value << 32); | |
1142 | break; | |
1143 | case SDHC_FEAER: | |
1144 | s->acmd12errsts |= value; | |
1145 | s->errintsts |= (value >> 16) & s->errintstsen; | |
1146 | if (s->acmd12errsts) { | |
1147 | s->errintsts |= SDHC_EIS_CMD12ERR; | |
1148 | } | |
1149 | if (s->errintsts) { | |
1150 | s->norintsts |= SDHC_NIS_ERR; | |
1151 | } | |
1152 | sdhci_update_irq(s); | |
1153 | break; | |
1154 | default: | |
1155 | ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", | |
d368ba43 | 1156 | size, (int)offset, value >> shift, value >> shift); |
d7dfca08 IM |
1157 | break; |
1158 | } | |
1159 | DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", | |
d368ba43 | 1160 | size, (int)offset, value >> shift, value >> shift); |
d7dfca08 IM |
1161 | } |
1162 | ||
1163 | static const MemoryRegionOps sdhci_mmio_ops = { | |
d368ba43 KC |
1164 | .read = sdhci_read, |
1165 | .write = sdhci_write, | |
d7dfca08 IM |
1166 | .valid = { |
1167 | .min_access_size = 1, | |
1168 | .max_access_size = 4, | |
1169 | .unaligned = false | |
1170 | }, | |
1171 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1172 | }; | |
1173 | ||
1174 | static inline unsigned int sdhci_get_fifolen(SDHCIState *s) | |
1175 | { | |
1176 | switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { | |
1177 | case 0: | |
1178 | return 512; | |
1179 | case 1: | |
1180 | return 1024; | |
1181 | case 2: | |
1182 | return 2048; | |
1183 | default: | |
1184 | hw_error("SDHC: unsupported value for maximum block size\n"); | |
1185 | return 0; | |
1186 | } | |
1187 | } | |
1188 | ||
b635d98c PMD |
1189 | /* --- qdev common --- */ |
1190 | ||
1191 | #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ | |
1192 | /* Capabilities registers provide information on supported features | |
1193 | * of this specific host controller implementation */ \ | |
1194 | DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ | |
1195 | DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0) | |
1196 | ||
40bbc194 | 1197 | static void sdhci_initfn(SDHCIState *s) |
d7dfca08 | 1198 | { |
40bbc194 PM |
1199 | qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), |
1200 | TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); | |
d7dfca08 | 1201 | |
bc72ad67 | 1202 | s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); |
d368ba43 | 1203 | s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); |
d7dfca08 IM |
1204 | } |
1205 | ||
7302dcd6 | 1206 | static void sdhci_uninitfn(SDHCIState *s) |
d7dfca08 | 1207 | { |
bc72ad67 AB |
1208 | timer_del(s->insert_timer); |
1209 | timer_free(s->insert_timer); | |
1210 | timer_del(s->transfer_timer); | |
1211 | timer_free(s->transfer_timer); | |
d7dfca08 | 1212 | |
012aef07 MA |
1213 | g_free(s->fifo_buffer); |
1214 | s->fifo_buffer = NULL; | |
d7dfca08 IM |
1215 | } |
1216 | ||
25367498 PMD |
1217 | static void sdhci_common_realize(SDHCIState *s, Error **errp) |
1218 | { | |
1219 | s->buf_maxsz = sdhci_get_fifolen(s); | |
1220 | s->fifo_buffer = g_malloc0(s->buf_maxsz); | |
1221 | ||
1222 | memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", | |
1223 | SDHC_REGISTERS_MAP_SIZE); | |
1224 | } | |
1225 | ||
0a7ac9f9 AB |
1226 | static bool sdhci_pending_insert_vmstate_needed(void *opaque) |
1227 | { | |
1228 | SDHCIState *s = opaque; | |
1229 | ||
1230 | return s->pending_insert_state; | |
1231 | } | |
1232 | ||
1233 | static const VMStateDescription sdhci_pending_insert_vmstate = { | |
1234 | .name = "sdhci/pending-insert", | |
1235 | .version_id = 1, | |
1236 | .minimum_version_id = 1, | |
1237 | .needed = sdhci_pending_insert_vmstate_needed, | |
1238 | .fields = (VMStateField[]) { | |
1239 | VMSTATE_BOOL(pending_insert_state, SDHCIState), | |
1240 | VMSTATE_END_OF_LIST() | |
1241 | }, | |
1242 | }; | |
1243 | ||
d7dfca08 IM |
1244 | const VMStateDescription sdhci_vmstate = { |
1245 | .name = "sdhci", | |
1246 | .version_id = 1, | |
1247 | .minimum_version_id = 1, | |
35d08458 | 1248 | .fields = (VMStateField[]) { |
d7dfca08 IM |
1249 | VMSTATE_UINT32(sdmasysad, SDHCIState), |
1250 | VMSTATE_UINT16(blksize, SDHCIState), | |
1251 | VMSTATE_UINT16(blkcnt, SDHCIState), | |
1252 | VMSTATE_UINT32(argument, SDHCIState), | |
1253 | VMSTATE_UINT16(trnmod, SDHCIState), | |
1254 | VMSTATE_UINT16(cmdreg, SDHCIState), | |
1255 | VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), | |
1256 | VMSTATE_UINT32(prnsts, SDHCIState), | |
1257 | VMSTATE_UINT8(hostctl, SDHCIState), | |
1258 | VMSTATE_UINT8(pwrcon, SDHCIState), | |
1259 | VMSTATE_UINT8(blkgap, SDHCIState), | |
1260 | VMSTATE_UINT8(wakcon, SDHCIState), | |
1261 | VMSTATE_UINT16(clkcon, SDHCIState), | |
1262 | VMSTATE_UINT8(timeoutcon, SDHCIState), | |
1263 | VMSTATE_UINT8(admaerr, SDHCIState), | |
1264 | VMSTATE_UINT16(norintsts, SDHCIState), | |
1265 | VMSTATE_UINT16(errintsts, SDHCIState), | |
1266 | VMSTATE_UINT16(norintstsen, SDHCIState), | |
1267 | VMSTATE_UINT16(errintstsen, SDHCIState), | |
1268 | VMSTATE_UINT16(norintsigen, SDHCIState), | |
1269 | VMSTATE_UINT16(errintsigen, SDHCIState), | |
1270 | VMSTATE_UINT16(acmd12errsts, SDHCIState), | |
1271 | VMSTATE_UINT16(data_count, SDHCIState), | |
1272 | VMSTATE_UINT64(admasysaddr, SDHCIState), | |
1273 | VMSTATE_UINT8(stopped_state, SDHCIState), | |
59046ec2 | 1274 | VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), |
e720677e PB |
1275 | VMSTATE_TIMER_PTR(insert_timer, SDHCIState), |
1276 | VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), | |
d7dfca08 | 1277 | VMSTATE_END_OF_LIST() |
0a7ac9f9 AB |
1278 | }, |
1279 | .subsections = (const VMStateDescription*[]) { | |
1280 | &sdhci_pending_insert_vmstate, | |
1281 | NULL | |
1282 | }, | |
d7dfca08 IM |
1283 | }; |
1284 | ||
1c92c505 PMD |
1285 | static void sdhci_common_class_init(ObjectClass *klass, void *data) |
1286 | { | |
1287 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1288 | ||
1289 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | |
1290 | dc->vmsd = &sdhci_vmstate; | |
1291 | dc->reset = sdhci_poweron_reset; | |
1292 | } | |
1293 | ||
b635d98c PMD |
1294 | /* --- qdev PCI --- */ |
1295 | ||
5ec911c3 | 1296 | static Property sdhci_pci_properties[] = { |
b635d98c | 1297 | DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), |
d7dfca08 IM |
1298 | DEFINE_PROP_END_OF_LIST(), |
1299 | }; | |
1300 | ||
9af21dbe | 1301 | static void sdhci_pci_realize(PCIDevice *dev, Error **errp) |
224d10ff KC |
1302 | { |
1303 | SDHCIState *s = PCI_SDHCI(dev); | |
25367498 PMD |
1304 | |
1305 | sdhci_initfn(s); | |
1306 | sdhci_common_realize(s, errp); | |
1307 | if (errp && *errp) { | |
1308 | return; | |
1309 | } | |
1310 | ||
224d10ff KC |
1311 | dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ |
1312 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ | |
224d10ff | 1313 | s->irq = pci_allocate_irq(dev); |
224d10ff | 1314 | pci_register_bar(dev, 0, 0, &s->iomem); |
224d10ff KC |
1315 | } |
1316 | ||
1317 | static void sdhci_pci_exit(PCIDevice *dev) | |
1318 | { | |
1319 | SDHCIState *s = PCI_SDHCI(dev); | |
1320 | sdhci_uninitfn(s); | |
1321 | } | |
1322 | ||
1323 | static void sdhci_pci_class_init(ObjectClass *klass, void *data) | |
1324 | { | |
1325 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1326 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1327 | ||
9af21dbe | 1328 | k->realize = sdhci_pci_realize; |
224d10ff KC |
1329 | k->exit = sdhci_pci_exit; |
1330 | k->vendor_id = PCI_VENDOR_ID_REDHAT; | |
1331 | k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; | |
1332 | k->class_id = PCI_CLASS_SYSTEM_SDHCI; | |
5ec911c3 | 1333 | dc->props = sdhci_pci_properties; |
1c92c505 PMD |
1334 | |
1335 | sdhci_common_class_init(klass, data); | |
224d10ff KC |
1336 | } |
1337 | ||
1338 | static const TypeInfo sdhci_pci_info = { | |
1339 | .name = TYPE_PCI_SDHCI, | |
1340 | .parent = TYPE_PCI_DEVICE, | |
1341 | .instance_size = sizeof(SDHCIState), | |
1342 | .class_init = sdhci_pci_class_init, | |
fd3b02c8 EH |
1343 | .interfaces = (InterfaceInfo[]) { |
1344 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
1345 | { }, | |
1346 | }, | |
224d10ff KC |
1347 | }; |
1348 | ||
b635d98c PMD |
1349 | /* --- qdev SysBus --- */ |
1350 | ||
5ec911c3 | 1351 | static Property sdhci_sysbus_properties[] = { |
b635d98c | 1352 | DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), |
0a7ac9f9 AB |
1353 | DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, |
1354 | false), | |
5ec911c3 KC |
1355 | DEFINE_PROP_END_OF_LIST(), |
1356 | }; | |
1357 | ||
7302dcd6 KC |
1358 | static void sdhci_sysbus_init(Object *obj) |
1359 | { | |
1360 | SDHCIState *s = SYSBUS_SDHCI(obj); | |
5ec911c3 | 1361 | |
40bbc194 | 1362 | sdhci_initfn(s); |
7302dcd6 KC |
1363 | } |
1364 | ||
1365 | static void sdhci_sysbus_finalize(Object *obj) | |
1366 | { | |
1367 | SDHCIState *s = SYSBUS_SDHCI(obj); | |
1368 | sdhci_uninitfn(s); | |
1369 | } | |
1370 | ||
1371 | static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) | |
d7dfca08 | 1372 | { |
7302dcd6 | 1373 | SDHCIState *s = SYSBUS_SDHCI(dev); |
d7dfca08 IM |
1374 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
1375 | ||
25367498 PMD |
1376 | sdhci_common_realize(s, errp); |
1377 | if (errp && *errp) { | |
1378 | return; | |
1379 | } | |
1380 | ||
d7dfca08 | 1381 | sysbus_init_irq(sbd, &s->irq); |
d7dfca08 IM |
1382 | sysbus_init_mmio(sbd, &s->iomem); |
1383 | } | |
1384 | ||
7302dcd6 | 1385 | static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) |
d7dfca08 IM |
1386 | { |
1387 | DeviceClass *dc = DEVICE_CLASS(klass); | |
d7dfca08 | 1388 | |
5ec911c3 | 1389 | dc->props = sdhci_sysbus_properties; |
7302dcd6 | 1390 | dc->realize = sdhci_sysbus_realize; |
1c92c505 PMD |
1391 | |
1392 | sdhci_common_class_init(klass, data); | |
d7dfca08 IM |
1393 | } |
1394 | ||
7302dcd6 KC |
1395 | static const TypeInfo sdhci_sysbus_info = { |
1396 | .name = TYPE_SYSBUS_SDHCI, | |
d7dfca08 IM |
1397 | .parent = TYPE_SYS_BUS_DEVICE, |
1398 | .instance_size = sizeof(SDHCIState), | |
7302dcd6 KC |
1399 | .instance_init = sdhci_sysbus_init, |
1400 | .instance_finalize = sdhci_sysbus_finalize, | |
1401 | .class_init = sdhci_sysbus_class_init, | |
d7dfca08 IM |
1402 | }; |
1403 | ||
b635d98c PMD |
1404 | /* --- qdev bus master --- */ |
1405 | ||
40bbc194 PM |
1406 | static void sdhci_bus_class_init(ObjectClass *klass, void *data) |
1407 | { | |
1408 | SDBusClass *sbc = SD_BUS_CLASS(klass); | |
1409 | ||
1410 | sbc->set_inserted = sdhci_set_inserted; | |
1411 | sbc->set_readonly = sdhci_set_readonly; | |
1412 | } | |
1413 | ||
1414 | static const TypeInfo sdhci_bus_info = { | |
1415 | .name = TYPE_SDHCI_BUS, | |
1416 | .parent = TYPE_SD_BUS, | |
1417 | .instance_size = sizeof(SDBus), | |
1418 | .class_init = sdhci_bus_class_init, | |
1419 | }; | |
1420 | ||
d7dfca08 IM |
1421 | static void sdhci_register_types(void) |
1422 | { | |
224d10ff | 1423 | type_register_static(&sdhci_pci_info); |
7302dcd6 | 1424 | type_register_static(&sdhci_sysbus_info); |
40bbc194 | 1425 | type_register_static(&sdhci_bus_info); |
d7dfca08 IM |
1426 | } |
1427 | ||
1428 | type_init(sdhci_register_types) |