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Add function prologue, fix pointer load on Sparc64 host
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
3475187d 25 Rest of V9 instructions, VIS instructions
bd497938 26 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 27 Optimize synthetic instructions
bd497938 28*/
7a3f1944
FB		 29
30#include <stdarg.h>
31#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <inttypes.h>
35
36#include "cpu.h"
37#include "exec-all.h"
38#include "disas.h"
1a2fb1c0 39#include "helper.h"
57fec1fe 40#include "tcg-op.h"
7a3f1944
FB		 41
42#define DEBUG_DISAS
43
72cbca10
FB		 44#define DYNAMIC_PC 1 /* dynamic pc value */
45#define JUMP_PC 2 /* dynamic pc value which takes only two values
46 according to jump_pc[T2] */
47
1a2fb1c0
BS		 48/* global register indexes */
49static TCGv cpu_env, cpu_T[3], cpu_regwptr;
50/* local register indexes (only used inside old micro ops) */
51static TCGv cpu_tmp0;
52
7a3f1944 53typedef struct DisasContext {
0f8a249a
BS		 54 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 56 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 57 int is_br;
e8af50a3 58 int mem_idx;
a80dde08 59 int fpu_enabled;
cf495bcf 60 struct TranslationBlock *tb;
7a3f1944
FB		 61} DisasContext;
62
aaed909a
FB		 63typedef struct sparc_def_t sparc_def_t;
64
62724a37
BS		 65struct sparc_def_t {
66 const unsigned char *name;
67 target_ulong iu_version;
68 uint32_t fpu_version;
69 uint32_t mmu_version;
6d5f237a 70 uint32_t mmu_bm;
3deaeab7
BS		 71 uint32_t mmu_ctpr_mask;
72 uint32_t mmu_cxr_mask;
73 uint32_t mmu_sfsr_mask;
74 uint32_t mmu_trcr_mask;
62724a37
BS		 75};
76
aaed909a
FB		 77static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
78
7a3f1944
FB		 79extern FILE *logfile;
80extern int loglevel;
81
3475187d 82// This function uses non-native bit order
7a3f1944
FB		 83#define GET_FIELD(X, FROM, TO) \
84 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
85
3475187d
FB		 86// This function uses the order in the manuals, i.e. bit 0 is 2^0
87#define GET_FIELD_SP(X, FROM, TO) \
88 GET_FIELD(X, 31 - (TO), 31 - (FROM))
89
90#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 91#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 92
93#ifdef TARGET_SPARC64
0387d928 94#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 95#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 96#else
c185970a 97#define DFPREG(r) (r & 0x1e)
1f587329 98#define QFPREG(r) (r & 0x1c)
3475187d
FB		 99#endif
100
101static int sign_extend(int x, int len)
102{
103 len = 32 - len;
104 return (x << len) >> len;
105}
106
7a3f1944
FB		 107#define IS_IMM (insn & (1<<13))
108
cf495bcf 109static void disas_sparc_insn(DisasContext * dc);
7a3f1944 110
3475187d
FB		 111#ifdef TARGET_SPARC64
112#define GEN32(func, NAME) \
a68156d0 113static GenOpFunc * const NAME ## _table [64] = { \
3475187d
FB		 114NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
115NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
116NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
117NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
118NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
119NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
120NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
121NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
122NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
123NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
124NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
125NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
126}; \
127static inline void func(int n) \
128{ \
129 NAME ## _table[n](); \
130}
131#else
e8af50a3 132#define GEN32(func, NAME) \
a68156d0 133static GenOpFunc *const NAME ## _table [32] = { \
e8af50a3
FB		 134NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
135NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
136NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
137NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
138NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
139NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
140NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
141NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
142}; \
143static inline void func(int n) \
144{ \
145 NAME ## _table[n](); \
146}
3475187d 147#endif
e8af50a3
FB		 148
149/* floating point registers moves */
150GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
151GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
e8af50a3
FB		 152GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
153GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
e8af50a3
FB		 154
155GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
156GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
e8af50a3
FB		 157GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
158GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
e8af50a3 159
1f587329
BS		 160#if defined(CONFIG_USER_ONLY)
161GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
162GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
163GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
164GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
165#endif
166
81ad8ba2
BS		 167/* moves */
168#ifdef CONFIG_USER_ONLY
3475187d 169#define supervisor(dc) 0
81ad8ba2 170#ifdef TARGET_SPARC64
e9ebed4d 171#define hypervisor(dc) 0
81ad8ba2 172#endif
3475187d 173#define gen_op_ldst(name) gen_op_##name##_raw()
3475187d 174#else
6f27aba6 175#define supervisor(dc) (dc->mem_idx >= 1)
81ad8ba2
BS		 176#ifdef TARGET_SPARC64
177#define hypervisor(dc) (dc->mem_idx == 2)
6f27aba6
BS		 178#define OP_LD_TABLE(width) \
179 static GenOpFunc * const gen_op_##width[] = { \
180 &gen_op_##width##_user, \
181 &gen_op_##width##_kernel, \
182 &gen_op_##width##_hypv, \
183 };
184#else
0f8a249a 185#define OP_LD_TABLE(width) \
a68156d0 186 static GenOpFunc * const gen_op_##width[] = { \
0f8a249a
BS		 187 &gen_op_##width##_user, \
188 &gen_op_##width##_kernel, \
81ad8ba2 189 };
3475187d 190#endif
6f27aba6
BS		 191#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
192#endif
e8af50a3 193
81ad8ba2 194#ifndef CONFIG_USER_ONLY
b25deda7
BS		 195#ifdef __i386__
196OP_LD_TABLE(std);
197#endif /* __i386__ */
e8af50a3
FB		 198OP_LD_TABLE(stf);
199OP_LD_TABLE(stdf);
200OP_LD_TABLE(ldf);
201OP_LD_TABLE(lddf);
81ad8ba2
BS		 202#endif
203
1a2fb1c0
BS		 204#ifdef TARGET_ABI32
205#define ABI32_MASK(addr) tcg_gen_andi_i64(addr, addr, 0xffffffffULL);
206#else
207#define ABI32_MASK(addr)
208#endif
3391c818 209
1a2fb1c0 210static inline void gen_movl_simm_T1(int32_t val)
81ad8ba2 211{
1a2fb1c0 212 tcg_gen_movi_tl(cpu_T[1], val);
81ad8ba2
BS		 213}
214
1a2fb1c0 215static inline void gen_movl_reg_TN(int reg, TCGv tn)
81ad8ba2 216{
1a2fb1c0
BS		 217 if (reg == 0)
218 tcg_gen_movi_tl(tn, 0);
219 else if (reg < 8)
220 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
221 else {
222 tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX
223 tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 224 }
225}
226
1a2fb1c0 227static inline void gen_movl_reg_T0(int reg)
81ad8ba2 228{
1a2fb1c0 229 gen_movl_reg_TN(reg, cpu_T[0]);
81ad8ba2
BS		 230}
231
1a2fb1c0 232static inline void gen_movl_reg_T1(int reg)
81ad8ba2 233{
1a2fb1c0 234 gen_movl_reg_TN(reg, cpu_T[1]);
81ad8ba2
BS		 235}
236
b25deda7
BS		 237#ifdef __i386__
238static inline void gen_movl_reg_T2(int reg)
239{
240 gen_movl_reg_TN(reg, cpu_T[2]);
241}
242
243#endif /* __i386__ */
1a2fb1c0 244static inline void gen_movl_TN_reg(int reg, TCGv tn)
81ad8ba2 245{
1a2fb1c0
BS		 246 if (reg == 0)
247 return;
248 else if (reg < 8)
249 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUState, gregs[reg]));
250 else {
251 tcg_gen_ld_ptr(cpu_regwptr, cpu_env, offsetof(CPUState, regwptr)); // XXX
252 tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
81ad8ba2
BS		 253 }
254}
255
1a2fb1c0 256static inline void gen_movl_T0_reg(int reg)
3475187d 257{
1a2fb1c0 258 gen_movl_TN_reg(reg, cpu_T[0]);
3475187d
FB		 259}
260
1a2fb1c0 261static inline void gen_movl_T1_reg(int reg)
3475187d 262{
1a2fb1c0 263 gen_movl_TN_reg(reg, cpu_T[1]);
3475187d
FB		 264}
265
1a2fb1c0 266static inline void gen_op_movl_T0_env(size_t offset)
7a3f1944 267{
1a2fb1c0 268 tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 269}
270
1a2fb1c0 271static inline void gen_op_movl_env_T0(size_t offset)
7a3f1944 272{
1a2fb1c0 273 tcg_gen_st_i32(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 274}
275
1a2fb1c0 276static inline void gen_op_movtl_T0_env(size_t offset)
7a3f1944 277{
1a2fb1c0 278 tcg_gen_ld_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 279}
280
1a2fb1c0 281static inline void gen_op_movtl_env_T0(size_t offset)
7a3f1944 282{
1a2fb1c0 283 tcg_gen_st_tl(cpu_T[0], cpu_env, offset);
7a3f1944
FB		 284}
285
1a2fb1c0 286static inline void gen_op_add_T1_T0(void)
7a3f1944 287{
1a2fb1c0 288 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 289}
290
1a2fb1c0 291static inline void gen_op_or_T1_T0(void)
7a3f1944 292{
1a2fb1c0 293 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 294}
295
1a2fb1c0 296static inline void gen_op_xor_T1_T0(void)
7a3f1944 297{
1a2fb1c0 298 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
7a3f1944
FB		 299}
300
3475187d
FB		 301static inline void gen_jmp_im(target_ulong pc)
302{
1a2fb1c0
BS		 303 tcg_gen_movi_tl(cpu_tmp0, pc);
304 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, pc));
3475187d
FB		 305}
306
307static inline void gen_movl_npc_im(target_ulong npc)
308{
1a2fb1c0
BS		 309 tcg_gen_movi_tl(cpu_tmp0, npc);
310 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, npc));
3475187d
FB		 311}
312
5fafdf24 313static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 314 target_ulong pc, target_ulong npc)
315{
316 TranslationBlock *tb;
317
318 tb = s->tb;
319 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
320 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
321 /* jump to same page: we can use a direct jump */
57fec1fe 322 tcg_gen_goto_tb(tb_num);
6e256c93
FB		 323 gen_jmp_im(pc);
324 gen_movl_npc_im(npc);
57fec1fe 325 tcg_gen_exit_tb((long)tb + tb_num);
6e256c93
FB		 326 } else {
327 /* jump to another page: currently not optimized */
328 gen_jmp_im(pc);
329 gen_movl_npc_im(npc);
57fec1fe 330 tcg_gen_exit_tb(0);
6e256c93
FB		 331 }
332}
333
46525e1f
BS		 334static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
335 target_ulong pc2)
83469015
FB		 336{
337 int l1;
338
339 l1 = gen_new_label();
340
341 gen_op_jz_T2_label(l1);
342
6e256c93 343 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 344
345 gen_set_label(l1);
6e256c93 346 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 347}
348
46525e1f
BS		 349static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
350 target_ulong pc2)
83469015
FB		 351{
352 int l1;
353
354 l1 = gen_new_label();
355
356 gen_op_jz_T2_label(l1);
357
6e256c93 358 gen_goto_tb(dc, 0, pc2, pc1);
83469015
FB		 359
360 gen_set_label(l1);
6e256c93 361 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
83469015
FB		 362}
363
46525e1f
BS		 364static inline void gen_branch(DisasContext *dc, target_ulong pc,
365 target_ulong npc)
83469015 366{
6e256c93 367 gen_goto_tb(dc, 0, pc, npc);
83469015
FB		 368}
369
46525e1f 370static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
83469015
FB		 371{
372 int l1, l2;
373
374 l1 = gen_new_label();
375 l2 = gen_new_label();
376 gen_op_jz_T2_label(l1);
377
378 gen_movl_npc_im(npc1);
379 gen_op_jmp_label(l2);
380
381 gen_set_label(l1);
382 gen_movl_npc_im(npc2);
383 gen_set_label(l2);
384}
385
386/* call this function before using T2 as it may have been set for a jump */
387static inline void flush_T2(DisasContext * dc)
388{
389 if (dc->npc == JUMP_PC) {
46525e1f 390 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
83469015
FB		 391 dc->npc = DYNAMIC_PC;
392 }
393}
394
72cbca10
FB		 395static inline void save_npc(DisasContext * dc)
396{
397 if (dc->npc == JUMP_PC) {
46525e1f 398 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 399 dc->npc = DYNAMIC_PC;
400 } else if (dc->npc != DYNAMIC_PC) {
3475187d 401 gen_movl_npc_im(dc->npc);
72cbca10
FB		 402 }
403}
404
405static inline void save_state(DisasContext * dc)
406{
3475187d 407 gen_jmp_im(dc->pc);
72cbca10
FB		 408 save_npc(dc);
409}
410
0bee699e
FB		 411static inline void gen_mov_pc_npc(DisasContext * dc)
412{
413 if (dc->npc == JUMP_PC) {
46525e1f 414 gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
38bc628b
BS		 415 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
416 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 417 dc->pc = DYNAMIC_PC;
418 } else if (dc->npc == DYNAMIC_PC) {
38bc628b
BS		 419 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
420 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
0bee699e
FB		 421 dc->pc = DYNAMIC_PC;
422 } else {
423 dc->pc = dc->npc;
424 }
425}
426
38bc628b
BS		 427static inline void gen_op_next_insn(void)
428{
429 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
430 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, pc));
431 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, 4);
432 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, npc));
433}
434
3475187d
FB		 435static GenOpFunc * const gen_cond[2][16] = {
436 {
0f8a249a
BS		 437 gen_op_eval_bn,
438 gen_op_eval_be,
439 gen_op_eval_ble,
440 gen_op_eval_bl,
441 gen_op_eval_bleu,
442 gen_op_eval_bcs,
443 gen_op_eval_bneg,
444 gen_op_eval_bvs,
445 gen_op_eval_ba,
446 gen_op_eval_bne,
447 gen_op_eval_bg,
448 gen_op_eval_bge,
449 gen_op_eval_bgu,
450 gen_op_eval_bcc,
451 gen_op_eval_bpos,
452 gen_op_eval_bvc,
3475187d
FB		 453 },
454 {
455#ifdef TARGET_SPARC64
0f8a249a
BS		 456 gen_op_eval_bn,
457 gen_op_eval_xbe,
458 gen_op_eval_xble,
459 gen_op_eval_xbl,
460 gen_op_eval_xbleu,
461 gen_op_eval_xbcs,
462 gen_op_eval_xbneg,
463 gen_op_eval_xbvs,
464 gen_op_eval_ba,
465 gen_op_eval_xbne,
466 gen_op_eval_xbg,
467 gen_op_eval_xbge,
468 gen_op_eval_xbgu,
469 gen_op_eval_xbcc,
470 gen_op_eval_xbpos,
471 gen_op_eval_xbvc,
3475187d
FB		 472#endif
473 },
474};
475
476static GenOpFunc * const gen_fcond[4][16] = {
477 {
0f8a249a
BS		 478 gen_op_eval_bn,
479 gen_op_eval_fbne,
480 gen_op_eval_fblg,
481 gen_op_eval_fbul,
482 gen_op_eval_fbl,
483 gen_op_eval_fbug,
484 gen_op_eval_fbg,
485 gen_op_eval_fbu,
486 gen_op_eval_ba,
487 gen_op_eval_fbe,
488 gen_op_eval_fbue,
489 gen_op_eval_fbge,
490 gen_op_eval_fbuge,
491 gen_op_eval_fble,
492 gen_op_eval_fbule,
493 gen_op_eval_fbo,
3475187d
FB		 494 },
495#ifdef TARGET_SPARC64
496 {
0f8a249a
BS		 497 gen_op_eval_bn,
498 gen_op_eval_fbne_fcc1,
499 gen_op_eval_fblg_fcc1,
500 gen_op_eval_fbul_fcc1,
501 gen_op_eval_fbl_fcc1,
502 gen_op_eval_fbug_fcc1,
503 gen_op_eval_fbg_fcc1,
504 gen_op_eval_fbu_fcc1,
505 gen_op_eval_ba,
506 gen_op_eval_fbe_fcc1,
507 gen_op_eval_fbue_fcc1,
508 gen_op_eval_fbge_fcc1,
509 gen_op_eval_fbuge_fcc1,
510 gen_op_eval_fble_fcc1,
511 gen_op_eval_fbule_fcc1,
512 gen_op_eval_fbo_fcc1,
3475187d
FB		 513 },
514 {
0f8a249a
BS		 515 gen_op_eval_bn,
516 gen_op_eval_fbne_fcc2,
517 gen_op_eval_fblg_fcc2,
518 gen_op_eval_fbul_fcc2,
519 gen_op_eval_fbl_fcc2,
520 gen_op_eval_fbug_fcc2,
521 gen_op_eval_fbg_fcc2,
522 gen_op_eval_fbu_fcc2,
523 gen_op_eval_ba,
524 gen_op_eval_fbe_fcc2,
525 gen_op_eval_fbue_fcc2,
526 gen_op_eval_fbge_fcc2,
527 gen_op_eval_fbuge_fcc2,
528 gen_op_eval_fble_fcc2,
529 gen_op_eval_fbule_fcc2,
530 gen_op_eval_fbo_fcc2,
3475187d
FB		 531 },
532 {
0f8a249a
BS		 533 gen_op_eval_bn,
534 gen_op_eval_fbne_fcc3,
535 gen_op_eval_fblg_fcc3,
536 gen_op_eval_fbul_fcc3,
537 gen_op_eval_fbl_fcc3,
538 gen_op_eval_fbug_fcc3,
539 gen_op_eval_fbg_fcc3,
540 gen_op_eval_fbu_fcc3,
541 gen_op_eval_ba,
542 gen_op_eval_fbe_fcc3,
543 gen_op_eval_fbue_fcc3,
544 gen_op_eval_fbge_fcc3,
545 gen_op_eval_fbuge_fcc3,
546 gen_op_eval_fble_fcc3,
547 gen_op_eval_fbule_fcc3,
548 gen_op_eval_fbo_fcc3,
3475187d
FB		 549 },
550#else
551 {}, {}, {},
552#endif
553};
7a3f1944 554
3475187d
FB		 555#ifdef TARGET_SPARC64
556static void gen_cond_reg(int cond)
e8af50a3 557{
0f8a249a
BS		 558 switch (cond) {
559 case 0x1:
560 gen_op_eval_brz();
561 break;
562 case 0x2:
563 gen_op_eval_brlez();
564 break;
565 case 0x3:
566 gen_op_eval_brlz();
567 break;
568 case 0x5:
569 gen_op_eval_brnz();
570 break;
571 case 0x6:
572 gen_op_eval_brgz();
573 break;
e8af50a3 574 default:
0f8a249a
BS		 575 case 0x7:
576 gen_op_eval_brgez();
577 break;
578 }
e8af50a3 579}
00f219bf
BS		 580
581// Inverted logic
582static const int gen_tcg_cond_reg[8] = {
583 -1,
584 TCG_COND_NE,
585 TCG_COND_GT,
586 TCG_COND_GE,
587 -1,
588 TCG_COND_EQ,
589 TCG_COND_LE,
590 TCG_COND_LT,
591};
3475187d 592#endif
cf495bcf 593
0bee699e 594/* XXX: potentially incorrect if dynamic npc */
3475187d 595static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 596{
cf495bcf 597 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 598 target_ulong target = dc->pc + offset;
5fafdf24 599
cf495bcf 600 if (cond == 0x0) {
0f8a249a
BS		 601 /* unconditional not taken */
602 if (a) {
603 dc->pc = dc->npc + 4;
604 dc->npc = dc->pc + 4;
605 } else {
606 dc->pc = dc->npc;
607 dc->npc = dc->pc + 4;
608 }
cf495bcf 609 } else if (cond == 0x8) {
0f8a249a
BS		 610 /* unconditional taken */
611 if (a) {
612 dc->pc = target;
613 dc->npc = dc->pc + 4;
614 } else {
615 dc->pc = dc->npc;
616 dc->npc = target;
617 }
cf495bcf 618 } else {
72cbca10 619 flush_T2(dc);
3475187d 620 gen_cond[cc][cond]();
0f8a249a
BS		 621 if (a) {
622 gen_branch_a(dc, target, dc->npc);
cf495bcf 623 dc->is_br = 1;
0f8a249a 624 } else {
cf495bcf 625 dc->pc = dc->npc;
72cbca10
FB		 626 dc->jump_pc[0] = target;
627 dc->jump_pc[1] = dc->npc + 4;
628 dc->npc = JUMP_PC;
0f8a249a 629 }
cf495bcf 630 }
7a3f1944
FB		 631}
632
0bee699e 633/* XXX: potentially incorrect if dynamic npc */
3475187d 634static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 635{
636 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 637 target_ulong target = dc->pc + offset;
638
e8af50a3 639 if (cond == 0x0) {
0f8a249a
BS		 640 /* unconditional not taken */
641 if (a) {
642 dc->pc = dc->npc + 4;
643 dc->npc = dc->pc + 4;
644 } else {
645 dc->pc = dc->npc;
646 dc->npc = dc->pc + 4;
647 }
e8af50a3 648 } else if (cond == 0x8) {
0f8a249a
BS		 649 /* unconditional taken */
650 if (a) {
651 dc->pc = target;
652 dc->npc = dc->pc + 4;
653 } else {
654 dc->pc = dc->npc;
655 dc->npc = target;
656 }
e8af50a3
FB		 657 } else {
658 flush_T2(dc);
3475187d 659 gen_fcond[cc][cond]();
0f8a249a
BS		 660 if (a) {
661 gen_branch_a(dc, target, dc->npc);
e8af50a3 662 dc->is_br = 1;
0f8a249a 663 } else {
e8af50a3
FB		 664 dc->pc = dc->npc;
665 dc->jump_pc[0] = target;
666 dc->jump_pc[1] = dc->npc + 4;
667 dc->npc = JUMP_PC;
0f8a249a 668 }
e8af50a3
FB		 669 }
670}
671
3475187d
FB		 672#ifdef TARGET_SPARC64
673/* XXX: potentially incorrect if dynamic npc */
674static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
7a3f1944 675{
3475187d
FB		 676 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
677 target_ulong target = dc->pc + offset;
678
679 flush_T2(dc);
680 gen_cond_reg(cond);
681 if (a) {
0f8a249a
BS		 682 gen_branch_a(dc, target, dc->npc);
683 dc->is_br = 1;
3475187d 684 } else {
0f8a249a
BS		 685 dc->pc = dc->npc;
686 dc->jump_pc[0] = target;
687 dc->jump_pc[1] = dc->npc + 4;
688 dc->npc = JUMP_PC;
3475187d 689 }
7a3f1944
FB		 690}
691
3475187d 692static GenOpFunc * const gen_fcmps[4] = {
7e8c2b6c
BS		 693 helper_fcmps,
694 helper_fcmps_fcc1,
695 helper_fcmps_fcc2,
696 helper_fcmps_fcc3,
3475187d
FB		 697};
698
699static GenOpFunc * const gen_fcmpd[4] = {
7e8c2b6c
BS		 700 helper_fcmpd,
701 helper_fcmpd_fcc1,
702 helper_fcmpd_fcc2,
703 helper_fcmpd_fcc3,
3475187d 704};
417454b0 705
1f587329
BS		 706#if defined(CONFIG_USER_ONLY)
707static GenOpFunc * const gen_fcmpq[4] = {
7e8c2b6c
BS		 708 helper_fcmpq,
709 helper_fcmpq_fcc1,
710 helper_fcmpq_fcc2,
711 helper_fcmpq_fcc3,
1f587329
BS		 712};
713#endif
714
417454b0 715static GenOpFunc * const gen_fcmpes[4] = {
7e8c2b6c
BS		 716 helper_fcmpes,
717 helper_fcmpes_fcc1,
718 helper_fcmpes_fcc2,
719 helper_fcmpes_fcc3,
417454b0
BS		 720};
721
722static GenOpFunc * const gen_fcmped[4] = {
7e8c2b6c
BS		 723 helper_fcmped,
724 helper_fcmped_fcc1,
725 helper_fcmped_fcc2,
726 helper_fcmped_fcc3,
417454b0
BS		 727};
728
1f587329
BS		 729#if defined(CONFIG_USER_ONLY)
730static GenOpFunc * const gen_fcmpeq[4] = {
7e8c2b6c
BS		 731 helper_fcmpeq,
732 helper_fcmpeq_fcc1,
733 helper_fcmpeq_fcc2,
734 helper_fcmpeq_fcc3,
1f587329
BS		 735};
736#endif
7e8c2b6c
BS		 737
738static inline void gen_op_fcmps(int fccno)
739{
740 tcg_gen_helper_0_0(gen_fcmps[fccno]);
741}
742
743static inline void gen_op_fcmpd(int fccno)
744{
745 tcg_gen_helper_0_0(gen_fcmpd[fccno]);
746}
747
748#if defined(CONFIG_USER_ONLY)
749static inline void gen_op_fcmpq(int fccno)
750{
751 tcg_gen_helper_0_0(gen_fcmpq[fccno]);
752}
753#endif
754
755static inline void gen_op_fcmpes(int fccno)
756{
757 tcg_gen_helper_0_0(gen_fcmpes[fccno]);
758}
759
760static inline void gen_op_fcmped(int fccno)
761{
762 tcg_gen_helper_0_0(gen_fcmped[fccno]);
763}
764
765#if defined(CONFIG_USER_ONLY)
766static inline void gen_op_fcmpeq(int fccno)
767{
768 tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
769}
770#endif
771
772#else
773
774static inline void gen_op_fcmps(int fccno)
775{
776 tcg_gen_helper_0_0(helper_fcmps);
777}
778
779static inline void gen_op_fcmpd(int fccno)
780{
781 tcg_gen_helper_0_0(helper_fcmpd);
782}
783
784#if defined(CONFIG_USER_ONLY)
785static inline void gen_op_fcmpq(int fccno)
786{
787 tcg_gen_helper_0_0(helper_fcmpq);
788}
789#endif
790
791static inline void gen_op_fcmpes(int fccno)
792{
793 tcg_gen_helper_0_0(helper_fcmpes);
794}
795
796static inline void gen_op_fcmped(int fccno)
797{
798 tcg_gen_helper_0_0(helper_fcmped);
799}
800
801#if defined(CONFIG_USER_ONLY)
802static inline void gen_op_fcmpeq(int fccno)
803{
804 tcg_gen_helper_0_0(helper_fcmpeq);
805}
806#endif
807
3475187d
FB		 808#endif
809
134d77a1
BS		 810static inline void gen_op_exception(int exception)
811{
812 TCGv r_except;
813
814 r_except = tcg_temp_new(TCG_TYPE_I32);
815 tcg_gen_movi_i32(r_except, exception);
816 tcg_gen_helper_0_1(raise_exception, r_except);
817}
818
819static inline void gen_op_fpexception_im(int fsr_flags)
820{
821 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
822 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~FSR_FTT_MASK);
823 tcg_gen_ori_tl(cpu_tmp0, cpu_tmp0, fsr_flags);
824 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
825 gen_op_exception(TT_FP_EXCP);
826}
827
a80dde08
FB		 828static int gen_trap_ifnofpu(DisasContext * dc)
829{
830#if !defined(CONFIG_USER_ONLY)
831 if (!dc->fpu_enabled) {
832 save_state(dc);
833 gen_op_exception(TT_NFPU_INSN);
834 dc->is_br = 1;
835 return 1;
836 }
837#endif
838 return 0;
839}
840
7e8c2b6c
BS		 841static inline void gen_op_clear_ieee_excp_and_FTT(void)
842{
843 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
844 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
845 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
846}
847
848static inline void gen_clear_float_exceptions(void)
849{
850 tcg_gen_helper_0_0(helper_clear_float_exceptions);
851}
852
1a2fb1c0
BS		 853/* asi moves */
854#ifdef TARGET_SPARC64
855static inline void gen_ld_asi(int insn, int size, int sign)
856{
857 int asi, offset;
858 TCGv r_size, r_sign;
859
860 r_size = tcg_temp_new(TCG_TYPE_I32);
861 r_sign = tcg_temp_new(TCG_TYPE_I32);
862 tcg_gen_movi_i32(r_size, size);
863 tcg_gen_movi_i32(r_sign, sign);
864 if (IS_IMM) {
865 offset = GET_FIELD(insn, 25, 31);
866 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
867 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
868 } else {
869 asi = GET_FIELD(insn, 19, 26);
870 tcg_gen_movi_i32(cpu_T[1], asi);
871 }
872 tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], cpu_T[1], r_size,
873 r_sign);
874}
875
876static inline void gen_st_asi(int insn, int size)
877{
878 int asi, offset;
879 TCGv r_asi, r_size;
880
881 r_asi = tcg_temp_new(TCG_TYPE_I32);
882 r_size = tcg_temp_new(TCG_TYPE_I32);
883 tcg_gen_movi_i32(r_size, size);
884 if (IS_IMM) {
885 offset = GET_FIELD(insn, 25, 31);
886 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
887 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
888 } else {
889 asi = GET_FIELD(insn, 19, 26);
890 tcg_gen_movi_i32(r_asi, asi);
891 }
892 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi, r_size);
893}
894
895static inline void gen_ldf_asi(int insn, int size, int rd)
896{
897 int asi, offset;
898 TCGv r_asi, r_size, r_rd;
899
900 r_asi = tcg_temp_new(TCG_TYPE_I32);
901 r_size = tcg_temp_new(TCG_TYPE_I32);
902 r_rd = tcg_temp_new(TCG_TYPE_I32);
903 tcg_gen_movi_i32(r_size, size);
904 tcg_gen_movi_i32(r_rd, rd);
905 if (IS_IMM) {
906 offset = GET_FIELD(insn, 25, 31);
907 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
908 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
909 } else {
910 asi = GET_FIELD(insn, 19, 26);
911 tcg_gen_movi_i32(r_asi, asi);
912 }
913 tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, r_size, r_rd);
914}
915
916static inline void gen_stf_asi(int insn, int size, int rd)
917{
918 int asi, offset;
919 TCGv r_asi, r_size, r_rd;
920
921 r_asi = tcg_temp_new(TCG_TYPE_I32);
922 r_size = tcg_temp_new(TCG_TYPE_I32);
923 r_rd = tcg_temp_new(TCG_TYPE_I32);
924 tcg_gen_movi_i32(r_size, size);
925 tcg_gen_movi_i32(r_rd, rd);
926 if (IS_IMM) {
927 offset = GET_FIELD(insn, 25, 31);
928 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
929 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
930 } else {
931 asi = GET_FIELD(insn, 19, 26);
932 tcg_gen_movi_i32(r_asi, asi);
933 }
934 tcg_gen_helper_0_4(helper_stf_asi, cpu_T[0], r_asi, r_size, r_rd);
935}
936
937static inline void gen_swap_asi(int insn)
938{
939 int asi, offset;
940 TCGv r_size, r_sign, r_temp;
941
942 r_size = tcg_temp_new(TCG_TYPE_I32);
943 r_sign = tcg_temp_new(TCG_TYPE_I32);
944 r_temp = tcg_temp_new(TCG_TYPE_I32);
945 tcg_gen_movi_i32(r_size, 4);
946 tcg_gen_movi_i32(r_sign, 0);
947 if (IS_IMM) {
948 offset = GET_FIELD(insn, 25, 31);
949 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
950 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
951 } else {
952 asi = GET_FIELD(insn, 19, 26);
953 tcg_gen_movi_i32(cpu_T[1], asi);
954 }
955 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
956 r_sign);
957 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
958 tcg_gen_mov_i32(cpu_T[1], r_temp);
959}
960
961static inline void gen_ldda_asi(int insn)
962{
963 int asi, offset;
964 TCGv r_size, r_sign, r_dword;
965
966 r_size = tcg_temp_new(TCG_TYPE_I32);
967 r_sign = tcg_temp_new(TCG_TYPE_I32);
968 r_dword = tcg_temp_new(TCG_TYPE_I64);
969 tcg_gen_movi_i32(r_size, 8);
970 tcg_gen_movi_i32(r_sign, 0);
971 if (IS_IMM) {
972 offset = GET_FIELD(insn, 25, 31);
973 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
974 tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUSPARCState, asi));
975 } else {
976 asi = GET_FIELD(insn, 19, 26);
977 tcg_gen_movi_i32(cpu_T[1], asi);
978 }
979 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
980 r_sign);
981 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
982 tcg_gen_shri_i64(r_dword, r_dword, 32);
983 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
984}
985
986static inline void gen_cas_asi(int insn, int rd)
987{
988 int asi, offset;
989 TCGv r_val1, r_asi;
990
991 r_val1 = tcg_temp_new(TCG_TYPE_I32);
992 r_asi = tcg_temp_new(TCG_TYPE_I32);
993 gen_movl_reg_TN(rd, r_val1);
994 if (IS_IMM) {
995 offset = GET_FIELD(insn, 25, 31);
996 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
997 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
998 } else {
999 asi = GET_FIELD(insn, 19, 26);
1000 tcg_gen_movi_i32(r_asi, asi);
1001 }
1002 tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1003 r_asi);
1004}
1005
1006static inline void gen_casx_asi(int insn, int rd)
1007{
1008 int asi, offset;
1009 TCGv r_val1, r_asi;
1010
1011 r_val1 = tcg_temp_new(TCG_TYPE_I64);
1012 r_asi = tcg_temp_new(TCG_TYPE_I32);
1013 gen_movl_reg_TN(rd, r_val1);
1014 if (IS_IMM) {
1015 offset = GET_FIELD(insn, 25, 31);
1016 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
1017 tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1018 } else {
1019 asi = GET_FIELD(insn, 19, 26);
1020 tcg_gen_movi_i32(r_asi, asi);
1021 }
1022 tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1023 r_asi);
1024}
1025
1026#elif !defined(CONFIG_USER_ONLY)
1027
1028static inline void gen_ld_asi(int insn, int size, int sign)
1029{
1030 int asi;
1031 TCGv r_size, r_sign, r_dword;
1032
1033 r_size = tcg_temp_new(TCG_TYPE_I32);
1034 r_sign = tcg_temp_new(TCG_TYPE_I32);
1035 r_dword = tcg_temp_new(TCG_TYPE_I64);
1036 tcg_gen_movi_i32(r_size, size);
1037 tcg_gen_movi_i32(r_sign, sign);
1038 asi = GET_FIELD(insn, 19, 26);
1039 tcg_gen_movi_i32(cpu_T[1], asi);
1040 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1041 r_sign);
1042 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1043}
1044
1045static inline void gen_st_asi(int insn, int size)
1046{
1047 int asi;
1048 TCGv r_dword, r_asi, r_size;
1049
1050 r_dword = tcg_temp_new(TCG_TYPE_I64);
1051 tcg_gen_extu_i32_i64(r_dword, cpu_T[1]);
1052 r_asi = tcg_temp_new(TCG_TYPE_I32);
1053 r_size = tcg_temp_new(TCG_TYPE_I32);
1054 asi = GET_FIELD(insn, 19, 26);
1055 tcg_gen_movi_i32(r_asi, asi);
1056 tcg_gen_movi_i32(r_size, size);
1057 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1058}
1059
1060static inline void gen_swap_asi(int insn)
1061{
1062 int asi;
1063 TCGv r_size, r_sign, r_temp;
1064
1065 r_size = tcg_temp_new(TCG_TYPE_I32);
1066 r_sign = tcg_temp_new(TCG_TYPE_I32);
1067 r_temp = tcg_temp_new(TCG_TYPE_I32);
1068 tcg_gen_movi_i32(r_size, 4);
1069 tcg_gen_movi_i32(r_sign, 0);
1070 asi = GET_FIELD(insn, 19, 26);
1071 tcg_gen_movi_i32(cpu_T[1], asi);
1072 tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], cpu_T[1], r_size,
1073 r_sign);
1074 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_size, r_sign);
1075 tcg_gen_mov_i32(cpu_T[1], r_temp);
1076}
1077
1078static inline void gen_ldda_asi(int insn)
1079{
1080 int asi;
1081 TCGv r_size, r_sign, r_dword;
1082
1083 r_size = tcg_temp_new(TCG_TYPE_I32);
1084 r_sign = tcg_temp_new(TCG_TYPE_I32);
1085 r_dword = tcg_temp_new(TCG_TYPE_I64);
1086 tcg_gen_movi_i32(r_size, 8);
1087 tcg_gen_movi_i32(r_sign, 0);
1088 asi = GET_FIELD(insn, 19, 26);
1089 tcg_gen_movi_i32(cpu_T[1], asi);
1090 tcg_gen_helper_1_4(helper_ld_asi, r_dword, cpu_T[0], cpu_T[1], r_size,
1091 r_sign);
1092 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
1093 tcg_gen_shri_i64(r_dword, r_dword, 32);
1094 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
1095}
1096#endif
1097
1098#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1099static inline void gen_ldstub_asi(int insn)
1100{
1101 int asi;
1102 TCGv r_dword, r_asi, r_size;
1103
1104 gen_ld_asi(insn, 1, 0);
1105
1106 r_dword = tcg_temp_new(TCG_TYPE_I64);
1107 r_asi = tcg_temp_new(TCG_TYPE_I32);
1108 r_size = tcg_temp_new(TCG_TYPE_I32);
1109 asi = GET_FIELD(insn, 19, 26);
1110 tcg_gen_movi_i32(r_dword, 0xff);
1111 tcg_gen_movi_i32(r_asi, asi);
1112 tcg_gen_movi_i32(r_size, 1);
1113 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_asi, r_size);
1114}
1115#endif
1116
38bc628b
BS		 1117static inline void gen_mov_reg_C(TCGv reg)
1118{
1119 tcg_gen_ld_i32(reg, cpu_env, offsetof(CPUSPARCState, psr));
1120 tcg_gen_shri_i32(reg, reg, 20);
1121 tcg_gen_andi_i32(reg, reg, 0x1);
1122}
1123
0bee699e 1124/* before an instruction, dc->pc must be static */
cf495bcf
FB		 1125static void disas_sparc_insn(DisasContext * dc)
1126{
1127 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 1128
0fa85d43 1129 insn = ldl_code(dc->pc);
cf495bcf 1130 opc = GET_FIELD(insn, 0, 1);
7a3f1944 1131
cf495bcf
FB		 1132 rd = GET_FIELD(insn, 2, 6);
1133 switch (opc) {
0f8a249a
BS		 1134 case 0: /* branches/sethi */
1135 {
1136 unsigned int xop = GET_FIELD(insn, 7, 9);
1137 int32_t target;
1138 switch (xop) {
3475187d 1139#ifdef TARGET_SPARC64
0f8a249a
BS		 1140 case 0x1: /* V9 BPcc */
1141 {
1142 int cc;
1143
1144 target = GET_FIELD_SP(insn, 0, 18);
1145 target = sign_extend(target, 18);
1146 target <<= 2;
1147 cc = GET_FIELD_SP(insn, 20, 21);
1148 if (cc == 0)
1149 do_branch(dc, target, insn, 0);
1150 else if (cc == 2)
1151 do_branch(dc, target, insn, 1);
1152 else
1153 goto illegal_insn;
1154 goto jmp_insn;
1155 }
1156 case 0x3: /* V9 BPr */
1157 {
1158 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 1159 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 1160 target = sign_extend(target, 16);
1161 target <<= 2;
1162 rs1 = GET_FIELD(insn, 13, 17);
1163 gen_movl_reg_T0(rs1);
1164 do_branch_reg(dc, target, insn);
1165 goto jmp_insn;
1166 }
1167 case 0x5: /* V9 FBPcc */
1168 {
1169 int cc = GET_FIELD_SP(insn, 20, 21);
a80dde08
FB		 1170 if (gen_trap_ifnofpu(dc))
1171 goto jmp_insn;
0f8a249a
BS		 1172 target = GET_FIELD_SP(insn, 0, 18);
1173 target = sign_extend(target, 19);
1174 target <<= 2;
1175 do_fbranch(dc, target, insn, cc);
1176 goto jmp_insn;
1177 }
a4d17f19 1178#else
0f8a249a
BS		 1179 case 0x7: /* CBN+x */
1180 {
1181 goto ncp_insn;
1182 }
1183#endif
1184 case 0x2: /* BN+x */
1185 {
1186 target = GET_FIELD(insn, 10, 31);
1187 target = sign_extend(target, 22);
1188 target <<= 2;
1189 do_branch(dc, target, insn, 0);
1190 goto jmp_insn;
1191 }
1192 case 0x6: /* FBN+x */
1193 {
a80dde08
FB		 1194 if (gen_trap_ifnofpu(dc))
1195 goto jmp_insn;
0f8a249a
BS		 1196 target = GET_FIELD(insn, 10, 31);
1197 target = sign_extend(target, 22);
1198 target <<= 2;
1199 do_fbranch(dc, target, insn, 0);
1200 goto jmp_insn;
1201 }
1202 case 0x4: /* SETHI */
e80cfcfc
FB		 1203#define OPTIM
1204#if defined(OPTIM)
0f8a249a 1205 if (rd) { // nop
e80cfcfc 1206#endif
0f8a249a 1207 uint32_t value = GET_FIELD(insn, 10, 31);
1a2fb1c0 1208 tcg_gen_movi_tl(cpu_T[0], value << 10);
0f8a249a 1209 gen_movl_T0_reg(rd);
e80cfcfc 1210#if defined(OPTIM)
0f8a249a 1211 }
e80cfcfc 1212#endif
0f8a249a
BS		 1213 break;
1214 case 0x0: /* UNIMPL */
1215 default:
3475187d 1216 goto illegal_insn;
0f8a249a
BS		 1217 }
1218 break;
1219 }
1220 break;
cf495bcf 1221 case 1:
0f8a249a
BS		 1222 /*CALL*/ {
1223 target_long target = GET_FIELDs(insn, 2, 31) << 2;
cf495bcf 1224
1a2fb1c0 1225 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 1226 gen_movl_T0_reg(15);
1227 target += dc->pc;
0bee699e 1228 gen_mov_pc_npc(dc);
0f8a249a
BS		 1229 dc->npc = target;
1230 }
1231 goto jmp_insn;
1232 case 2: /* FPU & Logical Operations */
1233 {
1234 unsigned int xop = GET_FIELD(insn, 7, 12);
1235 if (xop == 0x3a) { /* generate trap */
cf495bcf 1236 int cond;
3475187d 1237
cf495bcf
FB		 1238 rs1 = GET_FIELD(insn, 13, 17);
1239 gen_movl_reg_T0(rs1);
0f8a249a
BS		 1240 if (IS_IMM) {
1241 rs2 = GET_FIELD(insn, 25, 31);
1a2fb1c0 1242 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], rs2);
cf495bcf
FB		 1243 } else {
1244 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 1245#if defined(OPTIM)
0f8a249a 1246 if (rs2 != 0) {
e80cfcfc 1247#endif
0f8a249a
BS		 1248 gen_movl_reg_T1(rs2);
1249 gen_op_add_T1_T0();
e80cfcfc 1250#if defined(OPTIM)
0f8a249a 1251 }
e80cfcfc 1252#endif
cf495bcf 1253 }
cf495bcf
FB		 1254 cond = GET_FIELD(insn, 3, 6);
1255 if (cond == 0x8) {
a80dde08 1256 save_state(dc);
1a2fb1c0 1257 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
af7bf89b 1258 } else if (cond != 0) {
3475187d 1259#ifdef TARGET_SPARC64
0f8a249a
BS		 1260 /* V9 icc/xcc */
1261 int cc = GET_FIELD_SP(insn, 11, 12);
1262 flush_T2(dc);
a80dde08 1263 save_state(dc);
0f8a249a
BS		 1264 if (cc == 0)
1265 gen_cond[0][cond]();
1266 else if (cc == 2)
1267 gen_cond[1][cond]();
1268 else
1269 goto illegal_insn;
3475187d 1270#else
0f8a249a 1271 flush_T2(dc);
a80dde08 1272 save_state(dc);
0f8a249a 1273 gen_cond[0][cond]();
3475187d 1274#endif
1a2fb1c0 1275 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], cpu_T[2]);
cf495bcf 1276 }
a80dde08 1277 gen_op_next_insn();
57fec1fe 1278 tcg_gen_exit_tb(0);
a80dde08
FB		 1279 dc->is_br = 1;
1280 goto jmp_insn;
cf495bcf
FB		 1281 } else if (xop == 0x28) {
1282 rs1 = GET_FIELD(insn, 13, 17);
1283 switch(rs1) {
1284 case 0: /* rdy */
65fe7b09
BS		 1285#ifndef TARGET_SPARC64
1286 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1287 manual, rdy on the microSPARC
1288 II */
1289 case 0x0f: /* stbar in the SPARCv8 manual,
1290 rdy on the microSPARC II */
1291 case 0x10 ... 0x1f: /* implementation-dependent in the
1292 SPARCv8 manual, rdy on the
1293 microSPARC II */
1294#endif
1295 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
cf495bcf
FB		 1296 gen_movl_T0_reg(rd);
1297 break;
3475187d 1298#ifdef TARGET_SPARC64
0f8a249a 1299 case 0x2: /* V9 rdccr */
3475187d
FB		 1300 gen_op_rdccr();
1301 gen_movl_T0_reg(rd);
1302 break;
0f8a249a
BS		 1303 case 0x3: /* V9 rdasi */
1304 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
3475187d
FB		 1305 gen_movl_T0_reg(rd);
1306 break;
0f8a249a 1307 case 0x4: /* V9 rdtick */
ccd4a219
BS		 1308 {
1309 TCGv r_tickptr;
1310
1311 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
1312 tcg_gen_ld_ptr(r_tickptr, cpu_env,
1313 offsetof(CPUState, tick));
1314 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
1315 r_tickptr);
1316 gen_movl_T0_reg(rd);
1317 }
3475187d 1318 break;
0f8a249a 1319 case 0x5: /* V9 rdpc */
1a2fb1c0 1320 tcg_gen_movi_tl(cpu_T[0], dc->pc);
0f8a249a
BS		 1321 gen_movl_T0_reg(rd);
1322 break;
1323 case 0x6: /* V9 rdfprs */
1324 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
3475187d
FB		 1325 gen_movl_T0_reg(rd);
1326 break;
65fe7b09
BS		 1327 case 0xf: /* V9 membar */
1328 break; /* no effect */
0f8a249a 1329 case 0x13: /* Graphics Status */
725cb90b
FB		 1330 if (gen_trap_ifnofpu(dc))
1331 goto jmp_insn;
0f8a249a 1332 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
725cb90b
FB		 1333 gen_movl_T0_reg(rd);
1334 break;
0f8a249a
BS		 1335 case 0x17: /* Tick compare */
1336 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
83469015
FB		 1337 gen_movl_T0_reg(rd);
1338 break;
0f8a249a 1339 case 0x18: /* System tick */
ccd4a219
BS		 1340 {
1341 TCGv r_tickptr;
1342
1343 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
1344 tcg_gen_ld_ptr(r_tickptr, cpu_env,
1345 offsetof(CPUState, stick));
1346 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
1347 r_tickptr);
1348 gen_movl_T0_reg(rd);
1349 }
83469015 1350 break;
0f8a249a
BS		 1351 case 0x19: /* System tick compare */
1352 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
83469015
FB		 1353 gen_movl_T0_reg(rd);
1354 break;
0f8a249a
BS		 1355 case 0x10: /* Performance Control */
1356 case 0x11: /* Performance Instrumentation Counter */
1357 case 0x12: /* Dispatch Control */
1358 case 0x14: /* Softint set, WO */
1359 case 0x15: /* Softint clear, WO */
1360 case 0x16: /* Softint write */
3475187d
FB		 1361#endif
1362 default:
cf495bcf
FB		 1363 goto illegal_insn;
1364 }
e8af50a3 1365#if !defined(CONFIG_USER_ONLY)
e9ebed4d 1366 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 1367#ifndef TARGET_SPARC64
0f8a249a
BS		 1368 if (!supervisor(dc))
1369 goto priv_insn;
1a2fb1c0 1370 tcg_gen_helper_1_0(helper_rdpsr, cpu_T[0]);
e9ebed4d
BS		 1371#else
1372 if (!hypervisor(dc))
1373 goto priv_insn;
1374 rs1 = GET_FIELD(insn, 13, 17);
1375 switch (rs1) {
1376 case 0: // hpstate
1377 // gen_op_rdhpstate();
1378 break;
1379 case 1: // htstate
1380 // gen_op_rdhtstate();
1381 break;
1382 case 3: // hintp
1383 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1384 break;
1385 case 5: // htba
1386 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1387 break;
1388 case 6: // hver
1389 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1390 break;
1391 case 31: // hstick_cmpr
1392 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1393 break;
1394 default:
1395 goto illegal_insn;
1396 }
1397#endif
e8af50a3
FB		 1398 gen_movl_T0_reg(rd);
1399 break;
3475187d 1400 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
0f8a249a
BS		 1401 if (!supervisor(dc))
1402 goto priv_insn;
3475187d
FB		 1403#ifdef TARGET_SPARC64
1404 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1405 switch (rs1) {
1406 case 0: // tpc
375ee38b
BS		 1407 {
1408 TCGv r_tsptr;
1409
1410 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
1411 tcg_gen_ld_ptr(r_tsptr, cpu_env,
1412 offsetof(CPUState, tsptr));
1413 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
1414 offsetof(trap_state, tpc));
1415 }
0f8a249a
BS		 1416 break;
1417 case 1: // tnpc
375ee38b
BS		 1418 {
1419 TCGv r_tsptr;
1420
1421 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
1422 tcg_gen_ld_ptr(r_tsptr, cpu_env,
1423 offsetof(CPUState, tsptr));
1424 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
1425 offsetof(trap_state, tnpc));
1426 }
0f8a249a
BS		 1427 break;
1428 case 2: // tstate
375ee38b
BS		 1429 {
1430 TCGv r_tsptr;
1431
1432 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
1433 tcg_gen_ld_ptr(r_tsptr, cpu_env,
1434 offsetof(CPUState, tsptr));
1435 tcg_gen_ld_tl(cpu_T[0], r_tsptr,
1436 offsetof(trap_state, tstate));
1437 }
0f8a249a
BS		 1438 break;
1439 case 3: // tt
375ee38b
BS		 1440 {
1441 TCGv r_tsptr;
1442
1443 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
1444 tcg_gen_ld_ptr(r_tsptr, cpu_env,
1445 offsetof(CPUState, tsptr));
1446 tcg_gen_ld_i32(cpu_T[0], r_tsptr,
1447 offsetof(trap_state, tt));
1448 }
0f8a249a
BS		 1449 break;
1450 case 4: // tick
ccd4a219
BS		 1451 {
1452 TCGv r_tickptr;
1453
1454 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
1455 tcg_gen_ld_ptr(r_tickptr, cpu_env,
1456 offsetof(CPUState, tick));
1457 tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0],
1458 r_tickptr);
1459 gen_movl_T0_reg(rd);
1460 }
0f8a249a
BS		 1461 break;
1462 case 5: // tba
1463 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1464 break;
1465 case 6: // pstate
1a2fb1c0 1466 gen_op_movl_T0_env(offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 1467 break;
1468 case 7: // tl
1469 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1470 break;
1471 case 8: // pil
1472 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1473 break;
1474 case 9: // cwp
1475 gen_op_rdcwp();
1476 break;
1477 case 10: // cansave
1478 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1479 break;
1480 case 11: // canrestore
1481 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1482 break;
1483 case 12: // cleanwin
1484 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1485 break;
1486 case 13: // otherwin
1487 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1488 break;
1489 case 14: // wstate
1490 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1491 break;
e9ebed4d
BS		 1492 case 16: // UA2005 gl
1493 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1494 break;
1495 case 26: // UA2005 strand status
1496 if (!hypervisor(dc))
1497 goto priv_insn;
1498 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1499 break;
0f8a249a
BS		 1500 case 31: // ver
1501 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1502 break;
1503 case 15: // fq
1504 default:
1505 goto illegal_insn;
1506 }
3475187d 1507#else
0f8a249a 1508 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
3475187d 1509#endif
e8af50a3
FB		 1510 gen_movl_T0_reg(rd);
1511 break;
3475187d
FB		 1512 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1513#ifdef TARGET_SPARC64
0f8a249a 1514 gen_op_flushw();
3475187d 1515#else
0f8a249a
BS		 1516 if (!supervisor(dc))
1517 goto priv_insn;
1518 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
e8af50a3 1519 gen_movl_T0_reg(rd);
3475187d 1520#endif
e8af50a3
FB		 1521 break;
1522#endif
0f8a249a 1523 } else if (xop == 0x34) { /* FPU Operations */
a80dde08
FB		 1524 if (gen_trap_ifnofpu(dc))
1525 goto jmp_insn;
0f8a249a 1526 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 1527 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1528 rs2 = GET_FIELD(insn, 27, 31);
1529 xop = GET_FIELD(insn, 18, 26);
1530 switch (xop) {
1531 case 0x1: /* fmovs */
1532 gen_op_load_fpr_FT0(rs2);
1533 gen_op_store_FT0_fpr(rd);
1534 break;
1535 case 0x5: /* fnegs */
1536 gen_op_load_fpr_FT1(rs2);
1537 gen_op_fnegs();
1538 gen_op_store_FT0_fpr(rd);
1539 break;
1540 case 0x9: /* fabss */
1541 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1542 tcg_gen_helper_0_0(helper_fabss);
0f8a249a
BS		 1543 gen_op_store_FT0_fpr(rd);
1544 break;
1545 case 0x29: /* fsqrts */
1546 gen_op_load_fpr_FT1(rs2);
7e8c2b6c
BS		 1547 gen_clear_float_exceptions();
1548 tcg_gen_helper_0_0(helper_fsqrts);
1549 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1550 gen_op_store_FT0_fpr(rd);
1551 break;
1552 case 0x2a: /* fsqrtd */
1553 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c
BS		 1554 gen_clear_float_exceptions();
1555 tcg_gen_helper_0_0(helper_fsqrtd);
1556 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1557 gen_op_store_DT0_fpr(DFPREG(rd));
1558 break;
1559 case 0x2b: /* fsqrtq */
1f587329
BS		 1560#if defined(CONFIG_USER_ONLY)
1561 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c
BS		 1562 gen_clear_float_exceptions();
1563 tcg_gen_helper_0_0(helper_fsqrtq);
1564 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1565 gen_op_store_QT0_fpr(QFPREG(rd));
1566 break;
1567#else
0f8a249a 1568 goto nfpu_insn;
1f587329 1569#endif
0f8a249a
BS		 1570 case 0x41:
1571 gen_op_load_fpr_FT0(rs1);
1572 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1573 gen_clear_float_exceptions();
0f8a249a 1574 gen_op_fadds();
7e8c2b6c 1575 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1576 gen_op_store_FT0_fpr(rd);
1577 break;
1578 case 0x42:
1579 gen_op_load_fpr_DT0(DFPREG(rs1));
1580 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1581 gen_clear_float_exceptions();
0f8a249a 1582 gen_op_faddd();
7e8c2b6c 1583 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1584 gen_op_store_DT0_fpr(DFPREG(rd));
1585 break;
1586 case 0x43: /* faddq */
1f587329
BS		 1587#if defined(CONFIG_USER_ONLY)
1588 gen_op_load_fpr_QT0(QFPREG(rs1));
1589 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1590 gen_clear_float_exceptions();
1f587329 1591 gen_op_faddq();
7e8c2b6c 1592 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1593 gen_op_store_QT0_fpr(QFPREG(rd));
1594 break;
1595#else
0f8a249a 1596 goto nfpu_insn;
1f587329 1597#endif
0f8a249a
BS		 1598 case 0x45:
1599 gen_op_load_fpr_FT0(rs1);
1600 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1601 gen_clear_float_exceptions();
0f8a249a 1602 gen_op_fsubs();
7e8c2b6c 1603 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1604 gen_op_store_FT0_fpr(rd);
1605 break;
1606 case 0x46:
1607 gen_op_load_fpr_DT0(DFPREG(rs1));
1608 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1609 gen_clear_float_exceptions();
0f8a249a 1610 gen_op_fsubd();
7e8c2b6c 1611 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1612 gen_op_store_DT0_fpr(DFPREG(rd));
1613 break;
1614 case 0x47: /* fsubq */
1f587329
BS		 1615#if defined(CONFIG_USER_ONLY)
1616 gen_op_load_fpr_QT0(QFPREG(rs1));
1617 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1618 gen_clear_float_exceptions();
1f587329 1619 gen_op_fsubq();
7e8c2b6c 1620 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1621 gen_op_store_QT0_fpr(QFPREG(rd));
1622 break;
1623#else
0f8a249a 1624 goto nfpu_insn;
1f587329 1625#endif
0f8a249a
BS		 1626 case 0x49:
1627 gen_op_load_fpr_FT0(rs1);
1628 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1629 gen_clear_float_exceptions();
0f8a249a 1630 gen_op_fmuls();
7e8c2b6c 1631 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1632 gen_op_store_FT0_fpr(rd);
1633 break;
1634 case 0x4a:
1635 gen_op_load_fpr_DT0(DFPREG(rs1));
1636 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1637 gen_clear_float_exceptions();
0f8a249a 1638 gen_op_fmuld();
7e8c2b6c 1639 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2382dc6b 1640 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1641 break;
1642 case 0x4b: /* fmulq */
1f587329
BS		 1643#if defined(CONFIG_USER_ONLY)
1644 gen_op_load_fpr_QT0(QFPREG(rs1));
1645 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1646 gen_clear_float_exceptions();
1f587329 1647 gen_op_fmulq();
7e8c2b6c 1648 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1649 gen_op_store_QT0_fpr(QFPREG(rd));
1650 break;
1651#else
0f8a249a 1652 goto nfpu_insn;
1f587329 1653#endif
0f8a249a
BS		 1654 case 0x4d:
1655 gen_op_load_fpr_FT0(rs1);
1656 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1657 gen_clear_float_exceptions();
0f8a249a 1658 gen_op_fdivs();
7e8c2b6c 1659 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1660 gen_op_store_FT0_fpr(rd);
1661 break;
1662 case 0x4e:
1663 gen_op_load_fpr_DT0(DFPREG(rs1));
1664 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1665 gen_clear_float_exceptions();
0f8a249a 1666 gen_op_fdivd();
7e8c2b6c 1667 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1668 gen_op_store_DT0_fpr(DFPREG(rd));
1669 break;
1670 case 0x4f: /* fdivq */
1f587329
BS		 1671#if defined(CONFIG_USER_ONLY)
1672 gen_op_load_fpr_QT0(QFPREG(rs1));
1673 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1674 gen_clear_float_exceptions();
1f587329 1675 gen_op_fdivq();
7e8c2b6c 1676 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1677 gen_op_store_QT0_fpr(QFPREG(rd));
1678 break;
1679#else
0f8a249a 1680 goto nfpu_insn;
1f587329 1681#endif
0f8a249a
BS		 1682 case 0x69:
1683 gen_op_load_fpr_FT0(rs1);
1684 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1685 gen_clear_float_exceptions();
0f8a249a 1686 gen_op_fsmuld();
7e8c2b6c 1687 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1688 gen_op_store_DT0_fpr(DFPREG(rd));
1689 break;
1690 case 0x6e: /* fdmulq */
1f587329
BS		 1691#if defined(CONFIG_USER_ONLY)
1692 gen_op_load_fpr_DT0(DFPREG(rs1));
1693 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1694 gen_clear_float_exceptions();
1f587329 1695 gen_op_fdmulq();
7e8c2b6c 1696 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1697 gen_op_store_QT0_fpr(QFPREG(rd));
1698 break;
1699#else
0f8a249a 1700 goto nfpu_insn;
1f587329 1701#endif
0f8a249a
BS		 1702 case 0xc4:
1703 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1704 gen_clear_float_exceptions();
0f8a249a 1705 gen_op_fitos();
7e8c2b6c 1706 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1707 gen_op_store_FT0_fpr(rd);
1708 break;
1709 case 0xc6:
1710 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1711 gen_clear_float_exceptions();
0f8a249a 1712 gen_op_fdtos();
7e8c2b6c 1713 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1714 gen_op_store_FT0_fpr(rd);
1715 break;
1716 case 0xc7: /* fqtos */
1f587329
BS		 1717#if defined(CONFIG_USER_ONLY)
1718 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1719 gen_clear_float_exceptions();
1f587329 1720 gen_op_fqtos();
7e8c2b6c 1721 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1722 gen_op_store_FT0_fpr(rd);
1723 break;
1724#else
0f8a249a 1725 goto nfpu_insn;
1f587329 1726#endif
0f8a249a
BS		 1727 case 0xc8:
1728 gen_op_load_fpr_FT1(rs2);
1729 gen_op_fitod();
1730 gen_op_store_DT0_fpr(DFPREG(rd));
1731 break;
1732 case 0xc9:
1733 gen_op_load_fpr_FT1(rs2);
1734 gen_op_fstod();
1735 gen_op_store_DT0_fpr(DFPREG(rd));
1736 break;
1737 case 0xcb: /* fqtod */
1f587329
BS		 1738#if defined(CONFIG_USER_ONLY)
1739 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1740 gen_clear_float_exceptions();
1f587329 1741 gen_op_fqtod();
7e8c2b6c 1742 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1743 gen_op_store_DT0_fpr(DFPREG(rd));
1744 break;
1745#else
0f8a249a 1746 goto nfpu_insn;
1f587329 1747#endif
0f8a249a 1748 case 0xcc: /* fitoq */
1f587329
BS		 1749#if defined(CONFIG_USER_ONLY)
1750 gen_op_load_fpr_FT1(rs2);
1751 gen_op_fitoq();
1752 gen_op_store_QT0_fpr(QFPREG(rd));
1753 break;
1754#else
0f8a249a 1755 goto nfpu_insn;
1f587329 1756#endif
0f8a249a 1757 case 0xcd: /* fstoq */
1f587329
BS		 1758#if defined(CONFIG_USER_ONLY)
1759 gen_op_load_fpr_FT1(rs2);
1760 gen_op_fstoq();
1761 gen_op_store_QT0_fpr(QFPREG(rd));
1762 break;
1763#else
0f8a249a 1764 goto nfpu_insn;
1f587329 1765#endif
0f8a249a 1766 case 0xce: /* fdtoq */
1f587329
BS		 1767#if defined(CONFIG_USER_ONLY)
1768 gen_op_load_fpr_DT1(DFPREG(rs2));
1769 gen_op_fdtoq();
1770 gen_op_store_QT0_fpr(QFPREG(rd));
1771 break;
1772#else
0f8a249a 1773 goto nfpu_insn;
1f587329 1774#endif
0f8a249a
BS		 1775 case 0xd1:
1776 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1777 gen_clear_float_exceptions();
0f8a249a 1778 gen_op_fstoi();
7e8c2b6c 1779 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1780 gen_op_store_FT0_fpr(rd);
1781 break;
1782 case 0xd2:
2382dc6b 1783 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1784 gen_clear_float_exceptions();
0f8a249a 1785 gen_op_fdtoi();
7e8c2b6c 1786 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1787 gen_op_store_FT0_fpr(rd);
1788 break;
1789 case 0xd3: /* fqtoi */
1f587329
BS		 1790#if defined(CONFIG_USER_ONLY)
1791 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1792 gen_clear_float_exceptions();
1f587329 1793 gen_op_fqtoi();
7e8c2b6c 1794 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1795 gen_op_store_FT0_fpr(rd);
1796 break;
1797#else
0f8a249a 1798 goto nfpu_insn;
1f587329 1799#endif
3475187d 1800#ifdef TARGET_SPARC64
0f8a249a
BS		 1801 case 0x2: /* V9 fmovd */
1802 gen_op_load_fpr_DT0(DFPREG(rs2));
1803 gen_op_store_DT0_fpr(DFPREG(rd));
1804 break;
1f587329
BS		 1805 case 0x3: /* V9 fmovq */
1806#if defined(CONFIG_USER_ONLY)
1807 gen_op_load_fpr_QT0(QFPREG(rs2));
1808 gen_op_store_QT0_fpr(QFPREG(rd));
1809 break;
1810#else
1811 goto nfpu_insn;
1812#endif
0f8a249a
BS		 1813 case 0x6: /* V9 fnegd */
1814 gen_op_load_fpr_DT1(DFPREG(rs2));
1815 gen_op_fnegd();
1816 gen_op_store_DT0_fpr(DFPREG(rd));
1817 break;
1f587329
BS		 1818 case 0x7: /* V9 fnegq */
1819#if defined(CONFIG_USER_ONLY)
1820 gen_op_load_fpr_QT1(QFPREG(rs2));
1821 gen_op_fnegq();
1822 gen_op_store_QT0_fpr(QFPREG(rd));
1823 break;
1824#else
1825 goto nfpu_insn;
1826#endif
0f8a249a
BS		 1827 case 0xa: /* V9 fabsd */
1828 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1829 tcg_gen_helper_0_0(helper_fabsd);
0f8a249a
BS		 1830 gen_op_store_DT0_fpr(DFPREG(rd));
1831 break;
1f587329
BS		 1832 case 0xb: /* V9 fabsq */
1833#if defined(CONFIG_USER_ONLY)
1834 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1835 tcg_gen_helper_0_0(helper_fabsq);
1f587329
BS		 1836 gen_op_store_QT0_fpr(QFPREG(rd));
1837 break;
1838#else
1839 goto nfpu_insn;
1840#endif
0f8a249a
BS		 1841 case 0x81: /* V9 fstox */
1842 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 1843 gen_clear_float_exceptions();
0f8a249a 1844 gen_op_fstox();
7e8c2b6c 1845 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1846 gen_op_store_DT0_fpr(DFPREG(rd));
1847 break;
1848 case 0x82: /* V9 fdtox */
1849 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1850 gen_clear_float_exceptions();
0f8a249a 1851 gen_op_fdtox();
7e8c2b6c 1852 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1853 gen_op_store_DT0_fpr(DFPREG(rd));
1854 break;
1f587329
BS		 1855 case 0x83: /* V9 fqtox */
1856#if defined(CONFIG_USER_ONLY)
1857 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 1858 gen_clear_float_exceptions();
1f587329 1859 gen_op_fqtox();
7e8c2b6c 1860 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1861 gen_op_store_DT0_fpr(DFPREG(rd));
1862 break;
1863#else
1864 goto nfpu_insn;
1865#endif
0f8a249a
BS		 1866 case 0x84: /* V9 fxtos */
1867 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1868 gen_clear_float_exceptions();
0f8a249a 1869 gen_op_fxtos();
7e8c2b6c 1870 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1871 gen_op_store_FT0_fpr(rd);
1872 break;
1873 case 0x88: /* V9 fxtod */
1874 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1875 gen_clear_float_exceptions();
0f8a249a 1876 gen_op_fxtod();
7e8c2b6c 1877 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
0f8a249a
BS		 1878 gen_op_store_DT0_fpr(DFPREG(rd));
1879 break;
0f8a249a 1880 case 0x8c: /* V9 fxtoq */
1f587329
BS		 1881#if defined(CONFIG_USER_ONLY)
1882 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 1883 gen_clear_float_exceptions();
1f587329 1884 gen_op_fxtoq();
7e8c2b6c 1885 tcg_gen_helper_0_0(helper_check_ieee_exceptions);
1f587329
BS		 1886 gen_op_store_QT0_fpr(QFPREG(rd));
1887 break;
1888#else
0f8a249a 1889 goto nfpu_insn;
1f587329 1890#endif
0f8a249a
BS		 1891#endif
1892 default:
1893 goto illegal_insn;
1894 }
1895 } else if (xop == 0x35) { /* FPU Operations */
3475187d 1896#ifdef TARGET_SPARC64
0f8a249a 1897 int cond;
3475187d 1898#endif
a80dde08
FB		 1899 if (gen_trap_ifnofpu(dc))
1900 goto jmp_insn;
0f8a249a 1901 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 1902 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 1903 rs2 = GET_FIELD(insn, 27, 31);
1904 xop = GET_FIELD(insn, 18, 26);
3475187d 1905#ifdef TARGET_SPARC64
0f8a249a 1906 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
dcf24905
BS		 1907 TCGv r_zero;
1908 int l1;
1909
1910 l1 = gen_new_label();
1911 r_zero = tcg_temp_new(TCG_TYPE_TL);
0f8a249a 1912 cond = GET_FIELD_SP(insn, 14, 17);
0f8a249a
BS		 1913 rs1 = GET_FIELD(insn, 13, 17);
1914 gen_movl_reg_T0(rs1);
dcf24905
BS		 1915 tcg_gen_movi_tl(r_zero, 0);
1916 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
1917 gen_op_load_fpr_FT1(rs2);
0f8a249a 1918 gen_op_store_FT0_fpr(rd);
dcf24905 1919 gen_set_label(l1);
0f8a249a
BS		 1920 break;
1921 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
dcf24905
BS		 1922 TCGv r_zero;
1923 int l1;
1924
1925 l1 = gen_new_label();
1926 r_zero = tcg_temp_new(TCG_TYPE_TL);
0f8a249a 1927 cond = GET_FIELD_SP(insn, 14, 17);
0f8a249a
BS		 1928 rs1 = GET_FIELD(insn, 13, 17);
1929 gen_movl_reg_T0(rs1);
dcf24905
BS		 1930 tcg_gen_movi_tl(r_zero, 0);
1931 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
1932 gen_op_load_fpr_DT1(DFPREG(rs2));
2382dc6b 1933 gen_op_store_DT0_fpr(DFPREG(rd));
dcf24905 1934 gen_set_label(l1);
0f8a249a
BS		 1935 break;
1936 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1f587329 1937#if defined(CONFIG_USER_ONLY)
dcf24905
BS		 1938 TCGv r_zero;
1939 int l1;
1940
1941 l1 = gen_new_label();
1942 r_zero = tcg_temp_new(TCG_TYPE_TL);
1f587329 1943 cond = GET_FIELD_SP(insn, 14, 17);
1f587329
BS		 1944 rs1 = GET_FIELD(insn, 13, 17);
1945 gen_movl_reg_T0(rs1);
dcf24905
BS		 1946 tcg_gen_movi_tl(r_zero, 0);
1947 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
1948 gen_op_load_fpr_QT1(QFPREG(rs2));
1f587329 1949 gen_op_store_QT0_fpr(QFPREG(rd));
dcf24905 1950 gen_set_label(l1);
1f587329
BS		 1951 break;
1952#else
0f8a249a 1953 goto nfpu_insn;
1f587329 1954#endif
0f8a249a
BS		 1955 }
1956#endif
1957 switch (xop) {
3475187d 1958#ifdef TARGET_SPARC64
0f8a249a
BS		 1959 case 0x001: /* V9 fmovscc %fcc0 */
1960 cond = GET_FIELD_SP(insn, 14, 17);
1961 gen_op_load_fpr_FT0(rd);
1962 gen_op_load_fpr_FT1(rs2);
1963 flush_T2(dc);
1964 gen_fcond[0][cond]();
1965 gen_op_fmovs_cc();
1966 gen_op_store_FT0_fpr(rd);
1967 break;
1968 case 0x002: /* V9 fmovdcc %fcc0 */
1969 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 1970 gen_op_load_fpr_DT0(DFPREG(rd));
1971 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 1972 flush_T2(dc);
1973 gen_fcond[0][cond]();
1974 gen_op_fmovd_cc();
2382dc6b 1975 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 1976 break;
1977 case 0x003: /* V9 fmovqcc %fcc0 */
1f587329
BS		 1978#if defined(CONFIG_USER_ONLY)
1979 cond = GET_FIELD_SP(insn, 14, 17);
1980 gen_op_load_fpr_QT0(QFPREG(rd));
1981 gen_op_load_fpr_QT1(QFPREG(rs2));
1982 flush_T2(dc);
1983 gen_fcond[0][cond]();
1984 gen_op_fmovq_cc();
1985 gen_op_store_QT0_fpr(QFPREG(rd));
1986 break;
1987#else
0f8a249a 1988 goto nfpu_insn;
1f587329 1989#endif
0f8a249a
BS		 1990 case 0x041: /* V9 fmovscc %fcc1 */
1991 cond = GET_FIELD_SP(insn, 14, 17);
1992 gen_op_load_fpr_FT0(rd);
1993 gen_op_load_fpr_FT1(rs2);
1994 flush_T2(dc);
1995 gen_fcond[1][cond]();
1996 gen_op_fmovs_cc();
1997 gen_op_store_FT0_fpr(rd);
1998 break;
1999 case 0x042: /* V9 fmovdcc %fcc1 */
2000 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 2001 gen_op_load_fpr_DT0(DFPREG(rd));
2002 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 2003 flush_T2(dc);
2004 gen_fcond[1][cond]();
2005 gen_op_fmovd_cc();
2382dc6b 2006 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2007 break;
2008 case 0x043: /* V9 fmovqcc %fcc1 */
1f587329
BS		 2009#if defined(CONFIG_USER_ONLY)
2010 cond = GET_FIELD_SP(insn, 14, 17);
2011 gen_op_load_fpr_QT0(QFPREG(rd));
2012 gen_op_load_fpr_QT1(QFPREG(rs2));
2013 flush_T2(dc);
2014 gen_fcond[1][cond]();
2015 gen_op_fmovq_cc();
2016 gen_op_store_QT0_fpr(QFPREG(rd));
2017 break;
2018#else
0f8a249a 2019 goto nfpu_insn;
1f587329 2020#endif
0f8a249a
BS		 2021 case 0x081: /* V9 fmovscc %fcc2 */
2022 cond = GET_FIELD_SP(insn, 14, 17);
2023 gen_op_load_fpr_FT0(rd);
2024 gen_op_load_fpr_FT1(rs2);
2025 flush_T2(dc);
2026 gen_fcond[2][cond]();
2027 gen_op_fmovs_cc();
2028 gen_op_store_FT0_fpr(rd);
2029 break;
2030 case 0x082: /* V9 fmovdcc %fcc2 */
2031 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 2032 gen_op_load_fpr_DT0(DFPREG(rd));
2033 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 2034 flush_T2(dc);
2035 gen_fcond[2][cond]();
2036 gen_op_fmovd_cc();
2382dc6b 2037 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2038 break;
2039 case 0x083: /* V9 fmovqcc %fcc2 */
1f587329
BS		 2040#if defined(CONFIG_USER_ONLY)
2041 cond = GET_FIELD_SP(insn, 14, 17);
2042 gen_op_load_fpr_QT0(rd);
2043 gen_op_load_fpr_QT1(rs2);
2044 flush_T2(dc);
2045 gen_fcond[2][cond]();
2046 gen_op_fmovq_cc();
2047 gen_op_store_QT0_fpr(rd);
2048 break;
2049#else
0f8a249a 2050 goto nfpu_insn;
1f587329 2051#endif
0f8a249a
BS		 2052 case 0x0c1: /* V9 fmovscc %fcc3 */
2053 cond = GET_FIELD_SP(insn, 14, 17);
2054 gen_op_load_fpr_FT0(rd);
2055 gen_op_load_fpr_FT1(rs2);
2056 flush_T2(dc);
2057 gen_fcond[3][cond]();
2058 gen_op_fmovs_cc();
2059 gen_op_store_FT0_fpr(rd);
2060 break;
2061 case 0x0c2: /* V9 fmovdcc %fcc3 */
2062 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 2063 gen_op_load_fpr_DT0(DFPREG(rd));
2064 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 2065 flush_T2(dc);
2066 gen_fcond[3][cond]();
2067 gen_op_fmovd_cc();
2382dc6b 2068 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2069 break;
2070 case 0x0c3: /* V9 fmovqcc %fcc3 */
1f587329
BS		 2071#if defined(CONFIG_USER_ONLY)
2072 cond = GET_FIELD_SP(insn, 14, 17);
2073 gen_op_load_fpr_QT0(QFPREG(rd));
2074 gen_op_load_fpr_QT1(QFPREG(rs2));
2075 flush_T2(dc);
2076 gen_fcond[3][cond]();
2077 gen_op_fmovq_cc();
2078 gen_op_store_QT0_fpr(QFPREG(rd));
2079 break;
2080#else
0f8a249a 2081 goto nfpu_insn;
1f587329 2082#endif
0f8a249a
BS		 2083 case 0x101: /* V9 fmovscc %icc */
2084 cond = GET_FIELD_SP(insn, 14, 17);
2085 gen_op_load_fpr_FT0(rd);
2086 gen_op_load_fpr_FT1(rs2);
2087 flush_T2(dc);
2088 gen_cond[0][cond]();
2089 gen_op_fmovs_cc();
2090 gen_op_store_FT0_fpr(rd);
2091 break;
2092 case 0x102: /* V9 fmovdcc %icc */
2093 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 2094 gen_op_load_fpr_DT0(DFPREG(rd));
2095 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 2096 flush_T2(dc);
2097 gen_cond[0][cond]();
2098 gen_op_fmovd_cc();
2382dc6b 2099 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2100 break;
2101 case 0x103: /* V9 fmovqcc %icc */
1f587329
BS		 2102#if defined(CONFIG_USER_ONLY)
2103 cond = GET_FIELD_SP(insn, 14, 17);
2104 gen_op_load_fpr_QT0(rd);
2105 gen_op_load_fpr_QT1(rs2);
2106 flush_T2(dc);
2107 gen_cond[0][cond]();
2108 gen_op_fmovq_cc();
2109 gen_op_store_QT0_fpr(rd);
2110 break;
2111#else
0f8a249a 2112 goto nfpu_insn;
1f587329 2113#endif
0f8a249a
BS		 2114 case 0x181: /* V9 fmovscc %xcc */
2115 cond = GET_FIELD_SP(insn, 14, 17);
2116 gen_op_load_fpr_FT0(rd);
2117 gen_op_load_fpr_FT1(rs2);
2118 flush_T2(dc);
2119 gen_cond[1][cond]();
2120 gen_op_fmovs_cc();
2121 gen_op_store_FT0_fpr(rd);
2122 break;
2123 case 0x182: /* V9 fmovdcc %xcc */
2124 cond = GET_FIELD_SP(insn, 14, 17);
2382dc6b
BS		 2125 gen_op_load_fpr_DT0(DFPREG(rd));
2126 gen_op_load_fpr_DT1(DFPREG(rs2));
0f8a249a
BS		 2127 flush_T2(dc);
2128 gen_cond[1][cond]();
2129 gen_op_fmovd_cc();
2382dc6b 2130 gen_op_store_DT0_fpr(DFPREG(rd));
0f8a249a
BS		 2131 break;
2132 case 0x183: /* V9 fmovqcc %xcc */
1f587329
BS		 2133#if defined(CONFIG_USER_ONLY)
2134 cond = GET_FIELD_SP(insn, 14, 17);
2135 gen_op_load_fpr_QT0(rd);
2136 gen_op_load_fpr_QT1(rs2);
2137 flush_T2(dc);
2138 gen_cond[1][cond]();
2139 gen_op_fmovq_cc();
2140 gen_op_store_QT0_fpr(rd);
2141 break;
2142#else
0f8a249a
BS		 2143 goto nfpu_insn;
2144#endif
1f587329
BS		 2145#endif
2146 case 0x51: /* fcmps, V9 %fcc */
0f8a249a
BS		 2147 gen_op_load_fpr_FT0(rs1);
2148 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2149 gen_op_fcmps(rd & 3);
0f8a249a 2150 break;
1f587329 2151 case 0x52: /* fcmpd, V9 %fcc */
0f8a249a
BS		 2152 gen_op_load_fpr_DT0(DFPREG(rs1));
2153 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2154 gen_op_fcmpd(rd & 3);
0f8a249a 2155 break;
1f587329
BS		 2156 case 0x53: /* fcmpq, V9 %fcc */
2157#if defined(CONFIG_USER_ONLY)
2158 gen_op_load_fpr_QT0(QFPREG(rs1));
2159 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2160 gen_op_fcmpq(rd & 3);
1f587329
BS		 2161 break;
2162#else /* !defined(CONFIG_USER_ONLY) */
0f8a249a 2163 goto nfpu_insn;
1f587329 2164#endif
0f8a249a
BS		 2165 case 0x55: /* fcmpes, V9 %fcc */
2166 gen_op_load_fpr_FT0(rs1);
2167 gen_op_load_fpr_FT1(rs2);
7e8c2b6c 2168 gen_op_fcmpes(rd & 3);
0f8a249a
BS		 2169 break;
2170 case 0x56: /* fcmped, V9 %fcc */
2171 gen_op_load_fpr_DT0(DFPREG(rs1));
2172 gen_op_load_fpr_DT1(DFPREG(rs2));
7e8c2b6c 2173 gen_op_fcmped(rd & 3);
0f8a249a 2174 break;
1f587329
BS		 2175 case 0x57: /* fcmpeq, V9 %fcc */
2176#if defined(CONFIG_USER_ONLY)
2177 gen_op_load_fpr_QT0(QFPREG(rs1));
2178 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 2179 gen_op_fcmpeq(rd & 3);
1f587329
BS		 2180 break;
2181#else/* !defined(CONFIG_USER_ONLY) */
0f8a249a 2182 goto nfpu_insn;
1f587329 2183#endif
0f8a249a
BS		 2184 default:
2185 goto illegal_insn;
2186 }
e80cfcfc 2187#if defined(OPTIM)
0f8a249a
BS		 2188 } else if (xop == 0x2) {
2189 // clr/mov shortcut
e80cfcfc
FB		 2190
2191 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2192 if (rs1 == 0) {
1a2fb1c0 2193 // or %g0, x, y -> mov T0, x; mov y, T0
0f8a249a
BS		 2194 if (IS_IMM) { /* immediate */
2195 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2196 tcg_gen_movi_tl(cpu_T[0], (int)rs2);
0f8a249a
BS		 2197 } else { /* register */
2198 rs2 = GET_FIELD(insn, 27, 31);
1a2fb1c0 2199 gen_movl_reg_T0(rs2);
0f8a249a 2200 }
0f8a249a
BS		 2201 } else {
2202 gen_movl_reg_T0(rs1);
2203 if (IS_IMM) { /* immediate */
0f8a249a 2204 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 2205 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 2206 } else { /* register */
2207 // or x, %g0, y -> mov T1, x; mov y, T1
2208 rs2 = GET_FIELD(insn, 27, 31);
2209 if (rs2 != 0) {
2210 gen_movl_reg_T1(rs2);
2211 gen_op_or_T1_T0();
2212 }
2213 }
0f8a249a 2214 }
1a2fb1c0 2215 gen_movl_T0_reg(rd);
83469015
FB		 2216#endif
2217#ifdef TARGET_SPARC64
0f8a249a 2218 } else if (xop == 0x25) { /* sll, V9 sllx */
83469015 2219 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2220 gen_movl_reg_T0(rs1);
2221 if (IS_IMM) { /* immediate */
83469015 2222 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2223 if (insn & (1 << 12)) {
2224 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2225 } else {
2226 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2227 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2228 }
0f8a249a 2229 } else { /* register */
83469015
FB		 2230 rs2 = GET_FIELD(insn, 27, 31);
2231 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2232 if (insn & (1 << 12)) {
2233 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2234 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2235 } else {
2236 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2237 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2238 tcg_gen_shl_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2239 }
83469015 2240 }
0f8a249a
BS		 2241 gen_movl_T0_reg(rd);
2242 } else if (xop == 0x26) { /* srl, V9 srlx */
83469015 2243 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2244 gen_movl_reg_T0(rs1);
2245 if (IS_IMM) { /* immediate */
83469015 2246 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2247 if (insn & (1 << 12)) {
2248 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2249 } else {
2250 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2251 tcg_gen_shri_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2252 }
0f8a249a 2253 } else { /* register */
83469015
FB		 2254 rs2 = GET_FIELD(insn, 27, 31);
2255 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2256 if (insn & (1 << 12)) {
2257 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2258 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2259 } else {
2260 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2261 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2262 tcg_gen_shr_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2263 }
83469015 2264 }
0f8a249a
BS		 2265 gen_movl_T0_reg(rd);
2266 } else if (xop == 0x27) { /* sra, V9 srax */
83469015 2267 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2268 gen_movl_reg_T0(rs1);
2269 if (IS_IMM) { /* immediate */
83469015 2270 rs2 = GET_FIELDs(insn, 20, 31);
1a2fb1c0
BS		 2271 if (insn & (1 << 12)) {
2272 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x3f);
2273 } else {
2274 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2275 tcg_gen_ext_i32_i64(cpu_T[0], cpu_T[0]);
2276 tcg_gen_sari_i64(cpu_T[0], cpu_T[0], rs2 & 0x1f);
2277 }
0f8a249a 2278 } else { /* register */
83469015
FB		 2279 rs2 = GET_FIELD(insn, 27, 31);
2280 gen_movl_reg_T1(rs2);
1a2fb1c0
BS		 2281 if (insn & (1 << 12)) {
2282 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x3f);
2283 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2284 } else {
2285 tcg_gen_andi_i64(cpu_T[1], cpu_T[1], 0x1f);
2286 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], 0xffffffffULL);
2287 tcg_gen_sar_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2288 }
83469015 2289 }
0f8a249a 2290 gen_movl_T0_reg(rd);
e80cfcfc 2291#endif
fcc72045 2292 } else if (xop < 0x36) {
e80cfcfc 2293 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2294 gen_movl_reg_T0(rs1);
2295 if (IS_IMM) { /* immediate */
cf495bcf 2296 rs2 = GET_FIELDs(insn, 19, 31);
3475187d 2297 gen_movl_simm_T1(rs2);
0f8a249a 2298 } else { /* register */
cf495bcf
FB		 2299 rs2 = GET_FIELD(insn, 27, 31);
2300 gen_movl_reg_T1(rs2);
2301 }
2302 if (xop < 0x20) {
2303 switch (xop & ~0x10) {
2304 case 0x0:
2305 if (xop & 0x10)
2306 gen_op_add_T1_T0_cc();
2307 else
2308 gen_op_add_T1_T0();
2309 break;
2310 case 0x1:
1a2fb1c0 2311 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2312 if (xop & 0x10)
2313 gen_op_logic_T0_cc();
2314 break;
2315 case 0x2:
1a2fb1c0 2316 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
0f8a249a
BS		 2317 if (xop & 0x10)
2318 gen_op_logic_T0_cc();
2319 break;
cf495bcf 2320 case 0x3:
1a2fb1c0 2321 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2322 if (xop & 0x10)
2323 gen_op_logic_T0_cc();
2324 break;
2325 case 0x4:
2326 if (xop & 0x10)
2327 gen_op_sub_T1_T0_cc();
2328 else
1a2fb1c0 2329 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2330 break;
2331 case 0x5:
2332 gen_op_andn_T1_T0();
2333 if (xop & 0x10)
2334 gen_op_logic_T0_cc();
2335 break;
2336 case 0x6:
2337 gen_op_orn_T1_T0();
2338 if (xop & 0x10)
2339 gen_op_logic_T0_cc();
2340 break;
2341 case 0x7:
2342 gen_op_xnor_T1_T0();
2343 if (xop & 0x10)
2344 gen_op_logic_T0_cc();
2345 break;
2346 case 0x8:
cf495bcf 2347 if (xop & 0x10)
af7bf89b 2348 gen_op_addx_T1_T0_cc();
38bc628b
BS		 2349 else {
2350 gen_mov_reg_C(cpu_tmp0);
2351 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2352 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2353 }
cf495bcf 2354 break;
ded3ab80 2355#ifdef TARGET_SPARC64
0f8a249a 2356 case 0x9: /* V9 mulx */
1a2fb1c0 2357 tcg_gen_mul_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
ded3ab80
PB		 2358 break;
2359#endif
cf495bcf
FB		 2360 case 0xa:
2361 gen_op_umul_T1_T0();
2362 if (xop & 0x10)
2363 gen_op_logic_T0_cc();
2364 break;
2365 case 0xb:
2366 gen_op_smul_T1_T0();
2367 if (xop & 0x10)
2368 gen_op_logic_T0_cc();
2369 break;
2370 case 0xc:
cf495bcf 2371 if (xop & 0x10)
af7bf89b 2372 gen_op_subx_T1_T0_cc();
38bc628b
BS		 2373 else {
2374 gen_mov_reg_C(cpu_tmp0);
2375 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
2376 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2377 }
cf495bcf 2378 break;
ded3ab80 2379#ifdef TARGET_SPARC64
0f8a249a 2380 case 0xd: /* V9 udivx */
ded3ab80
PB		 2381 gen_op_udivx_T1_T0();
2382 break;
2383#endif
cf495bcf
FB		 2384 case 0xe:
2385 gen_op_udiv_T1_T0();
2386 if (xop & 0x10)
2387 gen_op_div_cc();
2388 break;
2389 case 0xf:
2390 gen_op_sdiv_T1_T0();
2391 if (xop & 0x10)
2392 gen_op_div_cc();
2393 break;
2394 default:
2395 goto illegal_insn;
2396 }
0f8a249a 2397 gen_movl_T0_reg(rd);
cf495bcf
FB		 2398 } else {
2399 switch (xop) {
0f8a249a
BS		 2400 case 0x20: /* taddcc */
2401 gen_op_tadd_T1_T0_cc();
2402 gen_movl_T0_reg(rd);
2403 break;
2404 case 0x21: /* tsubcc */
2405 gen_op_tsub_T1_T0_cc();
2406 gen_movl_T0_reg(rd);
2407 break;
2408 case 0x22: /* taddcctv */
90251fb9 2409 save_state(dc);
0f8a249a
BS		 2410 gen_op_tadd_T1_T0_ccTV();
2411 gen_movl_T0_reg(rd);
2412 break;
2413 case 0x23: /* tsubcctv */
90251fb9 2414 save_state(dc);
0f8a249a
BS		 2415 gen_op_tsub_T1_T0_ccTV();
2416 gen_movl_T0_reg(rd);
2417 break;
cf495bcf
FB		 2418 case 0x24: /* mulscc */
2419 gen_op_mulscc_T1_T0();
2420 gen_movl_T0_reg(rd);
2421 break;
83469015 2422#ifndef TARGET_SPARC64
0f8a249a 2423 case 0x25: /* sll */
1a2fb1c0
BS		 2424 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
2425 tcg_gen_shl_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2426 gen_movl_T0_reg(rd);
2427 break;
83469015 2428 case 0x26: /* srl */
1a2fb1c0
BS		 2429 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
2430 tcg_gen_shr_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2431 gen_movl_T0_reg(rd);
2432 break;
83469015 2433 case 0x27: /* sra */
1a2fb1c0
BS		 2434 tcg_gen_andi_i32(cpu_T[1], cpu_T[1], 0x1f);
2435 tcg_gen_sar_i32(cpu_T[0], cpu_T[0], cpu_T[1]);
cf495bcf
FB		 2436 gen_movl_T0_reg(rd);
2437 break;
83469015 2438#endif
cf495bcf
FB		 2439 case 0x30:
2440 {
cf495bcf 2441 switch(rd) {
3475187d 2442 case 0: /* wry */
0f8a249a
BS		 2443 gen_op_xor_T1_T0();
2444 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
cf495bcf 2445 break;
65fe7b09
BS		 2446#ifndef TARGET_SPARC64
2447 case 0x01 ... 0x0f: /* undefined in the
2448 SPARCv8 manual, nop
2449 on the microSPARC
2450 II */
2451 case 0x10 ... 0x1f: /* implementation-dependent
2452 in the SPARCv8
2453 manual, nop on the
2454 microSPARC II */
2455 break;
2456#else
0f8a249a 2457 case 0x2: /* V9 wrccr */
ee0b03fd 2458 gen_op_xor_T1_T0();
3475187d 2459 gen_op_wrccr();
0f8a249a
BS		 2460 break;
2461 case 0x3: /* V9 wrasi */
ee0b03fd 2462 gen_op_xor_T1_T0();
0f8a249a
BS		 2463 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
2464 break;
2465 case 0x6: /* V9 wrfprs */
2466 gen_op_xor_T1_T0();
2467 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
3299908c
BS		 2468 save_state(dc);
2469 gen_op_next_insn();
57fec1fe 2470 tcg_gen_exit_tb(0);
3299908c 2471 dc->is_br = 1;
0f8a249a
BS		 2472 break;
2473 case 0xf: /* V9 sir, nop if user */
3475187d 2474#if !defined(CONFIG_USER_ONLY)
0f8a249a 2475 if (supervisor(dc))
1a2fb1c0 2476 ; // XXX
3475187d 2477#endif
0f8a249a
BS		 2478 break;
2479 case 0x13: /* Graphics Status */
725cb90b
FB		 2480 if (gen_trap_ifnofpu(dc))
2481 goto jmp_insn;
ee0b03fd 2482 gen_op_xor_T1_T0();
0f8a249a
BS		 2483 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
2484 break;
2485 case 0x17: /* Tick compare */
83469015 2486#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2487 if (!supervisor(dc))
2488 goto illegal_insn;
83469015 2489#endif
ccd4a219
BS		 2490 {
2491 TCGv r_tickptr;
2492
2493 gen_op_xor_T1_T0();
2494 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
2495 tick_cmpr));
2496 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2497 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2498 offsetof(CPUState, tick));
2499 tcg_gen_helper_0_2(helper_tick_set_limit,
2500 r_tickptr, cpu_T[0]);
2501 }
0f8a249a
BS		 2502 break;
2503 case 0x18: /* System tick */
83469015 2504#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2505 if (!supervisor(dc))
2506 goto illegal_insn;
83469015 2507#endif
ccd4a219
BS		 2508 {
2509 TCGv r_tickptr;
2510
2511 gen_op_xor_T1_T0();
2512 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2513 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2514 offsetof(CPUState, stick));
2515 tcg_gen_helper_0_2(helper_tick_set_count,
2516 r_tickptr, cpu_T[0]);
2517 }
0f8a249a
BS		 2518 break;
2519 case 0x19: /* System tick compare */
83469015 2520#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 2521 if (!supervisor(dc))
2522 goto illegal_insn;
3475187d 2523#endif
ccd4a219
BS		 2524 {
2525 TCGv r_tickptr;
2526
2527 gen_op_xor_T1_T0();
2528 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
2529 stick_cmpr));
2530 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2531 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2532 offsetof(CPUState, stick));
2533 tcg_gen_helper_0_2(helper_tick_set_limit,
2534 r_tickptr, cpu_T[0]);
2535 }
0f8a249a 2536 break;
83469015 2537
0f8a249a
BS		 2538 case 0x10: /* Performance Control */
2539 case 0x11: /* Performance Instrumentation Counter */
2540 case 0x12: /* Dispatch Control */
2541 case 0x14: /* Softint set */
2542 case 0x15: /* Softint clear */
2543 case 0x16: /* Softint write */
83469015 2544#endif
3475187d 2545 default:
cf495bcf
FB		 2546 goto illegal_insn;
2547 }
2548 }
2549 break;
e8af50a3 2550#if !defined(CONFIG_USER_ONLY)
af7bf89b 2551 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 2552 {
0f8a249a
BS		 2553 if (!supervisor(dc))
2554 goto priv_insn;
3475187d 2555#ifdef TARGET_SPARC64
0f8a249a
BS		 2556 switch (rd) {
2557 case 0:
2558 gen_op_saved();
2559 break;
2560 case 1:
2561 gen_op_restored();
2562 break;
e9ebed4d
BS		 2563 case 2: /* UA2005 allclean */
2564 case 3: /* UA2005 otherw */
2565 case 4: /* UA2005 normalw */
2566 case 5: /* UA2005 invalw */
2567 // XXX
0f8a249a 2568 default:
3475187d
FB		 2569 goto illegal_insn;
2570 }
2571#else
e8af50a3 2572 gen_op_xor_T1_T0();
1a2fb1c0 2573 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
9e61bde5
FB		 2574 save_state(dc);
2575 gen_op_next_insn();
57fec1fe 2576 tcg_gen_exit_tb(0);
0f8a249a 2577 dc->is_br = 1;
3475187d 2578#endif
e8af50a3
FB		 2579 }
2580 break;
af7bf89b 2581 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 2582 {
0f8a249a
BS		 2583 if (!supervisor(dc))
2584 goto priv_insn;
e8af50a3 2585 gen_op_xor_T1_T0();
3475187d 2586#ifdef TARGET_SPARC64
0f8a249a
BS		 2587 switch (rd) {
2588 case 0: // tpc
375ee38b
BS		 2589 {
2590 TCGv r_tsptr;
2591
2592 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2593 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2594 offsetof(CPUState, tsptr));
2595 tcg_gen_st_tl(cpu_T[0], r_tsptr,
2596 offsetof(trap_state, tpc));
2597 }
0f8a249a
BS		 2598 break;
2599 case 1: // tnpc
375ee38b
BS		 2600 {
2601 TCGv r_tsptr;
2602
2603 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2604 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2605 offsetof(CPUState, tsptr));
2606 tcg_gen_st_tl(cpu_T[0], r_tsptr,
2607 offsetof(trap_state, tnpc));
2608 }
0f8a249a
BS		 2609 break;
2610 case 2: // tstate
375ee38b
BS		 2611 {
2612 TCGv r_tsptr;
2613
2614 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2615 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2616 offsetof(CPUState, tsptr));
2617 tcg_gen_st_tl(cpu_T[0], r_tsptr,
2618 offsetof(trap_state, tstate));
2619 }
0f8a249a
BS		 2620 break;
2621 case 3: // tt
375ee38b
BS		 2622 {
2623 TCGv r_tsptr;
2624
2625 r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2626 tcg_gen_ld_ptr(r_tsptr, cpu_env,
2627 offsetof(CPUState, tsptr));
2628 tcg_gen_st_i32(cpu_T[0], r_tsptr,
2629 offsetof(trap_state, tt));
2630 }
0f8a249a
BS		 2631 break;
2632 case 4: // tick
ccd4a219
BS		 2633 {
2634 TCGv r_tickptr;
2635
2636 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2637 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2638 offsetof(CPUState, tick));
2639 tcg_gen_helper_0_2(helper_tick_set_count,
2640 r_tickptr, cpu_T[0]);
2641 }
0f8a249a
BS		 2642 break;
2643 case 5: // tba
2644 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2645 break;
2646 case 6: // pstate
ded3ab80 2647 save_state(dc);
1a2fb1c0 2648 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
ded3ab80 2649 gen_op_next_insn();
57fec1fe 2650 tcg_gen_exit_tb(0);
ded3ab80 2651 dc->is_br = 1;
0f8a249a
BS		 2652 break;
2653 case 7: // tl
2654 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2655 break;
2656 case 8: // pil
2657 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2658 break;
2659 case 9: // cwp
2660 gen_op_wrcwp();
2661 break;
2662 case 10: // cansave
2663 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2664 break;
2665 case 11: // canrestore
2666 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2667 break;
2668 case 12: // cleanwin
2669 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2670 break;
2671 case 13: // otherwin
2672 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2673 break;
2674 case 14: // wstate
2675 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2676 break;
e9ebed4d
BS		 2677 case 16: // UA2005 gl
2678 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2679 break;
2680 case 26: // UA2005 strand status
2681 if (!hypervisor(dc))
2682 goto priv_insn;
2683 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2684 break;
0f8a249a
BS		 2685 default:
2686 goto illegal_insn;
2687 }
3475187d 2688#else
1a2fb1c0
BS		 2689 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ((1 << NWINDOWS) - 1));
2690 gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
3475187d 2691#endif
e8af50a3
FB		 2692 }
2693 break;
e9ebed4d 2694 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 2695 {
e9ebed4d 2696#ifndef TARGET_SPARC64
0f8a249a
BS		 2697 if (!supervisor(dc))
2698 goto priv_insn;
e8af50a3 2699 gen_op_xor_T1_T0();
e9ebed4d
BS		 2700 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2701#else
2702 if (!hypervisor(dc))
2703 goto priv_insn;
2704 gen_op_xor_T1_T0();
2705 switch (rd) {
2706 case 0: // hpstate
2707 // XXX gen_op_wrhpstate();
2708 save_state(dc);
2709 gen_op_next_insn();
57fec1fe 2710 tcg_gen_exit_tb(0);
e9ebed4d
BS		 2711 dc->is_br = 1;
2712 break;
2713 case 1: // htstate
2714 // XXX gen_op_wrhtstate();
2715 break;
2716 case 3: // hintp
2717 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2718 break;
2719 case 5: // htba
2720 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2721 break;
2722 case 31: // hstick_cmpr
ccd4a219
BS		 2723 {
2724 TCGv r_tickptr;
2725
2726 gen_op_movtl_env_T0(offsetof(CPUSPARCState,
2727 hstick_cmpr));
2728 r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2729 tcg_gen_ld_ptr(r_tickptr, cpu_env,
2730 offsetof(CPUState, hstick));
2731 tcg_gen_helper_0_2(helper_tick_set_limit,
2732 r_tickptr, cpu_T[0]);
2733 }
e9ebed4d
BS		 2734 break;
2735 case 6: // hver readonly
2736 default:
2737 goto illegal_insn;
2738 }
2739#endif
e8af50a3
FB		 2740 }
2741 break;
2742#endif
3475187d 2743#ifdef TARGET_SPARC64
0f8a249a
BS		 2744 case 0x2c: /* V9 movcc */
2745 {
2746 int cc = GET_FIELD_SP(insn, 11, 12);
2747 int cond = GET_FIELD_SP(insn, 14, 17);
00f219bf
BS		 2748 TCGv r_zero;
2749 int l1;
2750
0f8a249a
BS		 2751 flush_T2(dc);
2752 if (insn & (1 << 18)) {
2753 if (cc == 0)
2754 gen_cond[0][cond]();
2755 else if (cc == 2)
2756 gen_cond[1][cond]();
2757 else
2758 goto illegal_insn;
2759 } else {
2760 gen_fcond[cc][cond]();
2761 }
00f219bf
BS		 2762
2763 l1 = gen_new_label();
2764
2765 r_zero = tcg_temp_new(TCG_TYPE_TL);
2766 tcg_gen_movi_tl(r_zero, 0);
2767 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[2], r_zero, l1);
2768 if (IS_IMM) { /* immediate */
2769 rs2 = GET_FIELD_SPs(insn, 0, 10);
2770 gen_movl_simm_T1(rs2);
2771 } else {
2772 rs2 = GET_FIELD_SP(insn, 0, 4);
2773 gen_movl_reg_T1(rs2);
2774 }
2775 gen_movl_T1_reg(rd);
2776 gen_set_label(l1);
0f8a249a
BS		 2777 break;
2778 }
2779 case 0x2d: /* V9 sdivx */
3475187d 2780 gen_op_sdivx_T1_T0();
0f8a249a
BS		 2781 gen_movl_T0_reg(rd);
2782 break;
2783 case 0x2e: /* V9 popc */
2784 {
2785 if (IS_IMM) { /* immediate */
2786 rs2 = GET_FIELD_SPs(insn, 0, 12);
2787 gen_movl_simm_T1(rs2);
2788 // XXX optimize: popc(constant)
2789 }
2790 else {
2791 rs2 = GET_FIELD_SP(insn, 0, 4);
2792 gen_movl_reg_T1(rs2);
2793 }
1a2fb1c0
BS		 2794 tcg_gen_helper_1_1(helper_popc, cpu_T[0],
2795 cpu_T[1]);
0f8a249a
BS		 2796 gen_movl_T0_reg(rd);
2797 }
2798 case 0x2f: /* V9 movr */
2799 {
2800 int cond = GET_FIELD_SP(insn, 10, 12);
00f219bf
BS		 2801 TCGv r_zero;
2802 int l1;
2803
0f8a249a 2804 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 2805 gen_movl_reg_T0(rs1);
00f219bf
BS		 2806
2807 l1 = gen_new_label();
2808
2809 r_zero = tcg_temp_new(TCG_TYPE_TL);
2810 tcg_gen_movi_tl(r_zero, 0);
2811 tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], r_zero, l1);
0f8a249a
BS		 2812 if (IS_IMM) { /* immediate */
2813 rs2 = GET_FIELD_SPs(insn, 0, 9);
2814 gen_movl_simm_T1(rs2);
00f219bf 2815 } else {
0f8a249a
BS		 2816 rs2 = GET_FIELD_SP(insn, 0, 4);
2817 gen_movl_reg_T1(rs2);
2818 }
00f219bf
BS		 2819 gen_movl_T1_reg(rd);
2820 gen_set_label(l1);
0f8a249a
BS		 2821 break;
2822 }
2823#endif
2824 default:
2825 goto illegal_insn;
2826 }
2827 }
3299908c
BS		 2828 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2829#ifdef TARGET_SPARC64
2830 int opf = GET_FIELD_SP(insn, 5, 13);
2831 rs1 = GET_FIELD(insn, 13, 17);
2832 rs2 = GET_FIELD(insn, 27, 31);
e9ebed4d
BS		 2833 if (gen_trap_ifnofpu(dc))
2834 goto jmp_insn;
3299908c
BS		 2835
2836 switch (opf) {
e9ebed4d
BS		 2837 case 0x000: /* VIS I edge8cc */
2838 case 0x001: /* VIS II edge8n */
2839 case 0x002: /* VIS I edge8lcc */
2840 case 0x003: /* VIS II edge8ln */
2841 case 0x004: /* VIS I edge16cc */
2842 case 0x005: /* VIS II edge16n */
2843 case 0x006: /* VIS I edge16lcc */
2844 case 0x007: /* VIS II edge16ln */
2845 case 0x008: /* VIS I edge32cc */
2846 case 0x009: /* VIS II edge32n */
2847 case 0x00a: /* VIS I edge32lcc */
2848 case 0x00b: /* VIS II edge32ln */
2849 // XXX
2850 goto illegal_insn;
2851 case 0x010: /* VIS I array8 */
2852 gen_movl_reg_T0(rs1);
2853 gen_movl_reg_T1(rs2);
2854 gen_op_array8();
2855 gen_movl_T0_reg(rd);
2856 break;
2857 case 0x012: /* VIS I array16 */
2858 gen_movl_reg_T0(rs1);
2859 gen_movl_reg_T1(rs2);
2860 gen_op_array16();
2861 gen_movl_T0_reg(rd);
2862 break;
2863 case 0x014: /* VIS I array32 */
2864 gen_movl_reg_T0(rs1);
2865 gen_movl_reg_T1(rs2);
2866 gen_op_array32();
2867 gen_movl_T0_reg(rd);
2868 break;
3299908c 2869 case 0x018: /* VIS I alignaddr */
3299908c
BS		 2870 gen_movl_reg_T0(rs1);
2871 gen_movl_reg_T1(rs2);
2872 gen_op_alignaddr();
2873 gen_movl_T0_reg(rd);
2874 break;
e9ebed4d 2875 case 0x019: /* VIS II bmask */
3299908c 2876 case 0x01a: /* VIS I alignaddrl */
3299908c 2877 // XXX
e9ebed4d
BS		 2878 goto illegal_insn;
2879 case 0x020: /* VIS I fcmple16 */
2382dc6b
BS		 2880 gen_op_load_fpr_DT0(DFPREG(rs1));
2881 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2882 gen_op_fcmple16();
2382dc6b 2883 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2884 break;
2885 case 0x022: /* VIS I fcmpne16 */
2382dc6b
BS		 2886 gen_op_load_fpr_DT0(DFPREG(rs1));
2887 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2888 gen_op_fcmpne16();
2382dc6b 2889 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 2890 break;
e9ebed4d 2891 case 0x024: /* VIS I fcmple32 */
2382dc6b
BS		 2892 gen_op_load_fpr_DT0(DFPREG(rs1));
2893 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2894 gen_op_fcmple32();
2382dc6b 2895 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2896 break;
2897 case 0x026: /* VIS I fcmpne32 */
2382dc6b
BS		 2898 gen_op_load_fpr_DT0(DFPREG(rs1));
2899 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2900 gen_op_fcmpne32();
2382dc6b 2901 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2902 break;
2903 case 0x028: /* VIS I fcmpgt16 */
2382dc6b
BS		 2904 gen_op_load_fpr_DT0(DFPREG(rs1));
2905 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2906 gen_op_fcmpgt16();
2382dc6b 2907 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2908 break;
2909 case 0x02a: /* VIS I fcmpeq16 */
2382dc6b
BS		 2910 gen_op_load_fpr_DT0(DFPREG(rs1));
2911 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2912 gen_op_fcmpeq16();
2382dc6b 2913 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2914 break;
2915 case 0x02c: /* VIS I fcmpgt32 */
2382dc6b
BS		 2916 gen_op_load_fpr_DT0(DFPREG(rs1));
2917 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2918 gen_op_fcmpgt32();
2382dc6b 2919 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2920 break;
2921 case 0x02e: /* VIS I fcmpeq32 */
2382dc6b
BS		 2922 gen_op_load_fpr_DT0(DFPREG(rs1));
2923 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2924 gen_op_fcmpeq32();
2382dc6b 2925 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2926 break;
2927 case 0x031: /* VIS I fmul8x16 */
2382dc6b
BS		 2928 gen_op_load_fpr_DT0(DFPREG(rs1));
2929 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2930 gen_op_fmul8x16();
2382dc6b 2931 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2932 break;
2933 case 0x033: /* VIS I fmul8x16au */
2382dc6b
BS		 2934 gen_op_load_fpr_DT0(DFPREG(rs1));
2935 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2936 gen_op_fmul8x16au();
2382dc6b 2937 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2938 break;
2939 case 0x035: /* VIS I fmul8x16al */
2382dc6b
BS		 2940 gen_op_load_fpr_DT0(DFPREG(rs1));
2941 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2942 gen_op_fmul8x16al();
2382dc6b 2943 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2944 break;
2945 case 0x036: /* VIS I fmul8sux16 */
2382dc6b
BS		 2946 gen_op_load_fpr_DT0(DFPREG(rs1));
2947 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2948 gen_op_fmul8sux16();
2382dc6b 2949 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2950 break;
2951 case 0x037: /* VIS I fmul8ulx16 */
2382dc6b
BS		 2952 gen_op_load_fpr_DT0(DFPREG(rs1));
2953 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2954 gen_op_fmul8ulx16();
2382dc6b 2955 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2956 break;
2957 case 0x038: /* VIS I fmuld8sux16 */
2382dc6b
BS		 2958 gen_op_load_fpr_DT0(DFPREG(rs1));
2959 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2960 gen_op_fmuld8sux16();
2382dc6b 2961 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2962 break;
2963 case 0x039: /* VIS I fmuld8ulx16 */
2382dc6b
BS		 2964 gen_op_load_fpr_DT0(DFPREG(rs1));
2965 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2966 gen_op_fmuld8ulx16();
2382dc6b 2967 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2968 break;
2969 case 0x03a: /* VIS I fpack32 */
2970 case 0x03b: /* VIS I fpack16 */
2971 case 0x03d: /* VIS I fpackfix */
2972 case 0x03e: /* VIS I pdist */
2973 // XXX
2974 goto illegal_insn;
3299908c 2975 case 0x048: /* VIS I faligndata */
2382dc6b
BS		 2976 gen_op_load_fpr_DT0(DFPREG(rs1));
2977 gen_op_load_fpr_DT1(DFPREG(rs2));
3299908c 2978 gen_op_faligndata();
2382dc6b 2979 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c 2980 break;
e9ebed4d 2981 case 0x04b: /* VIS I fpmerge */
2382dc6b
BS		 2982 gen_op_load_fpr_DT0(DFPREG(rs1));
2983 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2984 gen_op_fpmerge();
2382dc6b 2985 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2986 break;
2987 case 0x04c: /* VIS II bshuffle */
2988 // XXX
2989 goto illegal_insn;
2990 case 0x04d: /* VIS I fexpand */
2382dc6b
BS		 2991 gen_op_load_fpr_DT0(DFPREG(rs1));
2992 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2993 gen_op_fexpand();
2382dc6b 2994 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 2995 break;
2996 case 0x050: /* VIS I fpadd16 */
2382dc6b
BS		 2997 gen_op_load_fpr_DT0(DFPREG(rs1));
2998 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 2999 gen_op_fpadd16();
2382dc6b 3000 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3001 break;
3002 case 0x051: /* VIS I fpadd16s */
3003 gen_op_load_fpr_FT0(rs1);
3004 gen_op_load_fpr_FT1(rs2);
3005 gen_op_fpadd16s();
3006 gen_op_store_FT0_fpr(rd);
3007 break;
3008 case 0x052: /* VIS I fpadd32 */
2382dc6b
BS		 3009 gen_op_load_fpr_DT0(DFPREG(rs1));
3010 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3011 gen_op_fpadd32();
2382dc6b 3012 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3013 break;
3014 case 0x053: /* VIS I fpadd32s */
3015 gen_op_load_fpr_FT0(rs1);
3016 gen_op_load_fpr_FT1(rs2);
3017 gen_op_fpadd32s();
3018 gen_op_store_FT0_fpr(rd);
3019 break;
3020 case 0x054: /* VIS I fpsub16 */
2382dc6b
BS		 3021 gen_op_load_fpr_DT0(DFPREG(rs1));
3022 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3023 gen_op_fpsub16();
2382dc6b 3024 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3025 break;
3026 case 0x055: /* VIS I fpsub16s */
3027 gen_op_load_fpr_FT0(rs1);
3028 gen_op_load_fpr_FT1(rs2);
3029 gen_op_fpsub16s();
3030 gen_op_store_FT0_fpr(rd);
3031 break;
3032 case 0x056: /* VIS I fpsub32 */
2382dc6b
BS		 3033 gen_op_load_fpr_DT0(DFPREG(rs1));
3034 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3035 gen_op_fpadd32();
2382dc6b 3036 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3037 break;
3038 case 0x057: /* VIS I fpsub32s */
3039 gen_op_load_fpr_FT0(rs1);
3040 gen_op_load_fpr_FT1(rs2);
3041 gen_op_fpsub32s();
3042 gen_op_store_FT0_fpr(rd);
3043 break;
3299908c 3044 case 0x060: /* VIS I fzero */
3299908c 3045 gen_op_movl_DT0_0();
2382dc6b 3046 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3047 break;
3048 case 0x061: /* VIS I fzeros */
3299908c
BS		 3049 gen_op_movl_FT0_0();
3050 gen_op_store_FT0_fpr(rd);
3051 break;
e9ebed4d 3052 case 0x062: /* VIS I fnor */
2382dc6b
BS		 3053 gen_op_load_fpr_DT0(DFPREG(rs1));
3054 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3055 gen_op_fnor();
2382dc6b 3056 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3057 break;
3058 case 0x063: /* VIS I fnors */
3059 gen_op_load_fpr_FT0(rs1);
3060 gen_op_load_fpr_FT1(rs2);
3061 gen_op_fnors();
3062 gen_op_store_FT0_fpr(rd);
3063 break;
3064 case 0x064: /* VIS I fandnot2 */
2382dc6b
BS		 3065 gen_op_load_fpr_DT1(DFPREG(rs1));
3066 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 3067 gen_op_fandnot();
2382dc6b 3068 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3069 break;
3070 case 0x065: /* VIS I fandnot2s */
3071 gen_op_load_fpr_FT1(rs1);
3072 gen_op_load_fpr_FT0(rs2);
3073 gen_op_fandnots();
3074 gen_op_store_FT0_fpr(rd);
3075 break;
3076 case 0x066: /* VIS I fnot2 */
2382dc6b 3077 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3078 gen_op_fnot();
2382dc6b 3079 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3080 break;
3081 case 0x067: /* VIS I fnot2s */
3082 gen_op_load_fpr_FT1(rs2);
3083 gen_op_fnot();
3084 gen_op_store_FT0_fpr(rd);
3085 break;
3086 case 0x068: /* VIS I fandnot1 */
2382dc6b
BS		 3087 gen_op_load_fpr_DT0(DFPREG(rs1));
3088 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3089 gen_op_fandnot();
2382dc6b 3090 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3091 break;
3092 case 0x069: /* VIS I fandnot1s */
3093 gen_op_load_fpr_FT0(rs1);
3094 gen_op_load_fpr_FT1(rs2);
3095 gen_op_fandnots();
3096 gen_op_store_FT0_fpr(rd);
3097 break;
3098 case 0x06a: /* VIS I fnot1 */
2382dc6b 3099 gen_op_load_fpr_DT1(DFPREG(rs1));
e9ebed4d 3100 gen_op_fnot();
2382dc6b 3101 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3102 break;
3103 case 0x06b: /* VIS I fnot1s */
3104 gen_op_load_fpr_FT1(rs1);
3105 gen_op_fnot();
3106 gen_op_store_FT0_fpr(rd);
3107 break;
3108 case 0x06c: /* VIS I fxor */
2382dc6b
BS		 3109 gen_op_load_fpr_DT0(DFPREG(rs1));
3110 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3111 gen_op_fxor();
2382dc6b 3112 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3113 break;
3114 case 0x06d: /* VIS I fxors */
3115 gen_op_load_fpr_FT0(rs1);
3116 gen_op_load_fpr_FT1(rs2);
3117 gen_op_fxors();
3118 gen_op_store_FT0_fpr(rd);
3119 break;
3120 case 0x06e: /* VIS I fnand */
2382dc6b
BS		 3121 gen_op_load_fpr_DT0(DFPREG(rs1));
3122 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3123 gen_op_fnand();
2382dc6b 3124 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3125 break;
3126 case 0x06f: /* VIS I fnands */
3127 gen_op_load_fpr_FT0(rs1);
3128 gen_op_load_fpr_FT1(rs2);
3129 gen_op_fnands();
3130 gen_op_store_FT0_fpr(rd);
3131 break;
3132 case 0x070: /* VIS I fand */
2382dc6b
BS		 3133 gen_op_load_fpr_DT0(DFPREG(rs1));
3134 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3135 gen_op_fand();
2382dc6b 3136 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3137 break;
3138 case 0x071: /* VIS I fands */
3139 gen_op_load_fpr_FT0(rs1);
3140 gen_op_load_fpr_FT1(rs2);
3141 gen_op_fands();
3142 gen_op_store_FT0_fpr(rd);
3143 break;
3144 case 0x072: /* VIS I fxnor */
2382dc6b
BS		 3145 gen_op_load_fpr_DT0(DFPREG(rs1));
3146 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3147 gen_op_fxnor();
2382dc6b 3148 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3149 break;
3150 case 0x073: /* VIS I fxnors */
3151 gen_op_load_fpr_FT0(rs1);
3152 gen_op_load_fpr_FT1(rs2);
3153 gen_op_fxnors();
3154 gen_op_store_FT0_fpr(rd);
3155 break;
3299908c 3156 case 0x074: /* VIS I fsrc1 */
2382dc6b
BS		 3157 gen_op_load_fpr_DT0(DFPREG(rs1));
3158 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3159 break;
3160 case 0x075: /* VIS I fsrc1s */
3299908c
BS		 3161 gen_op_load_fpr_FT0(rs1);
3162 gen_op_store_FT0_fpr(rd);
3163 break;
e9ebed4d 3164 case 0x076: /* VIS I fornot2 */
2382dc6b
BS		 3165 gen_op_load_fpr_DT1(DFPREG(rs1));
3166 gen_op_load_fpr_DT0(DFPREG(rs2));
e9ebed4d 3167 gen_op_fornot();
2382dc6b 3168 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3169 break;
3170 case 0x077: /* VIS I fornot2s */
3171 gen_op_load_fpr_FT1(rs1);
3172 gen_op_load_fpr_FT0(rs2);
3173 gen_op_fornots();
3174 gen_op_store_FT0_fpr(rd);
3175 break;
3299908c 3176 case 0x078: /* VIS I fsrc2 */
2382dc6b
BS		 3177 gen_op_load_fpr_DT0(DFPREG(rs2));
3178 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3179 break;
3180 case 0x079: /* VIS I fsrc2s */
3299908c
BS		 3181 gen_op_load_fpr_FT0(rs2);
3182 gen_op_store_FT0_fpr(rd);
3183 break;
e9ebed4d 3184 case 0x07a: /* VIS I fornot1 */
2382dc6b
BS		 3185 gen_op_load_fpr_DT0(DFPREG(rs1));
3186 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3187 gen_op_fornot();
2382dc6b 3188 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3189 break;
3190 case 0x07b: /* VIS I fornot1s */
3191 gen_op_load_fpr_FT0(rs1);
3192 gen_op_load_fpr_FT1(rs2);
3193 gen_op_fornots();
3194 gen_op_store_FT0_fpr(rd);
3195 break;
3196 case 0x07c: /* VIS I for */
2382dc6b
BS		 3197 gen_op_load_fpr_DT0(DFPREG(rs1));
3198 gen_op_load_fpr_DT1(DFPREG(rs2));
e9ebed4d 3199 gen_op_for();
2382dc6b 3200 gen_op_store_DT0_fpr(DFPREG(rd));
e9ebed4d
BS		 3201 break;
3202 case 0x07d: /* VIS I fors */
3203 gen_op_load_fpr_FT0(rs1);
3204 gen_op_load_fpr_FT1(rs2);
3205 gen_op_fors();
3206 gen_op_store_FT0_fpr(rd);
3207 break;
3299908c 3208 case 0x07e: /* VIS I fone */
3299908c 3209 gen_op_movl_DT0_1();
2382dc6b 3210 gen_op_store_DT0_fpr(DFPREG(rd));
3299908c
BS		 3211 break;
3212 case 0x07f: /* VIS I fones */
3299908c
BS		 3213 gen_op_movl_FT0_1();
3214 gen_op_store_FT0_fpr(rd);
3215 break;
e9ebed4d
BS		 3216 case 0x080: /* VIS I shutdown */
3217 case 0x081: /* VIS II siam */
3218 // XXX
3219 goto illegal_insn;
3299908c
BS		 3220 default:
3221 goto illegal_insn;
3222 }
3223#else
0f8a249a 3224 goto ncp_insn;
3299908c
BS		 3225#endif
3226 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 3227#ifdef TARGET_SPARC64
0f8a249a 3228 goto illegal_insn;
fcc72045 3229#else
0f8a249a 3230 goto ncp_insn;
fcc72045 3231#endif
3475187d 3232#ifdef TARGET_SPARC64
0f8a249a 3233 } else if (xop == 0x39) { /* V9 return */
3475187d 3234 rs1 = GET_FIELD(insn, 13, 17);
1ad21e69 3235 save_state(dc);
0f8a249a
BS		 3236 gen_movl_reg_T0(rs1);
3237 if (IS_IMM) { /* immediate */
3238 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3239 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 3240 } else { /* register */
3475187d
FB		 3241 rs2 = GET_FIELD(insn, 27, 31);
3242#if defined(OPTIM)
0f8a249a 3243 if (rs2) {
3475187d 3244#endif
0f8a249a
BS		 3245 gen_movl_reg_T1(rs2);
3246 gen_op_add_T1_T0();
3475187d 3247#if defined(OPTIM)
0f8a249a 3248 }
3475187d
FB		 3249#endif
3250 }
0f8a249a
BS		 3251 gen_op_restore();
3252 gen_mov_pc_npc(dc);
6ea4a6c8 3253 gen_op_check_align_T0_3();
1a2fb1c0 3254 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3255 dc->npc = DYNAMIC_PC;
3256 goto jmp_insn;
3475187d 3257#endif
0f8a249a 3258 } else {
e80cfcfc 3259 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3260 gen_movl_reg_T0(rs1);
3261 if (IS_IMM) { /* immediate */
3262 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3263 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a 3264 } else { /* register */
e80cfcfc
FB		 3265 rs2 = GET_FIELD(insn, 27, 31);
3266#if defined(OPTIM)
0f8a249a 3267 if (rs2) {
e80cfcfc 3268#endif
0f8a249a
BS		 3269 gen_movl_reg_T1(rs2);
3270 gen_op_add_T1_T0();
e80cfcfc 3271#if defined(OPTIM)
0f8a249a 3272 }
e8af50a3 3273#endif
cf495bcf 3274 }
0f8a249a
BS		 3275 switch (xop) {
3276 case 0x38: /* jmpl */
3277 {
3278 if (rd != 0) {
1a2fb1c0 3279 tcg_gen_movi_tl(cpu_T[1], dc->pc);
0f8a249a
BS		 3280 gen_movl_T1_reg(rd);
3281 }
0bee699e 3282 gen_mov_pc_npc(dc);
6ea4a6c8 3283 gen_op_check_align_T0_3();
1a2fb1c0 3284 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a
BS		 3285 dc->npc = DYNAMIC_PC;
3286 }
3287 goto jmp_insn;
3475187d 3288#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 3289 case 0x39: /* rett, V9 return */
3290 {
3291 if (!supervisor(dc))
3292 goto priv_insn;
0bee699e 3293 gen_mov_pc_npc(dc);
6ea4a6c8 3294 gen_op_check_align_T0_3();
1a2fb1c0 3295 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, npc));
0f8a249a 3296 dc->npc = DYNAMIC_PC;
1a2fb1c0 3297 tcg_gen_helper_0_0(helper_rett);
0f8a249a
BS		 3298 }
3299 goto jmp_insn;
3300#endif
3301 case 0x3b: /* flush */
1a2fb1c0 3302 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
0f8a249a
BS		 3303 break;
3304 case 0x3c: /* save */
3305 save_state(dc);
3306 gen_op_save();
3307 gen_movl_T0_reg(rd);
3308 break;
3309 case 0x3d: /* restore */
3310 save_state(dc);
3311 gen_op_restore();
3312 gen_movl_T0_reg(rd);
3313 break;
3475187d 3314#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 3315 case 0x3e: /* V9 done/retry */
3316 {
3317 switch (rd) {
3318 case 0:
3319 if (!supervisor(dc))
3320 goto priv_insn;
3321 dc->npc = DYNAMIC_PC;
3322 dc->pc = DYNAMIC_PC;
1a2fb1c0 3323 tcg_gen_helper_0_0(helper_done);
0f8a249a
BS		 3324 goto jmp_insn;
3325 case 1:
3326 if (!supervisor(dc))
3327 goto priv_insn;
3328 dc->npc = DYNAMIC_PC;
3329 dc->pc = DYNAMIC_PC;
1a2fb1c0 3330 tcg_gen_helper_0_0(helper_retry);
0f8a249a
BS		 3331 goto jmp_insn;
3332 default:
3333 goto illegal_insn;
3334 }
3335 }
3336 break;
3337#endif
3338 default:
3339 goto illegal_insn;
3340 }
cf495bcf 3341 }
0f8a249a
BS		 3342 break;
3343 }
3344 break;
3345 case 3: /* load/store instructions */
3346 {
3347 unsigned int xop = GET_FIELD(insn, 7, 12);
3348 rs1 = GET_FIELD(insn, 13, 17);
2371aaa2 3349 save_state(dc);
0f8a249a 3350 gen_movl_reg_T0(rs1);
81ad8ba2
BS		 3351 if (xop == 0x3c || xop == 0x3e)
3352 {
3353 rs2 = GET_FIELD(insn, 27, 31);
3354 gen_movl_reg_T1(rs2);
3355 }
3356 else if (IS_IMM) { /* immediate */
0f8a249a 3357 rs2 = GET_FIELDs(insn, 19, 31);
1a2fb1c0 3358 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], (int)rs2);
0f8a249a
BS		 3359 } else { /* register */
3360 rs2 = GET_FIELD(insn, 27, 31);
e80cfcfc 3361#if defined(OPTIM)
0f8a249a 3362 if (rs2 != 0) {
e80cfcfc 3363#endif
0f8a249a
BS		 3364 gen_movl_reg_T1(rs2);
3365 gen_op_add_T1_T0();
e80cfcfc 3366#if defined(OPTIM)
0f8a249a 3367 }
e80cfcfc 3368#endif
0f8a249a 3369 }
2f2ecb83
BS		 3370 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
3371 (xop > 0x17 && xop <= 0x1d ) ||
3372 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
0f8a249a 3373 switch (xop) {
1a2fb1c0 3374 case 0x0: /* load unsigned word */
6ea4a6c8 3375 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3376 ABI32_MASK(cpu_T[0]);
3377 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3378 break;
3379 case 0x1: /* load unsigned byte */
1a2fb1c0
BS		 3380 ABI32_MASK(cpu_T[0]);
3381 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3382 break;
3383 case 0x2: /* load unsigned halfword */
6ea4a6c8 3384 gen_op_check_align_T0_1();
1a2fb1c0
BS		 3385 ABI32_MASK(cpu_T[0]);
3386 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3387 break;
3388 case 0x3: /* load double word */
0f8a249a 3389 if (rd & 1)
d4218d99 3390 goto illegal_insn;
1a2fb1c0
BS		 3391 else {
3392 TCGv r_dword;
3393
3394 r_dword = tcg_temp_new(TCG_TYPE_I64);
3395 gen_op_check_align_T0_7();
3396 ABI32_MASK(cpu_T[0]);
3397 tcg_gen_qemu_ld64(r_dword, cpu_T[0], dc->mem_idx);
3398 tcg_gen_trunc_i64_i32(cpu_T[0], r_dword);
3399 gen_movl_T0_reg(rd + 1);
3400 tcg_gen_shri_i64(r_dword, r_dword, 32);
3401 tcg_gen_trunc_i64_i32(cpu_T[1], r_dword);
3402 }
0f8a249a
BS		 3403 break;
3404 case 0x9: /* load signed byte */
1a2fb1c0
BS		 3405 ABI32_MASK(cpu_T[0]);
3406 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3407 break;
3408 case 0xa: /* load signed halfword */
6ea4a6c8 3409 gen_op_check_align_T0_1();
1a2fb1c0
BS		 3410 ABI32_MASK(cpu_T[0]);
3411 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3412 break;
3413 case 0xd: /* ldstub -- XXX: should be atomically */
1a2fb1c0
BS		 3414 tcg_gen_movi_i32(cpu_tmp0, 0xff);
3415 ABI32_MASK(cpu_T[0]);
3416 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
3417 tcg_gen_qemu_st8(cpu_tmp0, cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3418 break;
3419 case 0x0f: /* swap register with memory. Also atomically */
6ea4a6c8 3420 gen_op_check_align_T0_3();
0f8a249a 3421 gen_movl_reg_T1(rd);
1a2fb1c0
BS		 3422 ABI32_MASK(cpu_T[0]);
3423 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_T[0], dc->mem_idx);
3424 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
3425 tcg_gen_mov_i32(cpu_T[1], cpu_tmp0);
0f8a249a 3426 break;
3475187d 3427#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 3428 case 0x10: /* load word alternate */
3475187d 3429#ifndef TARGET_SPARC64
0f8a249a
BS		 3430 if (IS_IMM)
3431 goto illegal_insn;
3432 if (!supervisor(dc))
3433 goto priv_insn;
6ea4a6c8 3434#endif
8f577d3d 3435 gen_op_check_align_T0_3();
81ad8ba2 3436 gen_ld_asi(insn, 4, 0);
0f8a249a
BS		 3437 break;
3438 case 0x11: /* load unsigned byte alternate */
3475187d 3439#ifndef TARGET_SPARC64
0f8a249a
BS		 3440 if (IS_IMM)
3441 goto illegal_insn;
3442 if (!supervisor(dc))
3443 goto priv_insn;
3444#endif
81ad8ba2 3445 gen_ld_asi(insn, 1, 0);
0f8a249a
BS		 3446 break;
3447 case 0x12: /* load unsigned halfword alternate */
3475187d 3448#ifndef TARGET_SPARC64
0f8a249a
BS		 3449 if (IS_IMM)
3450 goto illegal_insn;
3451 if (!supervisor(dc))
3452 goto priv_insn;
3475187d 3453#endif
8f577d3d 3454 gen_op_check_align_T0_1();
81ad8ba2 3455 gen_ld_asi(insn, 2, 0);
0f8a249a
BS		 3456 break;
3457 case 0x13: /* load double word alternate */
3475187d 3458#ifndef TARGET_SPARC64
0f8a249a
BS		 3459 if (IS_IMM)
3460 goto illegal_insn;
3461 if (!supervisor(dc))
3462 goto priv_insn;
3475187d 3463#endif
0f8a249a 3464 if (rd & 1)
d4218d99 3465 goto illegal_insn;
6ea4a6c8 3466 gen_op_check_align_T0_7();
81ad8ba2 3467 gen_ldda_asi(insn);
0f8a249a
BS		 3468 gen_movl_T0_reg(rd + 1);
3469 break;
3470 case 0x19: /* load signed byte alternate */
3475187d 3471#ifndef TARGET_SPARC64
0f8a249a
BS		 3472 if (IS_IMM)
3473 goto illegal_insn;
3474 if (!supervisor(dc))
3475 goto priv_insn;
3476#endif
81ad8ba2 3477 gen_ld_asi(insn, 1, 1);
0f8a249a
BS		 3478 break;
3479 case 0x1a: /* load signed halfword alternate */
3475187d 3480#ifndef TARGET_SPARC64
0f8a249a
BS		 3481 if (IS_IMM)
3482 goto illegal_insn;
3483 if (!supervisor(dc))
3484 goto priv_insn;
3475187d 3485#endif
8f577d3d 3486 gen_op_check_align_T0_1();
81ad8ba2 3487 gen_ld_asi(insn, 2, 1);
0f8a249a
BS		 3488 break;
3489 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 3490#ifndef TARGET_SPARC64
0f8a249a
BS		 3491 if (IS_IMM)
3492 goto illegal_insn;
3493 if (!supervisor(dc))
3494 goto priv_insn;
3495#endif
81ad8ba2 3496 gen_ldstub_asi(insn);
0f8a249a
BS		 3497 break;
3498 case 0x1f: /* swap reg with alt. memory. Also atomically */
3475187d 3499#ifndef TARGET_SPARC64
0f8a249a
BS		 3500 if (IS_IMM)
3501 goto illegal_insn;
3502 if (!supervisor(dc))
3503 goto priv_insn;
6ea4a6c8 3504#endif
8f577d3d 3505 gen_op_check_align_T0_3();
81ad8ba2
BS		 3506 gen_movl_reg_T1(rd);
3507 gen_swap_asi(insn);
0f8a249a 3508 break;
3475187d
FB		 3509
3510#ifndef TARGET_SPARC64
0f8a249a
BS		 3511 case 0x30: /* ldc */
3512 case 0x31: /* ldcsr */
3513 case 0x33: /* lddc */
3514 goto ncp_insn;
3475187d
FB		 3515#endif
3516#endif
3517#ifdef TARGET_SPARC64
0f8a249a 3518 case 0x08: /* V9 ldsw */
6ea4a6c8 3519 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3520 ABI32_MASK(cpu_T[0]);
3521 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3522 break;
3523 case 0x0b: /* V9 ldx */
6ea4a6c8 3524 gen_op_check_align_T0_7();
1a2fb1c0
BS		 3525 ABI32_MASK(cpu_T[0]);
3526 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3527 break;
3528 case 0x18: /* V9 ldswa */
6ea4a6c8 3529 gen_op_check_align_T0_3();
81ad8ba2 3530 gen_ld_asi(insn, 4, 1);
0f8a249a
BS		 3531 break;
3532 case 0x1b: /* V9 ldxa */
6ea4a6c8 3533 gen_op_check_align_T0_7();
81ad8ba2 3534 gen_ld_asi(insn, 8, 0);
0f8a249a
BS		 3535 break;
3536 case 0x2d: /* V9 prefetch, no effect */
3537 goto skip_move;
3538 case 0x30: /* V9 ldfa */
6ea4a6c8 3539 gen_op_check_align_T0_3();
2382dc6b 3540 gen_ldf_asi(insn, 4, rd);
81ad8ba2 3541 goto skip_move;
0f8a249a 3542 case 0x33: /* V9 lddfa */
3391c818 3543 gen_op_check_align_T0_3();
2382dc6b 3544 gen_ldf_asi(insn, 8, DFPREG(rd));
81ad8ba2 3545 goto skip_move;
0f8a249a
BS		 3546 case 0x3d: /* V9 prefetcha, no effect */
3547 goto skip_move;
3548 case 0x32: /* V9 ldqfa */
1f587329
BS		 3549#if defined(CONFIG_USER_ONLY)
3550 gen_op_check_align_T0_3();
2382dc6b 3551 gen_ldf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 3552 goto skip_move;
3553#else
0f8a249a 3554 goto nfpu_insn;
1f587329 3555#endif
0f8a249a
BS		 3556#endif
3557 default:
3558 goto illegal_insn;
3559 }
3560 gen_movl_T1_reg(rd);
3475187d 3561#ifdef TARGET_SPARC64
0f8a249a 3562 skip_move: ;
3475187d 3563#endif
0f8a249a 3564 } else if (xop >= 0x20 && xop < 0x24) {
a80dde08
FB		 3565 if (gen_trap_ifnofpu(dc))
3566 goto jmp_insn;
0f8a249a
BS		 3567 switch (xop) {
3568 case 0x20: /* load fpreg */
6ea4a6c8 3569 gen_op_check_align_T0_3();
0f8a249a
BS		 3570 gen_op_ldst(ldf);
3571 gen_op_store_FT0_fpr(rd);
3572 break;
3573 case 0x21: /* load fsr */
6ea4a6c8 3574 gen_op_check_align_T0_3();
0f8a249a
BS		 3575 gen_op_ldst(ldf);
3576 gen_op_ldfsr();
7e8c2b6c 3577 tcg_gen_helper_0_0(helper_ldfsr);
0f8a249a
BS		 3578 break;
3579 case 0x22: /* load quad fpreg */
1f587329
BS		 3580#if defined(CONFIG_USER_ONLY)
3581 gen_op_check_align_T0_7();
3582 gen_op_ldst(ldqf);
3583 gen_op_store_QT0_fpr(QFPREG(rd));
3584 break;
3585#else
0f8a249a 3586 goto nfpu_insn;
1f587329 3587#endif
0f8a249a 3588 case 0x23: /* load double fpreg */
6ea4a6c8 3589 gen_op_check_align_T0_7();
0f8a249a
BS		 3590 gen_op_ldst(lddf);
3591 gen_op_store_DT0_fpr(DFPREG(rd));
3592 break;
3593 default:
3594 goto illegal_insn;
3595 }
3596 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3597 xop == 0xe || xop == 0x1e) {
3598 gen_movl_reg_T1(rd);
3599 switch (xop) {
1a2fb1c0 3600 case 0x4: /* store word */
6ea4a6c8 3601 gen_op_check_align_T0_3();
1a2fb1c0
BS		 3602 ABI32_MASK(cpu_T[0]);
3603 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 3604 break;
1a2fb1c0
BS		 3605 case 0x5: /* store byte */
3606 ABI32_MASK(cpu_T[0]);
3607 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 3608 break;
1a2fb1c0 3609 case 0x6: /* store halfword */
6ea4a6c8 3610 gen_op_check_align_T0_1();
1a2fb1c0
BS		 3611 ABI32_MASK(cpu_T[0]);
3612 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a 3613 break;
1a2fb1c0 3614 case 0x7: /* store double word */
0f8a249a 3615 if (rd & 1)
d4218d99 3616 goto illegal_insn;
b25deda7 3617#ifndef __i386__
1a2fb1c0
BS		 3618 else {
3619 TCGv r_dword, r_low;
3620
3621 gen_op_check_align_T0_7();
3622 r_dword = tcg_temp_new(TCG_TYPE_I64);
3623 r_low = tcg_temp_new(TCG_TYPE_I32);
3624 gen_movl_reg_TN(rd + 1, r_low);
3625 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
3626 r_low);
3627 tcg_gen_qemu_st64(r_dword, cpu_T[0], dc->mem_idx);
3628 }
b25deda7
BS		 3629#else /* __i386__ */
3630 gen_op_check_align_T0_7();
3631 flush_T2(dc);
3632 gen_movl_reg_T2(rd + 1);
3633 gen_op_ldst(std);
3634#endif /* __i386__ */
0f8a249a 3635 break;
3475187d 3636#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1a2fb1c0 3637 case 0x14: /* store word alternate */
3475187d 3638#ifndef TARGET_SPARC64
0f8a249a
BS		 3639 if (IS_IMM)
3640 goto illegal_insn;
3641 if (!supervisor(dc))
3642 goto priv_insn;
6ea4a6c8 3643#endif
6ea4a6c8 3644 gen_op_check_align_T0_3();
81ad8ba2 3645 gen_st_asi(insn, 4);
d39c0b99 3646 break;
1a2fb1c0 3647 case 0x15: /* store byte alternate */
3475187d 3648#ifndef TARGET_SPARC64
0f8a249a
BS		 3649 if (IS_IMM)
3650 goto illegal_insn;
3651 if (!supervisor(dc))
3652 goto priv_insn;
3475187d 3653#endif
81ad8ba2 3654 gen_st_asi(insn, 1);
d39c0b99 3655 break;
1a2fb1c0 3656 case 0x16: /* store halfword alternate */
3475187d 3657#ifndef TARGET_SPARC64
0f8a249a
BS		 3658 if (IS_IMM)
3659 goto illegal_insn;
3660 if (!supervisor(dc))
3661 goto priv_insn;
6ea4a6c8 3662#endif
6ea4a6c8 3663 gen_op_check_align_T0_1();
81ad8ba2 3664 gen_st_asi(insn, 2);
d39c0b99 3665 break;
1a2fb1c0 3666 case 0x17: /* store double word alternate */
3475187d 3667#ifndef TARGET_SPARC64
0f8a249a
BS		 3668 if (IS_IMM)
3669 goto illegal_insn;
3670 if (!supervisor(dc))
3671 goto priv_insn;
3475187d 3672#endif
0f8a249a 3673 if (rd & 1)
d4218d99 3674 goto illegal_insn;
1a2fb1c0
BS		 3675 else {
3676 int asi;
3677 TCGv r_dword, r_temp, r_size;
3678
3679 gen_op_check_align_T0_7();
3680 r_dword = tcg_temp_new(TCG_TYPE_I64);
3681 r_temp = tcg_temp_new(TCG_TYPE_I32);
3682 r_size = tcg_temp_new(TCG_TYPE_I32);
3683 gen_movl_reg_TN(rd + 1, r_temp);
3684 tcg_gen_helper_1_2(helper_pack64, r_dword, cpu_T[1],
3685 r_temp);
3686#ifdef TARGET_SPARC64
3687 if (IS_IMM) {
3688 int offset;
3689
3690 offset = GET_FIELD(insn, 25, 31);
3691 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], offset);
3692 tcg_gen_ld_i32(r_dword, cpu_env, offsetof(CPUSPARCState, asi));
3693 } else {
3694#endif
3695 asi = GET_FIELD(insn, 19, 26);
3696 tcg_gen_movi_i32(r_temp, asi);
3697#ifdef TARGET_SPARC64
3698 }
3699#endif
3700 tcg_gen_movi_i32(r_size, 8);
3701 tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_dword, r_temp, r_size);
3702 }
d39c0b99 3703 break;
e80cfcfc 3704#endif
3475187d 3705#ifdef TARGET_SPARC64
0f8a249a 3706 case 0x0e: /* V9 stx */
6ea4a6c8 3707 gen_op_check_align_T0_7();
1a2fb1c0
BS		 3708 ABI32_MASK(cpu_T[0]);
3709 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
0f8a249a
BS		 3710 break;
3711 case 0x1e: /* V9 stxa */
6ea4a6c8 3712 gen_op_check_align_T0_7();
81ad8ba2 3713 gen_st_asi(insn, 8);
0f8a249a 3714 break;
3475187d 3715#endif
0f8a249a
BS		 3716 default:
3717 goto illegal_insn;
3718 }
3719 } else if (xop > 0x23 && xop < 0x28) {
a80dde08
FB		 3720 if (gen_trap_ifnofpu(dc))
3721 goto jmp_insn;
0f8a249a
BS		 3722 switch (xop) {
3723 case 0x24:
6ea4a6c8 3724 gen_op_check_align_T0_3();
e8af50a3 3725 gen_op_load_fpr_FT0(rd);
0f8a249a
BS		 3726 gen_op_ldst(stf);
3727 break;
3728 case 0x25: /* stfsr, V9 stxfsr */
6ea4a6c8
BS		 3729#ifdef CONFIG_USER_ONLY
3730 gen_op_check_align_T0_3();
3731#endif
0f8a249a
BS		 3732 gen_op_stfsr();
3733 gen_op_ldst(stf);
3734 break;
1f587329
BS		 3735 case 0x26:
3736#ifdef TARGET_SPARC64
3737#if defined(CONFIG_USER_ONLY)
3738 /* V9 stqf, store quad fpreg */
3739 gen_op_check_align_T0_7();
3740 gen_op_load_fpr_QT0(QFPREG(rd));
3741 gen_op_ldst(stqf);
3742 break;
3743#else
3744 goto nfpu_insn;
3745#endif
3746#else /* !TARGET_SPARC64 */
3747 /* stdfq, store floating point queue */
3748#if defined(CONFIG_USER_ONLY)
3749 goto illegal_insn;
3750#else
0f8a249a
BS		 3751 if (!supervisor(dc))
3752 goto priv_insn;
3753 if (gen_trap_ifnofpu(dc))
3754 goto jmp_insn;
3755 goto nfq_insn;
1f587329 3756#endif
0f8a249a
BS		 3757#endif
3758 case 0x27:
6ea4a6c8 3759 gen_op_check_align_T0_7();
3475187d 3760 gen_op_load_fpr_DT0(DFPREG(rd));
0f8a249a
BS		 3761 gen_op_ldst(stdf);
3762 break;
3763 default:
3764 goto illegal_insn;
3765 }
3766 } else if (xop > 0x33 && xop < 0x3f) {
3767 switch (xop) {
a4d17f19 3768#ifdef TARGET_SPARC64
0f8a249a 3769 case 0x34: /* V9 stfa */
6ea4a6c8 3770 gen_op_check_align_T0_3();
3391c818 3771 gen_op_load_fpr_FT0(rd);
2382dc6b 3772 gen_stf_asi(insn, 4, rd);
0f8a249a 3773 break;
1f587329
BS		 3774 case 0x36: /* V9 stqfa */
3775#if defined(CONFIG_USER_ONLY)
3776 gen_op_check_align_T0_7();
3777 gen_op_load_fpr_QT0(QFPREG(rd));
2382dc6b 3778 gen_stf_asi(insn, 16, QFPREG(rd));
1f587329
BS		 3779 break;
3780#else
3781 goto nfpu_insn;
3782#endif
0f8a249a 3783 case 0x37: /* V9 stdfa */
3391c818
BS		 3784 gen_op_check_align_T0_3();
3785 gen_op_load_fpr_DT0(DFPREG(rd));
2382dc6b 3786 gen_stf_asi(insn, 8, DFPREG(rd));
0f8a249a
BS		 3787 break;
3788 case 0x3c: /* V9 casa */
6ea4a6c8 3789 gen_op_check_align_T0_3();
1a2fb1c0 3790 gen_cas_asi(insn, rd);
81ad8ba2 3791 gen_movl_T1_reg(rd);
0f8a249a
BS		 3792 break;
3793 case 0x3e: /* V9 casxa */
6ea4a6c8 3794 gen_op_check_align_T0_7();
1a2fb1c0 3795 gen_casx_asi(insn, rd);
81ad8ba2 3796 gen_movl_T1_reg(rd);
0f8a249a 3797 break;
a4d17f19 3798#else
0f8a249a
BS		 3799 case 0x34: /* stc */
3800 case 0x35: /* stcsr */
3801 case 0x36: /* stdcq */
3802 case 0x37: /* stdc */
3803 goto ncp_insn;
3804#endif
3805 default:
3806 goto illegal_insn;
3807 }
e8af50a3 3808 }
0f8a249a
BS		 3809 else
3810 goto illegal_insn;
3811 }
3812 break;
cf495bcf
FB		 3813 }
3814 /* default case for non jump instructions */
72cbca10 3815 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 3816 dc->pc = DYNAMIC_PC;
3817 gen_op_next_insn();
72cbca10
FB		 3818 } else if (dc->npc == JUMP_PC) {
3819 /* we can do a static jump */
46525e1f 3820 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
72cbca10
FB		 3821 dc->is_br = 1;
3822 } else {
0f8a249a
BS		 3823 dc->pc = dc->npc;
3824 dc->npc = dc->npc + 4;
cf495bcf 3825 }
e80cfcfc 3826 jmp_insn:
cf495bcf
FB		 3827 return;
3828 illegal_insn:
72cbca10 3829 save_state(dc);
cf495bcf
FB		 3830 gen_op_exception(TT_ILL_INSN);
3831 dc->is_br = 1;
e8af50a3 3832 return;
e80cfcfc 3833#if !defined(CONFIG_USER_ONLY)
e8af50a3
FB		 3834 priv_insn:
3835 save_state(dc);
3836 gen_op_exception(TT_PRIV_INSN);
3837 dc->is_br = 1;
e80cfcfc 3838 return;
e80cfcfc
FB		 3839 nfpu_insn:
3840 save_state(dc);
3841 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3842 dc->is_br = 1;
fcc72045 3843 return;
1f587329 3844#ifndef TARGET_SPARC64
9143e598
BS		 3845 nfq_insn:
3846 save_state(dc);
3847 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3848 dc->is_br = 1;
3849 return;
3850#endif
1f587329 3851#endif
fcc72045
BS		 3852#ifndef TARGET_SPARC64
3853 ncp_insn:
3854 save_state(dc);
3855 gen_op_exception(TT_NCP_INSN);
3856 dc->is_br = 1;
3857 return;
3858#endif
7a3f1944
FB		 3859}
3860
1a2fb1c0
BS		 3861static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
3862{
3863}
3864
cf495bcf 3865static inline int gen_intermediate_code_internal(TranslationBlock * tb,
0f8a249a 3866 int spc, CPUSPARCState *env)
7a3f1944 3867{
72cbca10 3868 target_ulong pc_start, last_pc;
cf495bcf
FB		 3869 uint16_t *gen_opc_end;
3870 DisasContext dc1, *dc = &dc1;
e8af50a3 3871 int j, lj = -1;
cf495bcf
FB		 3872
3873 memset(dc, 0, sizeof(DisasContext));
cf495bcf 3874 dc->tb = tb;
72cbca10 3875 pc_start = tb->pc;
cf495bcf 3876 dc->pc = pc_start;
e80cfcfc 3877 last_pc = dc->pc;
72cbca10 3878 dc->npc = (target_ulong) tb->cs_base;
6f27aba6
BS		 3879 dc->mem_idx = cpu_mmu_index(env);
3880 dc->fpu_enabled = cpu_fpu_enabled(env);
cf495bcf 3881 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
cf495bcf 3882
1a2fb1c0
BS		 3883 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
3884 cpu_regwptr = tcg_temp_new(TCG_TYPE_PTR); // XXX
3885
cf495bcf 3886 do {
e8af50a3
FB		 3887 if (env->nb_breakpoints > 0) {
3888 for(j = 0; j < env->nb_breakpoints; j++) {
3889 if (env->breakpoints[j] == dc->pc) {
0f8a249a
BS		 3890 if (dc->pc != pc_start)
3891 save_state(dc);
1a2fb1c0 3892 tcg_gen_helper_0_0(helper_debug);
57fec1fe 3893 tcg_gen_exit_tb(0);
0f8a249a 3894 dc->is_br = 1;
e80cfcfc 3895 goto exit_gen_loop;
e8af50a3
FB		 3896 }
3897 }
3898 }
3899 if (spc) {
3900 if (loglevel > 0)
3901 fprintf(logfile, "Search PC...\n");
3902 j = gen_opc_ptr - gen_opc_buf;
3903 if (lj < j) {
3904 lj++;
3905 while (lj < j)
3906 gen_opc_instr_start[lj++] = 0;
3907 gen_opc_pc[lj] = dc->pc;
3908 gen_opc_npc[lj] = dc->npc;
3909 gen_opc_instr_start[lj] = 1;
3910 }
3911 }
0f8a249a
BS		 3912 last_pc = dc->pc;
3913 disas_sparc_insn(dc);
3914
3915 if (dc->is_br)
3916 break;
3917 /* if the next PC is different, we abort now */
3918 if (dc->pc != (last_pc + 4))
3919 break;
d39c0b99
FB		 3920 /* if we reach a page boundary, we stop generation so that the
3921 PC of a TT_TFAULT exception is always in the right page */
3922 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3923 break;
e80cfcfc
FB		 3924 /* if single step mode, we generate only one instruction and
3925 generate an exception */
3926 if (env->singlestep_enabled) {
3475187d 3927 gen_jmp_im(dc->pc);
57fec1fe 3928 tcg_gen_exit_tb(0);
e80cfcfc
FB		 3929 break;
3930 }
cf495bcf 3931 } while ((gen_opc_ptr < gen_opc_end) &&
0f8a249a 3932 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
e80cfcfc
FB		 3933
3934 exit_gen_loop:
72cbca10 3935 if (!dc->is_br) {
5fafdf24 3936 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 3937 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3938 /* static PC and NPC: we can use direct chaining */
46525e1f 3939 gen_branch(dc, dc->pc, dc->npc);
72cbca10
FB		 3940 } else {
3941 if (dc->pc != DYNAMIC_PC)
3475187d 3942 gen_jmp_im(dc->pc);
72cbca10 3943 save_npc(dc);
57fec1fe 3944 tcg_gen_exit_tb(0);
72cbca10
FB		 3945 }
3946 }
cf495bcf 3947 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 3948 if (spc) {
3949 j = gen_opc_ptr - gen_opc_buf;
3950 lj++;
3951 while (lj <= j)
3952 gen_opc_instr_start[lj++] = 0;
e8af50a3
FB		 3953#if 0
3954 if (loglevel > 0) {
3955 page_dump(logfile);
3956 }
3957#endif
c3278b7b
FB		 3958 gen_opc_jump_pc[0] = dc->jump_pc[0];
3959 gen_opc_jump_pc[1] = dc->jump_pc[1];
e8af50a3 3960 } else {
e80cfcfc 3961 tb->size = last_pc + 4 - pc_start;
e8af50a3 3962 }
7a3f1944 3963#ifdef DEBUG_DISAS
e19e89a5 3964 if (loglevel & CPU_LOG_TB_IN_ASM) {
0f8a249a
BS		 3965 fprintf(logfile, "--------------\n");
3966 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3967 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3968 fprintf(logfile, "\n");
cf495bcf 3969 }
7a3f1944 3970#endif
cf495bcf 3971 return 0;
7a3f1944
FB		 3972}
3973
cf495bcf 3974int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3975{
e8af50a3 3976 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 3977}
3978
cf495bcf 3979int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 3980{
e8af50a3 3981 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 3982}
3983
e80cfcfc
FB		 3984void cpu_reset(CPUSPARCState *env)
3985{
bb05683b 3986 tlb_flush(env, 1);
cf495bcf
FB		 3987 env->cwp = 0;
3988 env->wim = 1;
3989 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 3990#if defined(CONFIG_USER_ONLY)
cf495bcf 3991 env->user_mode_only = 1;
5ef54116 3992#ifdef TARGET_SPARC64
6ef905f6
BS		 3993 env->cleanwin = NWINDOWS - 2;
3994 env->cansave = NWINDOWS - 2;
3995 env->pstate = PS_RMO | PS_PEF | PS_IE;
3996 env->asi = 0x82; // Primary no-fault
5ef54116 3997#endif
e8af50a3 3998#else
32af58f9 3999 env->psret = 0;
e8af50a3 4000 env->psrs = 1;
0bee699e 4001 env->psrps = 1;
3475187d 4002#ifdef TARGET_SPARC64
83469015 4003 env->pstate = PS_PRIV;
6f27aba6 4004 env->hpstate = HS_PRIV;
83469015 4005 env->pc = 0x1fff0000000ULL;
375ee38b 4006 env->tsptr = &env->ts[env->tl];
3475187d 4007#else
40ce0a9a 4008 env->pc = 0;
32af58f9 4009 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
6d5f237a 4010 env->mmuregs[0] |= env->mmu_bm;
3475187d 4011#endif
83469015 4012 env->npc = env->pc + 4;
e8af50a3 4013#endif
e80cfcfc
FB		 4014}
4015
aaed909a 4016CPUSPARCState *cpu_sparc_init(const char *cpu_model)
e80cfcfc
FB		 4017{
4018 CPUSPARCState *env;
aaed909a 4019 const sparc_def_t *def;
1a2fb1c0 4020 static int inited;
aaed909a
FB		 4021
4022 def = cpu_sparc_find_by_name(cpu_model);
4023 if (!def)
4024 return NULL;
e80cfcfc 4025
c68ea704
FB		 4026 env = qemu_mallocz(sizeof(CPUSPARCState));
4027 if (!env)
0f8a249a 4028 return NULL;
c68ea704 4029 cpu_exec_init(env);
01ba9816 4030 env->cpu_model_str = cpu_model;
aaed909a
FB		 4031 env->version = def->iu_version;
4032 env->fsr = def->fpu_version;
4033#if !defined(TARGET_SPARC64)
4034 env->mmu_bm = def->mmu_bm;
3deaeab7
BS		 4035 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
4036 env->mmu_cxr_mask = def->mmu_cxr_mask;
4037 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
4038 env->mmu_trcr_mask = def->mmu_trcr_mask;
aaed909a
FB		 4039 env->mmuregs[0] |= def->mmu_version;
4040 cpu_sparc_set_id(env, 0);
4041#endif
1a2fb1c0
BS		 4042
4043 /* init various static tables */
4044 if (!inited) {
4045 inited = 1;
4046
4047 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4048 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4049 //#if TARGET_LONG_BITS > HOST_LONG_BITS
4050#ifdef TARGET_SPARC64
4051 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4052 TCG_AREG0, offsetof(CPUState, t0), "T0");
4053 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4054 TCG_AREG0, offsetof(CPUState, t1), "T1");
4055 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4056 TCG_AREG0, offsetof(CPUState, t2), "T2");
4057#else
4058 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4059 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4060 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4061#endif
4062 }
4063
aaed909a
FB		 4064 cpu_reset(env);
4065
4066 return env;
4067}
4068
4069void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
4070{
4071#if !defined(TARGET_SPARC64)
4072 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
4073#endif
7a3f1944
FB		 4074}
4075
62724a37
BS		 4076static const sparc_def_t sparc_defs[] = {
4077#ifdef TARGET_SPARC64
7d77bf20
BS		 4078 {
4079 .name = "Fujitsu Sparc64",
4080 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
4081 | (MAXTL << 8) | (NWINDOWS - 1)),
4082 .fpu_version = 0x00000000,
4083 .mmu_version = 0,
4084 },
4085 {
4086 .name = "Fujitsu Sparc64 III",
4087 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
4088 | (MAXTL << 8) | (NWINDOWS - 1)),
4089 .fpu_version = 0x00000000,
4090 .mmu_version = 0,
4091 },
4092 {
4093 .name = "Fujitsu Sparc64 IV",
4094 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
4095 | (MAXTL << 8) | (NWINDOWS - 1)),
4096 .fpu_version = 0x00000000,
4097 .mmu_version = 0,
4098 },
4099 {
4100 .name = "Fujitsu Sparc64 V",
4101 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
4102 | (MAXTL << 8) | (NWINDOWS - 1)),
4103 .fpu_version = 0x00000000,
4104 .mmu_version = 0,
4105 },
4106 {
4107 .name = "TI UltraSparc I",
4108 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
4109 | (MAXTL << 8) | (NWINDOWS - 1)),
4110 .fpu_version = 0x00000000,
4111 .mmu_version = 0,
4112 },
62724a37
BS		 4113 {
4114 .name = "TI UltraSparc II",
7d77bf20
BS		 4115 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
4116 | (MAXTL << 8) | (NWINDOWS - 1)),
4117 .fpu_version = 0x00000000,
4118 .mmu_version = 0,
4119 },
4120 {
4121 .name = "TI UltraSparc IIi",
4122 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
4123 | (MAXTL << 8) | (NWINDOWS - 1)),
4124 .fpu_version = 0x00000000,
4125 .mmu_version = 0,
4126 },
4127 {
4128 .name = "TI UltraSparc IIe",
4129 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
4130 | (MAXTL << 8) | (NWINDOWS - 1)),
4131 .fpu_version = 0x00000000,
4132 .mmu_version = 0,
4133 },
4134 {
4135 .name = "Sun UltraSparc III",
4136 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
4137 | (MAXTL << 8) | (NWINDOWS - 1)),
4138 .fpu_version = 0x00000000,
4139 .mmu_version = 0,
4140 },
4141 {
4142 .name = "Sun UltraSparc III Cu",
4143 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
4144 | (MAXTL << 8) | (NWINDOWS - 1)),
4145 .fpu_version = 0x00000000,
4146 .mmu_version = 0,
4147 },
4148 {
4149 .name = "Sun UltraSparc IIIi",
4150 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
4151 | (MAXTL << 8) | (NWINDOWS - 1)),
4152 .fpu_version = 0x00000000,
4153 .mmu_version = 0,
4154 },
4155 {
4156 .name = "Sun UltraSparc IV",
4157 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
4158 | (MAXTL << 8) | (NWINDOWS - 1)),
4159 .fpu_version = 0x00000000,
4160 .mmu_version = 0,
4161 },
4162 {
4163 .name = "Sun UltraSparc IV+",
4164 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
4165 | (MAXTL << 8) | (NWINDOWS - 1)),
4166 .fpu_version = 0x00000000,
4167 .mmu_version = 0,
4168 },
4169 {
4170 .name = "Sun UltraSparc IIIi+",
4171 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
4172 | (MAXTL << 8) | (NWINDOWS - 1)),
4173 .fpu_version = 0x00000000,
4174 .mmu_version = 0,
4175 },
4176 {
4177 .name = "NEC UltraSparc I",
4178 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
62724a37
BS		 4179 | (MAXTL << 8) | (NWINDOWS - 1)),
4180 .fpu_version = 0x00000000,
4181 .mmu_version = 0,
4182 },
4183#else
406f82e8
BS		 4184 {
4185 .name = "Fujitsu MB86900",
4186 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
4187 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4188 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
4189 .mmu_bm = 0x00004000,
3deaeab7
BS		 4190 .mmu_ctpr_mask = 0x007ffff0,
4191 .mmu_cxr_mask = 0x0000003f,
4192 .mmu_sfsr_mask = 0xffffffff,
4193 .mmu_trcr_mask = 0xffffffff,
406f82e8 4194 },
62724a37
BS		 4195 {
4196 .name = "Fujitsu MB86904",
4197 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
4198 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4199 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
6d5f237a 4200 .mmu_bm = 0x00004000,
3deaeab7
BS		 4201 .mmu_ctpr_mask = 0x00ffffc0,
4202 .mmu_cxr_mask = 0x000000ff,
4203 .mmu_sfsr_mask = 0x00016fff,
4204 .mmu_trcr_mask = 0x00ffffff,
62724a37 4205 },
e0353fe2 4206 {
5ef62c5c
BS		 4207 .name = "Fujitsu MB86907",
4208 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
4209 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4210 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
6d5f237a 4211 .mmu_bm = 0x00004000,
3deaeab7
BS		 4212 .mmu_ctpr_mask = 0xffffffc0,
4213 .mmu_cxr_mask = 0x000000ff,
4214 .mmu_sfsr_mask = 0x00016fff,
4215 .mmu_trcr_mask = 0xffffffff,
5ef62c5c 4216 },
406f82e8
BS		 4217 {
4218 .name = "LSI L64811",
4219 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
4220 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
4221 .mmu_version = 0x10 << 24,
4222 .mmu_bm = 0x00004000,
3deaeab7
BS		 4223 .mmu_ctpr_mask = 0x007ffff0,
4224 .mmu_cxr_mask = 0x0000003f,
4225 .mmu_sfsr_mask = 0xffffffff,
4226 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4227 },
4228 {
4229 .name = "Cypress CY7C601",
4230 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
4231 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4232 .mmu_version = 0x10 << 24,
4233 .mmu_bm = 0x00004000,
3deaeab7
BS		 4234 .mmu_ctpr_mask = 0x007ffff0,
4235 .mmu_cxr_mask = 0x0000003f,
4236 .mmu_sfsr_mask = 0xffffffff,
4237 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4238 },
4239 {
4240 .name = "Cypress CY7C611",
4241 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
4242 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
4243 .mmu_version = 0x10 << 24,
4244 .mmu_bm = 0x00004000,
3deaeab7
BS		 4245 .mmu_ctpr_mask = 0x007ffff0,
4246 .mmu_cxr_mask = 0x0000003f,
4247 .mmu_sfsr_mask = 0xffffffff,
4248 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4249 },
4250 {
4251 .name = "TI SuperSparc II",
4252 .iu_version = 0x40000000,
4253 .fpu_version = 0 << 17,
4254 .mmu_version = 0x04000000,
4255 .mmu_bm = 0x00002000,
3deaeab7
BS		 4256 .mmu_ctpr_mask = 0xffffffc0,
4257 .mmu_cxr_mask = 0x0000ffff,
4258 .mmu_sfsr_mask = 0xffffffff,
4259 .mmu_trcr_mask = 0xffffffff,
406f82e8 4260 },
5ef62c5c
BS		 4261 {
4262 .name = "TI MicroSparc I",
4263 .iu_version = 0x41000000,
4264 .fpu_version = 4 << 17,
4265 .mmu_version = 0x41000000,
6d5f237a 4266 .mmu_bm = 0x00004000,
3deaeab7
BS		 4267 .mmu_ctpr_mask = 0x007ffff0,
4268 .mmu_cxr_mask = 0x0000003f,
4269 .mmu_sfsr_mask = 0x00016fff,
4270 .mmu_trcr_mask = 0x0000003f,
5ef62c5c
BS		 4271 },
4272 {
406f82e8
BS		 4273 .name = "TI MicroSparc II",
4274 .iu_version = 0x42000000,
4275 .fpu_version = 4 << 17,
4276 .mmu_version = 0x02000000,
4277 .mmu_bm = 0x00004000,
3deaeab7
BS		 4278 .mmu_ctpr_mask = 0x00ffffc0,
4279 .mmu_cxr_mask = 0x000000ff,
a3ffaf30 4280 .mmu_sfsr_mask = 0x00016fff,
3deaeab7 4281 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4282 },
4283 {
4284 .name = "TI MicroSparc IIep",
4285 .iu_version = 0x42000000,
4286 .fpu_version = 4 << 17,
4287 .mmu_version = 0x04000000,
4288 .mmu_bm = 0x00004000,
3deaeab7
BS		 4289 .mmu_ctpr_mask = 0x00ffffc0,
4290 .mmu_cxr_mask = 0x000000ff,
4291 .mmu_sfsr_mask = 0x00016bff,
4292 .mmu_trcr_mask = 0x00ffffff,
406f82e8
BS		 4293 },
4294 {
4295 .name = "TI SuperSparc 51",
4296 .iu_version = 0x43000000,
5ef62c5c
BS		 4297 .fpu_version = 0 << 17,
4298 .mmu_version = 0x04000000,
6d5f237a 4299 .mmu_bm = 0x00002000,
3deaeab7
BS		 4300 .mmu_ctpr_mask = 0xffffffc0,
4301 .mmu_cxr_mask = 0x0000ffff,
4302 .mmu_sfsr_mask = 0xffffffff,
4303 .mmu_trcr_mask = 0xffffffff,
5ef62c5c
BS		 4304 },
4305 {
406f82e8
BS		 4306 .name = "TI SuperSparc 61",
4307 .iu_version = 0x44000000,
4308 .fpu_version = 0 << 17,
4309 .mmu_version = 0x04000000,
4310 .mmu_bm = 0x00002000,
3deaeab7
BS		 4311 .mmu_ctpr_mask = 0xffffffc0,
4312 .mmu_cxr_mask = 0x0000ffff,
4313 .mmu_sfsr_mask = 0xffffffff,
4314 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4315 },
4316 {
4317 .name = "Ross RT625",
5ef62c5c
BS		 4318 .iu_version = 0x1e000000,
4319 .fpu_version = 1 << 17,
406f82e8
BS		 4320 .mmu_version = 0x1e000000,
4321 .mmu_bm = 0x00004000,
3deaeab7
BS		 4322 .mmu_ctpr_mask = 0x007ffff0,
4323 .mmu_cxr_mask = 0x0000003f,
4324 .mmu_sfsr_mask = 0xffffffff,
4325 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4326 },
4327 {
4328 .name = "Ross RT620",
4329 .iu_version = 0x1f000000,
4330 .fpu_version = 1 << 17,
4331 .mmu_version = 0x1f000000,
4332 .mmu_bm = 0x00004000,
3deaeab7
BS		 4333 .mmu_ctpr_mask = 0x007ffff0,
4334 .mmu_cxr_mask = 0x0000003f,
4335 .mmu_sfsr_mask = 0xffffffff,
4336 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4337 },
4338 {
4339 .name = "BIT B5010",
4340 .iu_version = 0x20000000,
4341 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
4342 .mmu_version = 0x20000000,
4343 .mmu_bm = 0x00004000,
3deaeab7
BS		 4344 .mmu_ctpr_mask = 0x007ffff0,
4345 .mmu_cxr_mask = 0x0000003f,
4346 .mmu_sfsr_mask = 0xffffffff,
4347 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4348 },
4349 {
4350 .name = "Matsushita MN10501",
4351 .iu_version = 0x50000000,
4352 .fpu_version = 0 << 17,
4353 .mmu_version = 0x50000000,
4354 .mmu_bm = 0x00004000,
3deaeab7
BS		 4355 .mmu_ctpr_mask = 0x007ffff0,
4356 .mmu_cxr_mask = 0x0000003f,
4357 .mmu_sfsr_mask = 0xffffffff,
4358 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4359 },
4360 {
4361 .name = "Weitek W8601",
4362 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
4363 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
4364 .mmu_version = 0x10 << 24,
4365 .mmu_bm = 0x00004000,
3deaeab7
BS		 4366 .mmu_ctpr_mask = 0x007ffff0,
4367 .mmu_cxr_mask = 0x0000003f,
4368 .mmu_sfsr_mask = 0xffffffff,
4369 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4370 },
4371 {
4372 .name = "LEON2",
4373 .iu_version = 0xf2000000,
4374 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4375 .mmu_version = 0xf2000000,
4376 .mmu_bm = 0x00004000,
3deaeab7
BS		 4377 .mmu_ctpr_mask = 0x007ffff0,
4378 .mmu_cxr_mask = 0x0000003f,
4379 .mmu_sfsr_mask = 0xffffffff,
4380 .mmu_trcr_mask = 0xffffffff,
406f82e8
BS		 4381 },
4382 {
4383 .name = "LEON3",
4384 .iu_version = 0xf3000000,
4385 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4386 .mmu_version = 0xf3000000,
6d5f237a 4387 .mmu_bm = 0x00004000,
3deaeab7
BS		 4388 .mmu_ctpr_mask = 0x007ffff0,
4389 .mmu_cxr_mask = 0x0000003f,
4390 .mmu_sfsr_mask = 0xffffffff,
4391 .mmu_trcr_mask = 0xffffffff,
e0353fe2 4392 },
62724a37
BS		 4393#endif
4394};
4395
aaed909a 4396static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
62724a37 4397{
62724a37
BS		 4398 unsigned int i;
4399
62724a37
BS		 4400 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4401 if (strcasecmp(name, sparc_defs[i].name) == 0) {
aaed909a 4402 return &sparc_defs[i];
62724a37
BS		 4403 }
4404 }
aaed909a 4405 return NULL;
62724a37
BS		 4406}
4407
4408void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4409{
4410 unsigned int i;
4411
4412 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4413 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
4414 sparc_defs[i].name,
4415 sparc_defs[i].iu_version,
4416 sparc_defs[i].fpu_version,
4417 sparc_defs[i].mmu_version);
4418 }
4419}
4420
7a3f1944
FB		 4421#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
4422
5fafdf24 4423void cpu_dump_state(CPUState *env, FILE *f,
7fe48483
FB		 4424 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4425 int flags)
7a3f1944 4426{
cf495bcf
FB		 4427 int i, x;
4428
af7bf89b 4429 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
7fe48483 4430 cpu_fprintf(f, "General Registers:\n");
cf495bcf 4431 for (i = 0; i < 4; i++)
0f8a249a 4432 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 4433 cpu_fprintf(f, "\n");
cf495bcf 4434 for (; i < 8; i++)
0f8a249a 4435 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
7fe48483 4436 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf 4437 for (x = 0; x < 3; x++) {
0f8a249a
BS		 4438 for (i = 0; i < 4; i++)
4439 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4440 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
4441 env->regwptr[i + x * 8]);
4442 cpu_fprintf(f, "\n");
4443 for (; i < 8; i++)
4444 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4445 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
4446 env->regwptr[i + x * 8]);
4447 cpu_fprintf(f, "\n");
cf495bcf 4448 }
7fe48483 4449 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 4450 for (i = 0; i < 32; i++) {
4451 if ((i & 3) == 0)
7fe48483
FB		 4452 cpu_fprintf(f, "%%f%02d:", i);
4453 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 4454 if ((i & 3) == 3)
7fe48483 4455 cpu_fprintf(f, "\n");
e8af50a3 4456 }
ded3ab80 4457#ifdef TARGET_SPARC64
3299908c 4458 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
0f8a249a 4459 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
ded3ab80 4460 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
0f8a249a
BS		 4461 env->cansave, env->canrestore, env->otherwin, env->wstate,
4462 env->cleanwin, NWINDOWS - 1 - env->cwp);
ded3ab80 4463#else
7fe48483 4464 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
0f8a249a
BS		 4465 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
4466 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
4467 env->psrs?'S':'-', env->psrps?'P':'-',
4468 env->psret?'E':'-', env->wim);
ded3ab80 4469#endif
3475187d 4470 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
7a3f1944 4471}
edfcbd99 4472
e80cfcfc 4473#if defined(CONFIG_USER_ONLY)
9b3c35e0 4474target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
edfcbd99
FB		 4475{
4476 return addr;
4477}
658138bc 4478
e80cfcfc 4479#else
af7bf89b
FB		 4480extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
4481 int *access_index, target_ulong address, int rw,
6ebbf390 4482 int mmu_idx);
0fa85d43 4483
9b3c35e0 4484target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
e80cfcfc 4485{
af7bf89b 4486 target_phys_addr_t phys_addr;
e80cfcfc
FB		 4487 int prot, access_index;
4488
9e31b9e2
BS		 4489 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
4490 MMU_KERNEL_IDX) != 0)
4491 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
4492 0, MMU_KERNEL_IDX) != 0)
6b1575b7 4493 return -1;
6c36d3fa
BS		 4494 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
4495 return -1;
e80cfcfc
FB		 4496 return phys_addr;
4497}
4498#endif
4499
658138bc
FB		 4500void helper_flush(target_ulong addr)
4501{
4502 addr &= ~7;
4503 tb_invalidate_page_range(addr, addr + 8);
4504}
Mirror of https://git.qemu.org/git/qemu.git