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Commit | Line | Data |
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01b753ff S |
1 | /* |
2 | * | |
3 | * HW data initialization for OMAP5 | |
4 | * | |
5 | * (C) Copyright 2013 | |
6 | * Texas Instruments, <www.ti.com> | |
7 | * | |
8 | * Sricharan R <r.sricharan@ti.com> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
01b753ff S |
11 | */ |
12 | #include <common.h> | |
63fc0c77 | 13 | #include <palmas.h> |
01b753ff | 14 | #include <asm/arch/omap.h> |
ee9447bf | 15 | #include <asm/arch/sys_proto.h> |
01b753ff | 16 | #include <asm/omap_common.h> |
af1d002f | 17 | #include <asm/arch/clock.h> |
3fcdd4a5 | 18 | #include <asm/omap_gpio.h> |
ee9447bf | 19 | #include <asm/io.h> |
ef1697e9 | 20 | #include <asm/emif.h> |
01b753ff S |
21 | |
22 | struct prcm_regs const **prcm = | |
23 | (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; | |
ee9447bf S |
24 | struct dplls const **dplls_data = |
25 | (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; | |
3fcdd4a5 S |
26 | struct vcores_data const **omap_vcores = |
27 | (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; | |
c43c8339 | 28 | struct omap_sys_ctrl_regs const **ctrl = |
f92f2277 | 29 | (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; |
ee9447bf | 30 | |
47abc3df | 31 | /* OPP HIGH FREQUENCY for ES2.0 */ |
ee9447bf | 32 | static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { |
47abc3df S |
33 | {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
34 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
35 | {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
36 | {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
37 | {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
38 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
39 | {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
40 | }; |
41 | ||
47abc3df | 42 | /* OPP NOM FREQUENCY for ES1.0 */ |
ee9447bf | 43 | static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { |
47abc3df S |
44 | {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
45 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
46 | {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
47 | {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
48 | {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
49 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
50 | {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
51 | }; |
52 | ||
47abc3df | 53 | /* OPP LOW FREQUENCY for ES1.0 */ |
ee9447bf | 54 | static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { |
47abc3df S |
55 | {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
56 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
57 | {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
58 | {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
59 | {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
60 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
61 | {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
62 | }; |
63 | ||
47abc3df S |
64 | /* OPP LOW FREQUENCY for ES2.0 */ |
65 | static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { | |
66 | {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ | |
67 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
68 | {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
69 | {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
70 | {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
71 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
72 | {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
73 | }; |
74 | ||
d2c7074b | 75 | /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ |
ea8eff1f | 76 | static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { |
97405d84 LV |
77 | {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
78 | {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ | |
79 | {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
80 | {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
81 | {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
ea8eff1f | 82 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
97405d84 | 83 | {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
ea8eff1f LV |
84 | }; |
85 | ||
ee9447bf S |
86 | static const struct dpll_params |
87 | core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { | |
47abc3df S |
88 | {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ |
89 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
90 | {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ | |
91 | {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ | |
92 | {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ | |
93 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
94 | {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ | |
95 | }; | |
96 | ||
97 | static const struct dpll_params | |
98 | core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { | |
99 | {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ | |
100 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
101 | {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ | |
102 | {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ | |
103 | {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ | |
104 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
105 | {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ | |
ee9447bf S |
106 | }; |
107 | ||
ea8eff1f | 108 | static const struct dpll_params |
97405d84 LV |
109 | core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { |
110 | {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ | |
111 | {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ | |
112 | {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ | |
113 | {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ | |
114 | {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ | |
ea8eff1f | 115 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
97405d84 | 116 | {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ |
ea8eff1f LV |
117 | }; |
118 | ||
ee9447bf S |
119 | static const struct dpll_params |
120 | core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { | |
47abc3df S |
121 | {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ |
122 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
123 | {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ | |
124 | {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ | |
125 | {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ | |
126 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
127 | {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ | |
128 | }; | |
129 | ||
130 | static const struct dpll_params | |
131 | core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { | |
132 | {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ | |
133 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
134 | {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ | |
135 | {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ | |
136 | {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ | |
137 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
138 | {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ | |
ee9447bf S |
139 | }; |
140 | ||
141 | static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { | |
47abc3df S |
142 | {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ |
143 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
144 | {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ | |
145 | {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ | |
146 | {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ | |
147 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
148 | {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ | |
149 | }; | |
150 | ||
151 | static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { | |
152 | {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ | |
153 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
154 | {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ | |
155 | {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ | |
156 | {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ | |
157 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
158 | {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
159 | }; |
160 | ||
ea8eff1f | 161 | static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { |
5298f21a | 162 | {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ |
62d206dc | 163 | {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ |
5298f21a LV |
164 | {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
165 | {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ | |
166 | {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ | |
ea8eff1f | 167 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
5298f21a | 168 | {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ |
ea8eff1f LV |
169 | }; |
170 | ||
ee9447bf | 171 | static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { |
47abc3df S |
172 | {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
173 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
174 | {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
175 | {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
176 | {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
177 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
178 | {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
179 | }; |
180 | ||
97405d84 LV |
181 | static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { |
182 | {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ | |
183 | {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ | |
184 | {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
185 | {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
186 | {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
187 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
188 | {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ | |
189 | }; | |
190 | ||
ee9447bf S |
191 | /* ABE M & N values with sys_clk as source */ |
192 | static const struct dpll_params | |
193 | abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { | |
47abc3df S |
194 | {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
195 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ | |
196 | {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
197 | {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
198 | {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
199 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
200 | {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ | |
ee9447bf S |
201 | }; |
202 | ||
203 | /* ABE M & N values with 32K clock as source */ | |
204 | static const struct dpll_params abe_dpll_params_32k_196608khz = { | |
47abc3df | 205 | 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 |
ee9447bf S |
206 | }; |
207 | ||
97405d84 LV |
208 | /* ABE M & N values with sysclk2(22.5792 MHz) as input */ |
209 | static const struct dpll_params | |
210 | abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { | |
211 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ | |
212 | {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ | |
213 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
214 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
215 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
216 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
217 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ | |
218 | }; | |
219 | ||
ee9447bf | 220 | static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
47abc3df | 221 | {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
97405d84 | 222 | {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
47abc3df S |
223 | {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
224 | {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
225 | {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
226 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
ea8eff1f | 227 | {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
ea8eff1f LV |
228 | }; |
229 | ||
681f785f S |
230 | static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { |
231 | {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ | |
232 | {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ | |
233 | {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
234 | {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
235 | {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
236 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
237 | {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ | |
238 | }; | |
239 | ||
97405d84 LV |
240 | static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { |
241 | {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ | |
242 | {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ | |
243 | {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
244 | {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
245 | {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
ea8eff1f | 246 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
97405d84 | 247 | {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
ee9447bf S |
248 | }; |
249 | ||
65e9d56f LV |
250 | static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { |
251 | {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ | |
252 | {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ | |
253 | {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ | |
254 | {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ | |
255 | {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ | |
256 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ | |
257 | {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ | |
258 | }; | |
259 | ||
ee9447bf S |
260 | struct dplls omap5_dplls_es1 = { |
261 | .mpu = mpu_dpll_params_800mhz, | |
262 | .core = core_dpll_params_2128mhz_ddr532, | |
263 | .per = per_dpll_params_768mhz, | |
264 | .iva = iva_dpll_params_2330mhz, | |
265 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK | |
266 | .abe = abe_dpll_params_sysclk_196608khz, | |
267 | #else | |
268 | .abe = &abe_dpll_params_32k_196608khz, | |
269 | #endif | |
ea8eff1f LV |
270 | .usb = usb_dpll_params_1920mhz, |
271 | .ddr = NULL | |
ee9447bf S |
272 | }; |
273 | ||
47abc3df | 274 | struct dplls omap5_dplls_es2 = { |
d2c7074b | 275 | .mpu = mpu_dpll_params_1ghz, |
47abc3df S |
276 | .core = core_dpll_params_2128mhz_ddr532_es2, |
277 | .per = per_dpll_params_768mhz_es2, | |
278 | .iva = iva_dpll_params_2330mhz, | |
279 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK | |
280 | .abe = abe_dpll_params_sysclk_196608khz, | |
281 | #else | |
282 | .abe = &abe_dpll_params_32k_196608khz, | |
283 | #endif | |
ea8eff1f LV |
284 | .usb = usb_dpll_params_1920mhz, |
285 | .ddr = NULL | |
286 | }; | |
287 | ||
288 | struct dplls dra7xx_dplls = { | |
289 | .mpu = mpu_dpll_params_1ghz, | |
97405d84 | 290 | .core = core_dpll_params_2128mhz_dra7xx, |
ea8eff1f | 291 | .per = per_dpll_params_768mhz_dra7xx, |
97405d84 LV |
292 | .abe = abe_dpll_params_sysclk2_361267khz, |
293 | .iva = iva_dpll_params_2330mhz_dra7xx, | |
ea8eff1f | 294 | .usb = usb_dpll_params_1920mhz, |
97405d84 | 295 | .ddr = ddr_dpll_params_2128mhz, |
65e9d56f | 296 | .gmac = gmac_dpll_params_2000mhz, |
47abc3df S |
297 | }; |
298 | ||
681f785f S |
299 | struct dplls dra72x_dplls = { |
300 | .mpu = mpu_dpll_params_1ghz, | |
301 | .core = core_dpll_params_2128mhz_dra7xx, | |
302 | .per = per_dpll_params_768mhz_dra7xx, | |
303 | .abe = abe_dpll_params_sysclk2_361267khz, | |
304 | .iva = iva_dpll_params_2330mhz_dra7xx, | |
305 | .usb = usb_dpll_params_1920mhz, | |
306 | .ddr = ddr_dpll_params_2664mhz, | |
307 | .gmac = gmac_dpll_params_2000mhz, | |
308 | }; | |
309 | ||
3fcdd4a5 S |
310 | struct pmic_data palmas = { |
311 | .base_offset = PALMAS_SMPS_BASE_VOLT_UV, | |
312 | .step = 10000, /* 10 mV represented in uV */ | |
313 | /* | |
314 | * Offset codes 1-6 all give the base voltage in Palmas | |
315 | * Offset code 0 switches OFF the SMPS | |
316 | */ | |
317 | .start_code = 6, | |
4ca94d81 LV |
318 | .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, |
319 | .pmic_bus_init = sri2c_init, | |
320 | .pmic_write = omap_vc_bypass_send_value, | |
3fcdd4a5 S |
321 | }; |
322 | ||
b558af81 | 323 | /* The TPS659038 and TPS65917 are software-compatible, use common struct */ |
63fc0c77 LV |
324 | struct pmic_data tps659038 = { |
325 | .base_offset = PALMAS_SMPS_BASE_VOLT_UV, | |
326 | .step = 10000, /* 10 mV represented in uV */ | |
327 | /* | |
328 | * Offset codes 1-6 all give the base voltage in Palmas | |
329 | * Offset code 0 switches OFF the SMPS | |
330 | */ | |
331 | .start_code = 6, | |
332 | .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, | |
333 | .pmic_bus_init = gpi2c_init, | |
334 | .pmic_write = palmas_i2c_write_u8, | |
335 | }; | |
336 | ||
3fcdd4a5 S |
337 | struct vcores_data omap5430_volts = { |
338 | .mpu.value = VDD_MPU, | |
339 | .mpu.addr = SMPS_REG_ADDR_12_MPU, | |
340 | .mpu.pmic = &palmas, | |
341 | ||
342 | .core.value = VDD_CORE, | |
343 | .core.addr = SMPS_REG_ADDR_8_CORE, | |
344 | .core.pmic = &palmas, | |
345 | ||
346 | .mm.value = VDD_MM, | |
347 | .mm.addr = SMPS_REG_ADDR_45_IVA, | |
348 | .mm.pmic = &palmas, | |
349 | }; | |
350 | ||
47abc3df S |
351 | struct vcores_data omap5430_volts_es2 = { |
352 | .mpu.value = VDD_MPU_ES2, | |
3fcdd4a5 S |
353 | .mpu.addr = SMPS_REG_ADDR_12_MPU, |
354 | .mpu.pmic = &palmas, | |
3708e78c | 355 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
3fcdd4a5 | 356 | |
47abc3df | 357 | .core.value = VDD_CORE_ES2, |
3fcdd4a5 S |
358 | .core.addr = SMPS_REG_ADDR_8_CORE, |
359 | .core.pmic = &palmas, | |
360 | ||
47abc3df | 361 | .mm.value = VDD_MM_ES2, |
3fcdd4a5 S |
362 | .mm.addr = SMPS_REG_ADDR_45_IVA, |
363 | .mm.pmic = &palmas, | |
a818097a | 364 | .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, |
3fcdd4a5 S |
365 | }; |
366 | ||
ee9447bf S |
367 | /* |
368 | * Enable essential clock domains, modules and | |
369 | * do some additional special settings needed | |
370 | */ | |
371 | void enable_basic_clocks(void) | |
372 | { | |
373 | u32 const clk_domains_essential[] = { | |
374 | (*prcm)->cm_l4per_clkstctrl, | |
375 | (*prcm)->cm_l3init_clkstctrl, | |
376 | (*prcm)->cm_memif_clkstctrl, | |
377 | (*prcm)->cm_l4cfg_clkstctrl, | |
f986d972 M |
378 | #ifdef CONFIG_DRIVER_TI_CPSW |
379 | (*prcm)->cm_gmac_clkstctrl, | |
380 | #endif | |
ee9447bf S |
381 | 0 |
382 | }; | |
383 | ||
384 | u32 const clk_modules_hw_auto_essential[] = { | |
d4e4129c | 385 | (*prcm)->cm_l3_gpmc_clkctrl, |
ee9447bf S |
386 | (*prcm)->cm_memif_emif_1_clkctrl, |
387 | (*prcm)->cm_memif_emif_2_clkctrl, | |
388 | (*prcm)->cm_l4cfg_l4_cfg_clkctrl, | |
389 | (*prcm)->cm_wkup_gpio1_clkctrl, | |
390 | (*prcm)->cm_l4per_gpio2_clkctrl, | |
391 | (*prcm)->cm_l4per_gpio3_clkctrl, | |
392 | (*prcm)->cm_l4per_gpio4_clkctrl, | |
393 | (*prcm)->cm_l4per_gpio5_clkctrl, | |
394 | (*prcm)->cm_l4per_gpio6_clkctrl, | |
87bd05d7 AL |
395 | (*prcm)->cm_l4per_gpio7_clkctrl, |
396 | (*prcm)->cm_l4per_gpio8_clkctrl, | |
ee9447bf S |
397 | 0 |
398 | }; | |
399 | ||
400 | u32 const clk_modules_explicit_en_essential[] = { | |
401 | (*prcm)->cm_wkup_gptimer1_clkctrl, | |
402 | (*prcm)->cm_l3init_hsmmc1_clkctrl, | |
403 | (*prcm)->cm_l3init_hsmmc2_clkctrl, | |
404 | (*prcm)->cm_l4per_gptimer2_clkctrl, | |
405 | (*prcm)->cm_wkup_wdtimer2_clkctrl, | |
406 | (*prcm)->cm_l4per_uart3_clkctrl, | |
407 | (*prcm)->cm_l4per_i2c1_clkctrl, | |
f986d972 M |
408 | #ifdef CONFIG_DRIVER_TI_CPSW |
409 | (*prcm)->cm_gmac_gmac_clkctrl, | |
410 | #endif | |
c97a9b32 MP |
411 | |
412 | #ifdef CONFIG_TI_QSPI | |
413 | (*prcm)->cm_l4per_qspi_clkctrl, | |
414 | #endif | |
ee9447bf S |
415 | 0 |
416 | }; | |
417 | ||
418 | /* Enable optional additional functional clock for GPIO4 */ | |
419 | setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, | |
420 | GPIO4_CLKCTRL_OPTFCLKEN_MASK); | |
421 | ||
422 | /* Enable 96 MHz clock for MMC1 & MMC2 */ | |
423 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, | |
424 | HSMMC_CLKCTRL_CLKSEL_MASK); | |
425 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, | |
426 | HSMMC_CLKCTRL_CLKSEL_MASK); | |
427 | ||
428 | /* Set the correct clock dividers for mmc */ | |
429 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, | |
430 | HSMMC_CLKCTRL_CLKSEL_DIV_MASK); | |
431 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, | |
432 | HSMMC_CLKCTRL_CLKSEL_DIV_MASK); | |
433 | ||
434 | /* Select 32KHz clock as the source of GPTIMER1 */ | |
435 | setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, | |
436 | GPTIMER1_CLKCTRL_CLKSEL_MASK); | |
437 | ||
438 | do_enable_clocks(clk_domains_essential, | |
439 | clk_modules_hw_auto_essential, | |
440 | clk_modules_explicit_en_essential, | |
441 | 1); | |
442 | ||
c97a9b32 MP |
443 | #ifdef CONFIG_TI_QSPI |
444 | setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); | |
445 | #endif | |
446 | ||
ee9447bf S |
447 | /* Enable SCRM OPT clocks for PER and CORE dpll */ |
448 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, | |
449 | OPTFCLKEN_SCRM_PER_MASK); | |
450 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, | |
451 | OPTFCLKEN_SCRM_CORE_MASK); | |
452 | } | |
453 | ||
454 | void enable_basic_uboot_clocks(void) | |
455 | { | |
456 | u32 const clk_domains_essential[] = { | |
37be54fd LV |
457 | #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) |
458 | (*prcm)->cm_ipu_clkstctrl, | |
459 | #endif | |
ee9447bf S |
460 | 0 |
461 | }; | |
462 | ||
463 | u32 const clk_modules_hw_auto_essential[] = { | |
2bcc785a | 464 | (*prcm)->cm_l3init_hsusbtll_clkctrl, |
ee9447bf S |
465 | 0 |
466 | }; | |
467 | ||
468 | u32 const clk_modules_explicit_en_essential[] = { | |
469 | (*prcm)->cm_l4per_mcspi1_clkctrl, | |
470 | (*prcm)->cm_l4per_i2c2_clkctrl, | |
471 | (*prcm)->cm_l4per_i2c3_clkctrl, | |
472 | (*prcm)->cm_l4per_i2c4_clkctrl, | |
37be54fd LV |
473 | #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) |
474 | (*prcm)->cm_ipu_i2c5_clkctrl, | |
475 | #else | |
3935277d | 476 | (*prcm)->cm_l4per_i2c5_clkctrl, |
37be54fd | 477 | #endif |
ee9447bf S |
478 | (*prcm)->cm_l3init_hsusbhost_clkctrl, |
479 | (*prcm)->cm_l3init_fsusb_clkctrl, | |
480 | 0 | |
481 | }; | |
ee9447bf S |
482 | do_enable_clocks(clk_domains_essential, |
483 | clk_modules_hw_auto_essential, | |
484 | clk_modules_explicit_en_essential, | |
485 | 1); | |
486 | } | |
487 | ||
8a09cfe1 V |
488 | #ifdef CONFIG_TI_EDMA3 |
489 | void enable_edma3_clocks(void) | |
490 | { | |
491 | u32 const clk_domains_edma3[] = { | |
492 | 0 | |
493 | }; | |
494 | ||
495 | u32 const clk_modules_hw_auto_edma3[] = { | |
496 | (*prcm)->cm_l3main1_tptc1_clkctrl, | |
497 | (*prcm)->cm_l3main1_tptc2_clkctrl, | |
498 | 0 | |
499 | }; | |
500 | ||
501 | u32 const clk_modules_explicit_en_edma3[] = { | |
502 | 0 | |
503 | }; | |
504 | ||
505 | do_enable_clocks(clk_domains_edma3, | |
506 | clk_modules_hw_auto_edma3, | |
507 | clk_modules_explicit_en_edma3, | |
508 | 1); | |
509 | } | |
510 | ||
511 | void disable_edma3_clocks(void) | |
512 | { | |
513 | u32 const clk_domains_edma3[] = { | |
514 | 0 | |
515 | }; | |
516 | ||
517 | u32 const clk_modules_disable_edma3[] = { | |
518 | (*prcm)->cm_l3main1_tptc1_clkctrl, | |
519 | (*prcm)->cm_l3main1_tptc2_clkctrl, | |
520 | 0 | |
521 | }; | |
522 | ||
523 | do_disable_clocks(clk_domains_edma3, | |
524 | clk_modules_disable_edma3, | |
525 | 1); | |
526 | } | |
527 | #endif | |
528 | ||
383f4a0e | 529 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) |
ca5a0f17 KVA |
530 | void enable_usb_clocks(int index) |
531 | { | |
532 | u32 cm_l3init_usb_otg_ss_clkctrl = 0; | |
533 | ||
534 | if (index == 0) { | |
535 | cm_l3init_usb_otg_ss_clkctrl = | |
536 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; | |
537 | /* Enable 960 MHz clock for dwc3 */ | |
538 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, | |
539 | OPTFCLKEN_REFCLK960M); | |
540 | ||
3599774e | 541 | /* Enable 32 KHz clock for USB_PHY1 */ |
ca5a0f17 KVA |
542 | setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
543 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
3599774e RQ |
544 | |
545 | /* Enable 32 KHz clock for USB_PHY3 */ | |
546 | if (is_dra7xx()) | |
547 | setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, | |
548 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
ca5a0f17 KVA |
549 | } else if (index == 1) { |
550 | cm_l3init_usb_otg_ss_clkctrl = | |
551 | (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; | |
552 | /* Enable 960 MHz clock for dwc3 */ | |
553 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, | |
554 | OPTFCLKEN_REFCLK960M); | |
555 | ||
556 | /* Enable 32 KHz clock for dwc3 */ | |
557 | setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, | |
558 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
559 | ||
560 | /* Enable 60 MHz clock for USB2PHY2 */ | |
561 | setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, | |
562 | L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); | |
563 | } | |
564 | ||
565 | u32 const clk_domains_usb[] = { | |
566 | 0 | |
567 | }; | |
568 | ||
569 | u32 const clk_modules_hw_auto_usb[] = { | |
570 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, | |
571 | cm_l3init_usb_otg_ss_clkctrl, | |
572 | 0 | |
573 | }; | |
574 | ||
575 | u32 const clk_modules_explicit_en_usb[] = { | |
576 | 0 | |
577 | }; | |
578 | ||
579 | do_enable_clocks(clk_domains_usb, | |
580 | clk_modules_hw_auto_usb, | |
581 | clk_modules_explicit_en_usb, | |
582 | 1); | |
583 | } | |
584 | ||
585 | void disable_usb_clocks(int index) | |
586 | { | |
587 | u32 cm_l3init_usb_otg_ss_clkctrl = 0; | |
588 | ||
589 | if (index == 0) { | |
590 | cm_l3init_usb_otg_ss_clkctrl = | |
591 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; | |
592 | /* Disable 960 MHz clock for dwc3 */ | |
593 | clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, | |
594 | OPTFCLKEN_REFCLK960M); | |
595 | ||
3599774e | 596 | /* Disable 32 KHz clock for USB_PHY1 */ |
ca5a0f17 KVA |
597 | clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
598 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
3599774e RQ |
599 | |
600 | /* Disable 32 KHz clock for USB_PHY3 */ | |
601 | if (is_dra7xx()) | |
602 | clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, | |
603 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
ca5a0f17 KVA |
604 | } else if (index == 1) { |
605 | cm_l3init_usb_otg_ss_clkctrl = | |
606 | (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; | |
607 | /* Disable 960 MHz clock for dwc3 */ | |
608 | clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, | |
609 | OPTFCLKEN_REFCLK960M); | |
610 | ||
611 | /* Disable 32 KHz clock for dwc3 */ | |
612 | clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, | |
613 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); | |
614 | ||
615 | /* Disable 60 MHz clock for USB2PHY2 */ | |
616 | clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, | |
617 | L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); | |
618 | } | |
619 | ||
620 | u32 const clk_domains_usb[] = { | |
621 | 0 | |
622 | }; | |
623 | ||
624 | u32 const clk_modules_disable[] = { | |
625 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, | |
626 | cm_l3init_usb_otg_ss_clkctrl, | |
627 | 0 | |
628 | }; | |
629 | ||
630 | do_disable_clocks(clk_domains_usb, | |
631 | clk_modules_disable, | |
632 | 1); | |
633 | } | |
634 | #endif | |
635 | ||
ef1697e9 LV |
636 | const struct ctrl_ioregs ioregs_omap5430 = { |
637 | .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, | |
638 | .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, | |
639 | .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, | |
640 | .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, | |
641 | .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, | |
642 | }; | |
643 | ||
644 | const struct ctrl_ioregs ioregs_omap5432_es1 = { | |
645 | .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, | |
646 | .ctrl_lpddr2ch = 0x0, | |
647 | .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, | |
648 | .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, | |
649 | .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, | |
650 | .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, | |
651 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, | |
6c70935d | 652 | .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, |
ef1697e9 LV |
653 | }; |
654 | ||
9100edec LV |
655 | const struct ctrl_ioregs ioregs_omap5432_es2 = { |
656 | .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, | |
657 | .ctrl_lpddr2ch = 0x0, | |
658 | .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, | |
659 | .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, | |
660 | .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, | |
661 | .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, | |
662 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, | |
6c70935d | 663 | .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, |
9100edec LV |
664 | }; |
665 | ||
92b0482c S |
666 | const struct ctrl_ioregs ioregs_dra7xx_es1 = { |
667 | .ctrl_ddrch = 0x40404040, | |
668 | .ctrl_lpddr2ch = 0x40404040, | |
669 | .ctrl_ddr3ch = 0x80808080, | |
536d8747 LV |
670 | .ctrl_ddrio_0 = 0x00094A40, |
671 | .ctrl_ddrio_1 = 0x04A52000, | |
92b0482c | 672 | .ctrl_ddrio_2 = 0x84210000, |
67055bee NM |
673 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
674 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, | |
92b0482c S |
675 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
676 | }; | |
677 | ||
681f785f S |
678 | const struct ctrl_ioregs ioregs_dra72x_es1 = { |
679 | .ctrl_ddrch = 0x40404040, | |
680 | .ctrl_lpddr2ch = 0x40404040, | |
681 | .ctrl_ddr3ch = 0x60606080, | |
536d8747 LV |
682 | .ctrl_ddrio_0 = 0x00094A40, |
683 | .ctrl_ddrio_1 = 0x04A52000, | |
681f785f | 684 | .ctrl_ddrio_2 = 0x84210000, |
67055bee NM |
685 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
686 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, | |
681f785f S |
687 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
688 | }; | |
689 | ||
3d042e46 NM |
690 | const struct ctrl_ioregs ioregs_dra72x_es2 = { |
691 | .ctrl_ddrch = 0x40404040, | |
692 | .ctrl_lpddr2ch = 0x40404040, | |
693 | .ctrl_ddr3ch = 0x60606060, | |
694 | .ctrl_ddrio_0 = 0x00094A40, | |
695 | .ctrl_ddrio_1 = 0x00000000, | |
696 | .ctrl_ddrio_2 = 0x00000000, | |
697 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, | |
698 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, | |
699 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, | |
700 | }; | |
701 | ||
29bc86ad | 702 | void __weak hw_data_init(void) |
01b753ff | 703 | { |
ee9447bf S |
704 | u32 omap_rev = omap_revision(); |
705 | ||
706 | switch (omap_rev) { | |
707 | ||
708 | case OMAP5430_ES1_0: | |
ee9447bf S |
709 | case OMAP5432_ES1_0: |
710 | *prcm = &omap5_es1_prcm; | |
711 | *dplls_data = &omap5_dplls_es1; | |
47abc3df | 712 | *omap_vcores = &omap5430_volts; |
8b12f177 | 713 | *ctrl = &omap5_ctrl; |
ee9447bf S |
714 | break; |
715 | ||
afc2f9dc S |
716 | case OMAP5430_ES2_0: |
717 | case OMAP5432_ES2_0: | |
718 | *prcm = &omap5_es2_prcm; | |
47abc3df S |
719 | *dplls_data = &omap5_dplls_es2; |
720 | *omap_vcores = &omap5430_volts_es2; | |
8b12f177 | 721 | *ctrl = &omap5_ctrl; |
afc2f9dc S |
722 | break; |
723 | ||
d4e4129c | 724 | case DRA752_ES1_0: |
3ac8c0bf | 725 | case DRA752_ES1_1: |
c1ea3bec | 726 | case DRA752_ES2_0: |
d4e4129c | 727 | *prcm = &dra7xx_prcm; |
ea8eff1f | 728 | *dplls_data = &dra7xx_dplls; |
8b12f177 | 729 | *ctrl = &dra7xx_ctrl; |
d4e4129c LV |
730 | break; |
731 | ||
4d6bf554 | 732 | case DRA722_ES1_0: |
d851ad3a | 733 | case DRA722_ES2_0: |
4d6bf554 | 734 | *prcm = &dra7xx_prcm; |
681f785f | 735 | *dplls_data = &dra72x_dplls; |
4d6bf554 LV |
736 | *ctrl = &dra7xx_ctrl; |
737 | break; | |
738 | ||
ee9447bf S |
739 | default: |
740 | printf("\n INVALID OMAP REVISION "); | |
741 | } | |
01b753ff | 742 | } |
ef1697e9 LV |
743 | |
744 | void get_ioregs(const struct ctrl_ioregs **regs) | |
745 | { | |
746 | u32 omap_rev = omap_revision(); | |
747 | ||
748 | switch (omap_rev) { | |
749 | case OMAP5430_ES1_0: | |
9100edec | 750 | case OMAP5430_ES2_0: |
ef1697e9 | 751 | *regs = &ioregs_omap5430; |
92b0482c | 752 | break; |
ef1697e9 LV |
753 | case OMAP5432_ES1_0: |
754 | *regs = &ioregs_omap5432_es1; | |
92b0482c | 755 | break; |
9100edec LV |
756 | case OMAP5432_ES2_0: |
757 | *regs = &ioregs_omap5432_es2; | |
92b0482c S |
758 | break; |
759 | case DRA752_ES1_0: | |
3ac8c0bf | 760 | case DRA752_ES1_1: |
c1ea3bec | 761 | case DRA752_ES2_0: |
92b0482c S |
762 | *regs = &ioregs_dra7xx_es1; |
763 | break; | |
681f785f S |
764 | case DRA722_ES1_0: |
765 | *regs = &ioregs_dra72x_es1; | |
766 | break; | |
3d042e46 NM |
767 | case DRA722_ES2_0: |
768 | *regs = &ioregs_dra72x_es2; | |
769 | break; | |
ef1697e9 LV |
770 | |
771 | default: | |
772 | printf("\n INVALID OMAP REVISION "); | |
773 | } | |
774 | } |