[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

/*
 * Copyright 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Modified by Xianghua Xiao, X.Xiao@motorola.com
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <sata.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
#include <hwconfig.h>
#include <linux/compiler.h>
#include "mp.h"
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
#endif

#include "../../../../drivers/block/fsl_sata.h"

#define HWCONFIG_BUFFER_SIZE 128

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
				int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);

static void config_qe_ioports(void)
{
	u8      port, pin;
	int     dir, open_drain, assign;
	int     i;

	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
		port		= qe_iop_conf_tab[i].port;
		pin		= qe_iop_conf_tab[i].pin;
		dir		= qe_iop_conf_tab[i].dir;
		open_drain	= qe_iop_conf_tab[i].open_drain;
		assign		= qe_iop_conf_tab[i].assign;
		qe_config_iopin(port, pin, dir, open_drain, assign);
	}
}
#endif

#ifdef CONFIG_CPM2
void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
	int portnum;

	for (portnum = 0; portnum < 4; portnum++) {
		uint pmsk = 0,
		     ppar = 0,
		     psor = 0,
		     pdir = 0,
		     podr = 0,
		     pdat = 0;
		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
		iop_conf_t *eiopc = iopc + 32;
		uint msk = 1;

		/*
		 * NOTE:
		 * index 0 refers to pin 31,
		 * index 31 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
			}

			msk <<= 1;
			iopc++;
		}

		if (pmsk != 0) {
			volatile ioport_t *iop = ioport_addr (cpm, portnum);
			uint tpmsk = ~pmsk;

			/*
			 * the (somewhat confused) paragraph at the
			 * bottom of page 35-5 warns that there might
			 * be "unknown behaviour" when programming
			 * PSORx and PDIRx, if PPARx = 1, so I
			 * decided this meant I had to disable the
			 * dedicated function first, and enable it
			 * last.
			 */
			iop->ppar &= tpmsk;
			iop->psor = (iop->psor & tpmsk) | psor;
			iop->podr = (iop->podr & tpmsk) | podr;
			iop->pdat = (iop->pdat & tpmsk) | pdat;
			iop->pdir = (iop->pdir & tpmsk) | pdir;
			iop->ppar |= ppar;
		}
	}
}
#endif

#ifdef CONFIG_SYS_FSL_CPC
static void enable_cpc(void)
{
	int i;
	u32 size = 0;

	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
		size += CPC_CFG0_SZ_K(cpccfg0);
#ifdef CONFIG_RAMBOOT_PBL
		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
			/* find and disable LAW of SRAM */
			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);

			if (law.index == -1) {
				printf("\nFatal error happened\n");
				return;
			}
			disable_law(law.index);

			clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
			out_be32(&cpc->cpccsr0, 0);
			out_be32(&cpc->cpcsrcr0, 0);
		}
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
#endif

		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
		/* Read back to sync write */
		in_be32(&cpc->cpccsr0);

	}

	printf("Corenet Platform Cache: %d KB enabled\n", size);
}

void invalidate_cpc(void)
{
	int i;
	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
		/* skip CPC when it used as all SRAM */
		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
			continue;
		/* Flash invalidate the CPC and clear all the locks */
		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
			;
	}
}
#else
#define enable_cpc()
#define invalidate_cpc()
#endif /* CONFIG_SYS_FSL_CPC */

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map
 * initialize a bunch of registers
 */

#ifdef CONFIG_FSL_CORENET
static void corenet_tb_init(void)
{
	volatile ccsr_rcpm_t *rcpm =
		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	volatile ccsr_pic_t *pic =
		(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
	u32 whoami = in_be32(&pic->whoami);

	/* Enable the timebase register for this core */
	out_be32(&rcpm->ctbenrl, (1 << whoami));
}
#endif

void cpu_init_f (void)
{
	extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
	struct law_entry law;
#endif
#ifdef CONFIG_MPC8548
	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	uint svr = get_svr();

	/*
	 * CPU2 errata workaround: A core hang possible while executing
	 * a msync instruction and a snoopable transaction from an I/O
	 * master tagged to make quick forward progress is present.
	 * Fixed in silicon rev 2.1.
	 */
	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
#endif

	disable_tlb(14);
	disable_tlb(15);

#if defined(CONFIG_SECURE_BOOT)
	/* Disable the LAW created for NOR flash by the PBI commands */
	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
	if (law.index != -1)
		disable_law(law.index);
#endif

#ifdef CONFIG_CPM2
	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif

       init_early_memctl_regs();

#if defined(CONFIG_CPM2)
	m8560_cpm_reset();
#endif
#ifdef CONFIG_QE
	/* Config QE ioports */
	config_qe_ioports();
#endif
#if defined(CONFIG_FSL_DMA)
	dma_init();
#endif
#ifdef CONFIG_FSL_CORENET
	corenet_tb_init();
#endif
	init_used_tlb_cams();

	/* Invalidate the CPC before DDR gets enabled */
	invalidate_cpc();

 #ifdef CONFIG_SYS_DCSRBAR_PHYS
	/* set DCSRCR so that DCSR space is 1G */
	setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
	in_be32(&gur->dcsrcr);
#endif

}

/* Implement a dummy function for those platforms w/o SERDES */
static void __fsl_serdes__init(void)
{
	return ;
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);

/*
 * Initialize L2 as cache.
 *
 * The newer 8548, etc, parts have twice as much cache, but
 * use the same bit-encoding as the older 8555, etc, parts.
 *
 */
int cpu_init_r(void)
{
	__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif

#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
	/*
	 * CPU22 and NMG_CPU_A011 share the same workaround.
	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
	 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
	 * be disabled by hwconfig with syntax:
	 *
	 * fsl_cpu_a011:disable
	 */
	extern int enable_cpu_a011_workaround;
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
	enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
#else
	char buffer[HWCONFIG_BUFFER_SIZE];
	char *buf = NULL;
	int n, res;

	n = getenv_f("hwconfig", buffer, sizeof(buffer));
	if (n > 0)
		buf = buffer;

	res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
	if (res > 0)
		enable_cpu_a011_workaround = 0;
	else {
		if (n >= HWCONFIG_BUFFER_SIZE) {
			printf("fsl_cpu_a011 was not found. hwconfig variable "
				"may be too long\n");
		}
		enable_cpu_a011_workaround =
			(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
			(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
	}
#endif
	if (enable_cpu_a011_workaround) {
		flush_dcache();
		mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
		sync();
	}
#endif

	puts ("L2:    ");

#if defined(CONFIG_L2_CACHE)
	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
	volatile uint cache_ctl;
	uint ver;
	u32 l2siz_field;

	ver = SVR_SOC_VER(svr);

	asm("msync;isync");
	cache_ctl = l2cache->l2ctl;

#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	if (cache_ctl & MPC85xx_L2CTL_L2E) {
		/* Clear L2 SRAM memory-mapped base address */
		out_be32(&l2cache->l2srbar0, 0x0);
		out_be32(&l2cache->l2srbar1, 0x0);

		/* set MBECCDIS=0, SBECCDIS=0 */
		clrbits_be32(&l2cache->l2errdis,
				(MPC85xx_L2ERRDIS_MBECC |
				 MPC85xx_L2ERRDIS_SBECC));

		/* set L2E=0, L2SRAM=0 */
		clrbits_be32(&l2cache->l2ctl,
				(MPC85xx_L2CTL_L2E |
				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
	}
#endif

	l2siz_field = (cache_ctl >> 28) & 0x3;

	switch (l2siz_field) {
	case 0x0:
		printf(" unknown size (0x%08x)\n", cache_ctl);
		return -1;
		break;
	case 0x1:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8555) {
			puts("128 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
			cache_ctl = 0xc4000000;
		} else {
			puts("256 KB ");
			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
		}
		break;
	case 0x2:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8555) {
			puts("256 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
			cache_ctl = 0xc8000000;
		} else {
			puts ("512 KB ");
			/* set L2E=1, L2I=1, & L2SRAM=0 */
			cache_ctl = 0xc0000000;
		}
		break;
	case 0x3:
		puts("1024 KB ");
		/* set L2E=1, L2I=1, & L2SRAM=0 */
		cache_ctl = 0xc0000000;
		break;
	}

	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
		puts("already enabled");
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
		u32 l2srbar = l2cache->l2srbar0;
		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
			l2cache->l2srbar0 = l2srbar;
			printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
		}
#endif /* CONFIG_SYS_INIT_L2_ADDR */
		puts("\n");
	} else {
		asm("msync;isync");
		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
		asm("msync;isync");
		puts("enabled\n");
	}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	if (SVR_SOC_VER(svr) == SVR_P2040) {
		puts("N/A\n");
		goto skip_l2;
	}

	u32 l2cfg0 = mfspr(SPRN_L2CFG0);

	/* invalidate the L2 cache */
	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
		;

#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	mtspr(SPRN_L2CSR1, (32 + 1));
#endif

	/* enable the cache */
	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);

	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
			;
		printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
	}

skip_l2:
#else
	puts("disabled\n");
#endif

	enable_cpc();

	/* needs to be in ram since code uses global static vars */
	fsl_serdes_init();

#ifdef CONFIG_SYS_SRIO
	srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
	srio_boot_master();
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
	srio_boot_master_release_slave();
#endif
#endif
#endif

#if defined(CONFIG_MP)
	setup_mp();
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
	{
		void *p;
		p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
		setbits_be32(p, 1 << (31 - 14));
	}
#endif

#ifdef CONFIG_SYS_LBC_LCRR
	/*
	 * Modify the CLKDIV field of LCRR register to improve the writing
	 * speed for NOR flash.
	 */
	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	__raw_readl(&lbc->lcrr);
	isync();
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
	udelay(100);
#endif
#endif

#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
	{
		ccsr_usb_phy_t *usb_phy1 =
			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
		out_be32(&usb_phy1->usb_enable_override,
				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
	}
#endif
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
	{
		ccsr_usb_phy_t *usb_phy2 =
			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
		out_be32(&usb_phy2->usb_enable_override,
				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
	}
#endif

#ifdef CONFIG_FMAN_ENET
	fman_enet_init();
#endif

#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
	/*
	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
	 * controller is configured in legacy mode instead of the
	 * expected enterprise mode. Software needs to clear bit[28]
	 * of HControl register to change to enterprise mode from
	 * legacy mode.  We assume that the controller is offline.
	 */
	if (IS_SVR_REV(svr, 1, 0) &&
	    ((SVR_SOC_VER(svr) == SVR_P1022) ||
	     (SVR_SOC_VER(svr) == SVR_P1013))) {
		fsl_sata_reg_t *reg;

		/* first SATA controller */
		reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);

		/* second SATA controller */
		reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
	}
#endif


	return 0;
}

extern void setup_ivors(void);

void arch_preboot_os(void)
{
	u32 msr;

	/*
	 * We are changing interrupt offsets and are about to boot the OS so
	 * we need to make sure we disable all async interrupts. EE is already
	 * disabled by the time we get called.
	 */
	msr = mfmsr();
	msr &= ~(MSR_ME|MSR_CE);
	mtmsr(msr);

	setup_ivors();
}

#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
int sata_initialize(void)
{
	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
		return __sata_initialize();

	return 1;
}
#endif

void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
	int ret;
	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;

	/* load QE firmware from NAND flash to DDR first */
	ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
			&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);

	if (ret && ret == -EUCLEAN) {
		printf ("NAND read for QE firmware at offset %x failed %d\n",
				CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
	}
#endif
	qe_init(qe_base);
	qe_reset();
#endif
}
Commit	Line	Data
42d1f039	1	/*
a09b9b68	2	* Copyright 2007-2011 Freescale Semiconductor, Inc.
29372ff3	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Modified by Xianghua Xiao, X.Xiao@motorola.com
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <asm/processor.h>
	32	#include <ioports.h>
f54fe87a	33	#include <sata.h>
c916d7c9	34	#include <fm_eth.h>
42d1f039	35	#include <asm/io.h>
fd3c9bef	36	#include <asm/cache.h>
87163180	37	#include <asm/mmu.h>
83d40dfd	38	#include <asm/fsl_law.h>
f54fe87a	39	#include <asm/fsl_serdes.h>
5ffa88ec	40	#include <asm/fsl_srio.h>
57125f22	41	#include <hwconfig.h>
fbc20aab	42	#include <linux/compiler.h>
ec2b74ff	43	#include "mp.h"
f2717b47	44	#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
a7b1e1b7 HW	45	#include <nand.h>
	46	#include <errno.h>
	47	#endif
42d1f039	48
fbc20aab TT	49	#include "../../../../drivers/block/fsl_sata.h"
fbc20aab TT	50
57125f22 YS	51	#define HWCONFIG_BUFFER_SIZE 128
57125f22 YS	52
d87080b7 WD	53	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	54
da9d4610 AF	55	#ifdef CONFIG_QE
	56	extern qe_iop_conf_t qe_iop_conf_tab[];
	57	extern void qe_config_iopin(u8 port, u8 pin, int dir,
	58	int open_drain, int assign);
	59	extern void qe_init(uint qe_base);
	60	extern void qe_reset(void);
	61
	62	static void config_qe_ioports(void)
	63	{
	64	u8 port, pin;
	65	int dir, open_drain, assign;
	66	int i;
	67
	68	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	69	port = qe_iop_conf_tab[i].port;
	70	pin = qe_iop_conf_tab[i].pin;
	71	dir = qe_iop_conf_tab[i].dir;
	72	open_drain = qe_iop_conf_tab[i].open_drain;
	73	assign = qe_iop_conf_tab[i].assign;
	74	qe_config_iopin(port, pin, dir, open_drain, assign);
	75	}
	76	}
	77	#endif
40d5fa35	78
9c4c5ae3	79	#ifdef CONFIG_CPM2
aafeefbd	80	void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039 WD	81	{
	82	int portnum;
	83
	84	for (portnum = 0; portnum < 4; portnum++) {
	85	uint pmsk = 0,
	86	ppar = 0,
	87	psor = 0,
	88	pdir = 0,
	89	podr = 0,
	90	pdat = 0;
	91	iop_conf_t iopc = (iop_conf_t ) & iop_conf_tab[portnum][0];
	92	iop_conf_t *eiopc = iopc + 32;
	93	uint msk = 1;
	94
	95	/*
	96	* NOTE:
	97	* index 0 refers to pin 31,
	98	* index 31 refers to pin 0
	99	*/
	100	while (iopc < eiopc) {
	101	if (iopc->conf) {
	102	pmsk \|= msk;
	103	if (iopc->ppar)
	104	ppar \|= msk;
	105	if (iopc->psor)
	106	psor \|= msk;
	107	if (iopc->pdir)
	108	pdir \|= msk;
	109	if (iopc->podr)
	110	podr \|= msk;
	111	if (iopc->pdat)
	112	pdat \|= msk;
	113	}
	114
	115	msk <<= 1;
	116	iopc++;
	117	}
	118
	119	if (pmsk != 0) {
aafeefbd	120	volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039 WD	121	uint tpmsk = ~pmsk;
	122
	123	/*
	124	* the (somewhat confused) paragraph at the
	125	* bottom of page 35-5 warns that there might
	126	* be "unknown behaviour" when programming
	127	* PSORx and PDIRx, if PPARx = 1, so I
	128	* decided this meant I had to disable the
	129	* dedicated function first, and enable it
	130	* last.
	131	*/
	132	iop->ppar &= tpmsk;
	133	iop->psor = (iop->psor & tpmsk) \| psor;
	134	iop->podr = (iop->podr & tpmsk) \| podr;
	135	iop->pdat = (iop->pdat & tpmsk) \| pdat;
	136	iop->pdir = (iop->pdir & tpmsk) \| pdir;
	137	iop->ppar \|= ppar;
	138	}
	139	}
	140	}
	141	#endif
	142
6aba33e9 KG	143	#ifdef CONFIG_SYS_FSL_CPC
	144	static void enable_cpc(void)
	145	{
	146	int i;
	147	u32 size = 0;
	148
	149	cpc_corenet_t cpc = (cpc_corenet_t )CONFIG_SYS_FSL_CPC_ADDR;
	150
	151	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
	152	u32 cpccfg0 = in_be32(&cpc->cpccfg0);
	153	size += CPC_CFG0_SZ_K(cpccfg0);
2a9fab82 SX	154	#ifdef CONFIG_RAMBOOT_PBL
	155	if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
	156	/* find and disable LAW of SRAM */
	157	struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
	158
	159	if (law.index == -1) {
	160	printf("\nFatal error happened\n");
	161	return;
	162	}
	163	disable_law(law.index);
	164
	165	clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
	166	out_be32(&cpc->cpccsr0, 0);
	167	out_be32(&cpc->cpcsrcr0, 0);
	168	}
	169	#endif
6aba33e9	170
1d2c2a62 KG	171	#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
	172	setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
	173	#endif
868da593 KG	174	#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
	175	setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
	176	#endif
1d2c2a62	177
6aba33e9 KG	178	out_be32(&cpc->cpccsr0, CPC_CSR0_CE \| CPC_CSR0_PE);
	179	/* Read back to sync write */
	180	in_be32(&cpc->cpccsr0);
	181
	182	}
	183
	184	printf("Corenet Platform Cache: %d KB enabled\n", size);
	185	}
	186
	187	void invalidate_cpc(void)
	188	{
	189	int i;
	190	cpc_corenet_t cpc = (cpc_corenet_t )CONFIG_SYS_FSL_CPC_ADDR;
	191
	192	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
2a9fab82 SX	193	/* skip CPC when it used as all SRAM */
	194	if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
	195	continue;
6aba33e9 KG	196	/* Flash invalidate the CPC and clear all the locks */
	197	out_be32(&cpc->cpccsr0, CPC_CSR0_FI \| CPC_CSR0_LFC);
	198	while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI \| CPC_CSR0_LFC))
	199	;
	200	}
	201	}
	202	#else
	203	#define enable_cpc()
	204	#define invalidate_cpc()
	205	#endif /* CONFIG_SYS_FSL_CPC */
	206
42d1f039 WD	207	/*
	208	* Breathe some life into the CPU...
	209	*
	210	* Set up the memory map
	211	* initialize a bunch of registers
	212	*/
	213
3c2a67ee KG	214	#ifdef CONFIG_FSL_CORENET
	215	static void corenet_tb_init(void)
	216	{
	217	volatile ccsr_rcpm_t *rcpm =
	218	(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	219	volatile ccsr_pic_t *pic =
680c613a	220	(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
3c2a67ee KG	221	u32 whoami = in_be32(&pic->whoami);
	222
	223	/* Enable the timebase register for this core */
	224	out_be32(&rcpm->ctbenrl, (1 << whoami));
	225	}
	226	#endif
	227
42d1f039 WD	228	void cpu_init_f (void)
42d1f039 WD	229	{
42d1f039	230	extern void m8560_cpm_reset (void);
f110fe94 SG	231	#ifdef CONFIG_SYS_DCSRBAR_PHYS
	232	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	233	#endif
7065b7d4 RG	234	#if defined(CONFIG_SECURE_BOOT)
	235	struct law_entry law;
	236	#endif
a2cd50ed PT	237	#ifdef CONFIG_MPC8548
	238	ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	239	uint svr = get_svr();
	240
	241	/*
	242	* CPU2 errata workaround: A core hang possible while executing
	243	* a msync instruction and a snoopable transaction from an I/O
	244	* master tagged to make quick forward progress is present.
	245	* Fixed in silicon rev 2.1.
	246	*/
	247	if ((SVR_MAJ(svr) == 1) \|\| ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
	248	out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) \| (1 << 16));
	249	#endif
42d1f039	250
87163180 KG	251	disable_tlb(14);
	252	disable_tlb(15);
	253
7065b7d4 RG	254	#if defined(CONFIG_SECURE_BOOT)
	255	/* Disable the LAW created for NOR flash by the PBI commands */
	256	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
	257	if (law.index != -1)
	258	disable_law(law.index);
	259	#endif
	260
9c4c5ae3	261	#ifdef CONFIG_CPM2
6d0f6bcf	262	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039 WD	263	#endif
42d1f039 WD	264
f51cdaf1	265	init_early_memctl_regs();
42d1f039	266
9c4c5ae3	267	#if defined(CONFIG_CPM2)
42d1f039 WD	268	m8560_cpm_reset();
42d1f039 WD	269	#endif
da9d4610 AF	270	#ifdef CONFIG_QE
	271	/* Config QE ioports */
	272	config_qe_ioports();
	273	#endif
79f4333c PT	274	#if defined(CONFIG_FSL_DMA)
	275	dma_init();
	276	#endif
3c2a67ee KG	277	#ifdef CONFIG_FSL_CORENET
	278	corenet_tb_init();
	279	#endif
94e9411b	280	init_used_tlb_cams();
6aba33e9 KG	281
	282	/* Invalidate the CPC before DDR gets enabled */
	283	invalidate_cpc();
f110fe94 SG	284
	285	#ifdef CONFIG_SYS_DCSRBAR_PHYS
	286	/* set DCSRCR so that DCSR space is 1G */
	287	setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
	288	in_be32(&gur->dcsrcr);
	289	#endif
	290
42d1f039 WD	291	}
42d1f039 WD	292
35079aa9 KG	293	/* Implement a dummy function for those platforms w/o SERDES */
	294	static void __fsl_serdes__init(void)
	295	{
	296	return ;
	297	}
	298	__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
d9b94f28	299
42d1f039	300	/*
d9b94f28 JL	301	* Initialize L2 as cache.
	302	*
	303	* The newer 8548, etc, parts have twice as much cache, but
	304	* use the same bit-encoding as the older 8555, etc, parts.
	305	*
42d1f039	306	*/
d9b94f28	307	int cpu_init_r(void)
42d1f039	308	{
fbc20aab	309	__maybe_unused u32 svr = get_svr();
3f0202ed	310	#ifdef CONFIG_SYS_LBC_LCRR
f51cdaf1	311	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
3f0202ed LC	312	#endif
3f0202ed LC	313
5e23ab0a YS	314	#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) \|\| \
	315	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
	316	/*
57125f22	317	* CPU22 and NMG_CPU_A011 share the same workaround.
5e23ab0a YS	318	* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
5e23ab0a YS	319	* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
57125f22 YS	320	* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
	321	* fixed in 2.0. NMG_CPU_A011 is activated by default and can
	322	* be disabled by hwconfig with syntax:
	323	*
	324	* fsl_cpu_a011:disable
5e23ab0a	325	*/
57125f22 YS	326	extern int enable_cpu_a011_workaround;
	327	#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
	328	enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
	329	#else
	330	char buffer[HWCONFIG_BUFFER_SIZE];
	331	char *buf = NULL;
	332	int n, res;
	333
	334	n = getenv_f("hwconfig", buffer, sizeof(buffer));
	335	if (n > 0)
	336	buf = buffer;
	337
	338	res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
	339	if (res > 0)
	340	enable_cpu_a011_workaround = 0;
	341	else {
	342	if (n >= HWCONFIG_BUFFER_SIZE) {
	343	printf("fsl_cpu_a011 was not found. hwconfig variable "
	344	"may be too long\n");
	345	}
	346	enable_cpu_a011_workaround =
	347	(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) \|\|
	348	(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
	349	}
	350	#endif
	351	if (enable_cpu_a011_workaround) {
1e9ea85f YS	352	flush_dcache();
	353	mtspr(L1CSR2, (mfspr(L1CSR2) \| L1CSR2_DCWS));
	354	sync();
	355	}
fd3c9bef KG	356	#endif
fd3c9bef KG	357
6beecfbb WG	358	puts ("L2: ");
6beecfbb WG	359
42d1f039	360	#if defined(CONFIG_L2_CACHE)
6d0f6bcf	361	volatile ccsr_l2cache_t l2cache = (void )CONFIG_SYS_MPC85xx_L2_ADDR;
d9b94f28	362	volatile uint cache_ctl;
fbc20aab	363	uint ver;
73f15a06	364	u32 l2siz_field;
d9b94f28	365
f3e04bdc	366	ver = SVR_SOC_VER(svr);
42d1f039	367
d65cfe89	368	asm("msync;isync");
d9b94f28	369	cache_ctl = l2cache->l2ctl;
7da53351 MH	370
	371	#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	372	if (cache_ctl & MPC85xx_L2CTL_L2E) {
	373	/* Clear L2 SRAM memory-mapped base address */
	374	out_be32(&l2cache->l2srbar0, 0x0);
	375	out_be32(&l2cache->l2srbar1, 0x0);
	376
	377	/* set MBECCDIS=0, SBECCDIS=0 */
	378	clrbits_be32(&l2cache->l2errdis,
	379	(MPC85xx_L2ERRDIS_MBECC \|
	380	MPC85xx_L2ERRDIS_SBECC));
	381
	382	/* set L2E=0, L2SRAM=0 */
	383	clrbits_be32(&l2cache->l2ctl,
	384	(MPC85xx_L2CTL_L2E \|
	385	MPC85xx_L2CTL_L2SRAM_ENTIRE));
	386	}
	387	#endif
	388
73f15a06	389	l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28	390
73f15a06 KG	391	switch (l2siz_field) {
	392	case 0x0:
	393	printf(" unknown size (0x%08x)\n", cache_ctl);
	394	return -1;
	395	break;
	396	case 0x1:
	397	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
48f6a5c3	398	ver == SVR_8541 \|\| ver == SVR_8555) {
73f15a06 KG	399	puts("128 KB ");
	400	/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
	401	cache_ctl = 0xc4000000;
d9b94f28	402	} else {
73f15a06 KG	403	puts("256 KB ");
	404	cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
	405	}
	406	break;
	407	case 0x2:
	408	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
48f6a5c3	409	ver == SVR_8541 \|\| ver == SVR_8555) {
6beecfbb	410	puts("256 KB ");
29372ff3 ES	411	/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
29372ff3 ES	412	cache_ctl = 0xc8000000;
73f15a06 KG	413	} else {
	414	puts ("512 KB ");
	415	/* set L2E=1, L2I=1, & L2SRAM=0 */
	416	cache_ctl = 0xc0000000;
d9b94f28	417	}
d65cfe89	418	break;
73f15a06 KG	419	case 0x3:
	420	puts("1024 KB ");
	421	/* set L2E=1, L2I=1, & L2SRAM=0 */
	422	cache_ctl = 0xc0000000;
29372ff3	423	break;
d65cfe89 JL	424	}
d65cfe89 JL	425
76b474e2	426	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb	427	puts("already enabled");
888279b5	428	#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
e4c9a35d	429	u32 l2srbar = l2cache->l2srbar0;
76b474e2 MH	430	if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
76b474e2 MH	431	&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf	432	l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3	433	l2cache->l2srbar0 = l2srbar;
6d0f6bcf	434	printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3	435	}
6d0f6bcf	436	#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3 ES	437	puts("\n");
	438	} else {
	439	asm("msync;isync");
	440	l2cache->l2ctl = cache_ctl; /* invalidate & enable */
	441	asm("msync;isync");
6beecfbb	442	puts("enabled\n");
29372ff3	443	}
1b3e4044	444	#elif defined(CONFIG_BACKSIDE_L2_CACHE)
48f6a5c3	445	if (SVR_SOC_VER(svr) == SVR_P2040) {
acf3f8da KG	446	puts("N/A\n");
	447	goto skip_l2;
	448	}
	449
1b3e4044 KG	450	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
	451
	452	/* invalidate the L2 cache */
25bacf7a KG	453	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI\|L2CSR0_L2LFC));
25bacf7a KG	454	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI\|L2CSR0_L2LFC))
1b3e4044 KG	455	;
1b3e4044 KG	456
82fd1f8d KG	457	#ifdef CONFIG_SYS_CACHE_STASHING
	458	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	459	mtspr(SPRN_L2CSR1, (32 + 1));
	460	#endif
	461
1b3e4044 KG	462	/* enable the cache */
	463	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
	464
654ea1f3 DL	465	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
	466	while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
	467	;
1b3e4044	468	printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
654ea1f3	469	}
acf3f8da KG	470
acf3f8da KG	471	skip_l2:
42d1f039	472	#else
6beecfbb	473	puts("disabled\n");
42d1f039	474	#endif
6aba33e9 KG	475
	476	enable_cpc();
	477
af025065 KG	478	/* needs to be in ram since code uses global static vars */
af025065 KG	479	fsl_serdes_init();
af025065	480
a09b9b68 KG	481	#ifdef CONFIG_SYS_SRIO
a09b9b68 KG	482	srio_init();
5ffa88ec LG	483	#ifdef CONFIG_SRIOBOOT_MASTER
5ffa88ec LG	484	srio_boot_master();
5056c8e0 LG	485	#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
	486	srio_boot_master_release_slave();
	487	#endif
5ffa88ec	488	#endif
a09b9b68 KG	489	#endif
a09b9b68 KG	490
ec2b74ff KG	491	#if defined(CONFIG_MP)
	492	setup_mp();
	493	#endif
3f0202ed	494
ae026ffd RZ	495	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
	496	{
	497	void *p;
	498	p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
	499	setbits_be32(p, 1 << (31 - 14));
	500	}
	501	#endif
	502
3f0202ed LC	503	#ifdef CONFIG_SYS_LBC_LCRR
	504	/*
	505	* Modify the CLKDIV field of LCRR register to improve the writing
	506	* speed for NOR flash.
	507	*/
	508	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	509	__raw_readl(&lbc->lcrr);
	510	isync();
2b3a1cdd KG	511	#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
	512	udelay(100);
	513	#endif
3f0202ed LC	514	#endif
3f0202ed LC	515
86221f09 RZ	516	#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
	517	{
	518	ccsr_usb_phy_t *usb_phy1 =
	519	(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
	520	out_be32(&usb_phy1->usb_enable_override,
	521	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
	522	}
	523	#endif
	524	#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
	525	{
	526	ccsr_usb_phy_t *usb_phy2 =
	527	(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
	528	out_be32(&usb_phy2->usb_enable_override,
	529	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
	530	}
	531	#endif
	532
c916d7c9 KG	533	#ifdef CONFIG_FMAN_ENET
	534	fman_enet_init();
	535	#endif
	536
fbc20aab TT	537	#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
	538	/*
	539	* For P1022/1013 Rev1.0 silicon, after power on SATA host
	540	* controller is configured in legacy mode instead of the
	541	* expected enterprise mode. Software needs to clear bit[28]
	542	* of HControl register to change to enterprise mode from
	543	* legacy mode. We assume that the controller is offline.
	544	*/
	545	if (IS_SVR_REV(svr, 1, 0) &&
	546	((SVR_SOC_VER(svr) == SVR_P1022) \|\|
48f6a5c3	547	(SVR_SOC_VER(svr) == SVR_P1013))) {
fbc20aab TT	548	fsl_sata_reg_t *reg;
	549
	550	/* first SATA controller */
	551	reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
	552	clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
	553
	554	/* second SATA controller */
	555	reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
	556	clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
	557	}
	558	#endif
	559
	560
42d1f039 WD	561	return 0;
42d1f039 WD	562	}
26f4cdba KG	563
	564	extern void setup_ivors(void);
	565
	566	void arch_preboot_os(void)
	567	{
15fba327 KG	568	u32 msr;
	569
	570	/*
	571	* We are changing interrupt offsets and are about to boot the OS so
	572	* we need to make sure we disable all async interrupts. EE is already
	573	* disabled by the time we get called.
	574	*/
	575	msr = mfmsr();
5344f7a2	576	msr &= ~(MSR_ME\|MSR_CE);
15fba327 KG	577	mtmsr(msr);
15fba327 KG	578
26f4cdba KG	579	setup_ivors();
26f4cdba KG	580	}
f54fe87a KG	581
	582	#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
	583	int sata_initialize(void)
	584	{
	585	if (is_serdes_configured(SATA1) \|\| is_serdes_configured(SATA2))
	586	return __sata_initialize();
	587
	588	return 1;
	589	}
	590	#endif
f9a33f1c KG	591
	592	void cpu_secondary_init_r(void)
	593	{
	594	#ifdef CONFIG_QE
	595	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
f2717b47	596	#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
a7b1e1b7	597	int ret;
f2717b47	598	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
a7b1e1b7 HW	599
a7b1e1b7 HW	600	/* load QE firmware from NAND flash to DDR first */
f2717b47 TT	601	ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
f2717b47 TT	602	&fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
a7b1e1b7 HW	603
	604	if (ret && ret == -EUCLEAN) {
	605	printf ("NAND read for QE firmware at offset %x failed %d\n",
f2717b47	606	CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
a7b1e1b7 HW	607	}
a7b1e1b7 HW	608	#endif
f9a33f1c KG	609	qe_init(qe_base);
	610	qe_reset();
	611	#endif
	612	}