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powerpc/mpc8xxx: Add memory reset control
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c
CommitLineData
42d1f039 1/*
a09b9b68 2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
29372ff3 3 *
42d1f039
WD		 4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
42d1f039
WD		 11 */
12
13#include <common.h>
14#include <watchdog.h>
15#include <asm/processor.h>
16#include <ioports.h>
f54fe87a 17#include <sata.h>
c916d7c9 18#include <fm_eth.h>
42d1f039 19#include <asm/io.h>
fd3c9bef 20#include <asm/cache.h>
87163180 21#include <asm/mmu.h>
83d40dfd 22#include <asm/fsl_law.h>
f54fe87a 23#include <asm/fsl_serdes.h>
5ffa88ec 24#include <asm/fsl_srio.h>
57125f22 25#include <hwconfig.h>
fbc20aab 26#include <linux/compiler.h>
ec2b74ff 27#include "mp.h"
f2717b47 28#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
a7b1e1b7
HW		 29#include <nand.h>
30#include <errno.h>
31#endif
42d1f039 32
fbc20aab
TT		 33#include "../../../../drivers/block/fsl_sata.h"
34
d87080b7
WD		 35DECLARE_GLOBAL_DATA_PTR;
36
da9d4610
AF		 37#ifdef CONFIG_QE
38extern qe_iop_conf_t qe_iop_conf_tab[];
39extern void qe_config_iopin(u8 port, u8 pin, int dir,
40 int open_drain, int assign);
41extern void qe_init(uint qe_base);
42extern void qe_reset(void);
43
44static void config_qe_ioports(void)
45{
46 u8 port, pin;
47 int dir, open_drain, assign;
48 int i;
49
50 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
51 port = qe_iop_conf_tab[i].port;
52 pin = qe_iop_conf_tab[i].pin;
53 dir = qe_iop_conf_tab[i].dir;
54 open_drain = qe_iop_conf_tab[i].open_drain;
55 assign = qe_iop_conf_tab[i].assign;
56 qe_config_iopin(port, pin, dir, open_drain, assign);
57 }
58}
59#endif
40d5fa35 60
9c4c5ae3 61#ifdef CONFIG_CPM2
aafeefbd 62void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039
WD		 63{
64 int portnum;
65
66 for (portnum = 0; portnum < 4; portnum++) {
67 uint pmsk = 0,
68 ppar = 0,
69 psor = 0,
70 pdir = 0,
71 podr = 0,
72 pdat = 0;
73 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
74 iop_conf_t *eiopc = iopc + 32;
75 uint msk = 1;
76
77 /*
78 * NOTE:
79 * index 0 refers to pin 31,
80 * index 31 refers to pin 0
81 */
82 while (iopc < eiopc) {
83 if (iopc->conf) {
84 pmsk |= msk;
85 if (iopc->ppar)
86 ppar |= msk;
87 if (iopc->psor)
88 psor |= msk;
89 if (iopc->pdir)
90 pdir |= msk;
91 if (iopc->podr)
92 podr |= msk;
93 if (iopc->pdat)
94 pdat |= msk;
95 }
96
97 msk <<= 1;
98 iopc++;
99 }
100
101 if (pmsk != 0) {
aafeefbd 102 volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039
WD		 103 uint tpmsk = ~pmsk;
104
105 /*
106 * the (somewhat confused) paragraph at the
107 * bottom of page 35-5 warns that there might
108 * be "unknown behaviour" when programming
109 * PSORx and PDIRx, if PPARx = 1, so I
110 * decided this meant I had to disable the
111 * dedicated function first, and enable it
112 * last.
113 */
114 iop->ppar &= tpmsk;
115 iop->psor = (iop->psor & tpmsk) | psor;
116 iop->podr = (iop->podr & tpmsk) | podr;
117 iop->pdat = (iop->pdat & tpmsk) | pdat;
118 iop->pdir = (iop->pdir & tpmsk) | pdir;
119 iop->ppar |= ppar;
120 }
121 }
122}
123#endif
124
6aba33e9
KG		 125#ifdef CONFIG_SYS_FSL_CPC
126static void enable_cpc(void)
127{
128 int i;
129 u32 size = 0;
130
131 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
132
133 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
134 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
135 size += CPC_CFG0_SZ_K(cpccfg0);
2a9fab82
SX		 136#ifdef CONFIG_RAMBOOT_PBL
137 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
138 /* find and disable LAW of SRAM */
139 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
140
141 if (law.index == -1) {
142 printf("\nFatal error happened\n");
143 return;
144 }
145 disable_law(law.index);
146
147 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
148 out_be32(&cpc->cpccsr0, 0);
149 out_be32(&cpc->cpcsrcr0, 0);
150 }
151#endif
6aba33e9 152
1d2c2a62
KG		 153#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
154 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
155#endif
868da593
KG		 156#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
157 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
158#endif
82125192
SW		 159#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
160 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
161#endif
1d2c2a62 162
6aba33e9
KG		 163 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
164 /* Read back to sync write */
165 in_be32(&cpc->cpccsr0);
166
167 }
168
169 printf("Corenet Platform Cache: %d KB enabled\n", size);
170}
171
e56143e5 172static void invalidate_cpc(void)
6aba33e9
KG		 173{
174 int i;
175 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
176
177 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
2a9fab82
SX		 178 /* skip CPC when it used as all SRAM */
179 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
180 continue;
6aba33e9
KG		 181 /* Flash invalidate the CPC and clear all the locks */
182 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
183 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
184 ;
185 }
186}
187#else
188#define enable_cpc()
189#define invalidate_cpc()
190#endif /* CONFIG_SYS_FSL_CPC */
191
42d1f039
WD		 192/*
193 * Breathe some life into the CPU...
194 *
195 * Set up the memory map
196 * initialize a bunch of registers
197 */
198
3c2a67ee
KG		 199#ifdef CONFIG_FSL_CORENET
200static void corenet_tb_init(void)
201{
202 volatile ccsr_rcpm_t *rcpm =
203 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
204 volatile ccsr_pic_t *pic =
680c613a 205 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
3c2a67ee
KG		 206 u32 whoami = in_be32(&pic->whoami);
207
208 /* Enable the timebase register for this core */
209 out_be32(&rcpm->ctbenrl, (1 << whoami));
210}
211#endif
212
42d1f039
WD		 213void cpu_init_f (void)
214{
42d1f039 215 extern void m8560_cpm_reset (void);
f110fe94
SG		 216#ifdef CONFIG_SYS_DCSRBAR_PHYS
217 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
218#endif
7065b7d4
RG		 219#if defined(CONFIG_SECURE_BOOT)
220 struct law_entry law;
221#endif
a2cd50ed
PT		 222#ifdef CONFIG_MPC8548
223 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
224 uint svr = get_svr();
225
226 /*
227 * CPU2 errata workaround: A core hang possible while executing
228 * a msync instruction and a snoopable transaction from an I/O
229 * master tagged to make quick forward progress is present.
230 * Fixed in silicon rev 2.1.
231 */
232 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
233 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
234#endif
42d1f039 235
87163180
KG		 236 disable_tlb(14);
237 disable_tlb(15);
238
7065b7d4
RG		 239#if defined(CONFIG_SECURE_BOOT)
240 /* Disable the LAW created for NOR flash by the PBI commands */
241 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
242 if (law.index != -1)
243 disable_law(law.index);
244#endif
245
9c4c5ae3 246#ifdef CONFIG_CPM2
6d0f6bcf 247 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039
WD		 248#endif
249
f51cdaf1 250 init_early_memctl_regs();
42d1f039 251
9c4c5ae3 252#if defined(CONFIG_CPM2)
42d1f039
WD		 253 m8560_cpm_reset();
254#endif
da9d4610
AF		 255#ifdef CONFIG_QE
256 /* Config QE ioports */
257 config_qe_ioports();
258#endif
79f4333c
PT		 259#if defined(CONFIG_FSL_DMA)
260 dma_init();
261#endif
3c2a67ee
KG		 262#ifdef CONFIG_FSL_CORENET
263 corenet_tb_init();
264#endif
94e9411b 265 init_used_tlb_cams();
6aba33e9
KG		 266
267 /* Invalidate the CPC before DDR gets enabled */
268 invalidate_cpc();
f110fe94
SG		 269
270 #ifdef CONFIG_SYS_DCSRBAR_PHYS
271 /* set DCSRCR so that DCSR space is 1G */
272 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
273 in_be32(&gur->dcsrcr);
274#endif
275
42d1f039
WD		 276}
277
35079aa9
KG		 278/* Implement a dummy function for those platforms w/o SERDES */
279static void __fsl_serdes__init(void)
280{
281 return ;
282}
283__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
d9b94f28 284
6d2b9da1
YS		 285#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
286int enable_cluster_l2(void)
287{
288 int i = 0;
289 u32 cluster;
290 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
291 struct ccsr_cluster_l2 __iomem *l2cache;
292
293 cluster = in_be32(&gur->tp_cluster[i].lower);
294 if (cluster & TP_CLUSTER_EOC)
295 return 0;
296
297 /* The first cache has already been set up, so skip it */
298 i++;
299
300 /* Look through the remaining clusters, and set up their caches */
301 do {
db9a8070
PK		 302 int j, cluster_valid = 0;
303
6d2b9da1 304 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
db9a8070 305
6d2b9da1
YS		 306 cluster = in_be32(&gur->tp_cluster[i].lower);
307
db9a8070
PK		 308 /* check that at least one core/accel is enabled in cluster */
309 for (j = 0; j < 4; j++) {
310 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
311 u32 type = in_be32(&gur->tp_ityp[idx]);
6d2b9da1 312
db9a8070
PK		 313 if (type & TP_ITYP_AV)
314 cluster_valid = 1;
315 }
6d2b9da1 316
db9a8070
PK		 317 if (cluster_valid) {
318 /* set stash ID to (cluster) * 2 + 32 + 1 */
319 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
320
321 printf("enable l2 for cluster %d %p\n", i, l2cache);
322
323 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
324 while ((in_be32(&l2cache->l2csr0)
325 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
326 ;
9cd95ac7 327 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
db9a8070 328 }
6d2b9da1
YS		 329 i++;
330 } while (!(cluster & TP_CLUSTER_EOC));
331
332 return 0;
333}
334#endif
335
42d1f039 336/*
d9b94f28
JL		 337 * Initialize L2 as cache.
338 *
339 * The newer 8548, etc, parts have twice as much cache, but
340 * use the same bit-encoding as the older 8555, etc, parts.
341 *
42d1f039 342 */
d9b94f28 343int cpu_init_r(void)
42d1f039 344{
fbc20aab 345 __maybe_unused u32 svr = get_svr();
3f0202ed 346#ifdef CONFIG_SYS_LBC_LCRR
6d2b9da1
YS		 347 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
348#endif
349#ifdef CONFIG_L2_CACHE
350 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
351#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
352 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
3f0202ed 353#endif
afbfdf54 354#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
2a5fcb83
YS		 355 extern int spin_table_compat;
356 const char *spin;
357#endif
3f0202ed 358
5e23ab0a
YS		 359#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
360 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
361 /*
57125f22 362 * CPU22 and NMG_CPU_A011 share the same workaround.
5e23ab0a
YS		 363 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
364 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
57125f22
YS		 365 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
366 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
367 * be disabled by hwconfig with syntax:
368 *
369 * fsl_cpu_a011:disable
5e23ab0a 370 */
57125f22
YS		 371 extern int enable_cpu_a011_workaround;
372#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
373 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
374#else
375 char buffer[HWCONFIG_BUFFER_SIZE];
376 char *buf = NULL;
377 int n, res;
378
379 n = getenv_f("hwconfig", buffer, sizeof(buffer));
380 if (n > 0)
381 buf = buffer;
382
383 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
384 if (res > 0)
385 enable_cpu_a011_workaround = 0;
386 else {
387 if (n >= HWCONFIG_BUFFER_SIZE) {
388 printf("fsl_cpu_a011 was not found. hwconfig variable "
389 "may be too long\n");
390 }
391 enable_cpu_a011_workaround =
392 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
393 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
394 }
395#endif
396 if (enable_cpu_a011_workaround) {
1e9ea85f
YS		 397 flush_dcache();
398 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
399 sync();
400 }
fd3c9bef
KG		 401#endif
402
afbfdf54 403#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
2a5fcb83
YS		 404 spin = getenv("spin_table_compat");
405 if (spin && (*spin == 'n'))
406 spin_table_compat = 0;
407 else
408 spin_table_compat = 1;
409#endif
410
6beecfbb
WG		 411 puts ("L2: ");
412
42d1f039 413#if defined(CONFIG_L2_CACHE)
d9b94f28 414 volatile uint cache_ctl;
fbc20aab 415 uint ver;
73f15a06 416 u32 l2siz_field;
d9b94f28 417
f3e04bdc 418 ver = SVR_SOC_VER(svr);
42d1f039 419
d65cfe89 420 asm("msync;isync");
d9b94f28 421 cache_ctl = l2cache->l2ctl;
7da53351
MH		 422
423#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
424 if (cache_ctl & MPC85xx_L2CTL_L2E) {
425 /* Clear L2 SRAM memory-mapped base address */
426 out_be32(&l2cache->l2srbar0, 0x0);
427 out_be32(&l2cache->l2srbar1, 0x0);
428
429 /* set MBECCDIS=0, SBECCDIS=0 */
430 clrbits_be32(&l2cache->l2errdis,
431 (MPC85xx_L2ERRDIS_MBECC |
432 MPC85xx_L2ERRDIS_SBECC));
433
434 /* set L2E=0, L2SRAM=0 */
435 clrbits_be32(&l2cache->l2ctl,
436 (MPC85xx_L2CTL_L2E |
437 MPC85xx_L2CTL_L2SRAM_ENTIRE));
438 }
439#endif
440
73f15a06 441 l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28 442
73f15a06
KG		 443 switch (l2siz_field) {
444 case 0x0:
445 printf(" unknown size (0x%08x)\n", cache_ctl);
446 return -1;
447 break;
448 case 0x1:
449 if (ver == SVR_8540 || ver == SVR_8560 ||
48f6a5c3 450 ver == SVR_8541 || ver == SVR_8555) {
73f15a06
KG		 451 puts("128 KB ");
452 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
453 cache_ctl = 0xc4000000;
d9b94f28 454 } else {
73f15a06
KG		 455 puts("256 KB ");
456 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
457 }
458 break;
459 case 0x2:
460 if (ver == SVR_8540 || ver == SVR_8560 ||
48f6a5c3 461 ver == SVR_8541 || ver == SVR_8555) {
6beecfbb 462 puts("256 KB ");
29372ff3
ES		 463 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
464 cache_ctl = 0xc8000000;
73f15a06
KG		 465 } else {
466 puts ("512 KB ");
467 /* set L2E=1, L2I=1, & L2SRAM=0 */
468 cache_ctl = 0xc0000000;
d9b94f28 469 }
d65cfe89 470 break;
73f15a06
KG		 471 case 0x3:
472 puts("1024 KB ");
473 /* set L2E=1, L2I=1, & L2SRAM=0 */
474 cache_ctl = 0xc0000000;
29372ff3 475 break;
d65cfe89
JL		 476 }
477
76b474e2 478 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb 479 puts("already enabled");
888279b5 480#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
e4c9a35d 481 u32 l2srbar = l2cache->l2srbar0;
76b474e2
MH		 482 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
483 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf 484 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3 485 l2cache->l2srbar0 = l2srbar;
9a511bd6 486 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3 487 }
6d0f6bcf 488#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3
ES		 489 puts("\n");
490 } else {
491 asm("msync;isync");
492 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
493 asm("msync;isync");
6beecfbb 494 puts("enabled\n");
29372ff3 495 }
1b3e4044 496#elif defined(CONFIG_BACKSIDE_L2_CACHE)
48f6a5c3 497 if (SVR_SOC_VER(svr) == SVR_P2040) {
acf3f8da
KG		 498 puts("N/A\n");
499 goto skip_l2;
500 }
501
1b3e4044
KG		 502 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
503
504 /* invalidate the L2 cache */
25bacf7a
KG		 505 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
506 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
1b3e4044
KG		 507 ;
508
82fd1f8d
KG		 509#ifdef CONFIG_SYS_CACHE_STASHING
510 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
511 mtspr(SPRN_L2CSR1, (32 + 1));
512#endif
513
1b3e4044
KG		 514 /* enable the cache */
515 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
516
654ea1f3
DL		 517 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
518 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
519 ;
1b3e4044 520 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
654ea1f3 521 }
acf3f8da
KG		 522
523skip_l2:
6d2b9da1
YS		 524#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
525 if (l2cache->l2csr0 & L2CSR0_L2E)
526 printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
527
528 enable_cluster_l2();
42d1f039 529#else
6beecfbb 530 puts("disabled\n");
42d1f039 531#endif
6aba33e9
KG		 532
533 enable_cpc();
534
cb93071b 535#ifndef CONFIG_SYS_FSL_NO_SERDES
af025065
KG		 536 /* needs to be in ram since code uses global static vars */
537 fsl_serdes_init();
cb93071b 538#endif
af025065 539
72bd83cd
SL		 540#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
541 if (IS_SVR_REV(svr, 1, 0)) {
542 int i;
543 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
544
545 for (i = 0; i < 12; i++) {
546 p += i + (i > 5 ? 11 : 0);
547 out_be32(p, 0x2);
548 }
549 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
550 out_be32(p, 0x34);
551 }
552#endif
553
a09b9b68
KG		 554#ifdef CONFIG_SYS_SRIO
555 srio_init();
c8b28152 556#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
ff65f126
LG		 557 char *s = getenv("bootmaster");
558 if (s) {
559 if (!strcmp(s, "SRIO1")) {
560 srio_boot_master(1);
561 srio_boot_master_release_slave(1);
562 }
563 if (!strcmp(s, "SRIO2")) {
564 srio_boot_master(2);
565 srio_boot_master_release_slave(2);
566 }
567 }
5ffa88ec 568#endif
a09b9b68
KG		 569#endif
570
ec2b74ff
KG		 571#if defined(CONFIG_MP)
572 setup_mp();
573#endif
3f0202ed 574
4e0be34a 575#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
ae026ffd 576 {
4e0be34a
ZRR		 577 if (SVR_MAJ(svr) < 3) {
578 void *p;
579 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
580 setbits_be32(p, 1 << (31 - 14));
581 }
ae026ffd
RZ		 582 }
583#endif
584
3f0202ed
LC		 585#ifdef CONFIG_SYS_LBC_LCRR
586 /*
587 * Modify the CLKDIV field of LCRR register to improve the writing
588 * speed for NOR flash.
589 */
590 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
591 __raw_readl(&lbc->lcrr);
592 isync();
2b3a1cdd
KG		 593#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
594 udelay(100);
595#endif
3f0202ed
LC		 596#endif
597
86221f09
RZ		 598#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
599 {
600 ccsr_usb_phy_t *usb_phy1 =
601 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
602 out_be32(&usb_phy1->usb_enable_override,
603 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
604 }
605#endif
606#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
607 {
608 ccsr_usb_phy_t *usb_phy2 =
609 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
610 out_be32(&usb_phy2->usb_enable_override,
611 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
612 }
613#endif
614
99d7b0a4
X		 615#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
616 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
617 * multi-bit ECC errors which has impact on performance, so software
618 * should disable all ECC reporting from USB1 and USB2.
619 */
620 if (IS_SVR_REV(get_svr(), 1, 0)) {
621 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
622 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
623 setbits_be32(&dcfg->ecccr1,
624 (DCSR_DCFG_ECC_DISABLE_USB1 |
625 DCSR_DCFG_ECC_DISABLE_USB2));
626 }
627#endif
628
3fa75c87
RZ		 629#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
630 ccsr_usb_phy_t *usb_phy =
631 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
632 setbits_be32(&usb_phy->pllprg[1],
633 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
634 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
635 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
636 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
637 setbits_be32(&usb_phy->port1.ctrl,
638 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
639 setbits_be32(&usb_phy->port1.drvvbuscfg,
640 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
641 setbits_be32(&usb_phy->port1.pwrfltcfg,
642 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
643 setbits_be32(&usb_phy->port2.ctrl,
644 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
645 setbits_be32(&usb_phy->port2.drvvbuscfg,
646 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
647 setbits_be32(&usb_phy->port2.pwrfltcfg,
648 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
649#endif
650
c916d7c9
KG		 651#ifdef CONFIG_FMAN_ENET
652 fman_enet_init();
653#endif
654
fbc20aab
TT		 655#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
656 /*
657 * For P1022/1013 Rev1.0 silicon, after power on SATA host
658 * controller is configured in legacy mode instead of the
659 * expected enterprise mode. Software needs to clear bit[28]
660 * of HControl register to change to enterprise mode from
661 * legacy mode. We assume that the controller is offline.
662 */
663 if (IS_SVR_REV(svr, 1, 0) &&
664 ((SVR_SOC_VER(svr) == SVR_P1022) ||
48f6a5c3 665 (SVR_SOC_VER(svr) == SVR_P1013))) {
fbc20aab
TT		 666 fsl_sata_reg_t *reg;
667
668 /* first SATA controller */
669 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
670 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
671
672 /* second SATA controller */
673 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
674 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
675 }
676#endif
677
678
42d1f039
WD		 679 return 0;
680}
26f4cdba
KG		 681
682extern void setup_ivors(void);
683
684void arch_preboot_os(void)
685{
15fba327
KG		 686 u32 msr;
687
688 /*
689 * We are changing interrupt offsets and are about to boot the OS so
690 * we need to make sure we disable all async interrupts. EE is already
691 * disabled by the time we get called.
692 */
693 msr = mfmsr();
5344f7a2 694 msr &= ~(MSR_ME|MSR_CE);
15fba327
KG		 695 mtmsr(msr);
696
26f4cdba
KG		 697 setup_ivors();
698}
f54fe87a
KG		 699
700#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
701int sata_initialize(void)
702{
703 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
704 return __sata_initialize();
705
706 return 1;
707}
708#endif
f9a33f1c
KG		 709
710void cpu_secondary_init_r(void)
711{
712#ifdef CONFIG_QE
713 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
f2717b47 714#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
a7b1e1b7 715 int ret;
f2717b47 716 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
a7b1e1b7
HW		 717
718 /* load QE firmware from NAND flash to DDR first */
f2717b47
TT		 719 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
720 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
a7b1e1b7
HW		 721
722 if (ret && ret == -EUCLEAN) {
723 printf ("NAND read for QE firmware at offset %x failed %d\n",
f2717b47 724 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
a7b1e1b7
HW		 725 }
726#endif
f9a33f1c
KG		 727 qe_init(qe_base);
728 qe_reset();
729#endif
730}
"Das U-Boot" Source Tree