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powerpc: MPC8555: Remove macro CONFIG_MPC8555
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c
CommitLineData
42d1f039 1/*
beba93ed 2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f 3 *
42d1f039
WD		 4 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
42d1f039
WD		 11 */
12
13#include <common.h>
14#include <ppc_asm.tmpl>
a52d2f81 15#include <linux/compiler.h>
42d1f039 16#include <asm/processor.h>
ada591d2 17#include <asm/io.h>
42d1f039 18
d87080b7
WD		 19DECLARE_GLOBAL_DATA_PTR;
20
ce746fe0
PK		 21
22#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24#endif
42d1f039
WD		 25/* --------------------------------------------------------------- */
26
997399fa 27void get_sys_info(sys_info_t *sys_info)
42d1f039 28{
6d0f6bcf 29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 30#ifdef CONFIG_FSL_IFC
39b0bbbb 31 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
800c73c4
KG		 32 u32 ccr;
33#endif
39aaca1f
KG		 34#ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7 36 unsigned int cpu;
b8bf0adc
SL		 37#ifdef CONFIG_HETROGENOUS_CLUSTERS
38 unsigned int dsp_cpu;
39 uint rcw_tmp1, rcw_tmp2;
40#endif
ce746fe0
PK		 41#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
42 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
43#endif
14109c7a 44 __maybe_unused u32 svr;
39aaca1f
KG		 45
46 const u8 core_cplx_PLL[16] = {
47 [ 0] = 0, /* CC1 PPL / 1 */
48 [ 1] = 0, /* CC1 PPL / 2 */
49 [ 2] = 0, /* CC1 PPL / 4 */
50 [ 4] = 1, /* CC2 PPL / 1 */
51 [ 5] = 1, /* CC2 PPL / 2 */
52 [ 6] = 1, /* CC2 PPL / 4 */
53 [ 8] = 2, /* CC3 PPL / 1 */
54 [ 9] = 2, /* CC3 PPL / 2 */
55 [10] = 2, /* CC3 PPL / 4 */
56 [12] = 3, /* CC4 PPL / 1 */
57 [13] = 3, /* CC4 PPL / 2 */
58 [14] = 3, /* CC4 PPL / 4 */
59 };
60
997399fa 61 const u8 core_cplx_pll_div[16] = {
39aaca1f
KG		 62 [ 0] = 1, /* CC1 PPL / 1 */
63 [ 1] = 2, /* CC1 PPL / 2 */
64 [ 2] = 4, /* CC1 PPL / 4 */
65 [ 4] = 1, /* CC2 PPL / 1 */
66 [ 5] = 2, /* CC2 PPL / 2 */
67 [ 6] = 4, /* CC2 PPL / 4 */
68 [ 8] = 1, /* CC3 PPL / 1 */
69 [ 9] = 2, /* CC3 PPL / 2 */
70 [10] = 4, /* CC3 PPL / 4 */
71 [12] = 1, /* CC4 PPL / 1 */
72 [13] = 2, /* CC4 PPL / 2 */
73 [14] = 4, /* CC4 PPL / 4 */
74 };
ce746fe0 75 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
2d9ca2c7
YL		 76#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
77 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
ce746fe0
PK		 78 uint rcw_tmp;
79#endif
80 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
39aaca1f 81 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a 82 uint mem_pll_rat;
39aaca1f 83
997399fa 84 sys_info->freq_systembus = sysclk;
b135991a 85#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
0c12a159 86 uint ddr_refclk_sel;
87 unsigned int porsr1_sys_clk;
88 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
89 & FSL_DCFG_PORSR1_SYSCLK_MASK;
90 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
91 sys_info->diff_sysclk = 1;
92 else
93 sys_info->diff_sysclk = 0;
94
b135991a
PJ		 95 /*
96 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
97 * are driven by separate DDR Refclock or single source
98 * differential clock.
99 */
0c12a159 100 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
b135991a
PJ		 101 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
102 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
103 /*
0c12a159 104 * For single source clocking, both ddrclock and sysclock
b135991a
PJ		 105 * are driven by differential sysclock.
106 */
0c12a159 107 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
b135991a 108 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
0c12a159 109 else
b135991a 110#endif
98ffa190 111#ifdef CONFIG_DDR_CLK_FREQ
b135991a 112 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
98ffa190 113#else
b135991a 114 sys_info->freq_ddrbus = sysclk;
98ffa190 115#endif
39aaca1f 116
997399fa 117 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf
YS		 118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
120 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
c3678b09
YS		 121#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
122 if (mem_pll_rat == 0) {
123 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
124 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
125 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
126 }
127#endif
e88f421e
ZRR		 128 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
129 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
130 * it uses 6.
14109c7a 131 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
e88f421e 132 */
5122dfae 133#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
96d59e9d
SL		 134 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
135 defined(CONFIG_PPC_T2081)
14109c7a
YS		 136 svr = get_svr();
137 switch (SVR_SOC_VER(svr)) {
138 case SVR_T4240:
139 case SVR_T4160:
140 case SVR_T4120:
141 case SVR_T4080:
142 if (SVR_MAJ(svr) >= 2)
143 mem_pll_rat *= 2;
144 break;
145 case SVR_T2080:
146 case SVR_T2081:
147 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
148 mem_pll_rat *= 2;
149 break;
150 default:
151 break;
152 }
e88f421e 153#endif
ab48ca1a 154 if (mem_pll_rat > 2)
997399fa 155 sys_info->freq_ddrbus *= mem_pll_rat;
ab48ca1a 156 else
997399fa 157 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
39aaca1f 158
ce746fe0
PK		 159 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
160 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
ab48ca1a 161 if (ratio[i] > 4)
ce746fe0 162 freq_c_pll[i] = sysclk * ratio[i];
ab48ca1a 163 else
ce746fe0 164 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
ab48ca1a 165 }
b8bf0adc 166
9a653a98
YS		 167#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
168 /*
ce746fe0 169 * As per CHASSIS2 architeture total 12 clusters are posible and
9a653a98 170 * Each cluster has up to 4 cores, sharing the same PLL selection.
ce746fe0
PK		 171 * The cluster clock assignment is SoC defined.
172 *
173 * Total 4 clock groups are possible with 3 PLLs each.
174 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
175 * clock group B has 3, 4, 6 and so on.
176 *
177 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
178 * depends upon the SoC architeture. Same applies to other
179 * clock groups and clusters.
180 *
9a653a98 181 */
fbb9ecf7 182 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439
YS		 183 int cluster = fsl_qoriq_core_to_cluster(cpu);
184 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
9a653a98 185 & 0xf;
39aaca1f 186 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
ce746fe0 187 cplx_pll += cc_group[cluster] - 1;
997399fa 188 sys_info->freq_processor[cpu] =
ce746fe0 189 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
39aaca1f 190 }
b8bf0adc
SL		 191
192#ifdef CONFIG_HETROGENOUS_CLUSTERS
193 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
194 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
195 u32 c_pll_sel = (in_be32
196 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
197 & 0xf;
198 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
199 cplx_pll += cc_group[dsp_cluster] - 1;
200 sys_info->freq_processor_dsp[dsp_cpu] =
201 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
202 }
203#endif
204
b33bd8cd
PK		 205#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
206 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
0cb3325c
SS		 207#define FM1_CLK_SEL 0xe0000000
208#define FM1_CLK_SHIFT 29
f6050790
SL		 209#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
210#define FM1_CLK_SEL 0x00000007
211#define FM1_CLK_SHIFT 0
0cb3325c 212#else
9a653a98
YS		 213#define PME_CLK_SEL 0xe0000000
214#define PME_CLK_SHIFT 29
215#define FM1_CLK_SEL 0x1c000000
216#define FM1_CLK_SHIFT 26
0cb3325c 217#endif
ce746fe0 218#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
f6050790
SL		 219#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
220 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
221#else
9a653a98 222 rcw_tmp = in_be32(&gur->rcwsr[7]);
ce746fe0 223#endif
f6050790 224#endif
9a653a98
YS		 225
226#ifdef CONFIG_SYS_DPAA_PME
ce746fe0 227#ifndef CONFIG_PME_PLAT_CLK_DIV
9a653a98
YS		 228 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
229 case 1:
ce746fe0 230 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
9a653a98
YS		 231 break;
232 case 2:
ce746fe0 233 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
9a653a98
YS		 234 break;
235 case 3:
ce746fe0 236 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
9a653a98
YS		 237 break;
238 case 4:
ce746fe0 239 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
9a653a98
YS		 240 break;
241 case 6:
ce746fe0 242 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
9a653a98
YS		 243 break;
244 case 7:
ce746fe0 245 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
9a653a98
YS		 246 break;
247 default:
248 printf("Error: Unknown PME clock select!\n");
249 case 0:
997399fa 250 sys_info->freq_pme = sys_info->freq_systembus / 2;
9a653a98
YS		 251 break;
252
253 }
ce746fe0
PK		 254#else
255 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
256
257#endif
9a653a98
YS		 258#endif
259
990e1a8c 260#ifdef CONFIG_SYS_DPAA_QBMAN
f6050790
SL		 261#ifndef CONFIG_QBMAN_CLK_DIV
262#define CONFIG_QBMAN_CLK_DIV 2
263#endif
264 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
990e1a8c
HW		 265#endif
266
b8bf0adc
SL		 267#if defined(CONFIG_SYS_MAPLE)
268#define CPRI_CLK_SEL 0x1C000000
269#define CPRI_CLK_SHIFT 26
270#define CPRI_ALT_CLK_SEL 0x00007000
271#define CPRI_ALT_CLK_SHIFT 12
272
273 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
274 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
275 /* For MAPLE and CPRI frequency */
276 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
277 case 1:
278 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
279 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
280 break;
281 case 2:
282 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
283 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
284 break;
285 case 3:
286 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
287 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
288 break;
289 case 4:
290 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
291 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
292 break;
293 case 5:
294 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
295 >> CPRI_ALT_CLK_SHIFT) == 6) {
296 sys_info->freq_maple =
297 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
298 sys_info->freq_cpri =
299 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
300 }
301 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
302 >> CPRI_ALT_CLK_SHIFT) == 7) {
303 sys_info->freq_maple =
304 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
305 sys_info->freq_cpri =
306 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
307 }
308 break;
309 case 6:
310 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
311 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
312 break;
313 case 7:
314 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
315 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
316 break;
317 default:
318 printf("Error: Unknown MAPLE/CPRI clock select!\n");
319 }
320
321 /* For MAPLE ULB and eTVPE frequencies */
322#define ULB_CLK_SEL 0x00000038
323#define ULB_CLK_SHIFT 3
324#define ETVPE_CLK_SEL 0x00000007
325#define ETVPE_CLK_SHIFT 0
326
327 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
328 case 1:
329 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
330 break;
331 case 2:
332 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
333 break;
334 case 3:
335 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
336 break;
337 case 4:
338 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
339 break;
340 case 5:
341 sys_info->freq_maple_ulb = sys_info->freq_systembus;
342 break;
343 case 6:
344 sys_info->freq_maple_ulb =
345 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
346 break;
347 case 7:
348 sys_info->freq_maple_ulb =
349 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
350 break;
351 default:
352 printf("Error: Unknown MAPLE ULB clock select!\n");
353 }
354
355 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
356 case 1:
357 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
358 break;
359 case 2:
360 sys_info->freq_maple_etvpe =
361 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
362 break;
363 case 3:
364 sys_info->freq_maple_etvpe =
365 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
366 break;
367 case 4:
368 sys_info->freq_maple_etvpe =
369 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
370 break;
371 case 5:
372 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
373 break;
374 case 6:
375 sys_info->freq_maple_etvpe =
376 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
377 break;
378 case 7:
379 sys_info->freq_maple_etvpe =
380 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
381 break;
382 default:
383 printf("Error: Unknown MAPLE eTVPE clock select!\n");
384 }
385
386#endif
387
9a653a98 388#ifdef CONFIG_SYS_DPAA_FMAN
ce746fe0 389#ifndef CONFIG_FM_PLAT_CLK_DIV
9a653a98
YS		 390 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
391 case 1:
ce746fe0 392 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
9a653a98
YS		 393 break;
394 case 2:
ce746fe0 395 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
9a653a98
YS		 396 break;
397 case 3:
ce746fe0 398 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
9a653a98
YS		 399 break;
400 case 4:
ce746fe0 401 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
9a653a98 402 break;
0cb3325c 403 case 5:
997399fa 404 sys_info->freq_fman[0] = sys_info->freq_systembus;
0cb3325c 405 break;
9a653a98 406 case 6:
ce746fe0 407 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
9a653a98
YS		 408 break;
409 case 7:
ce746fe0 410 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
9a653a98
YS		 411 break;
412 default:
413 printf("Error: Unknown FMan1 clock select!\n");
414 case 0:
997399fa 415 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
9a653a98
YS		 416 break;
417 }
418#if (CONFIG_SYS_NUM_FMAN) == 2
ce746fe0 419#ifdef CONFIG_SYS_FM2_CLK
9a653a98
YS		 420#define FM2_CLK_SEL 0x00000038
421#define FM2_CLK_SHIFT 3
422 rcw_tmp = in_be32(&gur->rcwsr[15]);
423 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
424 case 1:
ce746fe0 425 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
9a653a98
YS		 426 break;
427 case 2:
ce746fe0 428 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
9a653a98
YS		 429 break;
430 case 3:
ce746fe0 431 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
9a653a98
YS		 432 break;
433 case 4:
ce746fe0 434 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
9a653a98 435 break;
c1015c67
SX		 436 case 5:
437 sys_info->freq_fman[1] = sys_info->freq_systembus;
438 break;
9a653a98 439 case 6:
ce746fe0 440 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
9a653a98
YS		 441 break;
442 case 7:
ce746fe0 443 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
9a653a98
YS		 444 break;
445 default:
446 printf("Error: Unknown FMan2 clock select!\n");
447 case 0:
997399fa 448 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
9a653a98
YS		 449 break;
450 }
ce746fe0 451#endif
9a653a98 452#endif /* CONFIG_SYS_NUM_FMAN == 2 */
ce746fe0
PK		 453#else
454 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
455#endif
456#endif
39aaca1f 457
2d9ca2c7
YL		 458#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
459#if defined(CONFIG_PPC_T2080)
460#define ESDHC_CLK_SEL 0x00000007
461#define ESDHC_CLK_SHIFT 0
462#define ESDHC_CLK_RCWSR 15
463#else /* Support T1040 T1024 by now */
464#define ESDHC_CLK_SEL 0xe0000000
465#define ESDHC_CLK_SHIFT 29
466#define ESDHC_CLK_RCWSR 7
467#endif
468 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
469 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
470 case 1:
471 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
472 break;
473 case 2:
474 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
475 break;
476 case 3:
477 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
478 break;
479#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
480 case 4:
481 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
482 break;
483#if defined(CONFIG_PPC_T2080)
484 case 5:
485 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
486 break;
487#endif
488 case 6:
489 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
490 break;
491 case 7:
492 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
493 break;
494#endif
495 default:
496 sys_info->freq_sdhc = 0;
497 printf("Error: Unknown SDHC peripheral clock select!\n");
498 }
499#endif
9a653a98
YS		 500#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
501
502 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439
YS		 503 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
504 & 0xf;
9a653a98
YS		 505 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
506
997399fa 507 sys_info->freq_processor[cpu] =
ce746fe0 508 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
9a653a98 509 }
39aaca1f
KG		 510#define PME_CLK_SEL 0x80000000
511#define FM1_CLK_SEL 0x40000000
512#define FM2_CLK_SEL 0x20000000
b5c8753f
KG		 513#define HWA_ASYNC_DIV 0x04000000
514#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
515#define HWA_CC_PLL 1
4905443f
TT		 516#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
517#define HWA_CC_PLL 2
b5c8753f 518#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5 519#define HWA_CC_PLL 2
b5c8753f
KG		 520#else
521#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
522#endif
39aaca1f
KG		 523 rcw_tmp = in_be32(&gur->rcwsr[7]);
524
525#ifdef CONFIG_SYS_DPAA_PME
b5c8753f
KG		 526 if (rcw_tmp & PME_CLK_SEL) {
527 if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0 528 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f 529 else
ce746fe0 530 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f 531 } else {
997399fa 532 sys_info->freq_pme = sys_info->freq_systembus / 2;
b5c8753f 533 }
39aaca1f
KG		 534#endif
535
536#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f
KG		 537 if (rcw_tmp & FM1_CLK_SEL) {
538 if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0 539 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f 540 else
ce746fe0 541 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f 542 } else {
997399fa 543 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
b5c8753f 544 }
39aaca1f 545#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f
KG		 546 if (rcw_tmp & FM2_CLK_SEL) {
547 if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0 548 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f 549 else
ce746fe0 550 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f 551 } else {
997399fa 552 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
b5c8753f 553 }
39aaca1f
KG		 554#endif
555#endif
556
3e83fc9b 557#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa 558 sys_info->freq_qman = sys_info->freq_systembus / 2;
3e83fc9b
SX		 559#endif
560
9a653a98
YS		 561#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
562
2a44efeb
ZQ		 563#ifdef CONFIG_U_QE
564 sys_info->freq_qe = sys_info->freq_systembus / 2;
565#endif
566
9a653a98 567#else /* CONFIG_FSL_CORENET */
997399fa 568 uint plat_ratio, e500_ratio, half_freq_systembus;
2fc7eb0c 569 int i;
b3d7f20f 570#ifdef CONFIG_QE
a52d2f81 571 __maybe_unused u32 qe_ratio;
b3d7f20f 572#endif
42d1f039
WD		 573
574 plat_ratio = (gur->porpllsr) & 0x0000003e;
575 plat_ratio >>= 1;
997399fa 576 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca
AF		 577
578 /* Divide before multiply to avoid integer
579 * overflow for processor speeds above 2GHz */
997399fa 580 half_freq_systembus = sys_info->freq_systembus/2;
0e870980 581 for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c 582 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
997399fa 583 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
2fc7eb0c 584 }
a3e77fa5 585
997399fa
PK		 586 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
587 sys_info->freq_ddrbus = sys_info->freq_systembus;
d4357932
KG		 588
589#ifdef CONFIG_DDR_CLK_FREQ
590 {
c0391111
JJ		 591 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
592 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932 593 if (ddr_ratio != 0x7)
997399fa 594 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
d4357932
KG		 595 }
596#endif
ada591d2 597
b3d7f20f 598#ifdef CONFIG_QE
be7bebea 599#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
997399fa 600 sys_info->freq_qe = sys_info->freq_systembus;
a52d2f81 601#else
b3d7f20f
HW		 602 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
603 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
997399fa 604 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
b3d7f20f 605#endif
a52d2f81 606#endif
b3d7f20f 607
24995d82 608#ifdef CONFIG_SYS_DPAA_FMAN
997399fa 609 sys_info->freq_fman[0] = sys_info->freq_systembus;
24995d82
HW		 610#endif
611
612#endif /* CONFIG_FSL_CORENET */
613
beba93ed 614#if defined(CONFIG_FSL_LBC)
9a653a98 615 uint lcrr_div;
ada591d2
TP		 616#if defined(CONFIG_SYS_LBC_LCRR)
617 /* We will program LCRR to this value later */
618 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
619#else
f51cdaf1 620 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2
TP		 621#endif
622 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
0fd2fa6c
DL		 623#if defined(CONFIG_FSL_CORENET)
624 /* If this is corenet based SoC, bit-representation
625 * for four times the clock divider values.
626 */
627 lcrr_div *= 4;
3aff3082 628#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
3c3d8ab5 629 !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_MPC8560)
ada591d2
TP		 630 /*
631 * Yes, the entire PQ38 family use the same
632 * bit-representation for twice the clock divider values.
633 */
634 lcrr_div *= 2;
635#endif
997399fa 636 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
ada591d2
TP		 637 } else {
638 /* In case anyone cares what the unknown value is */
997399fa 639 sys_info->freq_localbus = lcrr_div;
ada591d2 640 }
beba93ed 641#endif
800c73c4
KG		 642
643#if defined(CONFIG_FSL_IFC)
39b0bbbb 644 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
800c73c4
KG		 645 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
646
997399fa 647 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
800c73c4 648#endif
42d1f039
WD		 649}
650
66ed6cca 651
42d1f039
WD		 652int get_clocks (void)
653{
42d1f039 654 sys_info_t sys_info;
25cb74b3 655#ifdef CONFIG_ARCH_MPC8544
6d0f6bcf 656 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98 657#endif
9c4c5ae3 658#if defined(CONFIG_CPM2)
6d0f6bcf 659 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039
WD		 660 uint sccr, dfbrg;
661
662 /* set VCO = 4 * BRG */
aafeefbd
KG		 663 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
664 sccr = cpm->im_cpm_intctl.sccr;
42d1f039
WD		 665 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
666#endif
667 get_sys_info (&sys_info);
997399fa
PK		 668 gd->cpu_clk = sys_info.freq_processor[0];
669 gd->bus_clk = sys_info.freq_systembus;
670 gd->mem_clk = sys_info.freq_ddrbus;
671 gd->arch.lbc_clk = sys_info.freq_localbus;
88353a98 672
b3d7f20f 673#ifdef CONFIG_QE
997399fa 674 gd->arch.qe_clk = sys_info.freq_qe;
45bae2e3 675 gd->arch.brg_clk = gd->arch.qe_clk / 2;
b3d7f20f 676#endif
88353a98
TT		 677 /*
678 * The base clock for I2C depends on the actual SOC. Unfortunately,
679 * there is no pattern that can be used to determine the frequency, so
680 * the only choice is to look up the actual SOC number and use the value
681 * for that SOC. This information is taken from application note
682 * AN2919.
683 */
3aff3082 684#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
3c3d8ab5 685 defined(CONFIG_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
f62b1238 686 defined(CONFIG_P1022)
997399fa 687 gd->arch.i2c1_clk = sys_info.freq_systembus;
25cb74b3 688#elif defined(CONFIG_ARCH_MPC8544)
88353a98
TT		 689 /*
690 * On the 8544, the I2C clock is the same as the SEC clock. This can be
691 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
692 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
693 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
694 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
695 */
696 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
997399fa 697 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
42653b82 698 else
997399fa 699 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98
TT		 700#else
701 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
997399fa 702 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98 703#endif
609e6ec3 704 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
943afa22 705
6b9ea08c 706#if defined(CONFIG_FSL_ESDHC)
2d9ca2c7
YL		 707#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
708 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
709#else
7d640e9b
PJ		 710#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
711 defined(CONFIG_P1014)
e9adeca3 712 gd->arch.sdhc_clk = gd->bus_clk;
7f52ed5e 713#else
e9adeca3 714 gd->arch.sdhc_clk = gd->bus_clk / 2;
ef50d6c0 715#endif
2d9ca2c7 716#endif
7f52ed5e 717#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0 718
9c4c5ae3 719#if defined(CONFIG_CPM2)
997399fa 720 gd->arch.vco_out = 2*sys_info.freq_systembus;
748cd059
SG		 721 gd->arch.cpm_clk = gd->arch.vco_out / 2;
722 gd->arch.scc_clk = gd->arch.vco_out / 4;
723 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039
WD		 724#endif
725
726 if(gd->cpu_clk != 0) return (0);
727 else return (1);
728}
729
730
731/********************************************
732 * get_bus_freq
733 * return system bus freq in Hz
734 *********************************************/
735ulong get_bus_freq (ulong dummy)
736{
a3e77fa5 737 return gd->bus_clk;
42d1f039 738}
d4357932
KG		 739
740/********************************************
741 * get_ddr_freq
742 * return ddr bus freq in Hz
743 *********************************************/
744ulong get_ddr_freq (ulong dummy)
745{
a3e77fa5 746 return gd->mem_clk;
d4357932 747}
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