]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
powerpc: MPC8555: Remove macro CONFIG_MPC8555
authorYork Sun <york.sun@nxp.com>
Wed, 16 Nov 2016 19:23:23 +0000 (11:23 -0800)
committerYork Sun <york.sun@nxp.com>
Thu, 24 Nov 2016 07:42:05 +0000 (23:42 -0800)
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
13 files changed:
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/cpm_85xx.h
arch/powerpc/include/asm/fsl_lbc.h
arch/powerpc/include/asm/immap_85xx.h
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/mpc85xx_ddr_gen1.c
drivers/input/keyboard.c
include/configs/MPC8555CDS.h
include/keyboard.h
scripts/config_whitelist.txt

index 8b08ee2ad055beeb68f91a191e2e0ee246857942..c58f76ff91334dd67d4efd06c17a77cc0c7152c3 100644 (file)
@@ -76,6 +76,7 @@ config TARGET_MPC8548CDS
 
 config TARGET_MPC8555CDS
        bool "Support MPC8555CDS"
+       select ARCH_MPC8555
 
 config TARGET_MPC8560ADS
        bool "Support MPC8560ADS"
@@ -207,6 +208,9 @@ config ARCH_MPC8544
 config ARCH_MPC8548
        bool
 
+config ARCH_MPC8555
+       bool
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
index c563744cd7d19bae5a1e8954834c5c577f99b87e..3e6f8f379c76f5e3d2a4b62db7770afbc6513537 100644 (file)
@@ -294,7 +294,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-    defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
+       defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_MPC8560)
        unsigned long val, msr;
 
        /*
index bd810d7b6012a7262b2dc9233431c0b21b760907..93c7193852346715bfeb0c63468d58e35081c20c 100644 (file)
@@ -626,7 +626,7 @@ void get_sys_info(sys_info_t *sys_info)
                 */
                lcrr_div *= 4;
 #elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+       !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_MPC8560)
                /*
                 * Yes, the entire PQ38 family use the same
                 * bit-representation for twice the clock divider values.
@@ -682,7 +682,7 @@ int get_clocks (void)
         * AN2919.
         */
 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
-       defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
+       defined(CONFIG_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
        defined(CONFIG_P1022)
        gd->arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_ARCH_MPC8544)
index f16e32e97aaac94a4b5c7f72977d844822ac668f..4e38d23945537105ca7b9a1195be32518ac5ac2b 100644 (file)
@@ -85,7 +85,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
 
-#elif defined(CONFIG_MPC8555)
+#elif defined(CONFIG_ARCH_MPC8555)
 #define CONFIG_MAX_CPUS                        1
 #define CONFIG_SYS_FSL_NUM_LAWS                8
 #define CONFIG_SYS_FSL_DDRC_GEN1
index e89e2f04bcdab23944c4504fc4da31897a11a559..b46e20e5ce89c17bd2e9fa8d566b5f10d5cff42b 100644 (file)
@@ -77,7 +77,7 @@
  */
 #define CPM_DATAONLY_BASE      ((uint)128)
 #define CPM_DP_NOSPACE         ((uint)0x7FFFFFFF)
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
 #define CPM_FCC_SPECIAL_BASE   ((uint)0x00009000)
 #define CPM_DATAONLY_SIZE      ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
 #else  /* MPC8540, MPC8560 */
index c7805e90a19ee87997b9c44c6e9d62df2fafebf0..ff9b2d9cd917be9ae5980ddeae1b31e9caded084 100644 (file)
@@ -326,7 +326,7 @@ void lbc_sdram_init(void);
 #define LCRR_CLKDIV                    0x0000001F
 #define LCRR_CLKDIV_SHIFT              0
 #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
-       defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555) || \
+       defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
        defined(CONFIG_MPC8560)
 #define LCRR_CLKDIV_2                  0x00000002
 #define LCRR_CLKDIV_4                  0x00000004
index 4754aa862467460c25c581c3a38bc4251d5ceb6c..d6e7f62620a8fe96ee13756b38db74c059879a39 100644 (file)
@@ -127,7 +127,7 @@ typedef struct ccsr_i2c {
 #if defined(CONFIG_ARCH_MPC8540) || \
        defined(CONFIG_ARCH_MPC8541) || \
        defined(CONFIG_ARCH_MPC8548) || \
-       defined(CONFIG_MPC8555)
+       defined(CONFIG_ARCH_MPC8555)
 /* DUART Registers */
 typedef struct ccsr_duart {
        u8      res1[1280];
index b2e92a0b449ac8c5304c2c8a466104975f030c90..32b09679e2ec4fa9a24ad88ab03ddf9c4cb59fe8 100644 (file)
@@ -1831,7 +1831,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
        unsigned int clk_adjust;        /* Clock adjust */
        unsigned int ss_en = 0;         /* Source synchronous enable */
 
-#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
        /* Per FSL Application Note: AN2805 */
        ss_en = 1;
 #endif
index 67a9ad8bf81912a788865e68d6ad248a83b158dc..c005f5294cb8245e35fdf72212424734229129cd 100644 (file)
@@ -47,7 +47,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
        out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
-#if defined(CONFIG_MPC8555) || defined(CONFIG_ARCH_MPC8541)
+#if defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8541)
        out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 #endif
 
index f53a07afcc60514ed2ed44ae8977ff18d90c076f..7af5868dea727b1bf11fbabac38c54b3e98d3690 100644 (file)
@@ -21,7 +21,7 @@ static struct input_config config;
 static int kbd_read_keys(struct input_config *config)
 {
 #if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
-               defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
+               defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
        /* no ISR is used, so received chars must be polled */
        ps2ser_check();
 #endif
index 908b7eddd3578397286609fcdfb5239ec6df526b..d0498c63d2bae811886442d322f773630195a6b2 100644 (file)
@@ -17,7 +17,6 @@
 #define CONFIG_BOOKE           1       /* BOOKE */
 #define CONFIG_E500            1       /* BOOKE e500 family */
 #define CONFIG_CPM2            1       /* has CPM2 */
-#define CONFIG_MPC8555         1       /* MPC8555 specific */
 #define CONFIG_MPC8555CDS      1       /* MPC8555CDS board specific */
 
 #define        CONFIG_SYS_TEXT_BASE    0xfff80000
index a911ac8d468bc7fbe8b9f3f63325eed999bd915f..5cbd9f8ba8918e6087f121c1167ce5e3be452d62 100644 (file)
@@ -99,7 +99,7 @@ extern void pckbd_leds(unsigned char leds);
 #endif /* !CONFIG_DM_KEYBOARD */
 
 #if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \
-               defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_MPC8555)
+               defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
 int ps2ser_check(void);
 #endif
 
index 12841018521edf91454a1853b9e9ac17483f378e..aa7dcc8ec7094eaf8dba0a45cbe6e7e4148d1a96 100644 (file)
@@ -3141,7 +3141,6 @@ CONFIG_MPC83XX_GPIO_1_INIT_VALUE
 CONFIG_MPC83XX_PCI2
 CONFIG_MPC850
 CONFIG_MPC855
-CONFIG_MPC8555
 CONFIG_MPC8555CDS
 CONFIG_MPC8560
 CONFIG_MPC8560ADS