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Commit | Line | Data |
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0442ed86 WD |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
4 | * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> | |
3cb86f3e | 5 | * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering |
c821b5f1 GE |
6 | * Copyright (c) 2008 Nuovation System Designs, LLC |
7 | * Grant Erickson <gerickson@nuovations.com> | |
0442ed86 | 8 | * |
1b387ef5 | 9 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
83b4cfa3 | 10 | */ |
0442ed86 | 11 | |
f7b548ad SR |
12 | /* |
13 | * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards | |
0442ed86 | 14 | * |
f7b548ad SR |
15 | * The following description only applies to the NOR flash style booting. |
16 | * NAND booting is different. For more details about NAND booting on 4xx | |
17 | * take a look at doc/README.nand-boot-ppc440. | |
0442ed86 | 18 | * |
f7b548ad SR |
19 | * The CPU starts at address 0xfffffffc (last word in the address space). |
20 | * The U-Boot image therefore has to be located in the "upper" area of the | |
21 | * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for | |
22 | * the boot chip-select (CS0) is quite big and covers this area. On the | |
23 | * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will | |
24 | * reconfigure this CS0 (and other chip-selects as well when configured | |
25 | * this way) in the boot process to the "correct" values matching the | |
26 | * board layout. | |
0442ed86 | 27 | */ |
f7b548ad | 28 | |
25ddd1fb | 29 | #include <asm-offsets.h> |
0442ed86 | 30 | #include <config.h> |
b36df561 | 31 | #include <asm/ppc4xx.h> |
0442ed86 WD |
32 | #include <version.h> |
33 | ||
0442ed86 WD |
34 | #include <ppc_asm.tmpl> |
35 | #include <ppc_defs.h> | |
36 | ||
37 | #include <asm/cache.h> | |
38 | #include <asm/mmu.h> | |
b14ca4b6 | 39 | #include <asm/ppc4xx-isram.h> |
0442ed86 | 40 | |
6d0f6bcf JCPV |
41 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
42 | # if (CONFIG_SYS_INIT_DCACHE_CS == 0) | |
d1c3b275 SR |
43 | # define PBxAP PB1AP |
44 | # define PBxCR PB0CR | |
6d0f6bcf JCPV |
45 | # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) |
46 | # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP | |
47 | # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR | |
c821b5f1 | 48 | # endif |
0442ed86 | 49 | # endif |
6d0f6bcf | 50 | # if (CONFIG_SYS_INIT_DCACHE_CS == 1) |
d1c3b275 SR |
51 | # define PBxAP PB1AP |
52 | # define PBxCR PB1CR | |
6d0f6bcf JCPV |
53 | # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) |
54 | # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP | |
55 | # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR | |
c821b5f1 | 56 | # endif |
0442ed86 | 57 | # endif |
6d0f6bcf | 58 | # if (CONFIG_SYS_INIT_DCACHE_CS == 2) |
d1c3b275 SR |
59 | # define PBxAP PB2AP |
60 | # define PBxCR PB2CR | |
6d0f6bcf JCPV |
61 | # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) |
62 | # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP | |
63 | # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR | |
c821b5f1 | 64 | # endif |
0442ed86 | 65 | # endif |
6d0f6bcf | 66 | # if (CONFIG_SYS_INIT_DCACHE_CS == 3) |
d1c3b275 SR |
67 | # define PBxAP PB3AP |
68 | # define PBxCR PB3CR | |
6d0f6bcf JCPV |
69 | # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) |
70 | # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP | |
71 | # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR | |
c821b5f1 | 72 | # endif |
0442ed86 | 73 | # endif |
6d0f6bcf | 74 | # if (CONFIG_SYS_INIT_DCACHE_CS == 4) |
d1c3b275 SR |
75 | # define PBxAP PB4AP |
76 | # define PBxCR PB4CR | |
6d0f6bcf JCPV |
77 | # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) |
78 | # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP | |
79 | # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR | |
c821b5f1 | 80 | # endif |
0442ed86 | 81 | # endif |
6d0f6bcf | 82 | # if (CONFIG_SYS_INIT_DCACHE_CS == 5) |
d1c3b275 SR |
83 | # define PBxAP PB5AP |
84 | # define PBxCR PB5CR | |
6d0f6bcf JCPV |
85 | # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) |
86 | # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP | |
87 | # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR | |
c821b5f1 | 88 | # endif |
0442ed86 | 89 | # endif |
6d0f6bcf | 90 | # if (CONFIG_SYS_INIT_DCACHE_CS == 6) |
d1c3b275 SR |
91 | # define PBxAP PB6AP |
92 | # define PBxCR PB6CR | |
6d0f6bcf JCPV |
93 | # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) |
94 | # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP | |
95 | # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR | |
c821b5f1 | 96 | # endif |
0442ed86 | 97 | # endif |
6d0f6bcf | 98 | # if (CONFIG_SYS_INIT_DCACHE_CS == 7) |
d1c3b275 SR |
99 | # define PBxAP PB7AP |
100 | # define PBxCR PB7CR | |
6d0f6bcf JCPV |
101 | # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) |
102 | # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP | |
103 | # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR | |
c821b5f1 GE |
104 | # endif |
105 | # endif | |
106 | # ifndef PBxAP_VAL | |
107 | # define PBxAP_VAL 0 | |
108 | # endif | |
109 | # ifndef PBxCR_VAL | |
110 | # define PBxCR_VAL 0 | |
111 | # endif | |
112 | /* | |
6d0f6bcf | 113 | * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB |
c821b5f1 GE |
114 | * used as temporary stack pointer for the primordial stack |
115 | */ | |
6d0f6bcf JCPV |
116 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR |
117 | # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ | |
c821b5f1 GE |
118 | EBC_BXAP_TWT_ENCODE(7) | \ |
119 | EBC_BXAP_BCE_DISABLE | \ | |
120 | EBC_BXAP_BCT_2TRANS | \ | |
121 | EBC_BXAP_CSN_ENCODE(0) | \ | |
122 | EBC_BXAP_OEN_ENCODE(0) | \ | |
123 | EBC_BXAP_WBN_ENCODE(0) | \ | |
124 | EBC_BXAP_WBF_ENCODE(0) | \ | |
125 | EBC_BXAP_TH_ENCODE(2) | \ | |
126 | EBC_BXAP_RE_DISABLED | \ | |
127 | EBC_BXAP_SOR_NONDELAYED | \ | |
128 | EBC_BXAP_BEM_WRITEONLY | \ | |
129 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf JCPV |
130 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ |
131 | # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR | |
132 | # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ | |
c821b5f1 GE |
133 | EBC_BXCR_BS_64MB | \ |
134 | EBC_BXCR_BU_RW | \ | |
135 | EBC_BXCR_BW_16BIT) | |
6d0f6bcf JCPV |
136 | # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ |
137 | # ifndef CONFIG_SYS_INIT_RAM_PATTERN | |
138 | # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD | |
0442ed86 | 139 | # endif |
6d0f6bcf | 140 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 141 | |
553f0982 WD |
142 | #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10))) |
143 | #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE! | |
28d77d96 SR |
144 | #endif |
145 | ||
c821b5f1 GE |
146 | /* |
147 | * Unless otherwise overriden, enable two 128MB cachable instruction regions | |
6d0f6bcf JCPV |
148 | * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering |
149 | * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. | |
c821b5f1 | 150 | */ |
6d0f6bcf | 151 | #if !defined(CONFIG_SYS_FLASH_BASE) |
64852d09 | 152 | /* If not already defined, set it to the "last" 128MByte region */ |
6d0f6bcf | 153 | # define CONFIG_SYS_FLASH_BASE 0xf8000000 |
64852d09 | 154 | #endif |
6d0f6bcf JCPV |
155 | #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) |
156 | # define CONFIG_SYS_ICACHE_SACR_VALUE \ | |
157 | (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ | |
158 | PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ | |
159 | PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) | |
160 | #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ | |
161 | ||
162 | #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) | |
163 | # define CONFIG_SYS_DCACHE_SACR_VALUE \ | |
c821b5f1 | 164 | (0x00000000) |
6d0f6bcf | 165 | #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ |
c821b5f1 | 166 | |
4978e605 SR |
167 | #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH) |
168 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */ | |
169 | #endif | |
170 | ||
83b4cfa3 | 171 | #define function_prolog(func_name) .text; \ |
cf959c7d SR |
172 | .align 2; \ |
173 | .globl func_name; \ | |
174 | func_name: | |
83b4cfa3 | 175 | #define function_epilog(func_name) .type func_name,@function; \ |
cf959c7d SR |
176 | .size func_name,.-func_name |
177 | ||
0442ed86 WD |
178 | /* We don't want the MMU yet. |
179 | */ | |
180 | #undef MSR_KERNEL | |
181 | #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ | |
182 | ||
183 | ||
184 | .extern ext_bus_cntlr_init | |
0442ed86 WD |
185 | |
186 | /* | |
187 | * Set up GOT: Global Offset Table | |
188 | * | |
0f8aa159 | 189 | * Use r12 to access the GOT |
0442ed86 | 190 | */ |
345b77ba | 191 | #if !defined(CONFIG_SPL_BUILD) |
0442ed86 WD |
192 | START_GOT |
193 | GOT_ENTRY(_GOT2_TABLE_) | |
194 | GOT_ENTRY(_FIXUP_TABLE_) | |
195 | ||
196 | GOT_ENTRY(_start) | |
197 | GOT_ENTRY(_start_of_vectors) | |
198 | GOT_ENTRY(_end_of_vectors) | |
199 | GOT_ENTRY(transfer_to_handler) | |
200 | ||
3b57fe0a | 201 | GOT_ENTRY(__init_end) |
3929fb0a | 202 | GOT_ENTRY(__bss_end) |
5d232d0e | 203 | GOT_ENTRY(__bss_start) |
0442ed86 | 204 | END_GOT |
345b77ba | 205 | #endif /* CONFIG_SPL_BUILD */ |
0442ed86 | 206 | |
d20b9991 | 207 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) |
d873133f SR |
208 | /* |
209 | * 4xx RAM-booting U-Boot image is started from offset 0 | |
210 | */ | |
211 | .text | |
212 | bl _start_440 | |
213 | #endif | |
214 | ||
98f99e9f SR |
215 | #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
216 | /* | |
217 | * This is the entry of the real U-Boot from a board port | |
218 | * that supports SPL booting on the PPC4xx. We only need | |
219 | * to call board_init_f() here. Everything else has already | |
220 | * been done in the SPL u-boot version. | |
221 | */ | |
222 | GET_GOT /* initialize GOT access */ | |
223 | bl board_init_f /* run 1st part of board init code (in Flash)*/ | |
224 | /* NOTREACHED - board_init_f() does not return */ | |
225 | #endif | |
226 | ||
0442ed86 WD |
227 | /* |
228 | * 440 Startup -- on reset only the top 4k of the effective | |
229 | * address space is mapped in by an entry in the instruction | |
230 | * and data shadow TLB. The .bootpg section is located in the | |
231 | * top 4k & does only what's necessary to map in the the rest | |
232 | * of the boot rom. Once the boot rom is mapped in we can | |
233 | * proceed with normal startup. | |
234 | * | |
235 | * NOTE: CS0 only covers the top 2MB of the effective address | |
236 | * space after reset. | |
237 | */ | |
238 | ||
239 | #if defined(CONFIG_440) | |
240 | .section .bootpg,"ax" | |
241 | .globl _start_440 | |
242 | ||
243 | /**************************************************************************/ | |
244 | _start_440: | |
511d0c72 WD |
245 | /*--------------------------------------------------------------------+ |
246 | | 440EPX BUP Change - Hardware team request | |
247 | +--------------------------------------------------------------------*/ | |
887e2ec9 SR |
248 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
249 | sync | |
250 | nop | |
251 | nop | |
252 | #endif | |
6c5879f3 MB |
253 | /*----------------------------------------------------------------+ |
254 | | Core bug fix. Clear the esr | |
255 | +-----------------------------------------------------------------*/ | |
edd6cf20 | 256 | li r0,0 |
58ea142f | 257 | mtspr SPRN_ESR,r0 |
0442ed86 WD |
258 | /*----------------------------------------------------------------*/ |
259 | /* Clear and set up some registers. */ | |
260 | /*----------------------------------------------------------------*/ | |
f901a83b WD |
261 | iccci r0,r0 /* NOTE: operands not used for 440 */ |
262 | dccci r0,r0 /* NOTE: operands not used for 440 */ | |
0442ed86 WD |
263 | sync |
264 | li r0,0 | |
58ea142f MF |
265 | mtspr SPRN_SRR0,r0 |
266 | mtspr SPRN_SRR1,r0 | |
267 | mtspr SPRN_CSRR0,r0 | |
268 | mtspr SPRN_CSRR1,r0 | |
887e2ec9 SR |
269 | /* NOTE: 440GX adds machine check status regs */ |
270 | #if defined(CONFIG_440) && !defined(CONFIG_440GP) | |
58ea142f MF |
271 | mtspr SPRN_MCSRR0,r0 |
272 | mtspr SPRN_MCSRR1,r0 | |
273 | mfspr r1,SPRN_MCSR | |
274 | mtspr SPRN_MCSR,r1 | |
ba56f625 | 275 | #endif |
20532833 SR |
276 | |
277 | /*----------------------------------------------------------------*/ | |
278 | /* CCR0 init */ | |
279 | /*----------------------------------------------------------------*/ | |
280 | /* Disable store gathering & broadcast, guarantee inst/data | |
281 | * cache block touch, force load/store alignment | |
282 | * (see errata 1.12: 440_33) | |
283 | */ | |
284 | lis r1,0x0030 /* store gathering & broadcast disable */ | |
285 | ori r1,r1,0x6000 /* cache touch */ | |
58ea142f | 286 | mtspr SPRN_CCR0,r1 |
20532833 | 287 | |
0442ed86 WD |
288 | /*----------------------------------------------------------------*/ |
289 | /* Initialize debug */ | |
290 | /*----------------------------------------------------------------*/ | |
58ea142f | 291 | mfspr r1,SPRN_DBCR0 |
887e2ec9 SR |
292 | andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ |
293 | bne skip_debug_init /* if set, don't clear debug register */ | |
ad876fff VG |
294 | mfspr r1,SPRN_CCR0 |
295 | ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */ | |
296 | mtspr SPRN_CCR0,r1 | |
58ea142f MF |
297 | mtspr SPRN_DBCR0,r0 |
298 | mtspr SPRN_DBCR1,r0 | |
299 | mtspr SPRN_DBCR2,r0 | |
300 | mtspr SPRN_IAC1,r0 | |
301 | mtspr SPRN_IAC2,r0 | |
302 | mtspr SPRN_IAC3,r0 | |
303 | mtspr SPRN_DAC1,r0 | |
304 | mtspr SPRN_DAC2,r0 | |
305 | mtspr SPRN_DVC1,r0 | |
306 | mtspr SPRN_DVC2,r0 | |
307 | ||
308 | mfspr r1,SPRN_DBSR | |
309 | mtspr SPRN_DBSR,r1 /* Clear all valid bits */ | |
887e2ec9 | 310 | skip_debug_init: |
0442ed86 | 311 | |
6c5879f3 MB |
312 | #if defined (CONFIG_440SPE) |
313 | /*----------------------------------------------------------------+ | |
314 | | Initialize Core Configuration Reg1. | |
315 | | a. ICDPEI: Record even parity. Normal operation. | |
316 | | b. ICTPEI: Record even parity. Normal operation. | |
317 | | c. DCTPEI: Record even parity. Normal operation. | |
318 | | d. DCDPEI: Record even parity. Normal operation. | |
319 | | e. DCUPEI: Record even parity. Normal operation. | |
320 | | f. DCMPEI: Record even parity. Normal operation. | |
321 | | g. FCOM: Normal operation | |
322 | | h. MMUPEI: Record even parity. Normal operation. | |
323 | | i. FFF: Flush only as much data as necessary. | |
edd6cf20 | 324 | | j. TCS: Timebase increments from CPU clock. |
6c5879f3 | 325 | +-----------------------------------------------------------------*/ |
edd6cf20 | 326 | li r0,0 |
58ea142f | 327 | mtspr SPRN_CCR1, r0 |
6c5879f3 MB |
328 | |
329 | /*----------------------------------------------------------------+ | |
330 | | Reset the timebase. | |
331 | | The previous write to CCR1 sets the timebase source. | |
332 | +-----------------------------------------------------------------*/ | |
58ea142f MF |
333 | mtspr SPRN_TBWL, r0 |
334 | mtspr SPRN_TBWU, r0 | |
6c5879f3 MB |
335 | #endif |
336 | ||
0442ed86 WD |
337 | /*----------------------------------------------------------------*/ |
338 | /* Setup interrupt vectors */ | |
339 | /*----------------------------------------------------------------*/ | |
58ea142f | 340 | mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ |
f901a83b | 341 | li r1,0x0100 |
58ea142f | 342 | mtspr SPRN_IVOR0,r1 /* Critical input */ |
f901a83b | 343 | li r1,0x0200 |
58ea142f | 344 | mtspr SPRN_IVOR1,r1 /* Machine check */ |
f901a83b | 345 | li r1,0x0300 |
58ea142f | 346 | mtspr SPRN_IVOR2,r1 /* Data storage */ |
f901a83b | 347 | li r1,0x0400 |
58ea142f | 348 | mtspr SPRN_IVOR3,r1 /* Instruction storage */ |
0442ed86 | 349 | li r1,0x0500 |
58ea142f | 350 | mtspr SPRN_IVOR4,r1 /* External interrupt */ |
0442ed86 | 351 | li r1,0x0600 |
58ea142f | 352 | mtspr SPRN_IVOR5,r1 /* Alignment */ |
0442ed86 | 353 | li r1,0x0700 |
58ea142f | 354 | mtspr SPRN_IVOR6,r1 /* Program check */ |
0442ed86 | 355 | li r1,0x0800 |
58ea142f | 356 | mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ |
0442ed86 | 357 | li r1,0x0c00 |
58ea142f | 358 | mtspr SPRN_IVOR8,r1 /* System call */ |
efa35cf1 | 359 | li r1,0x0a00 |
58ea142f | 360 | mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ |
efa35cf1 | 361 | li r1,0x0900 |
58ea142f | 362 | mtspr SPRN_IVOR10,r1 /* Decrementer */ |
0442ed86 | 363 | li r1,0x1300 |
58ea142f | 364 | mtspr SPRN_IVOR13,r1 /* Data TLB error */ |
efa35cf1 | 365 | li r1,0x1400 |
58ea142f | 366 | mtspr SPRN_IVOR14,r1 /* Instr TLB error */ |
0442ed86 | 367 | li r1,0x2000 |
58ea142f | 368 | mtspr SPRN_IVOR15,r1 /* Debug */ |
0442ed86 WD |
369 | |
370 | /*----------------------------------------------------------------*/ | |
371 | /* Configure cache regions */ | |
372 | /*----------------------------------------------------------------*/ | |
58ea142f MF |
373 | mtspr SPRN_INV0,r0 |
374 | mtspr SPRN_INV1,r0 | |
375 | mtspr SPRN_INV2,r0 | |
376 | mtspr SPRN_INV3,r0 | |
377 | mtspr SPRN_DNV0,r0 | |
378 | mtspr SPRN_DNV1,r0 | |
379 | mtspr SPRN_DNV2,r0 | |
380 | mtspr SPRN_DNV3,r0 | |
381 | mtspr SPRN_ITV0,r0 | |
382 | mtspr SPRN_ITV1,r0 | |
383 | mtspr SPRN_ITV2,r0 | |
384 | mtspr SPRN_ITV3,r0 | |
385 | mtspr SPRN_DTV0,r0 | |
386 | mtspr SPRN_DTV1,r0 | |
387 | mtspr SPRN_DTV2,r0 | |
388 | mtspr SPRN_DTV3,r0 | |
0442ed86 WD |
389 | |
390 | /*----------------------------------------------------------------*/ | |
391 | /* Cache victim limits */ | |
392 | /*----------------------------------------------------------------*/ | |
393 | /* floors 0, ceiling max to use the entire cache -- nothing locked | |
394 | */ | |
395 | lis r1,0x0001 | |
396 | ori r1,r1,0xf800 | |
58ea142f MF |
397 | mtspr SPRN_IVLIM,r1 |
398 | mtspr SPRN_DVLIM,r1 | |
0442ed86 | 399 | |
6c5879f3 MB |
400 | /*----------------------------------------------------------------+ |
401 | |Initialize MMUCR[STID] = 0. | |
402 | +-----------------------------------------------------------------*/ | |
58ea142f | 403 | mfspr r0,SPRN_MMUCR |
6c5879f3 MB |
404 | addis r1,0,0xFFFF |
405 | ori r1,r1,0xFF00 | |
406 | and r0,r0,r1 | |
58ea142f | 407 | mtspr SPRN_MMUCR,r0 |
6c5879f3 | 408 | |
0442ed86 WD |
409 | /*----------------------------------------------------------------*/ |
410 | /* Clear all TLB entries -- TID = 0, TS = 0 */ | |
411 | /*----------------------------------------------------------------*/ | |
6c5879f3 | 412 | addis r0,0,0x0000 |
0a371ca0 | 413 | #ifdef CONFIG_SYS_RAMBOOT |
d873133f | 414 | li r4,0 /* Start with TLB #0 */ |
0a371ca0 SR |
415 | #else |
416 | li r4,1 /* Start with TLB #1 */ | |
417 | #endif | |
418 | li r1,64 /* 64 TLB entries */ | |
419 | sub r1,r1,r4 /* calculate last TLB # */ | |
420 | mtctr r1 | |
d873133f SR |
421 | rsttlb: |
422 | #ifdef CONFIG_SYS_RAMBOOT | |
423 | tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ | |
424 | rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ | |
425 | beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ | |
426 | #endif | |
427 | tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ | |
428 | tlbwe r0,r4,1 | |
429 | tlbwe r0,r4,2 | |
430 | tlbnxt: addi r4,r4,1 /* Next TLB */ | |
6c5879f3 | 431 | bdnz rsttlb |
0442ed86 WD |
432 | |
433 | /*----------------------------------------------------------------*/ | |
434 | /* TLB entry setup -- step thru tlbtab */ | |
435 | /*----------------------------------------------------------------*/ | |
2a72e9ed | 436 | #if defined(CONFIG_440SPE_REVA) |
692519b1 RJ |
437 | /*----------------------------------------------------------------*/ |
438 | /* We have different TLB tables for revA and rev B of 440SPe */ | |
439 | /*----------------------------------------------------------------*/ | |
440 | mfspr r1, PVR | |
441 | lis r0,0x5342 | |
442 | ori r0,r0,0x1891 | |
443 | cmpw r7,r1,r0 | |
444 | bne r7,..revA | |
445 | bl tlbtabB | |
446 | b ..goon | |
447 | ..revA: | |
448 | bl tlbtabA | |
449 | ..goon: | |
450 | #else | |
0442ed86 | 451 | bl tlbtab /* Get tlbtab pointer */ |
692519b1 | 452 | #endif |
0442ed86 WD |
453 | mr r5,r0 |
454 | li r1,0x003f /* 64 TLB entries max */ | |
455 | mtctr r1 | |
456 | li r4,0 /* TLB # */ | |
457 | ||
458 | addi r5,r5,-4 | |
d873133f SR |
459 | 1: |
460 | #ifdef CONFIG_SYS_RAMBOOT | |
461 | tlbre r3,r4,0 /* Read contents from TLB word #0 */ | |
462 | rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ | |
463 | bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ | |
464 | #endif | |
465 | lwzu r0,4(r5) | |
0442ed86 WD |
466 | cmpwi r0,0 |
467 | beq 2f /* 0 marks end */ | |
468 | lwzu r1,4(r5) | |
469 | lwzu r2,4(r5) | |
470 | tlbwe r0,r4,0 /* TLB Word 0 */ | |
471 | tlbwe r1,r4,1 /* TLB Word 1 */ | |
472 | tlbwe r2,r4,2 /* TLB Word 2 */ | |
d873133f | 473 | tlbnx2: addi r4,r4,1 /* Next TLB */ |
0442ed86 WD |
474 | bdnz 1b |
475 | ||
476 | /*----------------------------------------------------------------*/ | |
477 | /* Continue from 'normal' start */ | |
478 | /*----------------------------------------------------------------*/ | |
887e2ec9 | 479 | 2: |
887e2ec9 | 480 | bl 3f |
0442ed86 WD |
481 | b _start |
482 | ||
483 | 3: li r0,0 | |
58ea142f | 484 | mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ |
0442ed86 | 485 | mflr r1 |
58ea142f | 486 | mtspr SPRN_SRR0,r1 |
0442ed86 | 487 | rfi |
b867d705 | 488 | #endif /* CONFIG_440 */ |
0442ed86 WD |
489 | |
490 | /* | |
491 | * r3 - 1st arg to board_init(): IMMP pointer | |
492 | * r4 - 2nd arg to board_init(): boot flag | |
493 | */ | |
345b77ba | 494 | #if !defined(CONFIG_SPL_BUILD) |
0442ed86 WD |
495 | .text |
496 | .long 0x27051956 /* U-Boot Magic Number */ | |
497 | .globl version_string | |
498 | version_string: | |
09c2e90c | 499 | .ascii U_BOOT_VERSION_STRING, "\0" |
0442ed86 | 500 | |
0442ed86 | 501 | . = EXC_OFF_SYS_RESET |
efa35cf1 GB |
502 | .globl _start_of_vectors |
503 | _start_of_vectors: | |
504 | ||
505 | /* Critical input. */ | |
506 | CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) | |
507 | ||
508 | #ifdef CONFIG_440 | |
509 | /* Machine check */ | |
83b4cfa3 | 510 | MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 | 511 | #else |
83b4cfa3 | 512 | CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) |
efa35cf1 GB |
513 | #endif /* CONFIG_440 */ |
514 | ||
515 | /* Data Storage exception. */ | |
516 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
517 | ||
518 | /* Instruction Storage exception. */ | |
519 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
520 | ||
521 | /* External Interrupt exception. */ | |
522 | STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) | |
523 | ||
524 | /* Alignment exception. */ | |
525 | . = 0x600 | |
526 | Alignment: | |
527 | EXCEPTION_PROLOG(SRR0, SRR1) | |
528 | mfspr r4,DAR | |
529 | stw r4,_DAR(r21) | |
530 | mfspr r5,DSISR | |
531 | stw r5,_DSISR(r21) | |
532 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 | 533 | EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) |
efa35cf1 GB |
534 | |
535 | /* Program check exception */ | |
536 | . = 0x700 | |
537 | ProgramCheck: | |
538 | EXCEPTION_PROLOG(SRR0, SRR1) | |
539 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 JT |
540 | EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, |
541 | MSR_KERNEL, COPY_EE) | |
efa35cf1 GB |
542 | |
543 | #ifdef CONFIG_440 | |
544 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
545 | STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) | |
546 | STD_EXCEPTION(0xa00, APU, UnknownException) | |
df8a24cd | 547 | #endif |
efa35cf1 GB |
548 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) |
549 | ||
550 | #ifdef CONFIG_440 | |
551 | STD_EXCEPTION(0x1300, DataTLBError, UnknownException) | |
552 | STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) | |
553 | #else | |
554 | STD_EXCEPTION(0x1000, PIT, DecrementerPITException) | |
555 | STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) | |
556 | STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) | |
557 | #endif | |
558 | CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) | |
559 | ||
560 | .globl _end_of_vectors | |
561 | _end_of_vectors: | |
562 | . = _START_OFFSET | |
887e2ec9 | 563 | #endif |
0442ed86 WD |
564 | .globl _start |
565 | _start: | |
566 | ||
98f99e9f SR |
567 | #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
568 | /* | |
569 | * This is the entry of the real U-Boot from a board port | |
570 | * that supports SPL booting on the PPC4xx. We only need | |
571 | * to call board_init_f() here. Everything else has already | |
572 | * been done in the SPL u-boot version. | |
573 | */ | |
574 | GET_GOT /* initialize GOT access */ | |
575 | bl board_init_f /* run 1st part of board init code (in Flash)*/ | |
576 | /* NOTREACHED - board_init_f() does not return */ | |
577 | #endif | |
578 | ||
0442ed86 WD |
579 | /*****************************************************************************/ |
580 | #if defined(CONFIG_440) | |
581 | ||
582 | /*----------------------------------------------------------------*/ | |
583 | /* Clear and set up some registers. */ | |
584 | /*----------------------------------------------------------------*/ | |
585 | li r0,0x0000 | |
586 | lis r1,0xffff | |
58ea142f MF |
587 | mtspr SPRN_DEC,r0 /* prevent dec exceptions */ |
588 | mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ | |
589 | mtspr SPRN_TBWU,r0 | |
590 | mtspr SPRN_TSR,r1 /* clear all timer exception status */ | |
591 | mtspr SPRN_TCR,r0 /* disable all */ | |
592 | mtspr SPRN_ESR,r0 /* clear exception syndrome register */ | |
0442ed86 | 593 | mtxer r0 /* clear integer exception register */ |
0442ed86 WD |
594 | |
595 | /*----------------------------------------------------------------*/ | |
596 | /* Debug setup -- some (not very good) ice's need an event*/ | |
6d0f6bcf | 597 | /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ |
0442ed86 WD |
598 | /* value you need in this case 0x8cff 0000 should do the trick */ |
599 | /*----------------------------------------------------------------*/ | |
6d0f6bcf | 600 | #if defined(CONFIG_SYS_INIT_DBCR) |
0442ed86 WD |
601 | lis r1,0xffff |
602 | ori r1,r1,0xffff | |
58ea142f | 603 | mtspr SPRN_DBSR,r1 /* Clear all status bits */ |
6d0f6bcf JCPV |
604 | lis r0,CONFIG_SYS_INIT_DBCR@h |
605 | ori r0,r0,CONFIG_SYS_INIT_DBCR@l | |
58ea142f | 606 | mtspr SPRN_DBCR0,r0 |
0442ed86 WD |
607 | isync |
608 | #endif | |
609 | ||
610 | /*----------------------------------------------------------------*/ | |
611 | /* Setup the internal SRAM */ | |
612 | /*----------------------------------------------------------------*/ | |
613 | li r0,0 | |
887e2ec9 | 614 | |
6d0f6bcf | 615 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
c157d8e2 | 616 | /* Clear Dcache to use as RAM */ |
6d0f6bcf JCPV |
617 | addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h |
618 | ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l | |
553f0982 WD |
619 | addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h |
620 | ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l | |
c157d8e2 | 621 | rlwinm. r5,r4,0,27,31 |
f901a83b WD |
622 | rlwinm r5,r4,27,5,31 |
623 | beq ..d_ran | |
624 | addi r5,r5,0x0001 | |
c157d8e2 | 625 | ..d_ran: |
f901a83b | 626 | mtctr r5 |
c157d8e2 | 627 | ..d_ag: |
f901a83b WD |
628 | dcbz r0,r3 |
629 | addi r3,r3,32 | |
630 | bdnz ..d_ag | |
e02c521d SR |
631 | |
632 | /* | |
633 | * Lock the init-ram/stack in d-cache, so that other regions | |
634 | * may use d-cache as well | |
635 | * Note, that this current implementation locks exactly 4k | |
636 | * of d-cache, so please make sure that you don't define a | |
637 | * bigger init-ram area. Take a look at the lwmon5 440EPx | |
638 | * implementation as a reference. | |
639 | */ | |
640 | msync | |
641 | isync | |
642 | /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ | |
643 | lis r1,0x0201 | |
644 | ori r1,r1,0xf808 | |
58ea142f | 645 | mtspr SPRN_DVLIM,r1 |
e02c521d SR |
646 | lis r1,0x0808 |
647 | ori r1,r1,0x0808 | |
58ea142f MF |
648 | mtspr SPRN_DNV0,r1 |
649 | mtspr SPRN_DNV1,r1 | |
650 | mtspr SPRN_DNV2,r1 | |
651 | mtspr SPRN_DNV3,r1 | |
652 | mtspr SPRN_DTV0,r1 | |
653 | mtspr SPRN_DTV1,r1 | |
654 | mtspr SPRN_DTV2,r1 | |
655 | mtspr SPRN_DTV3,r1 | |
e02c521d SR |
656 | msync |
657 | isync | |
6d0f6bcf | 658 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
887e2ec9 SR |
659 | |
660 | /* 440EP & 440GR are only 440er PPC's without internal SRAM */ | |
661 | #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) | |
662 | /* not all PPC's have internal SRAM usable as L2-cache */ | |
2801b2d2 SR |
663 | #if defined(CONFIG_440GX) || \ |
664 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ | |
7d307936 | 665 | defined(CONFIG_460SX) |
b14ca4b6 | 666 | mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ |
9ed3246e | 667 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
ddf45cc7 DM |
668 | lis r1, 0x0000 |
669 | ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ | |
670 | mtdcr L2_CACHE_CFG,r1 | |
ba56f625 | 671 | #endif |
0442ed86 | 672 | |
887e2ec9 | 673 | lis r2,0x7fff |
0442ed86 | 674 | ori r2,r2,0xffff |
b14ca4b6 | 675 | mfdcr r1,ISRAM0_DPC |
0442ed86 | 676 | and r1,r1,r2 /* Disable parity check */ |
b14ca4b6 DM |
677 | mtdcr ISRAM0_DPC,r1 |
678 | mfdcr r1,ISRAM0_PMEG | |
887e2ec9 | 679 | and r1,r1,r2 /* Disable pwr mgmt */ |
b14ca4b6 | 680 | mtdcr ISRAM0_PMEG,r1 |
0442ed86 WD |
681 | |
682 | lis r1,0x8000 /* BAS = 8000_0000 */ | |
6e7fb6ea | 683 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) |
ba56f625 | 684 | ori r1,r1,0x0980 /* first 64k */ |
b14ca4b6 | 685 | mtdcr ISRAM0_SB0CR,r1 |
ba56f625 WD |
686 | lis r1,0x8001 |
687 | ori r1,r1,0x0980 /* second 64k */ | |
b14ca4b6 | 688 | mtdcr ISRAM0_SB1CR,r1 |
ba56f625 WD |
689 | lis r1, 0x8002 |
690 | ori r1,r1, 0x0980 /* third 64k */ | |
b14ca4b6 | 691 | mtdcr ISRAM0_SB2CR,r1 |
ba56f625 WD |
692 | lis r1, 0x8003 |
693 | ori r1,r1, 0x0980 /* fourth 64k */ | |
b14ca4b6 | 694 | mtdcr ISRAM0_SB3CR,r1 |
1b8fec13 | 695 | #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ |
9ed3246e | 696 | defined(CONFIG_460GT) |
ddf45cc7 | 697 | lis r1,0x0000 /* BAS = X_0000_0000 */ |
6c5879f3 | 698 | ori r1,r1,0x0984 /* first 64k */ |
b14ca4b6 | 699 | mtdcr ISRAM0_SB0CR,r1 |
6c5879f3 MB |
700 | lis r1,0x0001 |
701 | ori r1,r1,0x0984 /* second 64k */ | |
b14ca4b6 | 702 | mtdcr ISRAM0_SB1CR,r1 |
6c5879f3 MB |
703 | lis r1, 0x0002 |
704 | ori r1,r1, 0x0984 /* third 64k */ | |
b14ca4b6 | 705 | mtdcr ISRAM0_SB2CR,r1 |
6c5879f3 MB |
706 | lis r1, 0x0003 |
707 | ori r1,r1, 0x0984 /* fourth 64k */ | |
b14ca4b6 | 708 | mtdcr ISRAM0_SB3CR,r1 |
9ed3246e | 709 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
ddf45cc7 DM |
710 | lis r2,0x7fff |
711 | ori r2,r2,0xffff | |
712 | mfdcr r1,ISRAM1_DPC | |
713 | and r1,r1,r2 /* Disable parity check */ | |
455ae7e8 | 714 | mtdcr ISRAM1_DPC,r1 |
ddf45cc7 DM |
715 | mfdcr r1,ISRAM1_PMEG |
716 | and r1,r1,r2 /* Disable pwr mgmt */ | |
717 | mtdcr ISRAM1_PMEG,r1 | |
718 | ||
719 | lis r1,0x0004 /* BAS = 4_0004_0000 */ | |
1b8fec13 | 720 | ori r1,r1,ISRAM1_SIZE /* ocm size */ |
ddf45cc7 DM |
721 | mtdcr ISRAM1_SB0CR,r1 |
722 | #endif | |
7d307936 FK |
723 | #elif defined(CONFIG_460SX) |
724 | lis r1,0x0000 /* BAS = 0000_0000 */ | |
725 | ori r1,r1,0x0B84 /* first 128k */ | |
b14ca4b6 | 726 | mtdcr ISRAM0_SB0CR,r1 |
7d307936 FK |
727 | lis r1,0x0001 |
728 | ori r1,r1,0x0B84 /* second 128k */ | |
b14ca4b6 | 729 | mtdcr ISRAM0_SB1CR,r1 |
7d307936 FK |
730 | lis r1, 0x0002 |
731 | ori r1,r1, 0x0B84 /* third 128k */ | |
b14ca4b6 | 732 | mtdcr ISRAM0_SB2CR,r1 |
7d307936 FK |
733 | lis r1, 0x0003 |
734 | ori r1,r1, 0x0B84 /* fourth 128k */ | |
b14ca4b6 | 735 | mtdcr ISRAM0_SB3CR,r1 |
887e2ec9 | 736 | #elif defined(CONFIG_440GP) |
0442ed86 | 737 | ori r1,r1,0x0380 /* 8k rw */ |
b14ca4b6 DM |
738 | mtdcr ISRAM0_SB0CR,r1 |
739 | mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ | |
c157d8e2 | 740 | #endif |
887e2ec9 | 741 | #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ |
0442ed86 WD |
742 | |
743 | /*----------------------------------------------------------------*/ | |
744 | /* Setup the stack in internal SRAM */ | |
745 | /*----------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
746 | lis r1,CONFIG_SYS_INIT_RAM_ADDR@h |
747 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l | |
0442ed86 WD |
748 | li r0,0 |
749 | stwu r0,-4(r1) | |
750 | stwu r0,-4(r1) /* Terminate call chain */ | |
751 | ||
752 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
753 | lis r0,RESET_VECTOR@h /* Address of reset vector */ | |
754 | ori r0,r0, RESET_VECTOR@l | |
755 | stwu r1,-8(r1) /* Save back chain and move SP */ | |
756 | stw r0,+12(r1) /* Save return addr (underflow vect) */ | |
8c4734e9 | 757 | |
98f99e9f | 758 | #ifndef CONFIG_SPL_BUILD |
0442ed86 | 759 | GET_GOT |
98f99e9f | 760 | #endif |
5568e613 SR |
761 | |
762 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ | |
36ec4c02 SG |
763 | #ifdef CONFIG_SYS_GENERIC_BOARD |
764 | mr r3, r1 | |
765 | bl board_init_f_mem | |
766 | mr r1, r3 | |
767 | li r0,0 | |
768 | stwu r0, -4(r1) | |
769 | stwu r0, -4(r1) | |
770 | #endif | |
771 | li r3, 0 | |
0442ed86 | 772 | bl board_init_f |
52ebd9c1 | 773 | /* NOTREACHED - board_init_f() does not return */ |
0442ed86 WD |
774 | |
775 | #endif /* CONFIG_440 */ | |
776 | ||
0442ed86 | 777 | /*****************************************************************************/ |
3fb85889 | 778 | #if defined(CONFIG_405GP) || \ |
e01bd218 | 779 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ |
dbbd1257 | 780 | defined(CONFIG_405EX) || defined(CONFIG_405) |
0442ed86 WD |
781 | /*----------------------------------------------------------------------- */ |
782 | /* Clear and set up some registers. */ | |
783 | /*----------------------------------------------------------------------- */ | |
784 | addi r4,r0,0x0000 | |
dbbd1257 | 785 | #if !defined(CONFIG_405EX) |
58ea142f | 786 | mtspr SPRN_SGR,r4 |
dbbd1257 SR |
787 | #else |
788 | /* | |
789 | * On 405EX, completely clearing the SGR leads to PPC hangup | |
790 | * upon PCIe configuration access. The PCIe memory regions | |
791 | * need to be guarded! | |
792 | */ | |
793 | lis r3,0x0000 | |
794 | ori r3,r3,0x7FFC | |
58ea142f | 795 | mtspr SPRN_SGR,r3 |
dbbd1257 | 796 | #endif |
58ea142f | 797 | mtspr SPRN_DCWR,r4 |
0442ed86 WD |
798 | mtesr r4 /* clear Exception Syndrome Reg */ |
799 | mttcr r4 /* clear Timer Control Reg */ | |
800 | mtxer r4 /* clear Fixed-Point Exception Reg */ | |
801 | mtevpr r4 /* clear Exception Vector Prefix Reg */ | |
0442ed86 WD |
802 | addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ |
803 | /* dbsr is cleared by setting bits to 1) */ | |
804 | mtdbsr r4 /* clear/reset the dbsr */ | |
805 | ||
c821b5f1 | 806 | /* Invalidate the i- and d-caches. */ |
0442ed86 WD |
807 | bl invalidate_icache |
808 | bl invalidate_dcache | |
809 | ||
c821b5f1 | 810 | /* Set-up icache cacheability. */ |
6d0f6bcf JCPV |
811 | lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h |
812 | ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l | |
c821b5f1 | 813 | mticcr r4 |
0442ed86 WD |
814 | isync |
815 | ||
c821b5f1 | 816 | /* Set-up dcache cacheability. */ |
6d0f6bcf JCPV |
817 | lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h |
818 | ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l | |
c821b5f1 | 819 | mtdccr r4 |
0442ed86 | 820 | |
1f4d5326 RR |
821 | #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ |
822 | && !defined (CONFIG_XILINX_405) | |
0442ed86 WD |
823 | /*----------------------------------------------------------------------- */ |
824 | /* Tune the speed and size for flash CS0 */ | |
825 | /*----------------------------------------------------------------------- */ | |
826 | bl ext_bus_cntlr_init | |
827 | #endif | |
64852d09 | 828 | |
6d0f6bcf | 829 | #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) |
dbbd1257 | 830 | /* |
c821b5f1 GE |
831 | * For boards that don't have OCM and can't use the data cache |
832 | * for their primordial stack, setup stack here directly after the | |
833 | * SDRAM is initialized in ext_bus_cntlr_init. | |
dbbd1257 | 834 | */ |
6d0f6bcf JCPV |
835 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
836 | ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ | |
dbbd1257 SR |
837 | |
838 | li r0, 0 /* Make room for stack frame header and */ | |
839 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
840 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
841 | /* | |
842 | * Set up a dummy frame to store reset vector as return address. | |
843 | * this causes stack underflow to reset board. | |
844 | */ | |
845 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
846 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
847 | ori r0, r0, RESET_VECTOR@l | |
848 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
849 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 850 | #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ |
0442ed86 | 851 | |
b867d705 SR |
852 | #if defined(CONFIG_405EP) |
853 | /*----------------------------------------------------------------------- */ | |
854 | /* DMA Status, clear to come up clean */ | |
855 | /*----------------------------------------------------------------------- */ | |
53677ef1 | 856 | addis r3,r0, 0xFFFF /* Clear all existing DMA status */ |
f901a83b | 857 | ori r3,r3, 0xFFFF |
d1c3b275 | 858 | mtdcr DMASR, r3 |
b867d705 | 859 | |
53677ef1 | 860 | bl ppc405ep_init /* do ppc405ep specific init */ |
b867d705 SR |
861 | #endif /* CONFIG_405EP */ |
862 | ||
6d0f6bcf | 863 | #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) |
e01bd218 SR |
864 | #if defined(CONFIG_405EZ) |
865 | /******************************************************************** | |
866 | * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 | |
867 | *******************************************************************/ | |
868 | /* | |
869 | * We can map the OCM on the PLB3, so map it at | |
6d0f6bcf | 870 | * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 |
e01bd218 | 871 | */ |
6d0f6bcf JCPV |
872 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
873 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
df8a24cd | 874 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
d1c3b275 | 875 | mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ |
e01bd218 | 876 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
d1c3b275 | 877 | mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ |
e01bd218 SR |
878 | isync |
879 | ||
6d0f6bcf JCPV |
880 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
881 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
83b4cfa3 | 882 | ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ |
d1c3b275 SR |
883 | mtdcr OCM0_DSRC1, r3 /* Set Data Side */ |
884 | mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ | |
e01bd218 | 885 | ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ |
d1c3b275 SR |
886 | mtdcr OCM0_DSRC2, r3 /* Set Data Side */ |
887 | mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ | |
83b4cfa3 | 888 | addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ |
d1c3b275 | 889 | mtdcr OCM0_DISDPC,r3 |
e01bd218 SR |
890 | |
891 | isync | |
3cb86f3e | 892 | #else /* CONFIG_405EZ */ |
0442ed86 WD |
893 | /******************************************************************** |
894 | * Setup OCM - On Chip Memory | |
895 | *******************************************************************/ | |
896 | /* Setup OCM */ | |
8bde7f77 WD |
897 | lis r0, 0x7FFF |
898 | ori r0, r0, 0xFFFF | |
d1c3b275 SR |
899 | mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ |
900 | mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ | |
3cb86f3e SR |
901 | and r3, r3, r0 /* disable data-side IRAM */ |
902 | and r4, r4, r0 /* disable data-side IRAM */ | |
d1c3b275 SR |
903 | mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ |
904 | mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ | |
8bde7f77 | 905 | isync |
0442ed86 | 906 | |
6d0f6bcf JCPV |
907 | lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ |
908 | ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l | |
d1c3b275 | 909 | mtdcr OCM0_DSARC, r3 |
0442ed86 | 910 | addis r4, 0, 0xC000 /* OCM data area enabled */ |
d1c3b275 | 911 | mtdcr OCM0_DSCNTL, r4 |
8bde7f77 | 912 | isync |
e01bd218 | 913 | #endif /* CONFIG_405EZ */ |
0442ed86 WD |
914 | #endif |
915 | ||
916 | /*----------------------------------------------------------------------- */ | |
917 | /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ | |
918 | /*----------------------------------------------------------------------- */ | |
6d0f6bcf | 919 | #ifdef CONFIG_SYS_INIT_DCACHE_CS |
c821b5f1 | 920 | li r4, PBxAP |
d1c3b275 | 921 | mtdcr EBC0_CFGADDR, r4 |
6d0f6bcf JCPV |
922 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h |
923 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l | |
d1c3b275 | 924 | mtdcr EBC0_CFGDATA, r4 |
c821b5f1 GE |
925 | |
926 | addi r4, 0, PBxCR | |
d1c3b275 | 927 | mtdcr EBC0_CFGADDR, r4 |
6d0f6bcf JCPV |
928 | lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h |
929 | ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l | |
d1c3b275 | 930 | mtdcr EBC0_CFGDATA, r4 |
c821b5f1 GE |
931 | |
932 | /* | |
933 | * Enable the data cache for the 128MB storage access control region | |
6d0f6bcf | 934 | * at CONFIG_SYS_INIT_RAM_ADDR. |
c821b5f1 GE |
935 | */ |
936 | mfdccr r4 | |
6d0f6bcf JCPV |
937 | oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
938 | ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
0442ed86 WD |
939 | mtdccr r4 |
940 | ||
c821b5f1 GE |
941 | /* |
942 | * Preallocate data cache lines to be used to avoid a subsequent | |
943 | * cache miss and an ensuing machine check exception when exceptions | |
944 | * are enabled. | |
945 | */ | |
946 | li r0, 0 | |
0442ed86 | 947 | |
6d0f6bcf JCPV |
948 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
949 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
0442ed86 | 950 | |
553f0982 WD |
951 | lis r4, CONFIG_SYS_INIT_RAM_SIZE@h |
952 | ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l | |
c821b5f1 GE |
953 | |
954 | /* | |
955 | * Convert the size, in bytes, to the number of cache lines/blocks | |
956 | * to preallocate. | |
957 | */ | |
958 | clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) | |
959 | srwi r5, r4, L1_CACHE_SHIFT | |
960 | beq ..load_counter | |
961 | addi r5, r5, 0x0001 | |
962 | ..load_counter: | |
963 | mtctr r5 | |
964 | ||
965 | /* Preallocate the computed number of cache blocks. */ | |
966 | ..alloc_dcache_block: | |
967 | dcba r0, r3 | |
968 | addi r3, r3, L1_CACHE_BYTES | |
969 | bdnz ..alloc_dcache_block | |
970 | sync | |
971 | ||
972 | /* | |
973 | * Load the initial stack pointer and data area and convert the size, | |
974 | * in bytes, to the number of words to initialize to a known value. | |
975 | */ | |
6d0f6bcf JCPV |
976 | lis r1, CONFIG_SYS_INIT_RAM_ADDR@h |
977 | ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l | |
c821b5f1 | 978 | |
553f0982 WD |
979 | lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h |
980 | ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l | |
0442ed86 WD |
981 | mtctr r4 |
982 | ||
6d0f6bcf | 983 | lis r2, CONFIG_SYS_INIT_RAM_ADDR@h |
553f0982 | 984 | ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l |
0442ed86 | 985 | |
6d0f6bcf JCPV |
986 | lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h |
987 | ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l | |
0442ed86 WD |
988 | |
989 | ..stackloop: | |
c821b5f1 | 990 | stwu r4, -4(r2) |
0442ed86 WD |
991 | bdnz ..stackloop |
992 | ||
c821b5f1 GE |
993 | /* |
994 | * Make room for stack frame header and clear final stack frame so | |
995 | * that stack backtraces terminate cleanly. | |
996 | */ | |
997 | stwu r0, -4(r1) | |
998 | stwu r0, -4(r1) | |
999 | ||
0442ed86 WD |
1000 | /* |
1001 | * Set up a dummy frame to store reset vector as return address. | |
1002 | * this causes stack underflow to reset board. | |
1003 | */ | |
1004 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1005 | addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ | |
1006 | ori r0, r0, RESET_VECTOR@l | |
1007 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1008 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
1009 | ||
6d0f6bcf JCPV |
1010 | #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ |
1011 | (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) | |
0442ed86 WD |
1012 | /* |
1013 | * Stack in OCM. | |
1014 | */ | |
1015 | ||
1016 | /* Set up Stack at top of OCM */ | |
6d0f6bcf JCPV |
1017 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h |
1018 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l | |
0442ed86 WD |
1019 | |
1020 | /* Set up a zeroized stack frame so that backtrace works right */ | |
1021 | li r0, 0 | |
1022 | stwu r0, -4(r1) | |
1023 | stwu r0, -4(r1) | |
1024 | ||
1025 | /* | |
1026 | * Set up a dummy frame to store reset vector as return address. | |
1027 | * this causes stack underflow to reset board. | |
1028 | */ | |
1029 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1030 | lis r0, RESET_VECTOR@h /* Address of reset vector */ | |
1031 | ori r0, r0, RESET_VECTOR@l | |
1032 | stwu r1, -8(r1) /* Save back chain and move SP */ | |
1033 | stw r0, +12(r1) /* Save return addr (underflow vect) */ | |
6d0f6bcf | 1034 | #endif /* CONFIG_SYS_INIT_DCACHE_CS */ |
0442ed86 | 1035 | |
0442ed86 WD |
1036 | GET_GOT /* initialize GOT access */ |
1037 | ||
f901a83b | 1038 | bl cpu_init_f /* run low-level CPU init code (from Flash) */ |
36ec4c02 SG |
1039 | #ifdef CONFIG_SYS_GENERIC_BOARD |
1040 | mr r3, r1 | |
1041 | bl board_init_f_mem | |
1042 | mr r1, r3 | |
1043 | stwu r0, -4(r1) | |
1044 | stwu r0, -4(r1) | |
1045 | #endif | |
1046 | li r3, 0 | |
0442ed86 | 1047 | bl board_init_f /* run first part of init code (from Flash) */ |
52ebd9c1 PT |
1048 | /* NOTREACHED - board_init_f() does not return */ |
1049 | ||
3fb85889 | 1050 | #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */ |
12f34241 | 1051 | /*----------------------------------------------------------------------- */ |
0442ed86 WD |
1052 | |
1053 | ||
345b77ba | 1054 | #if !defined(CONFIG_SPL_BUILD) |
0442ed86 WD |
1055 | /* |
1056 | * This code finishes saving the registers to the exception frame | |
1057 | * and jumps to the appropriate handler for the exception. | |
1058 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
1059 | */ | |
1060 | .globl transfer_to_handler | |
1061 | transfer_to_handler: | |
1062 | stw r22,_NIP(r21) | |
1063 | lis r22,MSR_POW@h | |
1064 | andc r23,r23,r22 | |
1065 | stw r23,_MSR(r21) | |
1066 | SAVE_GPR(7, r21) | |
1067 | SAVE_4GPRS(8, r21) | |
1068 | SAVE_8GPRS(12, r21) | |
1069 | SAVE_8GPRS(24, r21) | |
0442ed86 WD |
1070 | mflr r23 |
1071 | andi. r24,r23,0x3f00 /* get vector offset */ | |
1072 | stw r24,TRAP(r21) | |
1073 | li r22,0 | |
1074 | stw r22,RESULT(r21) | |
1075 | mtspr SPRG2,r22 /* r1 is now kernel sp */ | |
0442ed86 WD |
1076 | lwz r24,0(r23) /* virtual address of handler */ |
1077 | lwz r23,4(r23) /* where to go when done */ | |
1078 | mtspr SRR0,r24 | |
1079 | mtspr SRR1,r20 | |
1080 | mtlr r23 | |
1081 | SYNC | |
1082 | rfi /* jump to handler, enable MMU */ | |
1083 | ||
1084 | int_return: | |
1085 | mfmsr r28 /* Disable interrupts */ | |
1086 | li r4,0 | |
1087 | ori r4,r4,MSR_EE | |
1088 | andc r28,r28,r4 | |
1089 | SYNC /* Some chip revs need this... */ | |
1090 | mtmsr r28 | |
1091 | SYNC | |
1092 | lwz r2,_CTR(r1) | |
1093 | lwz r0,_LINK(r1) | |
1094 | mtctr r2 | |
1095 | mtlr r0 | |
1096 | lwz r2,_XER(r1) | |
1097 | lwz r0,_CCR(r1) | |
1098 | mtspr XER,r2 | |
1099 | mtcrf 0xFF,r0 | |
1100 | REST_10GPRS(3, r1) | |
1101 | REST_10GPRS(13, r1) | |
1102 | REST_8GPRS(23, r1) | |
1103 | REST_GPR(31, r1) | |
1104 | lwz r2,_NIP(r1) /* Restore environment */ | |
1105 | lwz r0,_MSR(r1) | |
1106 | mtspr SRR0,r2 | |
1107 | mtspr SRR1,r0 | |
1108 | lwz r0,GPR0(r1) | |
1109 | lwz r2,GPR2(r1) | |
1110 | lwz r1,GPR1(r1) | |
1111 | SYNC | |
1112 | rfi | |
1113 | ||
1114 | crit_return: | |
1115 | mfmsr r28 /* Disable interrupts */ | |
1116 | li r4,0 | |
1117 | ori r4,r4,MSR_EE | |
1118 | andc r28,r28,r4 | |
1119 | SYNC /* Some chip revs need this... */ | |
1120 | mtmsr r28 | |
1121 | SYNC | |
1122 | lwz r2,_CTR(r1) | |
1123 | lwz r0,_LINK(r1) | |
1124 | mtctr r2 | |
1125 | mtlr r0 | |
1126 | lwz r2,_XER(r1) | |
1127 | lwz r0,_CCR(r1) | |
1128 | mtspr XER,r2 | |
1129 | mtcrf 0xFF,r0 | |
1130 | REST_10GPRS(3, r1) | |
1131 | REST_10GPRS(13, r1) | |
1132 | REST_8GPRS(23, r1) | |
1133 | REST_GPR(31, r1) | |
1134 | lwz r2,_NIP(r1) /* Restore environment */ | |
1135 | lwz r0,_MSR(r1) | |
58ea142f MF |
1136 | mtspr SPRN_CSRR0,r2 |
1137 | mtspr SPRN_CSRR1,r0 | |
0442ed86 WD |
1138 | lwz r0,GPR0(r1) |
1139 | lwz r2,GPR2(r1) | |
1140 | lwz r1,GPR1(r1) | |
1141 | SYNC | |
1142 | rfci | |
1143 | ||
efa35cf1 GB |
1144 | #ifdef CONFIG_440 |
1145 | mck_return: | |
83b4cfa3 WD |
1146 | mfmsr r28 /* Disable interrupts */ |
1147 | li r4,0 | |
1148 | ori r4,r4,MSR_EE | |
1149 | andc r28,r28,r4 | |
1150 | SYNC /* Some chip revs need this... */ | |
1151 | mtmsr r28 | |
1152 | SYNC | |
1153 | lwz r2,_CTR(r1) | |
1154 | lwz r0,_LINK(r1) | |
1155 | mtctr r2 | |
1156 | mtlr r0 | |
1157 | lwz r2,_XER(r1) | |
1158 | lwz r0,_CCR(r1) | |
1159 | mtspr XER,r2 | |
1160 | mtcrf 0xFF,r0 | |
1161 | REST_10GPRS(3, r1) | |
1162 | REST_10GPRS(13, r1) | |
1163 | REST_8GPRS(23, r1) | |
1164 | REST_GPR(31, r1) | |
1165 | lwz r2,_NIP(r1) /* Restore environment */ | |
1166 | lwz r0,_MSR(r1) | |
58ea142f MF |
1167 | mtspr SPRN_MCSRR0,r2 |
1168 | mtspr SPRN_MCSRR1,r0 | |
83b4cfa3 WD |
1169 | lwz r0,GPR0(r1) |
1170 | lwz r2,GPR2(r1) | |
1171 | lwz r1,GPR1(r1) | |
1172 | SYNC | |
1173 | rfmci | |
efa35cf1 GB |
1174 | #endif /* CONFIG_440 */ |
1175 | ||
1176 | ||
0442ed86 WD |
1177 | .globl get_pvr |
1178 | get_pvr: | |
1179 | mfspr r3, PVR | |
1180 | blr | |
1181 | ||
0442ed86 WD |
1182 | /*------------------------------------------------------------------------------- */ |
1183 | /* Function: out16 */ | |
1184 | /* Description: Output 16 bits */ | |
1185 | /*------------------------------------------------------------------------------- */ | |
1186 | .globl out16 | |
1187 | out16: | |
1188 | sth r4,0x0000(r3) | |
1189 | blr | |
1190 | ||
1191 | /*------------------------------------------------------------------------------- */ | |
1192 | /* Function: out16r */ | |
1193 | /* Description: Byte reverse and output 16 bits */ | |
1194 | /*------------------------------------------------------------------------------- */ | |
1195 | .globl out16r | |
1196 | out16r: | |
1197 | sthbrx r4,r0,r3 | |
1198 | blr | |
1199 | ||
0442ed86 WD |
1200 | /*------------------------------------------------------------------------------- */ |
1201 | /* Function: out32r */ | |
1202 | /* Description: Byte reverse and output 32 bits */ | |
1203 | /*------------------------------------------------------------------------------- */ | |
1204 | .globl out32r | |
1205 | out32r: | |
1206 | stwbrx r4,r0,r3 | |
1207 | blr | |
1208 | ||
1209 | /*------------------------------------------------------------------------------- */ | |
1210 | /* Function: in16 */ | |
1211 | /* Description: Input 16 bits */ | |
1212 | /*------------------------------------------------------------------------------- */ | |
1213 | .globl in16 | |
1214 | in16: | |
1215 | lhz r3,0x0000(r3) | |
1216 | blr | |
1217 | ||
1218 | /*------------------------------------------------------------------------------- */ | |
1219 | /* Function: in16r */ | |
1220 | /* Description: Input 16 bits and byte reverse */ | |
1221 | /*------------------------------------------------------------------------------- */ | |
1222 | .globl in16r | |
1223 | in16r: | |
1224 | lhbrx r3,r0,r3 | |
1225 | blr | |
1226 | ||
0442ed86 WD |
1227 | /*------------------------------------------------------------------------------- */ |
1228 | /* Function: in32r */ | |
1229 | /* Description: Input 32 bits and byte reverse */ | |
1230 | /*------------------------------------------------------------------------------- */ | |
1231 | .globl in32r | |
1232 | in32r: | |
1233 | lwbrx r3,r0,r3 | |
1234 | blr | |
1235 | ||
98f99e9f | 1236 | #if !defined(CONFIG_SPL_BUILD) |
0442ed86 WD |
1237 | /* |
1238 | * void relocate_code (addr_sp, gd, addr_moni) | |
1239 | * | |
1240 | * This "function" does not return, instead it continues in RAM | |
1241 | * after relocating the monitor code. | |
1242 | * | |
c821b5f1 GE |
1243 | * r3 = Relocated stack pointer |
1244 | * r4 = Relocated global data pointer | |
1245 | * r5 = Relocated text pointer | |
0442ed86 WD |
1246 | */ |
1247 | .globl relocate_code | |
1248 | relocate_code: | |
6d0f6bcf | 1249 | #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) |
9b94ac61 | 1250 | /* |
7920954b SR |
1251 | * We need to flush the initial global data (gd_t) and bd_info |
1252 | * before the dcache will be invalidated. | |
9b94ac61 SR |
1253 | */ |
1254 | ||
c821b5f1 GE |
1255 | /* Save registers */ |
1256 | mr r9, r3 | |
1257 | mr r10, r4 | |
1258 | mr r11, r5 | |
9b94ac61 | 1259 | |
7920954b SR |
1260 | /* |
1261 | * Flush complete dcache, this is faster than flushing the | |
1262 | * ranges for global_data and bd_info instead. | |
1263 | */ | |
1264 | bl flush_dcache | |
9b94ac61 | 1265 | |
6d0f6bcf | 1266 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
c821b5f1 GE |
1267 | /* |
1268 | * Undo the earlier data cache set-up for the primordial stack and | |
1269 | * data area. First, invalidate the data cache and then disable data | |
1270 | * cacheability for that area. Finally, restore the EBC values, if | |
1271 | * any. | |
1272 | */ | |
1273 | ||
1274 | /* Invalidate the primordial stack and data area in cache */ | |
6d0f6bcf JCPV |
1275 | lis r3, CONFIG_SYS_INIT_RAM_ADDR@h |
1276 | ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l | |
c821b5f1 | 1277 | |
553f0982 WD |
1278 | lis r4, CONFIG_SYS_INIT_RAM_SIZE@h |
1279 | ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l | |
c821b5f1 GE |
1280 | add r4, r4, r3 |
1281 | ||
1282 | bl invalidate_dcache_range | |
1283 | ||
1284 | /* Disable cacheability for the region */ | |
1285 | mfdccr r3 | |
6d0f6bcf JCPV |
1286 | lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h |
1287 | ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l | |
c821b5f1 GE |
1288 | and r3, r3, r4 |
1289 | mtdccr r3 | |
1290 | ||
1291 | /* Restore the EBC parameters */ | |
1292 | li r3, PBxAP | |
d1c3b275 | 1293 | mtdcr EBC0_CFGADDR, r3 |
c821b5f1 GE |
1294 | lis r3, PBxAP_VAL@h |
1295 | ori r3, r3, PBxAP_VAL@l | |
d1c3b275 | 1296 | mtdcr EBC0_CFGDATA, r3 |
c821b5f1 GE |
1297 | |
1298 | li r3, PBxCR | |
d1c3b275 | 1299 | mtdcr EBC0_CFGADDR, r3 |
c821b5f1 GE |
1300 | lis r3, PBxCR_VAL@h |
1301 | ori r3, r3, PBxCR_VAL@l | |
d1c3b275 | 1302 | mtdcr EBC0_CFGDATA, r3 |
6d0f6bcf | 1303 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
c821b5f1 GE |
1304 | |
1305 | /* Restore registers */ | |
1306 | mr r3, r9 | |
1307 | mr r4, r10 | |
1308 | mr r5, r11 | |
6d0f6bcf | 1309 | #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ |
e02c521d | 1310 | |
6d0f6bcf | 1311 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
e02c521d SR |
1312 | /* |
1313 | * Unlock the previously locked d-cache | |
1314 | */ | |
1315 | msync | |
1316 | isync | |
1317 | /* set TFLOOR/NFLOOR to 0 again */ | |
1318 | lis r6,0x0001 | |
1319 | ori r6,r6,0xf800 | |
58ea142f | 1320 | mtspr SPRN_DVLIM,r6 |
e02c521d SR |
1321 | lis r6,0x0000 |
1322 | ori r6,r6,0x0000 | |
58ea142f MF |
1323 | mtspr SPRN_DNV0,r6 |
1324 | mtspr SPRN_DNV1,r6 | |
1325 | mtspr SPRN_DNV2,r6 | |
1326 | mtspr SPRN_DNV3,r6 | |
1327 | mtspr SPRN_DTV0,r6 | |
1328 | mtspr SPRN_DTV1,r6 | |
1329 | mtspr SPRN_DTV2,r6 | |
1330 | mtspr SPRN_DTV3,r6 | |
e02c521d SR |
1331 | msync |
1332 | isync | |
f3cac538 SR |
1333 | |
1334 | /* Invalidate data cache, now no longer our stack */ | |
1335 | dccci 0,0 | |
1336 | sync | |
1337 | isync | |
6d0f6bcf | 1338 | #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ |
e02c521d | 1339 | |
a4c8d138 SR |
1340 | /* |
1341 | * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) | |
1342 | * to speed up the boot process. Now this cache needs to be disabled. | |
1343 | */ | |
4978e605 | 1344 | #if defined(CONFIG_440) |
25fb4eaa | 1345 | /* Clear all potential pending exceptions */ |
58ea142f MF |
1346 | mfspr r1,SPRN_MCSR |
1347 | mtspr SPRN_MCSR,r1 | |
6d0f6bcf | 1348 | addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ |
c157d8e2 | 1349 | tlbre r0,r1,0x0002 /* Read contents */ |
6e7fb6ea | 1350 | ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ |
f901a83b | 1351 | tlbwe r0,r1,0x0002 /* Save it out */ |
a4c8d138 | 1352 | sync |
c157d8e2 | 1353 | isync |
4978e605 | 1354 | #endif /* defined(CONFIG_440) */ |
0442ed86 WD |
1355 | mr r1, r3 /* Set new stack pointer */ |
1356 | mr r9, r4 /* Save copy of Init Data pointer */ | |
1357 | mr r10, r5 /* Save copy of Destination Address */ | |
1358 | ||
0f8aa159 | 1359 | GET_GOT |
0442ed86 | 1360 | mr r3, r5 /* Destination Address */ |
6d0f6bcf JCPV |
1361 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
1362 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
3b57fe0a WD |
1363 | lwz r5, GOT(__init_end) |
1364 | sub r5, r5, r4 | |
9b94ac61 | 1365 | li r6, L1_CACHE_BYTES /* Cache Line Size */ |
0442ed86 WD |
1366 | |
1367 | /* | |
1368 | * Fix GOT pointer: | |
1369 | * | |
6d0f6bcf | 1370 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address |
0442ed86 WD |
1371 | * |
1372 | * Offset: | |
1373 | */ | |
1374 | sub r15, r10, r4 | |
1375 | ||
1376 | /* First our own GOT */ | |
0f8aa159 | 1377 | add r12, r12, r15 |
c821b5f1 | 1378 | /* then the one used by the C code */ |
0442ed86 WD |
1379 | add r30, r30, r15 |
1380 | ||
1381 | /* | |
1382 | * Now relocate code | |
1383 | */ | |
1384 | ||
1385 | cmplw cr1,r3,r4 | |
1386 | addi r0,r5,3 | |
1387 | srwi. r0,r0,2 | |
1388 | beq cr1,4f /* In place copy is not necessary */ | |
1389 | beq 7f /* Protect against 0 count */ | |
1390 | mtctr r0 | |
1391 | bge cr1,2f | |
1392 | ||
1393 | la r8,-4(r4) | |
1394 | la r7,-4(r3) | |
1395 | 1: lwzu r0,4(r8) | |
1396 | stwu r0,4(r7) | |
1397 | bdnz 1b | |
1398 | b 4f | |
1399 | ||
1400 | 2: slwi r0,r0,2 | |
1401 | add r8,r4,r0 | |
1402 | add r7,r3,r0 | |
1403 | 3: lwzu r0,-4(r8) | |
1404 | stwu r0,-4(r7) | |
1405 | bdnz 3b | |
1406 | ||
1407 | /* | |
1408 | * Now flush the cache: note that we must start from a cache aligned | |
1409 | * address. Otherwise we might miss one cache line. | |
1410 | */ | |
1411 | 4: cmpwi r6,0 | |
1412 | add r5,r3,r5 | |
1413 | beq 7f /* Always flush prefetch queue in any case */ | |
1414 | subi r0,r6,1 | |
1415 | andc r3,r3,r0 | |
1416 | mr r4,r3 | |
1417 | 5: dcbst 0,r4 | |
1418 | add r4,r4,r6 | |
1419 | cmplw r4,r5 | |
1420 | blt 5b | |
1421 | sync /* Wait for all dcbst to complete on bus */ | |
1422 | mr r4,r3 | |
1423 | 6: icbi 0,r4 | |
1424 | add r4,r4,r6 | |
1425 | cmplw r4,r5 | |
1426 | blt 6b | |
1427 | 7: sync /* Wait for all icbi to complete on bus */ | |
1428 | isync | |
1429 | ||
1430 | /* | |
1431 | * We are done. Do not return, instead branch to second part of board | |
1432 | * initialization, now running from RAM. | |
1433 | */ | |
1434 | ||
efa35cf1 | 1435 | addi r0, r10, in_ram - _start + _START_OFFSET |
0442ed86 WD |
1436 | mtlr r0 |
1437 | blr /* NEVER RETURNS! */ | |
1438 | ||
1439 | in_ram: | |
1440 | ||
1441 | /* | |
0f8aa159 | 1442 | * Relocation Function, r12 point to got2+0x8000 |
0442ed86 WD |
1443 | * |
1444 | * Adjust got2 pointers, no need to check for 0, this code | |
1445 | * already puts a few entries in the table. | |
1446 | */ | |
1447 | li r0,__got2_entries@sectoff@l | |
1448 | la r3,GOT(_GOT2_TABLE_) | |
1449 | lwz r11,GOT(_GOT2_TABLE_) | |
1450 | mtctr r0 | |
1451 | sub r11,r3,r11 | |
1452 | addi r3,r3,-4 | |
1453 | 1: lwzu r0,4(r3) | |
afc3ba0f JT |
1454 | cmpwi r0,0 |
1455 | beq- 2f | |
0442ed86 WD |
1456 | add r0,r0,r11 |
1457 | stw r0,0(r3) | |
afc3ba0f | 1458 | 2: bdnz 1b |
0442ed86 WD |
1459 | |
1460 | /* | |
1461 | * Now adjust the fixups and the pointers to the fixups | |
1462 | * in case we need to move ourselves again. | |
1463 | */ | |
afc3ba0f | 1464 | li r0,__fixup_entries@sectoff@l |
0442ed86 WD |
1465 | lwz r3,GOT(_FIXUP_TABLE_) |
1466 | cmpwi r0,0 | |
1467 | mtctr r0 | |
1468 | addi r3,r3,-4 | |
1469 | beq 4f | |
1470 | 3: lwzu r4,4(r3) | |
1471 | lwzux r0,r4,r11 | |
d1e0b10a | 1472 | cmpwi r0,0 |
0442ed86 | 1473 | add r0,r0,r11 |
34bbf618 | 1474 | stw r4,0(r3) |
d1e0b10a | 1475 | beq- 5f |
0442ed86 | 1476 | stw r0,0(r4) |
d1e0b10a | 1477 | 5: bdnz 3b |
0442ed86 WD |
1478 | 4: |
1479 | clear_bss: | |
1480 | /* | |
1481 | * Now clear BSS segment | |
1482 | */ | |
5d232d0e | 1483 | lwz r3,GOT(__bss_start) |
3929fb0a | 1484 | lwz r4,GOT(__bss_end) |
0442ed86 WD |
1485 | |
1486 | cmplw 0, r3, r4 | |
42ed33ff | 1487 | beq 7f |
0442ed86 WD |
1488 | |
1489 | li r0, 0 | |
42ed33ff AG |
1490 | |
1491 | andi. r5, r4, 3 | |
1492 | beq 6f | |
1493 | sub r4, r4, r5 | |
1494 | mtctr r5 | |
1495 | mr r5, r4 | |
1496 | 5: stb r0, 0(r5) | |
1497 | addi r5, r5, 1 | |
1498 | bdnz 5b | |
1499 | 6: | |
0442ed86 WD |
1500 | stw r0, 0(r3) |
1501 | addi r3, r3, 4 | |
1502 | cmplw 0, r3, r4 | |
42ed33ff | 1503 | bne 6b |
0442ed86 | 1504 | |
42ed33ff | 1505 | 7: |
0442ed86 WD |
1506 | mr r3, r9 /* Init Data pointer */ |
1507 | mr r4, r10 /* Destination Address */ | |
1508 | bl board_init_r | |
1509 | ||
0442ed86 WD |
1510 | /* |
1511 | * Copy exception vector code to low memory | |
1512 | * | |
1513 | * r3: dest_addr | |
1514 | * r7: source address, r8: end address, r9: target address | |
1515 | */ | |
1516 | .globl trap_init | |
1517 | trap_init: | |
0f8aa159 JT |
1518 | mflr r4 /* save link register */ |
1519 | GET_GOT | |
efa35cf1 | 1520 | lwz r7, GOT(_start_of_vectors) |
0442ed86 WD |
1521 | lwz r8, GOT(_end_of_vectors) |
1522 | ||
682011ff | 1523 | li r9, 0x100 /* reset vector always at 0x100 */ |
0442ed86 WD |
1524 | |
1525 | cmplw 0, r7, r8 | |
1526 | bgelr /* return if r7>=r8 - just in case */ | |
0442ed86 WD |
1527 | 1: |
1528 | lwz r0, 0(r7) | |
1529 | stw r0, 0(r9) | |
1530 | addi r7, r7, 4 | |
1531 | addi r9, r9, 4 | |
1532 | cmplw 0, r7, r8 | |
1533 | bne 1b | |
1534 | ||
1535 | /* | |
1536 | * relocate `hdlr' and `int_return' entries | |
1537 | */ | |
efa35cf1 GB |
1538 | li r7, .L_MachineCheck - _start + _START_OFFSET |
1539 | li r8, Alignment - _start + _START_OFFSET | |
0442ed86 WD |
1540 | 2: |
1541 | bl trap_reloc | |
efa35cf1 | 1542 | addi r7, r7, 0x100 /* next exception vector */ |
0442ed86 WD |
1543 | cmplw 0, r7, r8 |
1544 | blt 2b | |
1545 | ||
efa35cf1 | 1546 | li r7, .L_Alignment - _start + _START_OFFSET |
0442ed86 WD |
1547 | bl trap_reloc |
1548 | ||
efa35cf1 | 1549 | li r7, .L_ProgramCheck - _start + _START_OFFSET |
0442ed86 WD |
1550 | bl trap_reloc |
1551 | ||
efa35cf1 GB |
1552 | #ifdef CONFIG_440 |
1553 | li r7, .L_FPUnavailable - _start + _START_OFFSET | |
83b4cfa3 | 1554 | bl trap_reloc |
0442ed86 | 1555 | |
efa35cf1 | 1556 | li r7, .L_Decrementer - _start + _START_OFFSET |
83b4cfa3 | 1557 | bl trap_reloc |
efa35cf1 GB |
1558 | |
1559 | li r7, .L_APU - _start + _START_OFFSET | |
83b4cfa3 | 1560 | bl trap_reloc |
df8a24cd | 1561 | |
83b4cfa3 WD |
1562 | li r7, .L_InstructionTLBError - _start + _START_OFFSET |
1563 | bl trap_reloc | |
efa35cf1 | 1564 | |
83b4cfa3 WD |
1565 | li r7, .L_DataTLBError - _start + _START_OFFSET |
1566 | bl trap_reloc | |
efa35cf1 GB |
1567 | #else /* CONFIG_440 */ |
1568 | li r7, .L_PIT - _start + _START_OFFSET | |
83b4cfa3 | 1569 | bl trap_reloc |
efa35cf1 GB |
1570 | |
1571 | li r7, .L_InstructionTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1572 | bl trap_reloc |
efa35cf1 GB |
1573 | |
1574 | li r7, .L_DataTLBMiss - _start + _START_OFFSET | |
83b4cfa3 | 1575 | bl trap_reloc |
efa35cf1 GB |
1576 | #endif /* CONFIG_440 */ |
1577 | ||
83b4cfa3 WD |
1578 | li r7, .L_DebugBreakpoint - _start + _START_OFFSET |
1579 | bl trap_reloc | |
0442ed86 | 1580 | |
887e2ec9 | 1581 | #if !defined(CONFIG_440) |
9a7b408c SR |
1582 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1583 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
1584 | mtmsr r7 /* change MSR */ | |
1585 | #else | |
887e2ec9 SR |
1586 | bl __440_msr_set |
1587 | b __440_msr_continue | |
9a7b408c | 1588 | |
887e2ec9 | 1589 | __440_msr_set: |
9a7b408c SR |
1590 | addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ |
1591 | oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ | |
58ea142f | 1592 | mtspr SPRN_SRR1,r7 |
9a7b408c | 1593 | mflr r7 |
58ea142f | 1594 | mtspr SPRN_SRR0,r7 |
9a7b408c | 1595 | rfi |
887e2ec9 | 1596 | __440_msr_continue: |
9a7b408c SR |
1597 | #endif |
1598 | ||
0442ed86 WD |
1599 | mtlr r4 /* restore link register */ |
1600 | blr | |
98f99e9f | 1601 | #endif /* CONFIG_SPL_BUILD */ |
0442ed86 | 1602 | |
cf959c7d SR |
1603 | #if defined(CONFIG_440) |
1604 | /*----------------------------------------------------------------------------+ | |
1605 | | dcbz_area. | |
1606 | +----------------------------------------------------------------------------*/ | |
1607 | function_prolog(dcbz_area) | |
1608 | rlwinm. r5,r4,0,27,31 | |
83b4cfa3 WD |
1609 | rlwinm r5,r4,27,5,31 |
1610 | beq ..d_ra2 | |
1611 | addi r5,r5,0x0001 | |
1612 | ..d_ra2:mtctr r5 | |
1613 | ..d_ag2:dcbz r0,r3 | |
1614 | addi r3,r3,32 | |
1615 | bdnz ..d_ag2 | |
cf959c7d SR |
1616 | sync |
1617 | blr | |
1618 | function_epilog(dcbz_area) | |
cf959c7d | 1619 | #endif /* CONFIG_440 */ |
345b77ba | 1620 | #endif /* CONFIG_SPL_BUILD */ |
b867d705 | 1621 | |
cf959c7d SR |
1622 | /*------------------------------------------------------------------------------- */ |
1623 | /* Function: in8 */ | |
1624 | /* Description: Input 8 bits */ | |
1625 | /*------------------------------------------------------------------------------- */ | |
1626 | .globl in8 | |
1627 | in8: | |
1628 | lbz r3,0x0000(r3) | |
1629 | blr | |
1630 | ||
1631 | /*------------------------------------------------------------------------------- */ | |
1632 | /* Function: out8 */ | |
1633 | /* Description: Output 8 bits */ | |
1634 | /*------------------------------------------------------------------------------- */ | |
1635 | .globl out8 | |
1636 | out8: | |
1637 | stb r4,0x0000(r3) | |
1638 | blr | |
1639 | ||
1640 | /*------------------------------------------------------------------------------- */ | |
1641 | /* Function: out32 */ | |
1642 | /* Description: Output 32 bits */ | |
1643 | /*------------------------------------------------------------------------------- */ | |
1644 | .globl out32 | |
1645 | out32: | |
1646 | stw r4,0x0000(r3) | |
1647 | blr | |
1648 | ||
1649 | /*------------------------------------------------------------------------------- */ | |
1650 | /* Function: in32 */ | |
1651 | /* Description: Input 32 bits */ | |
1652 | /*------------------------------------------------------------------------------- */ | |
1653 | .globl in32 | |
1654 | in32: | |
1655 | lwz 3,0x0000(3) | |
1656 | blr | |
b867d705 SR |
1657 | |
1658 | /**************************************************************************/ | |
f901a83b | 1659 | /* PPC405EP specific stuff */ |
b867d705 SR |
1660 | /**************************************************************************/ |
1661 | #ifdef CONFIG_405EP | |
1662 | ppc405ep_init: | |
b828dda6 | 1663 | |
c157d8e2 | 1664 | #ifdef CONFIG_BUBINGA |
b828dda6 SR |
1665 | /* |
1666 | * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate | |
1667 | * function) to support FPGA and NVRAM accesses below. | |
1668 | */ | |
1669 | ||
1670 | lis r3,GPIO0_OSRH@h /* config GPIO output select */ | |
1671 | ori r3,r3,GPIO0_OSRH@l | |
6d0f6bcf JCPV |
1672 | lis r4,CONFIG_SYS_GPIO0_OSRH@h |
1673 | ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l | |
b828dda6 SR |
1674 | stw r4,0(r3) |
1675 | lis r3,GPIO0_OSRL@h | |
1676 | ori r3,r3,GPIO0_OSRL@l | |
6d0f6bcf JCPV |
1677 | lis r4,CONFIG_SYS_GPIO0_OSRL@h |
1678 | ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l | |
b828dda6 SR |
1679 | stw r4,0(r3) |
1680 | ||
1681 | lis r3,GPIO0_ISR1H@h /* config GPIO input select */ | |
1682 | ori r3,r3,GPIO0_ISR1H@l | |
6d0f6bcf JCPV |
1683 | lis r4,CONFIG_SYS_GPIO0_ISR1H@h |
1684 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l | |
b828dda6 SR |
1685 | stw r4,0(r3) |
1686 | lis r3,GPIO0_ISR1L@h | |
1687 | ori r3,r3,GPIO0_ISR1L@l | |
6d0f6bcf JCPV |
1688 | lis r4,CONFIG_SYS_GPIO0_ISR1L@h |
1689 | ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l | |
b828dda6 SR |
1690 | stw r4,0(r3) |
1691 | ||
1692 | lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ | |
1693 | ori r3,r3,GPIO0_TSRH@l | |
6d0f6bcf JCPV |
1694 | lis r4,CONFIG_SYS_GPIO0_TSRH@h |
1695 | ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l | |
b828dda6 SR |
1696 | stw r4,0(r3) |
1697 | lis r3,GPIO0_TSRL@h | |
1698 | ori r3,r3,GPIO0_TSRL@l | |
6d0f6bcf JCPV |
1699 | lis r4,CONFIG_SYS_GPIO0_TSRL@h |
1700 | ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l | |
b828dda6 SR |
1701 | stw r4,0(r3) |
1702 | ||
1703 | lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ | |
1704 | ori r3,r3,GPIO0_TCR@l | |
6d0f6bcf JCPV |
1705 | lis r4,CONFIG_SYS_GPIO0_TCR@h |
1706 | ori r4,r4,CONFIG_SYS_GPIO0_TCR@l | |
b828dda6 SR |
1707 | stw r4,0(r3) |
1708 | ||
d1c3b275 SR |
1709 | li r3,PB1AP /* program EBC bank 1 for RTC access */ |
1710 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1711 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1712 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
d1c3b275 SR |
1713 | mtdcr EBC0_CFGDATA,r3 |
1714 | li r3,PB1CR | |
1715 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1716 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1717 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
d1c3b275 | 1718 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1719 | |
d1c3b275 SR |
1720 | li r3,PB1AP /* program EBC bank 1 for RTC access */ |
1721 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1722 | lis r3,CONFIG_SYS_EBC_PB1AP@h |
1723 | ori r3,r3,CONFIG_SYS_EBC_PB1AP@l | |
d1c3b275 SR |
1724 | mtdcr EBC0_CFGDATA,r3 |
1725 | li r3,PB1CR | |
1726 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1727 | lis r3,CONFIG_SYS_EBC_PB1CR@h |
1728 | ori r3,r3,CONFIG_SYS_EBC_PB1CR@l | |
d1c3b275 | 1729 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1730 | |
d1c3b275 SR |
1731 | li r3,PB4AP /* program EBC bank 4 for FPGA access */ |
1732 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1733 | lis r3,CONFIG_SYS_EBC_PB4AP@h |
1734 | ori r3,r3,CONFIG_SYS_EBC_PB4AP@l | |
d1c3b275 SR |
1735 | mtdcr EBC0_CFGDATA,r3 |
1736 | li r3,PB4CR | |
1737 | mtdcr EBC0_CFGADDR,r3 | |
6d0f6bcf JCPV |
1738 | lis r3,CONFIG_SYS_EBC_PB4CR@h |
1739 | ori r3,r3,CONFIG_SYS_EBC_PB4CR@l | |
d1c3b275 | 1740 | mtdcr EBC0_CFGDATA,r3 |
b828dda6 | 1741 | #endif |
8bde7f77 WD |
1742 | |
1743 | /* | |
1744 | !----------------------------------------------------------------------- | |
1745 | ! Check to see if chip is in bypass mode. | |
1746 | ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a | |
1747 | ! CPU reset Otherwise, skip this step and keep going. | |
f901a83b WD |
1748 | ! Note: Running BIOS in bypass mode is not supported since PLB speed |
1749 | ! will not be fast enough for the SDRAM (min 66MHz) | |
8bde7f77 | 1750 | !----------------------------------------------------------------------- |
b867d705 | 1751 | */ |
f901a83b | 1752 | mfdcr r5, CPC0_PLLMR1 |
53677ef1 | 1753 | rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ |
f901a83b | 1754 | cmpi cr0,0,r4,0x1 |
b867d705 | 1755 | |
53677ef1 WD |
1756 | beq pll_done /* if SSCS =b'1' then PLL has */ |
1757 | /* already been set */ | |
1758 | /* and CPU has been reset */ | |
1759 | /* so skip to next section */ | |
b867d705 | 1760 | |
c157d8e2 | 1761 | #ifdef CONFIG_BUBINGA |
b867d705 | 1762 | /* |
8bde7f77 WD |
1763 | !----------------------------------------------------------------------- |
1764 | ! Read NVRAM to get value to write in PLLMR. | |
1765 | ! If value has not been correctly saved, write default value | |
1766 | ! Default config values (assuming on-board 33MHz SYS_CLK) are above. | |
1767 | ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. | |
1768 | ! | |
1769 | ! WARNING: This code assumes the first three words in the nvram_t | |
f901a83b WD |
1770 | ! structure in openbios.h. Changing the beginning of |
1771 | ! the structure will break this code. | |
8bde7f77 WD |
1772 | ! |
1773 | !----------------------------------------------------------------------- | |
b867d705 | 1774 | */ |
f901a83b WD |
1775 | addis r3,0,NVRAM_BASE@h |
1776 | addi r3,r3,NVRAM_BASE@l | |
1777 | ||
1778 | lwz r4, 0(r3) | |
1779 | addis r5,0,NVRVFY1@h | |
1780 | addi r5,r5,NVRVFY1@l | |
53677ef1 | 1781 | cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ |
f901a83b WD |
1782 | bne ..no_pllset |
1783 | addi r3,r3,4 | |
1784 | lwz r4, 0(r3) | |
1785 | addis r5,0,NVRVFY2@h | |
1786 | addi r5,r5,NVRVFY2@l | |
53677ef1 | 1787 | cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ |
f901a83b WD |
1788 | bne ..no_pllset |
1789 | addi r3,r3,8 /* Skip over conf_size */ | |
1790 | lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ | |
1791 | lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ | |
1792 | rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ | |
1793 | cmpi cr0,0,r5,1 /* See if PLL is locked */ | |
1794 | beq pll_write | |
b867d705 | 1795 | ..no_pllset: |
c157d8e2 | 1796 | #endif /* CONFIG_BUBINGA */ |
b867d705 | 1797 | |
d4024bb7 JO |
1798 | #ifdef CONFIG_TAIHU |
1799 | mfdcr r4, CPC0_BOOT | |
1800 | andi. r5, r4, CPC0_BOOT_SEP@l | |
1801 | bne strap_1 /* serial eeprom present */ | |
1802 | addis r5,0,CPLD_REG0_ADDR@h | |
1803 | ori r5,r5,CPLD_REG0_ADDR@l | |
1804 | andi. r5, r5, 0x10 | |
1805 | bne _pci_66mhz | |
1806 | #endif /* CONFIG_TAIHU */ | |
1807 | ||
779e9751 SR |
1808 | #if defined(CONFIG_ZEUS) |
1809 | mfdcr r4, CPC0_BOOT | |
1810 | andi. r5, r4, CPC0_BOOT_SEP@l | |
53677ef1 | 1811 | bne strap_1 /* serial eeprom present */ |
779e9751 SR |
1812 | lis r3,0x0000 |
1813 | addi r3,r3,0x3030 | |
1814 | lis r4,0x8042 | |
1815 | addi r4,r4,0x223e | |
1816 | b 1f | |
1817 | strap_1: | |
1818 | mfdcr r3, CPC0_PLLMR0 | |
1819 | mfdcr r4, CPC0_PLLMR1 | |
1820 | b 1f | |
1821 | #endif | |
1822 | ||
53677ef1 WD |
1823 | addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ |
1824 | ori r3,r3,PLLMR0_DEFAULT@l /* */ | |
1825 | addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ | |
1826 | ori r4,r4,PLLMR1_DEFAULT@l /* */ | |
b867d705 | 1827 | |
d4024bb7 JO |
1828 | #ifdef CONFIG_TAIHU |
1829 | b 1f | |
1830 | _pci_66mhz: | |
1831 | addis r3,0,PLLMR0_DEFAULT_PCI66@h | |
1832 | ori r3,r3,PLLMR0_DEFAULT_PCI66@l | |
1833 | addis r4,0,PLLMR1_DEFAULT_PCI66@h | |
1834 | ori r4,r4,PLLMR1_DEFAULT_PCI66@l | |
1835 | b 1f | |
1836 | strap_1: | |
1837 | mfdcr r3, CPC0_PLLMR0 | |
1838 | mfdcr r4, CPC0_PLLMR1 | |
d4024bb7 JO |
1839 | #endif /* CONFIG_TAIHU */ |
1840 | ||
779e9751 | 1841 | 1: |
53677ef1 | 1842 | b pll_write /* Write the CPC0_PLLMR with new value */ |
b867d705 SR |
1843 | |
1844 | pll_done: | |
8bde7f77 WD |
1845 | /* |
1846 | !----------------------------------------------------------------------- | |
1847 | ! Clear Soft Reset Register | |
1848 | ! This is needed to enable PCI if not booting from serial EPROM | |
1849 | !----------------------------------------------------------------------- | |
b867d705 | 1850 | */ |
f901a83b WD |
1851 | addi r3, 0, 0x0 |
1852 | mtdcr CPC0_SRR, r3 | |
b867d705 | 1853 | |
f901a83b WD |
1854 | addis r3,0,0x0010 |
1855 | mtctr r3 | |
b867d705 | 1856 | pci_wait: |
f901a83b | 1857 | bdnz pci_wait |
b867d705 | 1858 | |
53677ef1 | 1859 | blr /* return to main code */ |
b867d705 SR |
1860 | |
1861 | /* | |
1862 | !----------------------------------------------------------------------------- | |
f901a83b WD |
1863 | ! Function: pll_write |
1864 | ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation | |
1865 | ! That is: | |
1866 | ! 1. Pll is first disabled (de-activated by putting in bypass mode) | |
1867 | ! 2. PLL is reset | |
1868 | ! 3. Clock dividers are set while PLL is held in reset and bypassed | |
1869 | ! 4. PLL Reset is cleared | |
1870 | ! 5. Wait 100us for PLL to lock | |
1871 | ! 6. A core reset is performed | |
b867d705 SR |
1872 | ! Input: r3 = Value to write to CPC0_PLLMR0 |
1873 | ! Input: r4 = Value to write to CPC0_PLLMR1 | |
1874 | ! Output r3 = none | |
1875 | !----------------------------------------------------------------------------- | |
1876 | */ | |
0580e48f | 1877 | .globl pll_write |
b867d705 | 1878 | pll_write: |
8bde7f77 WD |
1879 | mfdcr r5, CPC0_UCR |
1880 | andis. r5,r5,0xFFFF | |
53677ef1 WD |
1881 | ori r5,r5,0x0101 /* Stop the UART clocks */ |
1882 | mtdcr CPC0_UCR,r5 /* Before changing PLL */ | |
8bde7f77 WD |
1883 | |
1884 | mfdcr r5, CPC0_PLLMR1 | |
53677ef1 | 1885 | rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ |
f901a83b | 1886 | mtdcr CPC0_PLLMR1,r5 |
53677ef1 | 1887 | oris r5,r5,0x4000 /* Set PLL Reset */ |
f901a83b WD |
1888 | mtdcr CPC0_PLLMR1,r5 |
1889 | ||
53677ef1 WD |
1890 | mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ |
1891 | rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ | |
1892 | oris r5,r5,0x4000 /* Set PLL Reset */ | |
1893 | mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ | |
1894 | rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ | |
f901a83b | 1895 | mtdcr CPC0_PLLMR1,r5 |
b867d705 SR |
1896 | |
1897 | /* | |
8bde7f77 WD |
1898 | ! Wait min of 100us for PLL to lock. |
1899 | ! See CMOS 27E databook for more info. | |
1900 | ! At 200MHz, that means waiting 20,000 instructions | |
b867d705 | 1901 | */ |
f901a83b WD |
1902 | addi r3,0,20000 /* 2000 = 0x4e20 */ |
1903 | mtctr r3 | |
b867d705 | 1904 | pll_wait: |
f901a83b | 1905 | bdnz pll_wait |
8bde7f77 | 1906 | |
f901a83b WD |
1907 | oris r5,r5,0x8000 /* Enable PLL */ |
1908 | mtdcr CPC0_PLLMR1,r5 /* Engage */ | |
8bde7f77 WD |
1909 | |
1910 | /* | |
1911 | * Reset CPU to guarantee timings are OK | |
1912 | * Not sure if this is needed... | |
1913 | */ | |
1914 | addis r3,0,0x1000 | |
58ea142f | 1915 | mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ |
53677ef1 WD |
1916 | /* execution will continue from the poweron */ |
1917 | /* vector of 0xfffffffc */ | |
b867d705 | 1918 | #endif /* CONFIG_405EP */ |
4745acaa SR |
1919 | |
1920 | #if defined(CONFIG_440) | |
4745acaa SR |
1921 | /*----------------------------------------------------------------------------+ |
1922 | | mttlb3. | |
1923 | +----------------------------------------------------------------------------*/ | |
1924 | function_prolog(mttlb3) | |
1925 | TLBWE(4,3,2) | |
1926 | blr | |
1927 | function_epilog(mttlb3) | |
1928 | ||
1929 | /*----------------------------------------------------------------------------+ | |
1930 | | mftlb3. | |
1931 | +----------------------------------------------------------------------------*/ | |
1932 | function_prolog(mftlb3) | |
74357114 | 1933 | TLBRE(3,3,2) |
4745acaa SR |
1934 | blr |
1935 | function_epilog(mftlb3) | |
1936 | ||
1937 | /*----------------------------------------------------------------------------+ | |
1938 | | mttlb2. | |
1939 | +----------------------------------------------------------------------------*/ | |
1940 | function_prolog(mttlb2) | |
1941 | TLBWE(4,3,1) | |
1942 | blr | |
1943 | function_epilog(mttlb2) | |
1944 | ||
1945 | /*----------------------------------------------------------------------------+ | |
1946 | | mftlb2. | |
1947 | +----------------------------------------------------------------------------*/ | |
1948 | function_prolog(mftlb2) | |
74357114 | 1949 | TLBRE(3,3,1) |
4745acaa SR |
1950 | blr |
1951 | function_epilog(mftlb2) | |
1952 | ||
1953 | /*----------------------------------------------------------------------------+ | |
1954 | | mttlb1. | |
1955 | +----------------------------------------------------------------------------*/ | |
1956 | function_prolog(mttlb1) | |
1957 | TLBWE(4,3,0) | |
1958 | blr | |
1959 | function_epilog(mttlb1) | |
1960 | ||
1961 | /*----------------------------------------------------------------------------+ | |
1962 | | mftlb1. | |
1963 | +----------------------------------------------------------------------------*/ | |
1964 | function_prolog(mftlb1) | |
74357114 | 1965 | TLBRE(3,3,0) |
4745acaa SR |
1966 | blr |
1967 | function_epilog(mftlb1) | |
1968 | #endif /* CONFIG_440 */ |