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KVM: Fix __set_bit() race in mark_page_dirty() during dirty logging
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
476bc001
RR		 91static bool ignore_msrs = 0;
92module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
d6aa1000
AK		 156int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
157
af585b92
GN		 158static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
159{
160 int i;
161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
162 vcpu->arch.apf.gfns[i] = ~0;
163}
164
18863bdd
AK		 165static void kvm_on_user_return(struct user_return_notifier *urn)
166{
167 unsigned slot;
18863bdd
AK		 168 struct kvm_shared_msrs *locals
169 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 170 struct kvm_shared_msr_values *values;
18863bdd
AK		 171
172 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 173 values = &locals->values[slot];
174 if (values->host != values->curr) {
175 wrmsrl(shared_msrs_global.msrs[slot], values->host);
176 values->curr = values->host;
18863bdd
AK		 177 }
178 }
179 locals->registered = false;
180 user_return_notifier_unregister(urn);
181}
182
2bf78fa7 183static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 184{
2bf78fa7 185 struct kvm_shared_msrs *smsr;
18863bdd
AK		 186 u64 value;
187
2bf78fa7
SY		 188 smsr = &__get_cpu_var(shared_msrs);
189 /* only read, and nobody should modify it at this time,
190 * so don't need lock */
191 if (slot >= shared_msrs_global.nr) {
192 printk(KERN_ERR "kvm: invalid MSR slot!");
193 return;
194 }
195 rdmsrl_safe(msr, &value);
196 smsr->values[slot].host = value;
197 smsr->values[slot].curr = value;
198}
199
200void kvm_define_shared_msr(unsigned slot, u32 msr)
201{
18863bdd
AK		 202 if (slot >= shared_msrs_global.nr)
203 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 204 shared_msrs_global.msrs[slot] = msr;
205 /* we need ensured the shared_msr_global have been updated */
206 smp_wmb();
18863bdd
AK		 207}
208EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
209
210static void kvm_shared_msr_cpu_online(void)
211{
212 unsigned i;
18863bdd
AK		 213
214 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 215 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 216}
217
d5696725 218void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
2bf78fa7 222 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 223 return;
2bf78fa7
SY		 224 smsr->values[slot].curr = value;
225 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 226 if (!smsr->registered) {
227 smsr->urn.on_user_return = kvm_on_user_return;
228 user_return_notifier_register(&smsr->urn);
229 smsr->registered = true;
230 }
231}
232EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
233
3548bab5
AK		 234static void drop_user_return_notifiers(void *ignore)
235{
236 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
237
238 if (smsr->registered)
239 kvm_on_user_return(&smsr->urn);
240}
241
6866b83e
CO		 242u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
243{
244 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e 246 else
ad312c7c 247 return vcpu->arch.apic_base;
6866b83e
CO		 248}
249EXPORT_SYMBOL_GPL(kvm_get_apic_base);
250
251void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
252{
253 /* TODO: reserve bits check */
254 if (irqchip_in_kernel(vcpu->kvm))
255 kvm_lapic_set_base(vcpu, data);
256 else
ad312c7c 257 vcpu->arch.apic_base = data;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_set_apic_base);
260
3fd28fce
ED		 261#define EXCPT_BENIGN 0
262#define EXCPT_CONTRIBUTORY 1
263#define EXCPT_PF 2
264
265static int exception_class(int vector)
266{
267 switch (vector) {
268 case PF_VECTOR:
269 return EXCPT_PF;
270 case DE_VECTOR:
271 case TS_VECTOR:
272 case NP_VECTOR:
273 case SS_VECTOR:
274 case GP_VECTOR:
275 return EXCPT_CONTRIBUTORY;
276 default:
277 break;
278 }
279 return EXCPT_BENIGN;
280}
281
282static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 283 unsigned nr, bool has_error, u32 error_code,
284 bool reinject)
3fd28fce
ED		 285{
286 u32 prev_nr;
287 int class1, class2;
288
3842d135
AK		 289 kvm_make_request(KVM_REQ_EVENT, vcpu);
290
3fd28fce
ED		 291 if (!vcpu->arch.exception.pending) {
292 queue:
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = has_error;
295 vcpu->arch.exception.nr = nr;
296 vcpu->arch.exception.error_code = error_code;
3f0fd292 297 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 298 return;
299 }
300
301 /* to check exception */
302 prev_nr = vcpu->arch.exception.nr;
303 if (prev_nr == DF_VECTOR) {
304 /* triple fault -> shutdown */
a8eeb04a 305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 306 return;
307 }
308 class1 = exception_class(prev_nr);
309 class2 = exception_class(nr);
310 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
311 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
312 /* generate double fault per SDM Table 5-5 */
313 vcpu->arch.exception.pending = true;
314 vcpu->arch.exception.has_error_code = true;
315 vcpu->arch.exception.nr = DF_VECTOR;
316 vcpu->arch.exception.error_code = 0;
317 } else
318 /* replace previous exception with a new one in a hope
319 that instruction re-execution will regenerate lost
320 exception */
321 goto queue;
322}
323
298101da
AK		 324void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
ce7ddec4 326 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception);
329
ce7ddec4
JR		 330void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
332 kvm_multiple_exception(vcpu, nr, false, 0, true);
333}
334EXPORT_SYMBOL_GPL(kvm_requeue_exception);
335
db8fcefa 336void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 337{
db8fcefa
AP		 338 if (err)
339 kvm_inject_gp(vcpu, 0);
340 else
341 kvm_x86_ops->skip_emulated_instruction(vcpu);
342}
343EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 344
6389ee94 345void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 346{
347 ++vcpu->stat.pf_guest;
6389ee94
AK		 348 vcpu->arch.cr2 = fault->address;
349 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 350}
27d6c865 351EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
7460fb4a
AK		 363 atomic_inc(&vcpu->arch.nmi_queued);
364 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
d170c419 528 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 529 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 530 kvm_async_pf_hash_reset(vcpu);
531 }
e5f3f027 532
aad82703
SY		 533 if ((cr0 ^ old_cr0) & update_bits)
534 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 535 return 0;
536}
2d3ad1f4 537EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 538
2d3ad1f4 539void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 540{
49a9b07e 541 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 544
2acf923e
DC		 545int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
546{
547 u64 xcr0;
548
549 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
550 if (index != XCR_XFEATURE_ENABLED_MASK)
551 return 1;
552 xcr0 = xcr;
553 if (kvm_x86_ops->get_cpl(vcpu) != 0)
554 return 1;
555 if (!(xcr0 & XSTATE_FP))
556 return 1;
557 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
558 return 1;
559 if (xcr0 & ~host_xcr0)
560 return 1;
561 vcpu->arch.xcr0 = xcr0;
562 vcpu->guest_xcr0_loaded = 0;
563 return 0;
564}
565
566int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
567{
568 if (__kvm_set_xcr(vcpu, index, xcr)) {
569 kvm_inject_gp(vcpu, 0);
570 return 1;
571 }
572 return 0;
573}
574EXPORT_SYMBOL_GPL(kvm_set_xcr);
575
a83b29c6 576int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 577{
fc78f519 578 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 579 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
580 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 581 if (cr4 & CR4_RESERVED_BITS)
582 return 1;
a03490ed 583
2acf923e
DC		 584 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
585 return 1;
586
c68b734f
YW		 587 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
588 return 1;
589
74dc2b4f
YW		 590 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
591 return 1;
592
a03490ed 593 if (is_long_mode(vcpu)) {
0f12244f
GN		 594 if (!(cr4 & X86_CR4_PAE))
595 return 1;
a2edf57f
AK		 596 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
597 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 598 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
599 kvm_read_cr3(vcpu)))
0f12244f
GN		 600 return 1;
601
5e1746d6 602 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 603 return 1;
a03490ed 604
aad82703
SY		 605 if ((cr4 ^ old_cr4) & pdptr_bits)
606 kvm_mmu_reset_context(vcpu);
0f12244f 607
2acf923e 608 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 609 kvm_update_cpuid(vcpu);
2acf923e 610
0f12244f
GN		 611 return 0;
612}
2d3ad1f4 613EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 614
2390218b 615int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 616{
9f8fe504 617 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 618 kvm_mmu_sync_roots(vcpu);
d835dfec 619 kvm_mmu_flush_tlb(vcpu);
0f12244f 620 return 0;
d835dfec
AK		 621 }
622
a03490ed 623 if (is_long_mode(vcpu)) {
0f12244f
GN		 624 if (cr3 & CR3_L_MODE_RESERVED_BITS)
625 return 1;
a03490ed
CO		 626 } else {
627 if (is_pae(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_PAE_RESERVED_BITS)
629 return 1;
ff03a073
JR		 630 if (is_paging(vcpu) &&
631 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 632 return 1;
a03490ed
CO		 633 }
634 /*
635 * We don't check reserved bits in nonpae mode, because
636 * this isn't enforced, and VMware depends on this.
637 */
638 }
639
a03490ed
CO		 640 /*
641 * Does the new cr3 value map to physical memory? (Note, we
642 * catch an invalid cr3 even in real-mode, because it would
643 * cause trouble later on when we turn on paging anyway.)
644 *
645 * A real CPU would silently accept an invalid cr3 and would
646 * attempt to use it - with largely undefined (and often hard
647 * to debug) behavior on the guest side.
648 */
649 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 650 return 1;
651 vcpu->arch.cr3 = cr3;
aff48baa 652 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 653 vcpu->arch.mmu.new_cr3(vcpu);
654 return 0;
655}
2d3ad1f4 656EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 657
eea1cff9 658int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 659{
0f12244f
GN		 660 if (cr8 & CR8_RESERVED_BITS)
661 return 1;
a03490ed
CO		 662 if (irqchip_in_kernel(vcpu->kvm))
663 kvm_lapic_set_tpr(vcpu, cr8);
664 else
ad312c7c 665 vcpu->arch.cr8 = cr8;
0f12244f
GN		 666 return 0;
667}
2d3ad1f4 668EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 669
2d3ad1f4 670unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 671{
672 if (irqchip_in_kernel(vcpu->kvm))
673 return kvm_lapic_get_cr8(vcpu);
674 else
ad312c7c 675 return vcpu->arch.cr8;
a03490ed 676}
2d3ad1f4 677EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 678
338dbc97 679static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 680{
681 switch (dr) {
682 case 0 ... 3:
683 vcpu->arch.db[dr] = val;
684 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
685 vcpu->arch.eff_db[dr] = val;
686 break;
687 case 4:
338dbc97
GN		 688 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
689 return 1; /* #UD */
020df079
GN		 690 /* fall through */
691 case 6:
338dbc97
GN		 692 if (val & 0xffffffff00000000ULL)
693 return -1; /* #GP */
020df079
GN		 694 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
695 break;
696 case 5:
338dbc97
GN		 697 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
698 return 1; /* #UD */
020df079
GN		 699 /* fall through */
700 default: /* 7 */
338dbc97
GN		 701 if (val & 0xffffffff00000000ULL)
702 return -1; /* #GP */
020df079
GN		 703 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
704 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
705 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
706 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
707 }
708 break;
709 }
710
711 return 0;
712}
338dbc97
GN		 713
714int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
715{
716 int res;
717
718 res = __kvm_set_dr(vcpu, dr, val);
719 if (res > 0)
720 kvm_queue_exception(vcpu, UD_VECTOR);
721 else if (res < 0)
722 kvm_inject_gp(vcpu, 0);
723
724 return res;
725}
020df079
GN		 726EXPORT_SYMBOL_GPL(kvm_set_dr);
727
338dbc97 728static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 729{
730 switch (dr) {
731 case 0 ... 3:
732 *val = vcpu->arch.db[dr];
733 break;
734 case 4:
338dbc97 735 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 736 return 1;
020df079
GN		 737 /* fall through */
738 case 6:
739 *val = vcpu->arch.dr6;
740 break;
741 case 5:
338dbc97 742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 743 return 1;
020df079
GN		 744 /* fall through */
745 default: /* 7 */
746 *val = vcpu->arch.dr7;
747 break;
748 }
749
750 return 0;
751}
338dbc97
GN		 752
753int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
754{
755 if (_kvm_get_dr(vcpu, dr, val)) {
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 return 1;
758 }
759 return 0;
760}
020df079
GN		 761EXPORT_SYMBOL_GPL(kvm_get_dr);
762
022cd0e8
AK		 763bool kvm_rdpmc(struct kvm_vcpu *vcpu)
764{
765 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
766 u64 data;
767 int err;
768
769 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
770 if (err)
771 return err;
772 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
773 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
774 return err;
775}
776EXPORT_SYMBOL_GPL(kvm_rdpmc);
777
043405e1
CO		 778/*
779 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
780 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
781 *
782 * This list is modified at module load time to reflect the
e3267cbb
GC		 783 * capabilities of the host cpu. This capabilities test skips MSRs that are
784 * kvm-specific. Those are put in the beginning of the list.
043405e1 785 */
e3267cbb 786
c9aaa895 787#define KVM_SAVE_MSRS_BEGIN 9
043405e1 788static u32 msrs_to_save[] = {
e3267cbb 789 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 790 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 791 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 792 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 793 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 794 MSR_STAR,
043405e1
CO		 795#ifdef CONFIG_X86_64
796 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
797#endif
e90aa41e 798 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 799};
800
801static unsigned num_msrs_to_save;
802
803static u32 emulated_msrs[] = {
a3e06bbe 804 MSR_IA32_TSCDEADLINE,
043405e1 805 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
043405e1
CO		 808};
809
b69e8cae 810static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 811{
aad82703
SY		 812 u64 old_efer = vcpu->arch.efer;
813
b69e8cae
RJ		 814 if (efer & efer_reserved_bits)
815 return 1;
15c4a640
CO		 816
817 if (is_paging(vcpu)
b69e8cae
RJ		 818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
15c4a640 820
1b2fd70c
AG		 821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
1b2fd70c
AG		 827 }
828
d8017474
AG		 829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
d8017474
AG		 835 }
836
15c4a640 837 efer &= ~EFER_LMA;
f6801dff 838 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 839
a3d204e2
SY		 840 kvm_x86_ops->set_efer(vcpu, efer);
841
9645bb56 842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 843
aad82703
SY		 844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
b69e8cae 848 return 0;
15c4a640
CO		 849}
850
f2b4b7dd
JR		 851void kvm_enable_efer_bits(u64 mask)
852{
853 efer_reserved_bits &= ~mask;
854}
855EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
15c4a640
CO		 858/*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864{
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866}
867
313a3dc7
CO		 868/*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872{
873 return kvm_set_msr(vcpu, index, *data);
874}
875
18068523
GOC		 876static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877{
9ed3c444
AK		 878 int version;
879 int r;
50d0a0f9 880 struct pvclock_wall_clock wc;
923de3cf 881 struct timespec boot;
18068523
GOC		 882
883 if (!wall_clock)
884 return;
885
9ed3c444
AK		 886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
18068523 894
18068523
GOC		 895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
50d0a0f9
GH		 897 /*
898 * The guest calculates current wall clock time by adding
34c238a1 899 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
923de3cf 903 getboottime(&boot);
50d0a0f9
GH		 904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
18068523
GOC		 908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 913}
914
50d0a0f9
GH		 915static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916{
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925}
926
5f4e3f88
ZA		 927static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
50d0a0f9 929{
5f4e3f88 930 uint64_t scaled64;
50d0a0f9
GH		 931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
5f4e3f88
ZA		 935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
50933623 937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
50933623
JK		 943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
50d0a0f9
GH		 948 shift++;
949 }
950
5f4e3f88
ZA		 951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 953
5f4e3f88
ZA		 954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 956}
957
759379dd
ZA		 958static inline u64 get_kernel_ns(void)
959{
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
50d0a0f9
GH		 966}
967
c8076604 968static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 969unsigned long max_tsc_khz;
c8076604 970
8cfdc000
ZA		 971static inline int kvm_tsc_changes_freq(void)
972{
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978}
979
a3e06bbe 980u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1e993611
JR		 981{
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
984 else
985 return __this_cpu_read(cpu_tsc_khz);
986}
987
857e4099 988static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 989{
217fc9cf
AK		 990 u64 ret;
991
759379dd
ZA		 992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 996 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 997 do_div(ret, USEC_PER_SEC);
998 return ret;
759379dd
ZA		 999}
1000
1e993611 1001static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1002{
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1007}
1008
1009static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1010{
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1014 tsc += vcpu->arch.last_tsc_write;
1015 return tsc;
1016}
1017
99e3e30a
ZA		 1018void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1019{
1020 struct kvm *kvm = vcpu->kvm;
f38e098f 1021 u64 offset, ns, elapsed;
99e3e30a 1022 unsigned long flags;
46543ba4 1023 s64 sdiff;
99e3e30a 1024
038f8c11 1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1027 ns = get_kernel_ns();
f38e098f 1028 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1029 sdiff = data - kvm->arch.last_tsc_write;
1030 if (sdiff < 0)
1031 sdiff = -sdiff;
f38e098f
ZA		 1032
1033 /*
46543ba4 1034 * Special case: close write to TSC within 5 seconds of
f38e098f 1035 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1036 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1037 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1038 *
1039 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1040 * or make a best guest using elapsed value.
f38e098f 1041 */
857e4099 1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1043 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1047 } else {
857e4099 1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1049 offset += delta;
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1051 }
1052 ns = kvm->arch.last_tsc_nsec;
1053 }
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
99e3e30a 1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1059
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1064}
1065EXPORT_SYMBOL_GPL(kvm_write_tsc);
1066
34c238a1 1067static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1068{
18068523
GOC		 1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1071 void *shared_kaddr;
463656c0 1072 unsigned long this_tsc_khz;
1d5f066e
ZA		 1073 s64 kernel_ns, max_kernel_ns;
1074 u64 tsc_timestamp;
18068523 1075
18068523
GOC		 1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
d5c1785d 1078 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1079 kernel_ns = get_kernel_ns();
1e993611 1080 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1081 if (unlikely(this_tsc_khz == 0)) {
c285545f 1082 local_irq_restore(flags);
34c238a1 1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1084 return 1;
1085 }
18068523 1086
c285545f
ZA		 1087 /*
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1095 * very slowly.
1096 */
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1102 }
50d0a0f9
GH		 1103 }
1104
18068523
GOC		 1105 local_irq_restore(flags);
1106
c285545f
ZA		 1107 if (!vcpu->time_page)
1108 return 0;
18068523 1109
1d5f066e
ZA		 1110 /*
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1123 *
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1125 *
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1130 */
1131 max_kernel_ns = 0;
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1139 }
afbcf7ab 1140
e48672fa 1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1145 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1146 }
1147
1d5f066e
ZA		 1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1150
8cfdc000 1151 /* With all the info we got, fill in the values */
1d5f066e 1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1154 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1155 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1156 vcpu->hv_clock.flags = 0;
1157
18068523
GOC		 1158 /*
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1161 * state, we just increase by 2 at the end.
18068523 1162 */
50d0a0f9 1163 vcpu->hv_clock.version += 2;
18068523
GOC		 1164
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1166
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1168 sizeof(vcpu->hv_clock));
18068523
GOC		 1169
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1171
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1173 return 0;
c8076604
GH		 1174}
1175
9ba075a6
AK		 1176static bool msr_mtrr_valid(unsigned msr)
1177{
1178 switch (msr) {
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1193 return true;
1194 case 0x2f8:
1195 return true;
1196 }
1197 return false;
1198}
1199
d6289b93
MT		 1200static bool valid_pat_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1203}
1204
1205static bool valid_mtrr_type(unsigned t)
1206{
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1208}
1209
1210static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1211{
1212 int i;
1213
1214 if (!msr_mtrr_valid(msr))
1215 return false;
1216
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 } else if (msr == MSR_MTRRdefType) {
1223 if (data & ~0xcff)
1224 return false;
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1229 return false;
1230 return true;
1231 }
1232
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1235}
1236
9ba075a6
AK		 1237static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
d6289b93 1241 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1248 p[0] = data;
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pt = data;
1268 }
1269
1270 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1271 return 0;
1272}
15c4a640 1273
890ca9ae 1274static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1275{
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1278
15c4a640 1279 switch (msr) {
15c4a640 1280 case MSR_IA32_MCG_STATUS:
890ca9ae 1281 vcpu->arch.mcg_status = data;
15c4a640 1282 break;
c7ac679c 1283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 if (data != 0 && data != ~(u64)0)
1287 return -1;
1288 vcpu->arch.mcg_ctl = data;
1289 break;
1290 default:
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1298 */
890ca9ae 1299 if ((offset & 0x3) == 0 &&
114be429 1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1301 return -1;
1302 vcpu->arch.mce_banks[offset] = data;
1303 break;
1304 }
1305 return 1;
1306 }
1307 return 0;
1308}
1309
ffde22ac
ES		 1310static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1311{
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1320 u8 *page;
1321 int r;
1322
1323 r = -E2BIG;
1324 if (page_num >= blob_size)
1325 goto out;
1326 r = -ENOMEM;
ff5c2c03
SL		 1327 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1328 if (IS_ERR(page)) {
1329 r = PTR_ERR(page);
ffde22ac 1330 goto out;
ff5c2c03 1331 }
ffde22ac
ES		 1332 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1333 goto out_free;
1334 r = 0;
1335out_free:
1336 kfree(page);
1337out:
1338 return r;
1339}
1340
55cd8e5a
GN		 1341static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1342{
1343 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1344}
1345
1346static bool kvm_hv_msr_partition_wide(u32 msr)
1347{
1348 bool r = false;
1349 switch (msr) {
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 case HV_X64_MSR_HYPERCALL:
1352 r = true;
1353 break;
1354 }
1355
1356 return r;
1357}
1358
1359static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1360{
1361 struct kvm *kvm = vcpu->kvm;
1362
1363 switch (msr) {
1364 case HV_X64_MSR_GUEST_OS_ID:
1365 kvm->arch.hv_guest_os_id = data;
1366 /* setting guest os id to zero disables hypercall page */
1367 if (!kvm->arch.hv_guest_os_id)
1368 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1369 break;
1370 case HV_X64_MSR_HYPERCALL: {
1371 u64 gfn;
1372 unsigned long addr;
1373 u8 instructions[4];
1374
1375 /* if guest os id is not set hypercall should remain disabled */
1376 if (!kvm->arch.hv_guest_os_id)
1377 break;
1378 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1379 kvm->arch.hv_hypercall = data;
1380 break;
1381 }
1382 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1383 addr = gfn_to_hva(kvm, gfn);
1384 if (kvm_is_error_hva(addr))
1385 return 1;
1386 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1387 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1388 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1389 return 1;
1390 kvm->arch.hv_hypercall = data;
1391 break;
1392 }
1393 default:
1394 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1395 "data 0x%llx\n", msr, data);
1396 return 1;
1397 }
1398 return 0;
1399}
1400
1401static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1402{
10388a07
GN		 1403 switch (msr) {
1404 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1405 unsigned long addr;
55cd8e5a 1406
10388a07
GN		 1407 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1408 vcpu->arch.hv_vapic = data;
1409 break;
1410 }
1411 addr = gfn_to_hva(vcpu->kvm, data >>
1412 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1413 if (kvm_is_error_hva(addr))
1414 return 1;
8b0cedff 1415 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1416 return 1;
1417 vcpu->arch.hv_vapic = data;
1418 break;
1419 }
1420 case HV_X64_MSR_EOI:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1422 case HV_X64_MSR_ICR:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1424 case HV_X64_MSR_TPR:
1425 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1426 default:
1427 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1428 "data 0x%llx\n", msr, data);
1429 return 1;
1430 }
1431
1432 return 0;
55cd8e5a
GN		 1433}
1434
344d9588
GN		 1435static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1436{
1437 gpa_t gpa = data & ~0x3f;
1438
6adba527
GN		 1439 /* Bits 2:5 are resrved, Should be zero */
1440 if (data & 0x3c)
344d9588
GN		 1441 return 1;
1442
1443 vcpu->arch.apf.msr_val = data;
1444
1445 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1446 kvm_clear_async_pf_completion_queue(vcpu);
1447 kvm_async_pf_hash_reset(vcpu);
1448 return 0;
1449 }
1450
1451 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1452 return 1;
1453
6adba527 1454 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1455 kvm_async_pf_wakeup_all(vcpu);
1456 return 0;
1457}
1458
12f9a48f
GC		 1459static void kvmclock_reset(struct kvm_vcpu *vcpu)
1460{
1461 if (vcpu->arch.time_page) {
1462 kvm_release_page_dirty(vcpu->arch.time_page);
1463 vcpu->arch.time_page = NULL;
1464 }
1465}
1466
c9aaa895
GC		 1467static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1468{
1469 u64 delta;
1470
1471 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1472 return;
1473
1474 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1475 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1476 vcpu->arch.st.accum_steal = delta;
1477}
1478
1479static void record_steal_time(struct kvm_vcpu *vcpu)
1480{
1481 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1482 return;
1483
1484 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1485 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1486 return;
1487
1488 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1489 vcpu->arch.st.steal.version += 2;
1490 vcpu->arch.st.accum_steal = 0;
1491
1492 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1493 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1494}
1495
15c4a640
CO		 1496int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1497{
1498 switch (msr) {
15c4a640 1499 case MSR_EFER:
b69e8cae 1500 return set_efer(vcpu, data);
8f1589d9
AP		 1501 case MSR_K7_HWCR:
1502 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1503 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1504 if (data != 0) {
1505 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1506 data);
1507 return 1;
1508 }
15c4a640 1509 break;
f7c6d140
AP		 1510 case MSR_FAM10H_MMIO_CONF_BASE:
1511 if (data != 0) {
1512 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1513 "0x%llx\n", data);
1514 return 1;
1515 }
15c4a640 1516 break;
c323c0e5 1517 case MSR_AMD64_NB_CFG:
c7ac679c 1518 break;
b5e2fec0
AG		 1519 case MSR_IA32_DEBUGCTLMSR:
1520 if (!data) {
1521 /* We support the non-activated case already */
1522 break;
1523 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1524 /* Values other than LBR and BTF are vendor-specific,
1525 thus reserved and should throw a #GP */
1526 return 1;
1527 }
1528 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1529 __func__, data);
1530 break;
15c4a640
CO		 1531 case MSR_IA32_UCODE_REV:
1532 case MSR_IA32_UCODE_WRITE:
61a6bd67 1533 case MSR_VM_HSAVE_PA:
6098ca93 1534 case MSR_AMD64_PATCH_LOADER:
15c4a640 1535 break;
9ba075a6
AK		 1536 case 0x200 ... 0x2ff:
1537 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1538 case MSR_IA32_APICBASE:
1539 kvm_set_apic_base(vcpu, data);
1540 break;
0105d1a5
GN		 1541 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1542 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1543 case MSR_IA32_TSCDEADLINE:
1544 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1545 break;
15c4a640 1546 case MSR_IA32_MISC_ENABLE:
ad312c7c 1547 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1548 break;
11c6bffa 1549 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1550 case MSR_KVM_WALL_CLOCK:
1551 vcpu->kvm->arch.wall_clock = data;
1552 kvm_write_wall_clock(vcpu->kvm, data);
1553 break;
11c6bffa 1554 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1555 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1556 kvmclock_reset(vcpu);
18068523
GOC		 1557
1558 vcpu->arch.time = data;
c285545f 1559 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1560
1561 /* we verify if the enable bit is set... */
1562 if (!(data & 1))
1563 break;
1564
1565 /* ...but clean it before doing the actual write */
1566 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1567
18068523
GOC		 1568 vcpu->arch.time_page =
1569 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1570
1571 if (is_error_page(vcpu->arch.time_page)) {
1572 kvm_release_page_clean(vcpu->arch.time_page);
1573 vcpu->arch.time_page = NULL;
1574 }
18068523
GOC		 1575 break;
1576 }
344d9588
GN		 1577 case MSR_KVM_ASYNC_PF_EN:
1578 if (kvm_pv_enable_async_pf(vcpu, data))
1579 return 1;
1580 break;
c9aaa895
GC		 1581 case MSR_KVM_STEAL_TIME:
1582
1583 if (unlikely(!sched_info_on()))
1584 return 1;
1585
1586 if (data & KVM_STEAL_RESERVED_MASK)
1587 return 1;
1588
1589 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1590 data & KVM_STEAL_VALID_BITS))
1591 return 1;
1592
1593 vcpu->arch.st.msr_val = data;
1594
1595 if (!(data & KVM_MSR_ENABLED))
1596 break;
1597
1598 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1599
1600 preempt_disable();
1601 accumulate_steal_time(vcpu);
1602 preempt_enable();
1603
1604 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1605
1606 break;
1607
890ca9ae
HY		 1608 case MSR_IA32_MCG_CTL:
1609 case MSR_IA32_MCG_STATUS:
1610 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1611 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1612
1613 /* Performance counters are not protected by a CPUID bit,
1614 * so we should check all of them in the generic path for the sake of
1615 * cross vendor migration.
1616 * Writing a zero into the event select MSRs disables them,
1617 * which we perfectly emulate ;-). Any other value should be at least
1618 * reported, some guests depend on them.
1619 */
71db6023
AP		 1620 case MSR_K7_EVNTSEL0:
1621 case MSR_K7_EVNTSEL1:
1622 case MSR_K7_EVNTSEL2:
1623 case MSR_K7_EVNTSEL3:
1624 if (data != 0)
1625 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1626 "0x%x data 0x%llx\n", msr, data);
1627 break;
1628 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1629 * so we ignore writes to make it happy.
1630 */
71db6023
AP		 1631 case MSR_K7_PERFCTR0:
1632 case MSR_K7_PERFCTR1:
1633 case MSR_K7_PERFCTR2:
1634 case MSR_K7_PERFCTR3:
1635 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1636 "0x%x data 0x%llx\n", msr, data);
1637 break;
84e0cefa
JS		 1638 case MSR_K7_CLK_CTL:
1639 /*
1640 * Ignore all writes to this no longer documented MSR.
1641 * Writes are only relevant for old K7 processors,
1642 * all pre-dating SVM, but a recommended workaround from
1643 * AMD for these chips. It is possible to speicify the
1644 * affected processor models on the command line, hence
1645 * the need to ignore the workaround.
1646 */
1647 break;
55cd8e5a
GN		 1648 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1649 if (kvm_hv_msr_partition_wide(msr)) {
1650 int r;
1651 mutex_lock(&vcpu->kvm->lock);
1652 r = set_msr_hyperv_pw(vcpu, msr, data);
1653 mutex_unlock(&vcpu->kvm->lock);
1654 return r;
1655 } else
1656 return set_msr_hyperv(vcpu, msr, data);
1657 break;
91c9c3ed 1658 case MSR_IA32_BBL_CR_CTL3:
1659 /* Drop writes to this legacy MSR -- see rdmsr
1660 * counterpart for further detail.
1661 */
1662 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1663 break;
15c4a640 1664 default:
ffde22ac
ES		 1665 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1666 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1667 if (kvm_pmu_msr(vcpu, msr))
1668 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1669 if (!ignore_msrs) {
1670 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1671 msr, data);
1672 return 1;
1673 } else {
1674 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1675 msr, data);
1676 break;
1677 }
15c4a640
CO		 1678 }
1679 return 0;
1680}
1681EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1682
1683
1684/*
1685 * Reads an msr value (of 'msr_index') into 'pdata'.
1686 * Returns 0 on success, non-0 otherwise.
1687 * Assumes vcpu_load() was already called.
1688 */
1689int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1690{
1691 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1692}
1693
9ba075a6
AK		 1694static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1695{
0bed3b56
SY		 1696 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1697
9ba075a6
AK		 1698 if (!msr_mtrr_valid(msr))
1699 return 1;
1700
0bed3b56
SY		 1701 if (msr == MSR_MTRRdefType)
1702 *pdata = vcpu->arch.mtrr_state.def_type +
1703 (vcpu->arch.mtrr_state.enabled << 10);
1704 else if (msr == MSR_MTRRfix64K_00000)
1705 *pdata = p[0];
1706 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1707 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1708 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1709 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1710 else if (msr == MSR_IA32_CR_PAT)
1711 *pdata = vcpu->arch.pat;
1712 else { /* Variable MTRRs */
1713 int idx, is_mtrr_mask;
1714 u64 *pt;
1715
1716 idx = (msr - 0x200) / 2;
1717 is_mtrr_mask = msr - 0x200 - 2 * idx;
1718 if (!is_mtrr_mask)
1719 pt =
1720 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1721 else
1722 pt =
1723 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1724 *pdata = *pt;
1725 }
1726
9ba075a6
AK		 1727 return 0;
1728}
1729
890ca9ae 1730static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1731{
1732 u64 data;
890ca9ae
HY		 1733 u64 mcg_cap = vcpu->arch.mcg_cap;
1734 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1735
1736 switch (msr) {
15c4a640
CO		 1737 case MSR_IA32_P5_MC_ADDR:
1738 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1739 data = 0;
1740 break;
15c4a640 1741 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1742 data = vcpu->arch.mcg_cap;
1743 break;
c7ac679c 1744 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1745 if (!(mcg_cap & MCG_CTL_P))
1746 return 1;
1747 data = vcpu->arch.mcg_ctl;
1748 break;
1749 case MSR_IA32_MCG_STATUS:
1750 data = vcpu->arch.mcg_status;
1751 break;
1752 default:
1753 if (msr >= MSR_IA32_MC0_CTL &&
1754 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1755 u32 offset = msr - MSR_IA32_MC0_CTL;
1756 data = vcpu->arch.mce_banks[offset];
1757 break;
1758 }
1759 return 1;
1760 }
1761 *pdata = data;
1762 return 0;
1763}
1764
55cd8e5a
GN		 1765static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1766{
1767 u64 data = 0;
1768 struct kvm *kvm = vcpu->kvm;
1769
1770 switch (msr) {
1771 case HV_X64_MSR_GUEST_OS_ID:
1772 data = kvm->arch.hv_guest_os_id;
1773 break;
1774 case HV_X64_MSR_HYPERCALL:
1775 data = kvm->arch.hv_hypercall;
1776 break;
1777 default:
1778 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1779 return 1;
1780 }
1781
1782 *pdata = data;
1783 return 0;
1784}
1785
1786static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1787{
1788 u64 data = 0;
1789
1790 switch (msr) {
1791 case HV_X64_MSR_VP_INDEX: {
1792 int r;
1793 struct kvm_vcpu *v;
1794 kvm_for_each_vcpu(r, v, vcpu->kvm)
1795 if (v == vcpu)
1796 data = r;
1797 break;
1798 }
10388a07
GN		 1799 case HV_X64_MSR_EOI:
1800 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1801 case HV_X64_MSR_ICR:
1802 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1803 case HV_X64_MSR_TPR:
1804 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1805 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1806 data = vcpu->arch.hv_vapic;
1807 break;
55cd8e5a
GN		 1808 default:
1809 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1810 return 1;
1811 }
1812 *pdata = data;
1813 return 0;
1814}
1815
890ca9ae
HY		 1816int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1817{
1818 u64 data;
1819
1820 switch (msr) {
890ca9ae 1821 case MSR_IA32_PLATFORM_ID:
15c4a640 1822 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1823 case MSR_IA32_DEBUGCTLMSR:
1824 case MSR_IA32_LASTBRANCHFROMIP:
1825 case MSR_IA32_LASTBRANCHTOIP:
1826 case MSR_IA32_LASTINTFROMIP:
1827 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1828 case MSR_K8_SYSCFG:
1829 case MSR_K7_HWCR:
61a6bd67 1830 case MSR_VM_HSAVE_PA:
9e699624 1831 case MSR_K7_EVNTSEL0:
1f3ee616 1832 case MSR_K7_PERFCTR0:
1fdbd48c 1833 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1834 case MSR_AMD64_NB_CFG:
f7c6d140 1835 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1836 data = 0;
1837 break;
742bc670
MT		 1838 case MSR_IA32_UCODE_REV:
1839 data = 0x100000000ULL;
1840 break;
9ba075a6
AK		 1841 case MSR_MTRRcap:
1842 data = 0x500 | KVM_NR_VAR_MTRR;
1843 break;
1844 case 0x200 ... 0x2ff:
1845 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1846 case 0xcd: /* fsb frequency */
1847 data = 3;
1848 break;
7b914098
JS		 1849 /*
1850 * MSR_EBC_FREQUENCY_ID
1851 * Conservative value valid for even the basic CPU models.
1852 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1853 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1854 * and 266MHz for model 3, or 4. Set Core Clock
1855 * Frequency to System Bus Frequency Ratio to 1 (bits
1856 * 31:24) even though these are only valid for CPU
1857 * models > 2, however guests may end up dividing or
1858 * multiplying by zero otherwise.
1859 */
1860 case MSR_EBC_FREQUENCY_ID:
1861 data = 1 << 24;
1862 break;
15c4a640
CO		 1863 case MSR_IA32_APICBASE:
1864 data = kvm_get_apic_base(vcpu);
1865 break;
0105d1a5
GN		 1866 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1867 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1868 break;
a3e06bbe
LJ		 1869 case MSR_IA32_TSCDEADLINE:
1870 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1871 break;
15c4a640 1872 case MSR_IA32_MISC_ENABLE:
ad312c7c 1873 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1874 break;
847f0ad8
AG		 1875 case MSR_IA32_PERF_STATUS:
1876 /* TSC increment by tick */
1877 data = 1000ULL;
1878 /* CPU multiplier */
1879 data |= (((uint64_t)4ULL) << 40);
1880 break;
15c4a640 1881 case MSR_EFER:
f6801dff 1882 data = vcpu->arch.efer;
15c4a640 1883 break;
18068523 1884 case MSR_KVM_WALL_CLOCK:
11c6bffa 1885 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1886 data = vcpu->kvm->arch.wall_clock;
1887 break;
1888 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1889 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1890 data = vcpu->arch.time;
1891 break;
344d9588
GN		 1892 case MSR_KVM_ASYNC_PF_EN:
1893 data = vcpu->arch.apf.msr_val;
1894 break;
c9aaa895
GC		 1895 case MSR_KVM_STEAL_TIME:
1896 data = vcpu->arch.st.msr_val;
1897 break;
890ca9ae
HY		 1898 case MSR_IA32_P5_MC_ADDR:
1899 case MSR_IA32_P5_MC_TYPE:
1900 case MSR_IA32_MCG_CAP:
1901 case MSR_IA32_MCG_CTL:
1902 case MSR_IA32_MCG_STATUS:
1903 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1904 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1905 case MSR_K7_CLK_CTL:
1906 /*
1907 * Provide expected ramp-up count for K7. All other
1908 * are set to zero, indicating minimum divisors for
1909 * every field.
1910 *
1911 * This prevents guest kernels on AMD host with CPU
1912 * type 6, model 8 and higher from exploding due to
1913 * the rdmsr failing.
1914 */
1915 data = 0x20000000;
1916 break;
55cd8e5a
GN		 1917 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1918 if (kvm_hv_msr_partition_wide(msr)) {
1919 int r;
1920 mutex_lock(&vcpu->kvm->lock);
1921 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1922 mutex_unlock(&vcpu->kvm->lock);
1923 return r;
1924 } else
1925 return get_msr_hyperv(vcpu, msr, pdata);
1926 break;
91c9c3ed 1927 case MSR_IA32_BBL_CR_CTL3:
1928 /* This legacy MSR exists but isn't fully documented in current
1929 * silicon. It is however accessed by winxp in very narrow
1930 * scenarios where it sets bit #19, itself documented as
1931 * a "reserved" bit. Best effort attempt to source coherent
1932 * read data here should the balance of the register be
1933 * interpreted by the guest:
1934 *
1935 * L2 cache control register 3: 64GB range, 256KB size,
1936 * enabled, latency 0x1, configured
1937 */
1938 data = 0xbe702111;
1939 break;
15c4a640 1940 default:
f5132b01
GN		 1941 if (kvm_pmu_msr(vcpu, msr))
1942 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 1943 if (!ignore_msrs) {
1944 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1945 return 1;
1946 } else {
1947 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1948 data = 0;
1949 }
1950 break;
15c4a640
CO		 1951 }
1952 *pdata = data;
1953 return 0;
1954}
1955EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1956
313a3dc7
CO		 1957/*
1958 * Read or write a bunch of msrs. All parameters are kernel addresses.
1959 *
1960 * @return number of msrs set successfully.
1961 */
1962static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1963 struct kvm_msr_entry *entries,
1964 int (*do_msr)(struct kvm_vcpu *vcpu,
1965 unsigned index, u64 *data))
1966{
f656ce01 1967 int i, idx;
313a3dc7 1968
f656ce01 1969 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1970 for (i = 0; i < msrs->nmsrs; ++i)
1971 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1972 break;
f656ce01 1973 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1974
313a3dc7
CO		 1975 return i;
1976}
1977
1978/*
1979 * Read or write a bunch of msrs. Parameters are user addresses.
1980 *
1981 * @return number of msrs set successfully.
1982 */
1983static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1984 int (*do_msr)(struct kvm_vcpu *vcpu,
1985 unsigned index, u64 *data),
1986 int writeback)
1987{
1988 struct kvm_msrs msrs;
1989 struct kvm_msr_entry *entries;
1990 int r, n;
1991 unsigned size;
1992
1993 r = -EFAULT;
1994 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1995 goto out;
1996
1997 r = -E2BIG;
1998 if (msrs.nmsrs >= MAX_IO_MSRS)
1999 goto out;
2000
313a3dc7 2001 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2002 entries = memdup_user(user_msrs->entries, size);
2003 if (IS_ERR(entries)) {
2004 r = PTR_ERR(entries);
313a3dc7 2005 goto out;
ff5c2c03 2006 }
313a3dc7
CO		 2007
2008 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2009 if (r < 0)
2010 goto out_free;
2011
2012 r = -EFAULT;
2013 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2014 goto out_free;
2015
2016 r = n;
2017
2018out_free:
7a73c028 2019 kfree(entries);
313a3dc7
CO		 2020out:
2021 return r;
2022}
2023
018d00d2
ZX		 2024int kvm_dev_ioctl_check_extension(long ext)
2025{
2026 int r;
2027
2028 switch (ext) {
2029 case KVM_CAP_IRQCHIP:
2030 case KVM_CAP_HLT:
2031 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2032 case KVM_CAP_SET_TSS_ADDR:
07716717 2033 case KVM_CAP_EXT_CPUID:
c8076604 2034 case KVM_CAP_CLOCKSOURCE:
7837699f 2035 case KVM_CAP_PIT:
a28e4f5a 2036 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2037 case KVM_CAP_MP_STATE:
ed848624 2038 case KVM_CAP_SYNC_MMU:
a355c85c 2039 case KVM_CAP_USER_NMI:
52d939a0 2040 case KVM_CAP_REINJECT_CONTROL:
4925663a 2041 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2042 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2043 case KVM_CAP_IRQFD:
d34e6b17 2044 case KVM_CAP_IOEVENTFD:
c5ff41ce 2045 case KVM_CAP_PIT2:
e9f42757 2046 case KVM_CAP_PIT_STATE2:
b927a3ce 2047 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2048 case KVM_CAP_XEN_HVM:
afbcf7ab 2049 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2050 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2051 case KVM_CAP_HYPERV:
10388a07 2052 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2053 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2054 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2055 case KVM_CAP_DEBUGREGS:
d2be1651 2056 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2057 case KVM_CAP_XSAVE:
344d9588 2058 case KVM_CAP_ASYNC_PF:
92a1f12d 2059 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2060 r = 1;
2061 break;
542472b5
LV		 2062 case KVM_CAP_COALESCED_MMIO:
2063 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2064 break;
774ead3a
AK		 2065 case KVM_CAP_VAPIC:
2066 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2067 break;
f725230a 2068 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2069 r = KVM_SOFT_MAX_VCPUS;
2070 break;
2071 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2072 r = KVM_MAX_VCPUS;
2073 break;
a988b910
AK		 2074 case KVM_CAP_NR_MEMSLOTS:
2075 r = KVM_MEMORY_SLOTS;
2076 break;
a68a6a72
MT		 2077 case KVM_CAP_PV_MMU: /* obsolete */
2078 r = 0;
2f333bcb 2079 break;
62c476c7 2080 case KVM_CAP_IOMMU:
a1b60c1c 2081 r = iommu_present(&pci_bus_type);
62c476c7 2082 break;
890ca9ae
HY		 2083 case KVM_CAP_MCE:
2084 r = KVM_MAX_MCE_BANKS;
2085 break;
2d5b5a66
SY		 2086 case KVM_CAP_XCRS:
2087 r = cpu_has_xsave;
2088 break;
92a1f12d
JR		 2089 case KVM_CAP_TSC_CONTROL:
2090 r = kvm_has_tsc_control;
2091 break;
4d25a066
JK		 2092 case KVM_CAP_TSC_DEADLINE_TIMER:
2093 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2094 break;
018d00d2
ZX		 2095 default:
2096 r = 0;
2097 break;
2098 }
2099 return r;
2100
2101}
2102
043405e1
CO		 2103long kvm_arch_dev_ioctl(struct file *filp,
2104 unsigned int ioctl, unsigned long arg)
2105{
2106 void __user *argp = (void __user *)arg;
2107 long r;
2108
2109 switch (ioctl) {
2110 case KVM_GET_MSR_INDEX_LIST: {
2111 struct kvm_msr_list __user *user_msr_list = argp;
2112 struct kvm_msr_list msr_list;
2113 unsigned n;
2114
2115 r = -EFAULT;
2116 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2117 goto out;
2118 n = msr_list.nmsrs;
2119 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2120 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2121 goto out;
2122 r = -E2BIG;
e125e7b6 2123 if (n < msr_list.nmsrs)
043405e1
CO		 2124 goto out;
2125 r = -EFAULT;
2126 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2127 num_msrs_to_save * sizeof(u32)))
2128 goto out;
e125e7b6 2129 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2130 &emulated_msrs,
2131 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2132 goto out;
2133 r = 0;
2134 break;
2135 }
674eea0f
AK		 2136 case KVM_GET_SUPPORTED_CPUID: {
2137 struct kvm_cpuid2 __user *cpuid_arg = argp;
2138 struct kvm_cpuid2 cpuid;
2139
2140 r = -EFAULT;
2141 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2142 goto out;
2143 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2144 cpuid_arg->entries);
674eea0f
AK		 2145 if (r)
2146 goto out;
2147
2148 r = -EFAULT;
2149 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2150 goto out;
2151 r = 0;
2152 break;
2153 }
890ca9ae
HY		 2154 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2155 u64 mce_cap;
2156
2157 mce_cap = KVM_MCE_CAP_SUPPORTED;
2158 r = -EFAULT;
2159 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2160 goto out;
2161 r = 0;
2162 break;
2163 }
043405e1
CO		 2164 default:
2165 r = -EINVAL;
2166 }
2167out:
2168 return r;
2169}
2170
f5f48ee1
SY		 2171static void wbinvd_ipi(void *garbage)
2172{
2173 wbinvd();
2174}
2175
2176static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2177{
2178 return vcpu->kvm->arch.iommu_domain &&
2179 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2180}
2181
313a3dc7
CO		 2182void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2183{
f5f48ee1
SY		 2184 /* Address WBINVD may be executed by guest */
2185 if (need_emulate_wbinvd(vcpu)) {
2186 if (kvm_x86_ops->has_wbinvd_exit())
2187 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2188 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2189 smp_call_function_single(vcpu->cpu,
2190 wbinvd_ipi, NULL, 1);
2191 }
2192
313a3dc7 2193 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2194 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2195 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2196 s64 tsc_delta;
2197 u64 tsc;
2198
d5c1785d 2199 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2200 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2201 tsc - vcpu->arch.last_guest_tsc;
2202
e48672fa
ZA		 2203 if (tsc_delta < 0)
2204 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2205 if (check_tsc_unstable()) {
e48672fa 2206 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2207 vcpu->arch.tsc_catchup = 1;
c285545f 2208 }
1aa8ceef 2209 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2210 if (vcpu->cpu != cpu)
2211 kvm_migrate_timers(vcpu);
e48672fa 2212 vcpu->cpu = cpu;
6b7d7e76 2213 }
c9aaa895
GC		 2214
2215 accumulate_steal_time(vcpu);
2216 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2217}
2218
2219void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2220{
02daab21 2221 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2222 kvm_put_guest_fpu(vcpu);
d5c1785d 2223 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2224}
2225
313a3dc7
CO		 2226static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2227 struct kvm_lapic_state *s)
2228{
ad312c7c 2229 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2230
2231 return 0;
2232}
2233
2234static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2235 struct kvm_lapic_state *s)
2236{
ad312c7c 2237 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2238 kvm_apic_post_state_restore(vcpu);
cb142eb7 2239 update_cr8_intercept(vcpu);
313a3dc7
CO		 2240
2241 return 0;
2242}
2243
f77bc6a4
ZX		 2244static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2245 struct kvm_interrupt *irq)
2246{
2247 if (irq->irq < 0 || irq->irq >= 256)
2248 return -EINVAL;
2249 if (irqchip_in_kernel(vcpu->kvm))
2250 return -ENXIO;
f77bc6a4 2251
66fd3f7f 2252 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2253 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2254
f77bc6a4
ZX		 2255 return 0;
2256}
2257
c4abb7c9
JK		 2258static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2259{
c4abb7c9 2260 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2261
2262 return 0;
2263}
2264
b209749f
AK		 2265static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2266 struct kvm_tpr_access_ctl *tac)
2267{
2268 if (tac->flags)
2269 return -EINVAL;
2270 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2271 return 0;
2272}
2273
890ca9ae
HY		 2274static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2275 u64 mcg_cap)
2276{
2277 int r;
2278 unsigned bank_num = mcg_cap & 0xff, bank;
2279
2280 r = -EINVAL;
a9e38c3e 2281 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2282 goto out;
2283 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2284 goto out;
2285 r = 0;
2286 vcpu->arch.mcg_cap = mcg_cap;
2287 /* Init IA32_MCG_CTL to all 1s */
2288 if (mcg_cap & MCG_CTL_P)
2289 vcpu->arch.mcg_ctl = ~(u64)0;
2290 /* Init IA32_MCi_CTL to all 1s */
2291 for (bank = 0; bank < bank_num; bank++)
2292 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2293out:
2294 return r;
2295}
2296
2297static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2298 struct kvm_x86_mce *mce)
2299{
2300 u64 mcg_cap = vcpu->arch.mcg_cap;
2301 unsigned bank_num = mcg_cap & 0xff;
2302 u64 *banks = vcpu->arch.mce_banks;
2303
2304 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2305 return -EINVAL;
2306 /*
2307 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2308 * reporting is disabled
2309 */
2310 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2311 vcpu->arch.mcg_ctl != ~(u64)0)
2312 return 0;
2313 banks += 4 * mce->bank;
2314 /*
2315 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2316 * reporting is disabled for the bank
2317 */
2318 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2319 return 0;
2320 if (mce->status & MCI_STATUS_UC) {
2321 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2322 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2323 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2324 return 0;
2325 }
2326 if (banks[1] & MCI_STATUS_VAL)
2327 mce->status |= MCI_STATUS_OVER;
2328 banks[2] = mce->addr;
2329 banks[3] = mce->misc;
2330 vcpu->arch.mcg_status = mce->mcg_status;
2331 banks[1] = mce->status;
2332 kvm_queue_exception(vcpu, MC_VECTOR);
2333 } else if (!(banks[1] & MCI_STATUS_VAL)
2334 || !(banks[1] & MCI_STATUS_UC)) {
2335 if (banks[1] & MCI_STATUS_VAL)
2336 mce->status |= MCI_STATUS_OVER;
2337 banks[2] = mce->addr;
2338 banks[3] = mce->misc;
2339 banks[1] = mce->status;
2340 } else
2341 banks[1] |= MCI_STATUS_OVER;
2342 return 0;
2343}
2344
3cfc3092
JK		 2345static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2346 struct kvm_vcpu_events *events)
2347{
7460fb4a 2348 process_nmi(vcpu);
03b82a30
JK		 2349 events->exception.injected =
2350 vcpu->arch.exception.pending &&
2351 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2352 events->exception.nr = vcpu->arch.exception.nr;
2353 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2354 events->exception.pad = 0;
3cfc3092
JK		 2355 events->exception.error_code = vcpu->arch.exception.error_code;
2356
03b82a30
JK		 2357 events->interrupt.injected =
2358 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2359 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2360 events->interrupt.soft = 0;
48005f64
JK		 2361 events->interrupt.shadow =
2362 kvm_x86_ops->get_interrupt_shadow(vcpu,
2363 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2364
2365 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2366 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2367 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2368 events->nmi.pad = 0;
3cfc3092
JK		 2369
2370 events->sipi_vector = vcpu->arch.sipi_vector;
2371
dab4b911 2372 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2373 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2374 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2375 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2376}
2377
2378static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2379 struct kvm_vcpu_events *events)
2380{
dab4b911 2381 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2382 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2383 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2384 return -EINVAL;
2385
7460fb4a 2386 process_nmi(vcpu);
3cfc3092
JK		 2387 vcpu->arch.exception.pending = events->exception.injected;
2388 vcpu->arch.exception.nr = events->exception.nr;
2389 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2390 vcpu->arch.exception.error_code = events->exception.error_code;
2391
2392 vcpu->arch.interrupt.pending = events->interrupt.injected;
2393 vcpu->arch.interrupt.nr = events->interrupt.nr;
2394 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2395 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2396 kvm_x86_ops->set_interrupt_shadow(vcpu,
2397 events->interrupt.shadow);
3cfc3092
JK		 2398
2399 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2400 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2401 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2402 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2403
dab4b911
JK		 2404 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2405 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2406
3842d135
AK		 2407 kvm_make_request(KVM_REQ_EVENT, vcpu);
2408
3cfc3092
JK		 2409 return 0;
2410}
2411
a1efbe77
JK		 2412static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2413 struct kvm_debugregs *dbgregs)
2414{
a1efbe77
JK		 2415 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2416 dbgregs->dr6 = vcpu->arch.dr6;
2417 dbgregs->dr7 = vcpu->arch.dr7;
2418 dbgregs->flags = 0;
97e69aa6 2419 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2420}
2421
2422static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2423 struct kvm_debugregs *dbgregs)
2424{
2425 if (dbgregs->flags)
2426 return -EINVAL;
2427
a1efbe77
JK		 2428 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2429 vcpu->arch.dr6 = dbgregs->dr6;
2430 vcpu->arch.dr7 = dbgregs->dr7;
2431
a1efbe77
JK		 2432 return 0;
2433}
2434
2d5b5a66
SY		 2435static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2436 struct kvm_xsave *guest_xsave)
2437{
2438 if (cpu_has_xsave)
2439 memcpy(guest_xsave->region,
2440 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2441 xstate_size);
2d5b5a66
SY		 2442 else {
2443 memcpy(guest_xsave->region,
2444 &vcpu->arch.guest_fpu.state->fxsave,
2445 sizeof(struct i387_fxsave_struct));
2446 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2447 XSTATE_FPSSE;
2448 }
2449}
2450
2451static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2452 struct kvm_xsave *guest_xsave)
2453{
2454 u64 xstate_bv =
2455 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2456
2457 if (cpu_has_xsave)
2458 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2459 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2460 else {
2461 if (xstate_bv & ~XSTATE_FPSSE)
2462 return -EINVAL;
2463 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2464 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2465 }
2466 return 0;
2467}
2468
2469static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2470 struct kvm_xcrs *guest_xcrs)
2471{
2472 if (!cpu_has_xsave) {
2473 guest_xcrs->nr_xcrs = 0;
2474 return;
2475 }
2476
2477 guest_xcrs->nr_xcrs = 1;
2478 guest_xcrs->flags = 0;
2479 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2480 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2481}
2482
2483static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2484 struct kvm_xcrs *guest_xcrs)
2485{
2486 int i, r = 0;
2487
2488 if (!cpu_has_xsave)
2489 return -EINVAL;
2490
2491 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2492 return -EINVAL;
2493
2494 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2495 /* Only support XCR0 currently */
2496 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2497 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2498 guest_xcrs->xcrs[0].value);
2499 break;
2500 }
2501 if (r)
2502 r = -EINVAL;
2503 return r;
2504}
2505
313a3dc7
CO		 2506long kvm_arch_vcpu_ioctl(struct file *filp,
2507 unsigned int ioctl, unsigned long arg)
2508{
2509 struct kvm_vcpu *vcpu = filp->private_data;
2510 void __user *argp = (void __user *)arg;
2511 int r;
d1ac91d8
AK		 2512 union {
2513 struct kvm_lapic_state *lapic;
2514 struct kvm_xsave *xsave;
2515 struct kvm_xcrs *xcrs;
2516 void *buffer;
2517 } u;
2518
2519 u.buffer = NULL;
313a3dc7
CO		 2520 switch (ioctl) {
2521 case KVM_GET_LAPIC: {
2204ae3c
MT		 2522 r = -EINVAL;
2523 if (!vcpu->arch.apic)
2524 goto out;
d1ac91d8 2525 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2526
b772ff36 2527 r = -ENOMEM;
d1ac91d8 2528 if (!u.lapic)
b772ff36 2529 goto out;
d1ac91d8 2530 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2531 if (r)
2532 goto out;
2533 r = -EFAULT;
d1ac91d8 2534 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2535 goto out;
2536 r = 0;
2537 break;
2538 }
2539 case KVM_SET_LAPIC: {
2204ae3c
MT		 2540 r = -EINVAL;
2541 if (!vcpu->arch.apic)
2542 goto out;
ff5c2c03
SL		 2543 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2544 if (IS_ERR(u.lapic)) {
2545 r = PTR_ERR(u.lapic);
313a3dc7 2546 goto out;
ff5c2c03
SL		 2547 }
2548
d1ac91d8 2549 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2550 if (r)
2551 goto out;
2552 r = 0;
2553 break;
2554 }
f77bc6a4
ZX		 2555 case KVM_INTERRUPT: {
2556 struct kvm_interrupt irq;
2557
2558 r = -EFAULT;
2559 if (copy_from_user(&irq, argp, sizeof irq))
2560 goto out;
2561 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2562 if (r)
2563 goto out;
2564 r = 0;
2565 break;
2566 }
c4abb7c9
JK		 2567 case KVM_NMI: {
2568 r = kvm_vcpu_ioctl_nmi(vcpu);
2569 if (r)
2570 goto out;
2571 r = 0;
2572 break;
2573 }
313a3dc7
CO		 2574 case KVM_SET_CPUID: {
2575 struct kvm_cpuid __user *cpuid_arg = argp;
2576 struct kvm_cpuid cpuid;
2577
2578 r = -EFAULT;
2579 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2580 goto out;
2581 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2582 if (r)
2583 goto out;
2584 break;
2585 }
07716717
DK		 2586 case KVM_SET_CPUID2: {
2587 struct kvm_cpuid2 __user *cpuid_arg = argp;
2588 struct kvm_cpuid2 cpuid;
2589
2590 r = -EFAULT;
2591 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2592 goto out;
2593 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2594 cpuid_arg->entries);
07716717
DK		 2595 if (r)
2596 goto out;
2597 break;
2598 }
2599 case KVM_GET_CPUID2: {
2600 struct kvm_cpuid2 __user *cpuid_arg = argp;
2601 struct kvm_cpuid2 cpuid;
2602
2603 r = -EFAULT;
2604 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2605 goto out;
2606 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2607 cpuid_arg->entries);
07716717
DK		 2608 if (r)
2609 goto out;
2610 r = -EFAULT;
2611 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2612 goto out;
2613 r = 0;
2614 break;
2615 }
313a3dc7
CO		 2616 case KVM_GET_MSRS:
2617 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2618 break;
2619 case KVM_SET_MSRS:
2620 r = msr_io(vcpu, argp, do_set_msr, 0);
2621 break;
b209749f
AK		 2622 case KVM_TPR_ACCESS_REPORTING: {
2623 struct kvm_tpr_access_ctl tac;
2624
2625 r = -EFAULT;
2626 if (copy_from_user(&tac, argp, sizeof tac))
2627 goto out;
2628 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2629 if (r)
2630 goto out;
2631 r = -EFAULT;
2632 if (copy_to_user(argp, &tac, sizeof tac))
2633 goto out;
2634 r = 0;
2635 break;
2636 };
b93463aa
AK		 2637 case KVM_SET_VAPIC_ADDR: {
2638 struct kvm_vapic_addr va;
2639
2640 r = -EINVAL;
2641 if (!irqchip_in_kernel(vcpu->kvm))
2642 goto out;
2643 r = -EFAULT;
2644 if (copy_from_user(&va, argp, sizeof va))
2645 goto out;
2646 r = 0;
2647 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2648 break;
2649 }
890ca9ae
HY		 2650 case KVM_X86_SETUP_MCE: {
2651 u64 mcg_cap;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2655 goto out;
2656 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2657 break;
2658 }
2659 case KVM_X86_SET_MCE: {
2660 struct kvm_x86_mce mce;
2661
2662 r = -EFAULT;
2663 if (copy_from_user(&mce, argp, sizeof mce))
2664 goto out;
2665 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2666 break;
2667 }
3cfc3092
JK		 2668 case KVM_GET_VCPU_EVENTS: {
2669 struct kvm_vcpu_events events;
2670
2671 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2672
2673 r = -EFAULT;
2674 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2675 break;
2676 r = 0;
2677 break;
2678 }
2679 case KVM_SET_VCPU_EVENTS: {
2680 struct kvm_vcpu_events events;
2681
2682 r = -EFAULT;
2683 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2684 break;
2685
2686 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2687 break;
2688 }
a1efbe77
JK		 2689 case KVM_GET_DEBUGREGS: {
2690 struct kvm_debugregs dbgregs;
2691
2692 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2693
2694 r = -EFAULT;
2695 if (copy_to_user(argp, &dbgregs,
2696 sizeof(struct kvm_debugregs)))
2697 break;
2698 r = 0;
2699 break;
2700 }
2701 case KVM_SET_DEBUGREGS: {
2702 struct kvm_debugregs dbgregs;
2703
2704 r = -EFAULT;
2705 if (copy_from_user(&dbgregs, argp,
2706 sizeof(struct kvm_debugregs)))
2707 break;
2708
2709 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2710 break;
2711 }
2d5b5a66 2712 case KVM_GET_XSAVE: {
d1ac91d8 2713 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2714 r = -ENOMEM;
d1ac91d8 2715 if (!u.xsave)
2d5b5a66
SY		 2716 break;
2717
d1ac91d8 2718 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2719
2720 r = -EFAULT;
d1ac91d8 2721 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2722 break;
2723 r = 0;
2724 break;
2725 }
2726 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2727 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2728 if (IS_ERR(u.xsave)) {
2729 r = PTR_ERR(u.xsave);
2730 goto out;
2731 }
2d5b5a66 2732
d1ac91d8 2733 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2734 break;
2735 }
2736 case KVM_GET_XCRS: {
d1ac91d8 2737 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2738 r = -ENOMEM;
d1ac91d8 2739 if (!u.xcrs)
2d5b5a66
SY		 2740 break;
2741
d1ac91d8 2742 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2743
2744 r = -EFAULT;
d1ac91d8 2745 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2746 sizeof(struct kvm_xcrs)))
2747 break;
2748 r = 0;
2749 break;
2750 }
2751 case KVM_SET_XCRS: {
ff5c2c03
SL		 2752 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2753 if (IS_ERR(u.xcrs)) {
2754 r = PTR_ERR(u.xcrs);
2755 goto out;
2756 }
2d5b5a66 2757
d1ac91d8 2758 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2759 break;
2760 }
92a1f12d
JR		 2761 case KVM_SET_TSC_KHZ: {
2762 u32 user_tsc_khz;
2763
2764 r = -EINVAL;
2765 if (!kvm_has_tsc_control)
2766 break;
2767
2768 user_tsc_khz = (u32)arg;
2769
2770 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2771 goto out;
2772
2773 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
2774
2775 r = 0;
2776 goto out;
2777 }
2778 case KVM_GET_TSC_KHZ: {
2779 r = -EIO;
2780 if (check_tsc_unstable())
2781 goto out;
2782
2783 r = vcpu_tsc_khz(vcpu);
2784
2785 goto out;
2786 }
313a3dc7
CO		 2787 default:
2788 r = -EINVAL;
2789 }
2790out:
d1ac91d8 2791 kfree(u.buffer);
313a3dc7
CO		 2792 return r;
2793}
2794
1fe779f8
CO		 2795static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2796{
2797 int ret;
2798
2799 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2800 return -1;
2801 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2802 return ret;
2803}
2804
b927a3ce
SY		 2805static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2806 u64 ident_addr)
2807{
2808 kvm->arch.ept_identity_map_addr = ident_addr;
2809 return 0;
2810}
2811
1fe779f8
CO		 2812static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2813 u32 kvm_nr_mmu_pages)
2814{
2815 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2816 return -EINVAL;
2817
79fac95e 2818 mutex_lock(&kvm->slots_lock);
7c8a83b7 2819 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2820
2821 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2822 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2823
7c8a83b7 2824 spin_unlock(&kvm->mmu_lock);
79fac95e 2825 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2826 return 0;
2827}
2828
2829static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2830{
39de71ec 2831 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2832}
2833
1fe779f8
CO		 2834static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2835{
2836 int r;
2837
2838 r = 0;
2839 switch (chip->chip_id) {
2840 case KVM_IRQCHIP_PIC_MASTER:
2841 memcpy(&chip->chip.pic,
2842 &pic_irqchip(kvm)->pics[0],
2843 sizeof(struct kvm_pic_state));
2844 break;
2845 case KVM_IRQCHIP_PIC_SLAVE:
2846 memcpy(&chip->chip.pic,
2847 &pic_irqchip(kvm)->pics[1],
2848 sizeof(struct kvm_pic_state));
2849 break;
2850 case KVM_IRQCHIP_IOAPIC:
eba0226b 2851 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2852 break;
2853 default:
2854 r = -EINVAL;
2855 break;
2856 }
2857 return r;
2858}
2859
2860static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2861{
2862 int r;
2863
2864 r = 0;
2865 switch (chip->chip_id) {
2866 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2867 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2868 memcpy(&pic_irqchip(kvm)->pics[0],
2869 &chip->chip.pic,
2870 sizeof(struct kvm_pic_state));
f4f51050 2871 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2872 break;
2873 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2874 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2875 memcpy(&pic_irqchip(kvm)->pics[1],
2876 &chip->chip.pic,
2877 sizeof(struct kvm_pic_state));
f4f51050 2878 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2879 break;
2880 case KVM_IRQCHIP_IOAPIC:
eba0226b 2881 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2882 break;
2883 default:
2884 r = -EINVAL;
2885 break;
2886 }
2887 kvm_pic_update_irq(pic_irqchip(kvm));
2888 return r;
2889}
2890
e0f63cb9
SY		 2891static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2892{
2893 int r = 0;
2894
894a9c55 2895 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2896 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2897 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2898 return r;
2899}
2900
2901static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2902{
2903 int r = 0;
2904
894a9c55 2905 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2906 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2907 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2908 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2909 return r;
2910}
2911
2912static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2913{
2914 int r = 0;
2915
2916 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2917 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2918 sizeof(ps->channels));
2919 ps->flags = kvm->arch.vpit->pit_state.flags;
2920 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 2921 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 2922 return r;
2923}
2924
2925static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2926{
2927 int r = 0, start = 0;
2928 u32 prev_legacy, cur_legacy;
2929 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2930 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2931 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2932 if (!prev_legacy && cur_legacy)
2933 start = 1;
2934 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2935 sizeof(kvm->arch.vpit->pit_state.channels));
2936 kvm->arch.vpit->pit_state.flags = ps->flags;
2937 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2938 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2939 return r;
2940}
2941
52d939a0
MT		 2942static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2943 struct kvm_reinject_control *control)
2944{
2945 if (!kvm->arch.vpit)
2946 return -ENXIO;
894a9c55 2947 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2948 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2949 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2950 return 0;
2951}
2952
95d4c16c
TY		 2953/**
2954 * write_protect_slot - write protect a slot for dirty logging
2955 * @kvm: the kvm instance
2956 * @memslot: the slot we protect
2957 * @dirty_bitmap: the bitmap indicating which pages are dirty
2958 * @nr_dirty_pages: the number of dirty pages
2959 *
2960 * We have two ways to find all sptes to protect:
2961 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
2962 * checks ones that have a spte mapping a page in the slot.
2963 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
2964 *
2965 * Generally speaking, if there are not so many dirty pages compared to the
2966 * number of shadow pages, we should use the latter.
2967 *
2968 * Note that letting others write into a page marked dirty in the old bitmap
2969 * by using the remaining tlb entry is not a problem. That page will become
2970 * write protected again when we flush the tlb and then be reported dirty to
2971 * the user space by copying the old bitmap.
2972 */
2973static void write_protect_slot(struct kvm *kvm,
2974 struct kvm_memory_slot *memslot,
2975 unsigned long *dirty_bitmap,
2976 unsigned long nr_dirty_pages)
2977{
2978 /* Not many dirty pages compared to # of shadow pages. */
2979 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
2980 unsigned long gfn_offset;
2981
2982 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
2983 unsigned long gfn = memslot->base_gfn + gfn_offset;
2984
2985 spin_lock(&kvm->mmu_lock);
2986 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
2987 spin_unlock(&kvm->mmu_lock);
2988 }
2989 kvm_flush_remote_tlbs(kvm);
2990 } else {
2991 spin_lock(&kvm->mmu_lock);
2992 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
2993 spin_unlock(&kvm->mmu_lock);
2994 }
2995}
2996
5bb064dc
ZX		 2997/*
2998 * Get (and clear) the dirty memory log for a memory slot.
2999 */
3000int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3001 struct kvm_dirty_log *log)
3002{
7850ac54 3003 int r;
5bb064dc 3004 struct kvm_memory_slot *memslot;
95d4c16c 3005 unsigned long n, nr_dirty_pages;
5bb064dc 3006
79fac95e 3007 mutex_lock(&kvm->slots_lock);
5bb064dc 3008
b050b015
MT		 3009 r = -EINVAL;
3010 if (log->slot >= KVM_MEMORY_SLOTS)
3011 goto out;
3012
28a37544 3013 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3014 r = -ENOENT;
3015 if (!memslot->dirty_bitmap)
3016 goto out;
3017
87bf6e7d 3018 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3019 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3020
5bb064dc 3021 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3022 if (nr_dirty_pages) {
b050b015 3023 struct kvm_memslots *slots, *old_slots;
28a37544 3024 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3025
28a37544
XG		 3026 dirty_bitmap = memslot->dirty_bitmap;
3027 dirty_bitmap_head = memslot->dirty_bitmap_head;
3028 if (dirty_bitmap == dirty_bitmap_head)
3029 dirty_bitmap_head += n / sizeof(long);
3030 memset(dirty_bitmap_head, 0, n);
b050b015 3031
914ebccd 3032 r = -ENOMEM;
cdfca7b3 3033 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3034 if (!slots)
914ebccd 3035 goto out;
cdfca7b3 3036
28a37544 3037 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3038 memslot->nr_dirty_pages = 0;
28a37544 3039 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3040 update_memslots(slots, NULL);
b050b015
MT		 3041
3042 old_slots = kvm->memslots;
3043 rcu_assign_pointer(kvm->memslots, slots);
3044 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3045 kfree(old_slots);
914ebccd 3046
95d4c16c 3047 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3048
914ebccd 3049 r = -EFAULT;
515a0127 3050 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3051 goto out;
914ebccd
TY		 3052 } else {
3053 r = -EFAULT;
3054 if (clear_user(log->dirty_bitmap, n))
3055 goto out;
5bb064dc 3056 }
b050b015 3057
5bb064dc
ZX		 3058 r = 0;
3059out:
79fac95e 3060 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3061 return r;
3062}
3063
1fe779f8
CO		 3064long kvm_arch_vm_ioctl(struct file *filp,
3065 unsigned int ioctl, unsigned long arg)
3066{
3067 struct kvm *kvm = filp->private_data;
3068 void __user *argp = (void __user *)arg;
367e1319 3069 int r = -ENOTTY;
f0d66275
DH		 3070 /*
3071 * This union makes it completely explicit to gcc-3.x
3072 * that these two variables' stack usage should be
3073 * combined, not added together.
3074 */
3075 union {
3076 struct kvm_pit_state ps;
e9f42757 3077 struct kvm_pit_state2 ps2;
c5ff41ce 3078 struct kvm_pit_config pit_config;
f0d66275 3079 } u;
1fe779f8
CO		 3080
3081 switch (ioctl) {
3082 case KVM_SET_TSS_ADDR:
3083 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3084 if (r < 0)
3085 goto out;
3086 break;
b927a3ce
SY		 3087 case KVM_SET_IDENTITY_MAP_ADDR: {
3088 u64 ident_addr;
3089
3090 r = -EFAULT;
3091 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3092 goto out;
3093 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3094 if (r < 0)
3095 goto out;
3096 break;
3097 }
1fe779f8
CO		 3098 case KVM_SET_NR_MMU_PAGES:
3099 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3100 if (r)
3101 goto out;
3102 break;
3103 case KVM_GET_NR_MMU_PAGES:
3104 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3105 break;
3ddea128
MT		 3106 case KVM_CREATE_IRQCHIP: {
3107 struct kvm_pic *vpic;
3108
3109 mutex_lock(&kvm->lock);
3110 r = -EEXIST;
3111 if (kvm->arch.vpic)
3112 goto create_irqchip_unlock;
1fe779f8 3113 r = -ENOMEM;
3ddea128
MT		 3114 vpic = kvm_create_pic(kvm);
3115 if (vpic) {
1fe779f8
CO		 3116 r = kvm_ioapic_init(kvm);
3117 if (r) {
175504cd 3118 mutex_lock(&kvm->slots_lock);
72bb2fcd 3119 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3120 &vpic->dev_master);
3121 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3122 &vpic->dev_slave);
3123 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3124 &vpic->dev_eclr);
175504cd 3125 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3126 kfree(vpic);
3127 goto create_irqchip_unlock;
1fe779f8
CO		 3128 }
3129 } else
3ddea128
MT		 3130 goto create_irqchip_unlock;
3131 smp_wmb();
3132 kvm->arch.vpic = vpic;
3133 smp_wmb();
399ec807
AK		 3134 r = kvm_setup_default_irq_routing(kvm);
3135 if (r) {
175504cd 3136 mutex_lock(&kvm->slots_lock);
3ddea128 3137 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3138 kvm_ioapic_destroy(kvm);
3139 kvm_destroy_pic(kvm);
3ddea128 3140 mutex_unlock(&kvm->irq_lock);
175504cd 3141 mutex_unlock(&kvm->slots_lock);
399ec807 3142 }
3ddea128
MT		 3143 create_irqchip_unlock:
3144 mutex_unlock(&kvm->lock);
1fe779f8 3145 break;
3ddea128 3146 }
7837699f 3147 case KVM_CREATE_PIT:
c5ff41ce
JK		 3148 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3149 goto create_pit;
3150 case KVM_CREATE_PIT2:
3151 r = -EFAULT;
3152 if (copy_from_user(&u.pit_config, argp,
3153 sizeof(struct kvm_pit_config)))
3154 goto out;
3155 create_pit:
79fac95e 3156 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3157 r = -EEXIST;
3158 if (kvm->arch.vpit)
3159 goto create_pit_unlock;
7837699f 3160 r = -ENOMEM;
c5ff41ce 3161 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3162 if (kvm->arch.vpit)
3163 r = 0;
269e05e4 3164 create_pit_unlock:
79fac95e 3165 mutex_unlock(&kvm->slots_lock);
7837699f 3166 break;
4925663a 3167 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3168 case KVM_IRQ_LINE: {
3169 struct kvm_irq_level irq_event;
3170
3171 r = -EFAULT;
3172 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3173 goto out;
160d2f6c 3174 r = -ENXIO;
1fe779f8 3175 if (irqchip_in_kernel(kvm)) {
4925663a 3176 __s32 status;
4925663a
GN		 3177 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3178 irq_event.irq, irq_event.level);
4925663a 3179 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3180 r = -EFAULT;
4925663a
GN		 3181 irq_event.status = status;
3182 if (copy_to_user(argp, &irq_event,
3183 sizeof irq_event))
3184 goto out;
3185 }
1fe779f8
CO		 3186 r = 0;
3187 }
3188 break;
3189 }
3190 case KVM_GET_IRQCHIP: {
3191 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3192 struct kvm_irqchip *chip;
1fe779f8 3193
ff5c2c03
SL		 3194 chip = memdup_user(argp, sizeof(*chip));
3195 if (IS_ERR(chip)) {
3196 r = PTR_ERR(chip);
1fe779f8 3197 goto out;
ff5c2c03
SL		 3198 }
3199
1fe779f8
CO		 3200 r = -ENXIO;
3201 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3202 goto get_irqchip_out;
3203 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3204 if (r)
f0d66275 3205 goto get_irqchip_out;
1fe779f8 3206 r = -EFAULT;
f0d66275
DH		 3207 if (copy_to_user(argp, chip, sizeof *chip))
3208 goto get_irqchip_out;
1fe779f8 3209 r = 0;
f0d66275
DH		 3210 get_irqchip_out:
3211 kfree(chip);
3212 if (r)
3213 goto out;
1fe779f8
CO		 3214 break;
3215 }
3216 case KVM_SET_IRQCHIP: {
3217 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3218 struct kvm_irqchip *chip;
1fe779f8 3219
ff5c2c03
SL		 3220 chip = memdup_user(argp, sizeof(*chip));
3221 if (IS_ERR(chip)) {
3222 r = PTR_ERR(chip);
1fe779f8 3223 goto out;
ff5c2c03
SL		 3224 }
3225
1fe779f8
CO		 3226 r = -ENXIO;
3227 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3228 goto set_irqchip_out;
3229 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3230 if (r)
f0d66275 3231 goto set_irqchip_out;
1fe779f8 3232 r = 0;
f0d66275
DH		 3233 set_irqchip_out:
3234 kfree(chip);
3235 if (r)
3236 goto out;
1fe779f8
CO		 3237 break;
3238 }
e0f63cb9 3239 case KVM_GET_PIT: {
e0f63cb9 3240 r = -EFAULT;
f0d66275 3241 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3242 goto out;
3243 r = -ENXIO;
3244 if (!kvm->arch.vpit)
3245 goto out;
f0d66275 3246 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3247 if (r)
3248 goto out;
3249 r = -EFAULT;
f0d66275 3250 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3251 goto out;
3252 r = 0;
3253 break;
3254 }
3255 case KVM_SET_PIT: {
e0f63cb9 3256 r = -EFAULT;
f0d66275 3257 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3258 goto out;
3259 r = -ENXIO;
3260 if (!kvm->arch.vpit)
3261 goto out;
f0d66275 3262 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3263 if (r)
3264 goto out;
3265 r = 0;
3266 break;
3267 }
e9f42757
BK		 3268 case KVM_GET_PIT2: {
3269 r = -ENXIO;
3270 if (!kvm->arch.vpit)
3271 goto out;
3272 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3273 if (r)
3274 goto out;
3275 r = -EFAULT;
3276 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3277 goto out;
3278 r = 0;
3279 break;
3280 }
3281 case KVM_SET_PIT2: {
3282 r = -EFAULT;
3283 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3284 goto out;
3285 r = -ENXIO;
3286 if (!kvm->arch.vpit)
3287 goto out;
3288 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3289 if (r)
3290 goto out;
3291 r = 0;
3292 break;
3293 }
52d939a0
MT		 3294 case KVM_REINJECT_CONTROL: {
3295 struct kvm_reinject_control control;
3296 r = -EFAULT;
3297 if (copy_from_user(&control, argp, sizeof(control)))
3298 goto out;
3299 r = kvm_vm_ioctl_reinject(kvm, &control);
3300 if (r)
3301 goto out;
3302 r = 0;
3303 break;
3304 }
ffde22ac
ES		 3305 case KVM_XEN_HVM_CONFIG: {
3306 r = -EFAULT;
3307 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3308 sizeof(struct kvm_xen_hvm_config)))
3309 goto out;
3310 r = -EINVAL;
3311 if (kvm->arch.xen_hvm_config.flags)
3312 goto out;
3313 r = 0;
3314 break;
3315 }
afbcf7ab 3316 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3317 struct kvm_clock_data user_ns;
3318 u64 now_ns;
3319 s64 delta;
3320
3321 r = -EFAULT;
3322 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3323 goto out;
3324
3325 r = -EINVAL;
3326 if (user_ns.flags)
3327 goto out;
3328
3329 r = 0;
395c6b0a 3330 local_irq_disable();
759379dd 3331 now_ns = get_kernel_ns();
afbcf7ab 3332 delta = user_ns.clock - now_ns;
395c6b0a 3333 local_irq_enable();
afbcf7ab
GC		 3334 kvm->arch.kvmclock_offset = delta;
3335 break;
3336 }
3337 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3338 struct kvm_clock_data user_ns;
3339 u64 now_ns;
3340
395c6b0a 3341 local_irq_disable();
759379dd 3342 now_ns = get_kernel_ns();
afbcf7ab 3343 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3344 local_irq_enable();
afbcf7ab 3345 user_ns.flags = 0;
97e69aa6 3346 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3347
3348 r = -EFAULT;
3349 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3350 goto out;
3351 r = 0;
3352 break;
3353 }
3354
1fe779f8
CO		 3355 default:
3356 ;
3357 }
3358out:
3359 return r;
3360}
3361
a16b043c 3362static void kvm_init_msr_list(void)
043405e1
CO		 3363{
3364 u32 dummy[2];
3365 unsigned i, j;
3366
e3267cbb
GC		 3367 /* skip the first msrs in the list. KVM-specific */
3368 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3369 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3370 continue;
3371 if (j < i)
3372 msrs_to_save[j] = msrs_to_save[i];
3373 j++;
3374 }
3375 num_msrs_to_save = j;
3376}
3377
bda9020e
MT		 3378static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3379 const void *v)
bbd9b64e 3380{
70252a10
AK		 3381 int handled = 0;
3382 int n;
3383
3384 do {
3385 n = min(len, 8);
3386 if (!(vcpu->arch.apic &&
3387 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3388 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3389 break;
3390 handled += n;
3391 addr += n;
3392 len -= n;
3393 v += n;
3394 } while (len);
bbd9b64e 3395
70252a10 3396 return handled;
bbd9b64e
CO		 3397}
3398
bda9020e 3399static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3400{
70252a10
AK		 3401 int handled = 0;
3402 int n;
3403
3404 do {
3405 n = min(len, 8);
3406 if (!(vcpu->arch.apic &&
3407 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3408 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3409 break;
3410 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3411 handled += n;
3412 addr += n;
3413 len -= n;
3414 v += n;
3415 } while (len);
bbd9b64e 3416
70252a10 3417 return handled;
bbd9b64e
CO		 3418}
3419
2dafc6c2
GN		 3420static void kvm_set_segment(struct kvm_vcpu *vcpu,
3421 struct kvm_segment *var, int seg)
3422{
3423 kvm_x86_ops->set_segment(vcpu, var, seg);
3424}
3425
3426void kvm_get_segment(struct kvm_vcpu *vcpu,
3427 struct kvm_segment *var, int seg)
3428{
3429 kvm_x86_ops->get_segment(vcpu, var, seg);
3430}
3431
e459e322 3432gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3433{
3434 gpa_t t_gpa;
ab9ae313 3435 struct x86_exception exception;
02f59dc9
JR		 3436
3437 BUG_ON(!mmu_is_nested(vcpu));
3438
3439 /* NPT walks are always user-walks */
3440 access |= PFERR_USER_MASK;
ab9ae313 3441 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3442
3443 return t_gpa;
3444}
3445
ab9ae313
AK		 3446gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3447 struct x86_exception *exception)
1871c602
GN		 3448{
3449 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3450 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3451}
3452
ab9ae313
AK		 3453 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3454 struct x86_exception *exception)
1871c602
GN		 3455{
3456 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3457 access |= PFERR_FETCH_MASK;
ab9ae313 3458 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3459}
3460
ab9ae313
AK		 3461gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3462 struct x86_exception *exception)
1871c602
GN		 3463{
3464 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3465 access |= PFERR_WRITE_MASK;
ab9ae313 3466 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3467}
3468
3469/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3470gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3471 struct x86_exception *exception)
1871c602 3472{
ab9ae313 3473 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3474}
3475
3476static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3477 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3478 struct x86_exception *exception)
bbd9b64e
CO		 3479{
3480 void *data = val;
10589a46 3481 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3482
3483 while (bytes) {
14dfe855 3484 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3485 exception);
bbd9b64e 3486 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3487 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3488 int ret;
3489
bcc55cba 3490 if (gpa == UNMAPPED_GVA)
ab9ae313 3491 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3492 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3493 if (ret < 0) {
c3cd7ffa 3494 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3495 goto out;
3496 }
bbd9b64e 3497
77c2002e
IE		 3498 bytes -= toread;
3499 data += toread;
3500 addr += toread;
bbd9b64e 3501 }
10589a46 3502out:
10589a46 3503 return r;
bbd9b64e 3504}
77c2002e 3505
1871c602 3506/* used for instruction fetching */
0f65dd70
AK		 3507static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3508 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3509 struct x86_exception *exception)
1871c602 3510{
0f65dd70 3511 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3512 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3513
1871c602 3514 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3515 access | PFERR_FETCH_MASK,
3516 exception);
1871c602
GN		 3517}
3518
064aea77 3519int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3520 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3521 struct x86_exception *exception)
1871c602 3522{
0f65dd70 3523 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3524 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3525
1871c602 3526 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3527 exception);
1871c602 3528}
064aea77 3529EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3530
0f65dd70
AK		 3531static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3532 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3533 struct x86_exception *exception)
1871c602 3534{
0f65dd70 3535 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3536 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3537}
3538
6a4d7550 3539int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3540 gva_t addr, void *val,
2dafc6c2 3541 unsigned int bytes,
bcc55cba 3542 struct x86_exception *exception)
77c2002e 3543{
0f65dd70 3544 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3545 void *data = val;
3546 int r = X86EMUL_CONTINUE;
3547
3548 while (bytes) {
14dfe855
JR		 3549 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3550 PFERR_WRITE_MASK,
ab9ae313 3551 exception);
77c2002e
IE		 3552 unsigned offset = addr & (PAGE_SIZE-1);
3553 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3554 int ret;
3555
bcc55cba 3556 if (gpa == UNMAPPED_GVA)
ab9ae313 3557 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3558 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3559 if (ret < 0) {
c3cd7ffa 3560 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3561 goto out;
3562 }
3563
3564 bytes -= towrite;
3565 data += towrite;
3566 addr += towrite;
3567 }
3568out:
3569 return r;
3570}
6a4d7550 3571EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3572
af7cc7d1
XG		 3573static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3574 gpa_t *gpa, struct x86_exception *exception,
3575 bool write)
3576{
3577 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3578
bebb106a
XG		 3579 if (vcpu_match_mmio_gva(vcpu, gva) &&
3580 check_write_user_access(vcpu, write, access,
3581 vcpu->arch.access)) {
3582 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3583 (gva & (PAGE_SIZE - 1));
4f022648 3584 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3585 return 1;
3586 }
3587
af7cc7d1
XG		 3588 if (write)
3589 access |= PFERR_WRITE_MASK;
3590
3591 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3592
3593 if (*gpa == UNMAPPED_GVA)
3594 return -1;
3595
3596 /* For APIC access vmexit */
3597 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3598 return 1;
3599
4f022648
XG		 3600 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3601 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3602 return 1;
4f022648 3603 }
bebb106a 3604
af7cc7d1
XG		 3605 return 0;
3606}
3607
3200f405 3608int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3609 const void *val, int bytes)
bbd9b64e
CO		 3610{
3611 int ret;
3612
3613 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3614 if (ret < 0)
bbd9b64e 3615 return 0;
f57f2ef5 3616 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3617 return 1;
3618}
3619
77d197b2
XG		 3620struct read_write_emulator_ops {
3621 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3622 int bytes);
3623 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3624 void *val, int bytes);
3625 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3626 int bytes, void *val);
3627 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3628 void *val, int bytes);
3629 bool write;
3630};
3631
3632static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3633{
3634 if (vcpu->mmio_read_completed) {
3635 memcpy(val, vcpu->mmio_data, bytes);
3636 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3637 vcpu->mmio_phys_addr, *(u64 *)val);
3638 vcpu->mmio_read_completed = 0;
3639 return 1;
3640 }
3641
3642 return 0;
3643}
3644
3645static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3646 void *val, int bytes)
3647{
3648 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3649}
3650
3651static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3652 void *val, int bytes)
3653{
3654 return emulator_write_phys(vcpu, gpa, val, bytes);
3655}
3656
3657static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3658{
3659 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3660 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3661}
3662
3663static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3664 void *val, int bytes)
3665{
3666 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3667 return X86EMUL_IO_NEEDED;
3668}
3669
3670static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3671 void *val, int bytes)
3672{
3673 memcpy(vcpu->mmio_data, val, bytes);
3674 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3675 return X86EMUL_CONTINUE;
3676}
3677
3678static struct read_write_emulator_ops read_emultor = {
3679 .read_write_prepare = read_prepare,
3680 .read_write_emulate = read_emulate,
3681 .read_write_mmio = vcpu_mmio_read,
3682 .read_write_exit_mmio = read_exit_mmio,
3683};
3684
3685static struct read_write_emulator_ops write_emultor = {
3686 .read_write_emulate = write_emulate,
3687 .read_write_mmio = write_mmio,
3688 .read_write_exit_mmio = write_exit_mmio,
3689 .write = true,
3690};
3691
22388a3c
XG		 3692static int emulator_read_write_onepage(unsigned long addr, void *val,
3693 unsigned int bytes,
3694 struct x86_exception *exception,
3695 struct kvm_vcpu *vcpu,
3696 struct read_write_emulator_ops *ops)
bbd9b64e 3697{
af7cc7d1
XG		 3698 gpa_t gpa;
3699 int handled, ret;
22388a3c
XG		 3700 bool write = ops->write;
3701
3702 if (ops->read_write_prepare &&
3703 ops->read_write_prepare(vcpu, val, bytes))
3704 return X86EMUL_CONTINUE;
10589a46 3705
22388a3c 3706 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3707
af7cc7d1 3708 if (ret < 0)
bbd9b64e 3709 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3710
3711 /* For APIC access vmexit */
af7cc7d1 3712 if (ret)
bbd9b64e
CO		 3713 goto mmio;
3714
22388a3c 3715 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3716 return X86EMUL_CONTINUE;
3717
3718mmio:
3719 /*
3720 * Is this MMIO handled locally?
3721 */
22388a3c 3722 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3723 if (handled == bytes)
bbd9b64e 3724 return X86EMUL_CONTINUE;
bbd9b64e 3725
70252a10
AK		 3726 gpa += handled;
3727 bytes -= handled;
3728 val += handled;
3729
bbd9b64e 3730 vcpu->mmio_needed = 1;
411c35b7
GN		 3731 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3732 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3733 vcpu->mmio_size = bytes;
3734 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3735 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3736 vcpu->mmio_index = 0;
bbd9b64e 3737
22388a3c 3738 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3739}
3740
22388a3c
XG		 3741int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3742 void *val, unsigned int bytes,
3743 struct x86_exception *exception,
3744 struct read_write_emulator_ops *ops)
bbd9b64e 3745{
0f65dd70
AK		 3746 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3747
bbd9b64e
CO		 3748 /* Crossing a page boundary? */
3749 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3750 int rc, now;
3751
3752 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3753 rc = emulator_read_write_onepage(addr, val, now, exception,
3754 vcpu, ops);
3755
bbd9b64e
CO		 3756 if (rc != X86EMUL_CONTINUE)
3757 return rc;
3758 addr += now;
3759 val += now;
3760 bytes -= now;
3761 }
22388a3c
XG		 3762
3763 return emulator_read_write_onepage(addr, val, bytes, exception,
3764 vcpu, ops);
3765}
3766
3767static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3768 unsigned long addr,
3769 void *val,
3770 unsigned int bytes,
3771 struct x86_exception *exception)
3772{
3773 return emulator_read_write(ctxt, addr, val, bytes,
3774 exception, &read_emultor);
3775}
3776
3777int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3778 unsigned long addr,
3779 const void *val,
3780 unsigned int bytes,
3781 struct x86_exception *exception)
3782{
3783 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3784 exception, &write_emultor);
bbd9b64e 3785}
bbd9b64e 3786
daea3e73
AK		 3787#define CMPXCHG_TYPE(t, ptr, old, new) \
3788 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3789
3790#ifdef CONFIG_X86_64
3791# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3792#else
3793# define CMPXCHG64(ptr, old, new) \
9749a6c0 3794 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3795#endif
3796
0f65dd70
AK		 3797static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3798 unsigned long addr,
bbd9b64e
CO		 3799 const void *old,
3800 const void *new,
3801 unsigned int bytes,
0f65dd70 3802 struct x86_exception *exception)
bbd9b64e 3803{
0f65dd70 3804 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3805 gpa_t gpa;
3806 struct page *page;
3807 char *kaddr;
3808 bool exchanged;
2bacc55c 3809
daea3e73
AK		 3810 /* guests cmpxchg8b have to be emulated atomically */
3811 if (bytes > 8 || (bytes & (bytes - 1)))
3812 goto emul_write;
10589a46 3813
daea3e73 3814 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3815
daea3e73
AK		 3816 if (gpa == UNMAPPED_GVA ||
3817 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3818 goto emul_write;
2bacc55c 3819
daea3e73
AK		 3820 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3821 goto emul_write;
72dc67a6 3822
daea3e73 3823 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3824 if (is_error_page(page)) {
3825 kvm_release_page_clean(page);
3826 goto emul_write;
3827 }
72dc67a6 3828
daea3e73
AK		 3829 kaddr = kmap_atomic(page, KM_USER0);
3830 kaddr += offset_in_page(gpa);
3831 switch (bytes) {
3832 case 1:
3833 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3834 break;
3835 case 2:
3836 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3837 break;
3838 case 4:
3839 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3840 break;
3841 case 8:
3842 exchanged = CMPXCHG64(kaddr, old, new);
3843 break;
3844 default:
3845 BUG();
2bacc55c 3846 }
daea3e73
AK		 3847 kunmap_atomic(kaddr, KM_USER0);
3848 kvm_release_page_dirty(page);
3849
3850 if (!exchanged)
3851 return X86EMUL_CMPXCHG_FAILED;
3852
f57f2ef5 3853 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3854
3855 return X86EMUL_CONTINUE;
4a5f48f6 3856
3200f405 3857emul_write:
daea3e73 3858 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3859
0f65dd70 3860 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3861}
3862
cf8f70bf
GN		 3863static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3864{
3865 /* TODO: String I/O for in kernel device */
3866 int r;
3867
3868 if (vcpu->arch.pio.in)
3869 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3870 vcpu->arch.pio.size, pd);
3871 else
3872 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3873 vcpu->arch.pio.port, vcpu->arch.pio.size,
3874 pd);
3875 return r;
3876}
3877
6f6fbe98
XG		 3878static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3879 unsigned short port, void *val,
3880 unsigned int count, bool in)
cf8f70bf 3881{
6f6fbe98 3882 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3883
3884 vcpu->arch.pio.port = port;
6f6fbe98 3885 vcpu->arch.pio.in = in;
7972995b 3886 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3887 vcpu->arch.pio.size = size;
3888
3889 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3890 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3891 return 1;
3892 }
3893
3894 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3895 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3896 vcpu->run->io.size = size;
3897 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3898 vcpu->run->io.count = count;
3899 vcpu->run->io.port = port;
3900
3901 return 0;
3902}
3903
6f6fbe98
XG		 3904static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3905 int size, unsigned short port, void *val,
3906 unsigned int count)
cf8f70bf 3907{
ca1d4a9e 3908 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 3909 int ret;
ca1d4a9e 3910
6f6fbe98
XG		 3911 if (vcpu->arch.pio.count)
3912 goto data_avail;
cf8f70bf 3913
6f6fbe98
XG		 3914 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3915 if (ret) {
3916data_avail:
3917 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3918 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3919 return 1;
3920 }
3921
cf8f70bf
GN		 3922 return 0;
3923}
3924
6f6fbe98
XG		 3925static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3926 int size, unsigned short port,
3927 const void *val, unsigned int count)
3928{
3929 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3930
3931 memcpy(vcpu->arch.pio_data, val, size * count);
3932 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3933}
3934
bbd9b64e
CO		 3935static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3936{
3937 return kvm_x86_ops->get_segment_base(vcpu, seg);
3938}
3939
3cb16fe7 3940static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 3941{
3cb16fe7 3942 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 3943}
3944
f5f48ee1
SY		 3945int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3946{
3947 if (!need_emulate_wbinvd(vcpu))
3948 return X86EMUL_CONTINUE;
3949
3950 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 3951 int cpu = get_cpu();
3952
3953 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 3954 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3955 wbinvd_ipi, NULL, 1);
2eec7343 3956 put_cpu();
f5f48ee1 3957 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 3958 } else
3959 wbinvd();
f5f48ee1
SY		 3960 return X86EMUL_CONTINUE;
3961}
3962EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3963
bcaf5cc5
AK		 3964static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
3965{
3966 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
3967}
3968
717746e3 3969int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 3970{
717746e3 3971 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 3972}
3973
717746e3 3974int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 3975{
338dbc97 3976
717746e3 3977 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 3978}
3979
52a46617 3980static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3981{
52a46617 3982 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3983}
3984
717746e3 3985static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 3986{
717746e3 3987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 3988 unsigned long value;
3989
3990 switch (cr) {
3991 case 0:
3992 value = kvm_read_cr0(vcpu);
3993 break;
3994 case 2:
3995 value = vcpu->arch.cr2;
3996 break;
3997 case 3:
9f8fe504 3998 value = kvm_read_cr3(vcpu);
52a46617
GN		 3999 break;
4000 case 4:
4001 value = kvm_read_cr4(vcpu);
4002 break;
4003 case 8:
4004 value = kvm_get_cr8(vcpu);
4005 break;
4006 default:
4007 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4008 return 0;
4009 }
4010
4011 return value;
4012}
4013
717746e3 4014static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4015{
717746e3 4016 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4017 int res = 0;
4018
52a46617
GN		 4019 switch (cr) {
4020 case 0:
49a9b07e 4021 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4022 break;
4023 case 2:
4024 vcpu->arch.cr2 = val;
4025 break;
4026 case 3:
2390218b 4027 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4028 break;
4029 case 4:
a83b29c6 4030 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4031 break;
4032 case 8:
eea1cff9 4033 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4034 break;
4035 default:
4036 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4037 res = -1;
52a46617 4038 }
0f12244f
GN		 4039
4040 return res;
52a46617
GN		 4041}
4042
717746e3 4043static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4044{
717746e3 4045 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4046}
4047
4bff1e86 4048static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4049{
4bff1e86 4050 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4051}
4052
4bff1e86 4053static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4054{
4bff1e86 4055 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4056}
4057
1ac9d0cf
AK		 4058static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4059{
4060 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4061}
4062
4063static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4064{
4065 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4066}
4067
4bff1e86
AK		 4068static unsigned long emulator_get_cached_segment_base(
4069 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4070{
4bff1e86 4071 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4072}
4073
1aa36616
AK		 4074static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4075 struct desc_struct *desc, u32 *base3,
4076 int seg)
2dafc6c2
GN		 4077{
4078 struct kvm_segment var;
4079
4bff1e86 4080 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4081 *selector = var.selector;
2dafc6c2
GN		 4082
4083 if (var.unusable)
4084 return false;
4085
4086 if (var.g)
4087 var.limit >>= 12;
4088 set_desc_limit(desc, var.limit);
4089 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4090#ifdef CONFIG_X86_64
4091 if (base3)
4092 *base3 = var.base >> 32;
4093#endif
2dafc6c2
GN		 4094 desc->type = var.type;
4095 desc->s = var.s;
4096 desc->dpl = var.dpl;
4097 desc->p = var.present;
4098 desc->avl = var.avl;
4099 desc->l = var.l;
4100 desc->d = var.db;
4101 desc->g = var.g;
4102
4103 return true;
4104}
4105
1aa36616
AK		 4106static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4107 struct desc_struct *desc, u32 base3,
4108 int seg)
2dafc6c2 4109{
4bff1e86 4110 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4111 struct kvm_segment var;
4112
1aa36616 4113 var.selector = selector;
2dafc6c2 4114 var.base = get_desc_base(desc);
5601d05b
GN		 4115#ifdef CONFIG_X86_64
4116 var.base |= ((u64)base3) << 32;
4117#endif
2dafc6c2
GN		 4118 var.limit = get_desc_limit(desc);
4119 if (desc->g)
4120 var.limit = (var.limit << 12) | 0xfff;
4121 var.type = desc->type;
4122 var.present = desc->p;
4123 var.dpl = desc->dpl;
4124 var.db = desc->d;
4125 var.s = desc->s;
4126 var.l = desc->l;
4127 var.g = desc->g;
4128 var.avl = desc->avl;
4129 var.present = desc->p;
4130 var.unusable = !var.present;
4131 var.padding = 0;
4132
4133 kvm_set_segment(vcpu, &var, seg);
4134 return;
4135}
4136
717746e3
AK		 4137static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4138 u32 msr_index, u64 *pdata)
4139{
4140 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4141}
4142
4143static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4144 u32 msr_index, u64 data)
4145{
4146 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4147}
4148
222d21aa
AK		 4149static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4150 u32 pmc, u64 *pdata)
4151{
4152 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4153}
4154
6c3287f7
AK		 4155static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4156{
4157 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4158}
4159
5037f6f3
AK		 4160static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4161{
4162 preempt_disable();
5197b808 4163 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4164 /*
4165 * CR0.TS may reference the host fpu state, not the guest fpu state,
4166 * so it may be clear at this point.
4167 */
4168 clts();
4169}
4170
4171static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4172{
4173 preempt_enable();
4174}
4175
2953538e 4176static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4177 struct x86_instruction_info *info,
c4f035c6
AK		 4178 enum x86_intercept_stage stage)
4179{
2953538e 4180 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4181}
4182
14af3f3c 4183static struct x86_emulate_ops emulate_ops = {
1871c602 4184 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4185 .write_std = kvm_write_guest_virt_system,
1871c602 4186 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4187 .read_emulated = emulator_read_emulated,
4188 .write_emulated = emulator_write_emulated,
4189 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4190 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4191 .pio_in_emulated = emulator_pio_in_emulated,
4192 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4193 .get_segment = emulator_get_segment,
4194 .set_segment = emulator_set_segment,
5951c442 4195 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4196 .get_gdt = emulator_get_gdt,
160ce1f1 4197 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4198 .set_gdt = emulator_set_gdt,
4199 .set_idt = emulator_set_idt,
52a46617
GN		 4200 .get_cr = emulator_get_cr,
4201 .set_cr = emulator_set_cr,
9c537244 4202 .cpl = emulator_get_cpl,
35aa5375
GN		 4203 .get_dr = emulator_get_dr,
4204 .set_dr = emulator_set_dr,
717746e3
AK		 4205 .set_msr = emulator_set_msr,
4206 .get_msr = emulator_get_msr,
222d21aa 4207 .read_pmc = emulator_read_pmc,
6c3287f7 4208 .halt = emulator_halt,
bcaf5cc5 4209 .wbinvd = emulator_wbinvd,
d6aa1000 4210 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4211 .get_fpu = emulator_get_fpu,
4212 .put_fpu = emulator_put_fpu,
c4f035c6 4213 .intercept = emulator_intercept,
bbd9b64e
CO		 4214};
4215
5fdbf976
MT		 4216static void cache_all_regs(struct kvm_vcpu *vcpu)
4217{
4218 kvm_register_read(vcpu, VCPU_REGS_RAX);
4219 kvm_register_read(vcpu, VCPU_REGS_RSP);
4220 kvm_register_read(vcpu, VCPU_REGS_RIP);
4221 vcpu->arch.regs_dirty = ~0;
4222}
4223
95cb2295
GN		 4224static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4225{
4226 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4227 /*
4228 * an sti; sti; sequence only disable interrupts for the first
4229 * instruction. So, if the last instruction, be it emulated or
4230 * not, left the system with the INT_STI flag enabled, it
4231 * means that the last instruction is an sti. We should not
4232 * leave the flag on in this case. The same goes for mov ss
4233 */
4234 if (!(int_shadow & mask))
4235 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4236}
4237
54b8486f
GN		 4238static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4239{
4240 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4241 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4242 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4243 else if (ctxt->exception.error_code_valid)
4244 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4245 ctxt->exception.error_code);
54b8486f 4246 else
da9cb575 4247 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4248}
4249
9dac77fa 4250static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4251 const unsigned long *regs)
4252{
9dac77fa
AK		 4253 memset(&ctxt->twobyte, 0,
4254 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4255 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4256
9dac77fa
AK		 4257 ctxt->fetch.start = 0;
4258 ctxt->fetch.end = 0;
4259 ctxt->io_read.pos = 0;
4260 ctxt->io_read.end = 0;
4261 ctxt->mem_read.pos = 0;
4262 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4263}
4264
8ec4722d
MG		 4265static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4266{
adf52235 4267 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4268 int cs_db, cs_l;
4269
2aab2c5b
GN		 4270 /*
4271 * TODO: fix emulate.c to use guest_read/write_register
4272 * instead of direct ->regs accesses, can save hundred cycles
4273 * on Intel for instructions that don't read/change RSP, for
4274 * for example.
4275 */
8ec4722d
MG		 4276 cache_all_regs(vcpu);
4277
4278 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4279
adf52235
TY		 4280 ctxt->eflags = kvm_get_rflags(vcpu);
4281 ctxt->eip = kvm_rip_read(vcpu);
4282 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4283 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4284 cs_l ? X86EMUL_MODE_PROT64 :
4285 cs_db ? X86EMUL_MODE_PROT32 :
4286 X86EMUL_MODE_PROT16;
4287 ctxt->guest_mode = is_guest_mode(vcpu);
4288
9dac77fa 4289 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4290 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4291}
4292
71f9833b 4293int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4294{
9d74191a 4295 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4296 int ret;
4297
4298 init_emulate_ctxt(vcpu);
4299
9dac77fa
AK		 4300 ctxt->op_bytes = 2;
4301 ctxt->ad_bytes = 2;
4302 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4303 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4304
4305 if (ret != X86EMUL_CONTINUE)
4306 return EMULATE_FAIL;
4307
9dac77fa
AK		 4308 ctxt->eip = ctxt->_eip;
4309 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4310 kvm_rip_write(vcpu, ctxt->eip);
4311 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4312
4313 if (irq == NMI_VECTOR)
7460fb4a 4314 vcpu->arch.nmi_pending = 0;
63995653
MG		 4315 else
4316 vcpu->arch.interrupt.pending = false;
4317
4318 return EMULATE_DONE;
4319}
4320EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4321
6d77dbfc
GN		 4322static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4323{
fc3a9157
JR		 4324 int r = EMULATE_DONE;
4325
6d77dbfc
GN		 4326 ++vcpu->stat.insn_emulation_fail;
4327 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4328 if (!is_guest_mode(vcpu)) {
4329 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4330 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4331 vcpu->run->internal.ndata = 0;
4332 r = EMULATE_FAIL;
4333 }
6d77dbfc 4334 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4335
4336 return r;
6d77dbfc
GN		 4337}
4338
a6f177ef
GN		 4339static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4340{
4341 gpa_t gpa;
4342
68be0803
GN		 4343 if (tdp_enabled)
4344 return false;
4345
a6f177ef
GN		 4346 /*
4347 * if emulation was due to access to shadowed page table
4348 * and it failed try to unshadow page and re-entetr the
4349 * guest to let CPU execute the instruction.
4350 */
4351 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4352 return true;
4353
4354 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4355
4356 if (gpa == UNMAPPED_GVA)
4357 return true; /* let cpu generate fault */
4358
4359 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4360 return true;
4361
4362 return false;
4363}
4364
1cb3f3ae
XG		 4365static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4366 unsigned long cr2, int emulation_type)
4367{
4368 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4369 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4370
4371 last_retry_eip = vcpu->arch.last_retry_eip;
4372 last_retry_addr = vcpu->arch.last_retry_addr;
4373
4374 /*
4375 * If the emulation is caused by #PF and it is non-page_table
4376 * writing instruction, it means the VM-EXIT is caused by shadow
4377 * page protected, we can zap the shadow page and retry this
4378 * instruction directly.
4379 *
4380 * Note: if the guest uses a non-page-table modifying instruction
4381 * on the PDE that points to the instruction, then we will unmap
4382 * the instruction and go to an infinite loop. So, we cache the
4383 * last retried eip and the last fault address, if we meet the eip
4384 * and the address again, we can break out of the potential infinite
4385 * loop.
4386 */
4387 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4388
4389 if (!(emulation_type & EMULTYPE_RETRY))
4390 return false;
4391
4392 if (x86_page_table_writing_insn(ctxt))
4393 return false;
4394
4395 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4396 return false;
4397
4398 vcpu->arch.last_retry_eip = ctxt->eip;
4399 vcpu->arch.last_retry_addr = cr2;
4400
4401 if (!vcpu->arch.mmu.direct_map)
4402 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4403
4404 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4405
4406 return true;
4407}
4408
51d8b661
AP		 4409int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4410 unsigned long cr2,
dc25e89e
AP		 4411 int emulation_type,
4412 void *insn,
4413 int insn_len)
bbd9b64e 4414{
95cb2295 4415 int r;
9d74191a 4416 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4417 bool writeback = true;
bbd9b64e 4418
26eef70c 4419 kvm_clear_exception_queue(vcpu);
8d7d8102 4420
571008da 4421 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4422 init_emulate_ctxt(vcpu);
9d74191a
TY		 4423 ctxt->interruptibility = 0;
4424 ctxt->have_exception = false;
4425 ctxt->perm_ok = false;
bbd9b64e 4426
9d74191a 4427 ctxt->only_vendor_specific_insn
4005996e
AK		 4428 = emulation_type & EMULTYPE_TRAP_UD;
4429
9d74191a 4430 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4431
e46479f8 4432 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4433 ++vcpu->stat.insn_emulation;
1d2887e2 4434 if (r != EMULATION_OK) {
4005996e
AK		 4435 if (emulation_type & EMULTYPE_TRAP_UD)
4436 return EMULATE_FAIL;
a6f177ef 4437 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4438 return EMULATE_DONE;
6d77dbfc
GN		 4439 if (emulation_type & EMULTYPE_SKIP)
4440 return EMULATE_FAIL;
4441 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4442 }
4443 }
4444
ba8afb6b 4445 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4446 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4447 return EMULATE_DONE;
4448 }
4449
1cb3f3ae
XG		 4450 if (retry_instruction(ctxt, cr2, emulation_type))
4451 return EMULATE_DONE;
4452
7ae441ea 4453 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4454 changes registers values during IO operation */
7ae441ea
GN		 4455 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4456 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4457 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4458 }
4d2179e1 4459
5cd21917 4460restart:
9d74191a 4461 r = x86_emulate_insn(ctxt);
bbd9b64e 4462
775fde86
JR		 4463 if (r == EMULATION_INTERCEPTED)
4464 return EMULATE_DONE;
4465
d2ddd1c4 4466 if (r == EMULATION_FAILED) {
a6f177ef 4467 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4468 return EMULATE_DONE;
4469
6d77dbfc 4470 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4471 }
4472
9d74191a 4473 if (ctxt->have_exception) {
54b8486f 4474 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4475 r = EMULATE_DONE;
4476 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4477 if (!vcpu->arch.pio.in)
4478 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4479 else
4480 writeback = false;
e85d28f8 4481 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4482 } else if (vcpu->mmio_needed) {
4483 if (!vcpu->mmio_is_write)
4484 writeback = false;
e85d28f8 4485 r = EMULATE_DO_MMIO;
7ae441ea 4486 } else if (r == EMULATION_RESTART)
5cd21917 4487 goto restart;
d2ddd1c4
GN		 4488 else
4489 r = EMULATE_DONE;
f850e2e6 4490
7ae441ea 4491 if (writeback) {
9d74191a
TY		 4492 toggle_interruptibility(vcpu, ctxt->interruptibility);
4493 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4494 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4495 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4496 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4497 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4498 } else
4499 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4500
4501 return r;
de7d789a 4502}
51d8b661 4503EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4504
cf8f70bf 4505int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4506{
cf8f70bf 4507 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4508 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4509 size, port, &val, 1);
cf8f70bf 4510 /* do not return to emulator after return from userspace */
7972995b 4511 vcpu->arch.pio.count = 0;
de7d789a
CO		 4512 return ret;
4513}
cf8f70bf 4514EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4515
8cfdc000
ZA		 4516static void tsc_bad(void *info)
4517{
0a3aee0d 4518 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4519}
4520
4521static void tsc_khz_changed(void *data)
c8076604 4522{
8cfdc000
ZA		 4523 struct cpufreq_freqs *freq = data;
4524 unsigned long khz = 0;
4525
4526 if (data)
4527 khz = freq->new;
4528 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4529 khz = cpufreq_quick_get(raw_smp_processor_id());
4530 if (!khz)
4531 khz = tsc_khz;
0a3aee0d 4532 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4533}
4534
c8076604
GH		 4535static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4536 void *data)
4537{
4538 struct cpufreq_freqs *freq = data;
4539 struct kvm *kvm;
4540 struct kvm_vcpu *vcpu;
4541 int i, send_ipi = 0;
4542
8cfdc000
ZA		 4543 /*
4544 * We allow guests to temporarily run on slowing clocks,
4545 * provided we notify them after, or to run on accelerating
4546 * clocks, provided we notify them before. Thus time never
4547 * goes backwards.
4548 *
4549 * However, we have a problem. We can't atomically update
4550 * the frequency of a given CPU from this function; it is
4551 * merely a notifier, which can be called from any CPU.
4552 * Changing the TSC frequency at arbitrary points in time
4553 * requires a recomputation of local variables related to
4554 * the TSC for each VCPU. We must flag these local variables
4555 * to be updated and be sure the update takes place with the
4556 * new frequency before any guests proceed.
4557 *
4558 * Unfortunately, the combination of hotplug CPU and frequency
4559 * change creates an intractable locking scenario; the order
4560 * of when these callouts happen is undefined with respect to
4561 * CPU hotplug, and they can race with each other. As such,
4562 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4563 * undefined; you can actually have a CPU frequency change take
4564 * place in between the computation of X and the setting of the
4565 * variable. To protect against this problem, all updates of
4566 * the per_cpu tsc_khz variable are done in an interrupt
4567 * protected IPI, and all callers wishing to update the value
4568 * must wait for a synchronous IPI to complete (which is trivial
4569 * if the caller is on the CPU already). This establishes the
4570 * necessary total order on variable updates.
4571 *
4572 * Note that because a guest time update may take place
4573 * anytime after the setting of the VCPU's request bit, the
4574 * correct TSC value must be set before the request. However,
4575 * to ensure the update actually makes it to any guest which
4576 * starts running in hardware virtualization between the set
4577 * and the acquisition of the spinlock, we must also ping the
4578 * CPU after setting the request bit.
4579 *
4580 */
4581
c8076604
GH		 4582 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4583 return 0;
4584 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4585 return 0;
8cfdc000
ZA		 4586
4587 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4588
e935b837 4589 raw_spin_lock(&kvm_lock);
c8076604 4590 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4591 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4592 if (vcpu->cpu != freq->cpu)
4593 continue;
c285545f 4594 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4595 if (vcpu->cpu != smp_processor_id())
8cfdc000 4596 send_ipi = 1;
c8076604
GH		 4597 }
4598 }
e935b837 4599 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4600
4601 if (freq->old < freq->new && send_ipi) {
4602 /*
4603 * We upscale the frequency. Must make the guest
4604 * doesn't see old kvmclock values while running with
4605 * the new frequency, otherwise we risk the guest sees
4606 * time go backwards.
4607 *
4608 * In case we update the frequency for another cpu
4609 * (which might be in guest context) send an interrupt
4610 * to kick the cpu out of guest context. Next time
4611 * guest context is entered kvmclock will be updated,
4612 * so the guest will not see stale values.
4613 */
8cfdc000 4614 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4615 }
4616 return 0;
4617}
4618
4619static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4620 .notifier_call = kvmclock_cpufreq_notifier
4621};
4622
4623static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4624 unsigned long action, void *hcpu)
4625{
4626 unsigned int cpu = (unsigned long)hcpu;
4627
4628 switch (action) {
4629 case CPU_ONLINE:
4630 case CPU_DOWN_FAILED:
4631 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4632 break;
4633 case CPU_DOWN_PREPARE:
4634 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4635 break;
4636 }
4637 return NOTIFY_OK;
4638}
4639
4640static struct notifier_block kvmclock_cpu_notifier_block = {
4641 .notifier_call = kvmclock_cpu_notifier,
4642 .priority = -INT_MAX
c8076604
GH		 4643};
4644
b820cc0c
ZA		 4645static void kvm_timer_init(void)
4646{
4647 int cpu;
4648
c285545f 4649 max_tsc_khz = tsc_khz;
8cfdc000 4650 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4651 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4652#ifdef CONFIG_CPU_FREQ
4653 struct cpufreq_policy policy;
4654 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4655 cpu = get_cpu();
4656 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4657 if (policy.cpuinfo.max_freq)
4658 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4659 put_cpu();
c285545f 4660#endif
b820cc0c
ZA		 4661 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4662 CPUFREQ_TRANSITION_NOTIFIER);
4663 }
c285545f 4664 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4665 for_each_online_cpu(cpu)
4666 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4667}
4668
ff9d07a0
ZY		 4669static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4670
f5132b01 4671int kvm_is_in_guest(void)
ff9d07a0 4672{
086c9855 4673 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4674}
4675
4676static int kvm_is_user_mode(void)
4677{
4678 int user_mode = 3;
dcf46b94 4679
086c9855
AS		 4680 if (__this_cpu_read(current_vcpu))
4681 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4682
ff9d07a0
ZY		 4683 return user_mode != 0;
4684}
4685
4686static unsigned long kvm_get_guest_ip(void)
4687{
4688 unsigned long ip = 0;
dcf46b94 4689
086c9855
AS		 4690 if (__this_cpu_read(current_vcpu))
4691 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4692
ff9d07a0
ZY		 4693 return ip;
4694}
4695
4696static struct perf_guest_info_callbacks kvm_guest_cbs = {
4697 .is_in_guest = kvm_is_in_guest,
4698 .is_user_mode = kvm_is_user_mode,
4699 .get_guest_ip = kvm_get_guest_ip,
4700};
4701
4702void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4703{
086c9855 4704 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4705}
4706EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4707
4708void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4709{
086c9855 4710 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4711}
4712EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4713
ce88decf
XG		 4714static void kvm_set_mmio_spte_mask(void)
4715{
4716 u64 mask;
4717 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4718
4719 /*
4720 * Set the reserved bits and the present bit of an paging-structure
4721 * entry to generate page fault with PFER.RSV = 1.
4722 */
4723 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4724 mask |= 1ull;
4725
4726#ifdef CONFIG_X86_64
4727 /*
4728 * If reserved bit is not supported, clear the present bit to disable
4729 * mmio page fault.
4730 */
4731 if (maxphyaddr == 52)
4732 mask &= ~1ull;
4733#endif
4734
4735 kvm_mmu_set_mmio_spte_mask(mask);
4736}
4737
f8c16bba 4738int kvm_arch_init(void *opaque)
043405e1 4739{
b820cc0c 4740 int r;
f8c16bba
ZX		 4741 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4742
f8c16bba
ZX		 4743 if (kvm_x86_ops) {
4744 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4745 r = -EEXIST;
4746 goto out;
f8c16bba
ZX		 4747 }
4748
4749 if (!ops->cpu_has_kvm_support()) {
4750 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4751 r = -EOPNOTSUPP;
4752 goto out;
f8c16bba
ZX		 4753 }
4754 if (ops->disabled_by_bios()) {
4755 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4756 r = -EOPNOTSUPP;
4757 goto out;
f8c16bba
ZX		 4758 }
4759
97db56ce
AK		 4760 r = kvm_mmu_module_init();
4761 if (r)
4762 goto out;
4763
ce88decf 4764 kvm_set_mmio_spte_mask();
97db56ce
AK		 4765 kvm_init_msr_list();
4766
f8c16bba 4767 kvm_x86_ops = ops;
7b52345e 4768 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4769 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4770
b820cc0c 4771 kvm_timer_init();
c8076604 4772
ff9d07a0
ZY		 4773 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4774
2acf923e
DC		 4775 if (cpu_has_xsave)
4776 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4777
f8c16bba 4778 return 0;
56c6d28a
ZX		 4779
4780out:
56c6d28a 4781 return r;
043405e1 4782}
8776e519 4783
f8c16bba
ZX		 4784void kvm_arch_exit(void)
4785{
ff9d07a0
ZY		 4786 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4787
888d256e
JK		 4788 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4789 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4790 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4791 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4792 kvm_x86_ops = NULL;
56c6d28a
ZX		 4793 kvm_mmu_module_exit();
4794}
f8c16bba 4795
8776e519
HB		 4796int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4797{
4798 ++vcpu->stat.halt_exits;
4799 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4800 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4801 return 1;
4802 } else {
4803 vcpu->run->exit_reason = KVM_EXIT_HLT;
4804 return 0;
4805 }
4806}
4807EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4808
55cd8e5a
GN		 4809int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4810{
4811 u64 param, ingpa, outgpa, ret;
4812 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4813 bool fast, longmode;
4814 int cs_db, cs_l;
4815
4816 /*
4817 * hypercall generates UD from non zero cpl and real mode
4818 * per HYPER-V spec
4819 */
3eeb3288 4820 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4821 kvm_queue_exception(vcpu, UD_VECTOR);
4822 return 0;
4823 }
4824
4825 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4826 longmode = is_long_mode(vcpu) && cs_l == 1;
4827
4828 if (!longmode) {
ccd46936
GN		 4829 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4830 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4831 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4832 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4833 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4834 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4835 }
4836#ifdef CONFIG_X86_64
4837 else {
4838 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4839 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4840 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4841 }
4842#endif
4843
4844 code = param & 0xffff;
4845 fast = (param >> 16) & 0x1;
4846 rep_cnt = (param >> 32) & 0xfff;
4847 rep_idx = (param >> 48) & 0xfff;
4848
4849 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4850
c25bc163
GN		 4851 switch (code) {
4852 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4853 kvm_vcpu_on_spin(vcpu);
4854 break;
4855 default:
4856 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4857 break;
4858 }
55cd8e5a
GN		 4859
4860 ret = res | (((u64)rep_done & 0xfff) << 32);
4861 if (longmode) {
4862 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4863 } else {
4864 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4865 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4866 }
4867
4868 return 1;
4869}
4870
8776e519
HB		 4871int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4872{
4873 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4874 int r = 1;
8776e519 4875
55cd8e5a
GN		 4876 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4877 return kvm_hv_hypercall(vcpu);
4878
5fdbf976
MT		 4879 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4880 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4881 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4882 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4883 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4884
229456fc 4885 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4886
8776e519
HB		 4887 if (!is_long_mode(vcpu)) {
4888 nr &= 0xFFFFFFFF;
4889 a0 &= 0xFFFFFFFF;
4890 a1 &= 0xFFFFFFFF;
4891 a2 &= 0xFFFFFFFF;
4892 a3 &= 0xFFFFFFFF;
4893 }
4894
07708c4a
JK		 4895 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4896 ret = -KVM_EPERM;
4897 goto out;
4898 }
4899
8776e519 4900 switch (nr) {
b93463aa
AK		 4901 case KVM_HC_VAPIC_POLL_IRQ:
4902 ret = 0;
4903 break;
8776e519
HB		 4904 default:
4905 ret = -KVM_ENOSYS;
4906 break;
4907 }
07708c4a 4908out:
5fdbf976 4909 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4910 ++vcpu->stat.hypercalls;
2f333bcb 4911 return r;
8776e519
HB		 4912}
4913EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4914
d6aa1000 4915int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 4916{
d6aa1000 4917 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 4918 char instruction[3];
5fdbf976 4919 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4920
8776e519
HB		 4921 /*
4922 * Blow out the MMU to ensure that no other VCPU has an active mapping
4923 * to ensure that the updated hypercall appears atomically across all
4924 * VCPUs.
4925 */
4926 kvm_mmu_zap_all(vcpu->kvm);
4927
8776e519 4928 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4929
9d74191a 4930 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 4931}
4932
b6c7a5dc
HB		 4933/*
4934 * Check if userspace requested an interrupt window, and that the
4935 * interrupt window is open.
4936 *
4937 * No need to exit to userspace if we already have an interrupt queued.
4938 */
851ba692 4939static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4940{
8061823a 4941 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4942 vcpu->run->request_interrupt_window &&
5df56646 4943 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4944}
4945
851ba692 4946static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4947{
851ba692
AK		 4948 struct kvm_run *kvm_run = vcpu->run;
4949
91586a3b 4950 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4951 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4952 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4953 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4954 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4955 else
b6c7a5dc 4956 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4957 kvm_arch_interrupt_allowed(vcpu) &&
4958 !kvm_cpu_has_interrupt(vcpu) &&
4959 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4960}
4961
b93463aa
AK		 4962static void vapic_enter(struct kvm_vcpu *vcpu)
4963{
4964 struct kvm_lapic *apic = vcpu->arch.apic;
4965 struct page *page;
4966
4967 if (!apic || !apic->vapic_addr)
4968 return;
4969
4970 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4971
4972 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4973}
4974
4975static void vapic_exit(struct kvm_vcpu *vcpu)
4976{
4977 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4978 int idx;
b93463aa
AK		 4979
4980 if (!apic || !apic->vapic_addr)
4981 return;
4982
f656ce01 4983 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4984 kvm_release_page_dirty(apic->vapic_page);
4985 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4986 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4987}
4988
95ba8273
GN		 4989static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4990{
4991 int max_irr, tpr;
4992
4993 if (!kvm_x86_ops->update_cr8_intercept)
4994 return;
4995
88c808fd
AK		 4996 if (!vcpu->arch.apic)
4997 return;
4998
8db3baa2
GN		 4999 if (!vcpu->arch.apic->vapic_addr)
5000 max_irr = kvm_lapic_find_highest_irr(vcpu);
5001 else
5002 max_irr = -1;
95ba8273
GN		 5003
5004 if (max_irr != -1)
5005 max_irr >>= 4;
5006
5007 tpr = kvm_lapic_get_cr8(vcpu);
5008
5009 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5010}
5011
851ba692 5012static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5013{
5014 /* try to reinject previous events if any */
b59bb7bd 5015 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5016 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5017 vcpu->arch.exception.has_error_code,
5018 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5019 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5020 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5021 vcpu->arch.exception.error_code,
5022 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5023 return;
5024 }
5025
95ba8273
GN		 5026 if (vcpu->arch.nmi_injected) {
5027 kvm_x86_ops->set_nmi(vcpu);
5028 return;
5029 }
5030
5031 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5032 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5033 return;
5034 }
5035
5036 /* try to inject new event if pending */
5037 if (vcpu->arch.nmi_pending) {
5038 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5039 --vcpu->arch.nmi_pending;
95ba8273
GN		 5040 vcpu->arch.nmi_injected = true;
5041 kvm_x86_ops->set_nmi(vcpu);
5042 }
5043 } else if (kvm_cpu_has_interrupt(vcpu)) {
5044 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5045 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5046 false);
5047 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5048 }
5049 }
5050}
5051
2acf923e
DC		 5052static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5053{
5054 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5055 !vcpu->guest_xcr0_loaded) {
5056 /* kvm_set_xcr() also depends on this */
5057 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5058 vcpu->guest_xcr0_loaded = 1;
5059 }
5060}
5061
5062static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5063{
5064 if (vcpu->guest_xcr0_loaded) {
5065 if (vcpu->arch.xcr0 != host_xcr0)
5066 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5067 vcpu->guest_xcr0_loaded = 0;
5068 }
5069}
5070
7460fb4a
AK		 5071static void process_nmi(struct kvm_vcpu *vcpu)
5072{
5073 unsigned limit = 2;
5074
5075 /*
5076 * x86 is limited to one NMI running, and one NMI pending after it.
5077 * If an NMI is already in progress, limit further NMIs to just one.
5078 * Otherwise, allow two (and we'll inject the first one immediately).
5079 */
5080 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5081 limit = 1;
5082
5083 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5084 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5085 kvm_make_request(KVM_REQ_EVENT, vcpu);
5086}
5087
851ba692 5088static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5089{
5090 int r;
6a8b1d13 5091 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5092 vcpu->run->request_interrupt_window;
d6185f20 5093 bool req_immediate_exit = 0;
b6c7a5dc 5094
3e007509 5095 if (vcpu->requests) {
a8eeb04a 5096 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5097 kvm_mmu_unload(vcpu);
a8eeb04a 5098 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5099 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5100 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5101 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5102 if (unlikely(r))
5103 goto out;
5104 }
a8eeb04a 5105 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5106 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5107 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5108 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5109 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5110 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5111 r = 0;
5112 goto out;
5113 }
a8eeb04a 5114 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5115 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5116 r = 0;
5117 goto out;
5118 }
a8eeb04a 5119 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5120 vcpu->fpu_active = 0;
5121 kvm_x86_ops->fpu_deactivate(vcpu);
5122 }
af585b92
GN		 5123 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5124 /* Page is swapped out. Do synthetic halt */
5125 vcpu->arch.apf.halted = true;
5126 r = 1;
5127 goto out;
5128 }
c9aaa895
GC		 5129 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5130 record_steal_time(vcpu);
7460fb4a
AK		 5131 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5132 process_nmi(vcpu);
d6185f20
NHE		 5133 req_immediate_exit =
5134 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5135 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5136 kvm_handle_pmu_event(vcpu);
5137 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5138 kvm_deliver_pmi(vcpu);
2f52d58c 5139 }
b93463aa 5140
3e007509
AK		 5141 r = kvm_mmu_reload(vcpu);
5142 if (unlikely(r))
5143 goto out;
5144
b463a6f7
AK		 5145 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5146 inject_pending_event(vcpu);
5147
5148 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5149 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5150 kvm_x86_ops->enable_nmi_window(vcpu);
5151 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5152 kvm_x86_ops->enable_irq_window(vcpu);
5153
5154 if (kvm_lapic_enabled(vcpu)) {
5155 update_cr8_intercept(vcpu);
5156 kvm_lapic_sync_to_vapic(vcpu);
5157 }
5158 }
5159
b6c7a5dc
HB		 5160 preempt_disable();
5161
5162 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5163 if (vcpu->fpu_active)
5164 kvm_load_guest_fpu(vcpu);
2acf923e 5165 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5166
6b7e2d09
XG		 5167 vcpu->mode = IN_GUEST_MODE;
5168
5169 /* We should set ->mode before check ->requests,
5170 * see the comment in make_all_cpus_request.
5171 */
5172 smp_mb();
b6c7a5dc 5173
d94e1dc9 5174 local_irq_disable();
32f88400 5175
6b7e2d09 5176 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5177 || need_resched() || signal_pending(current)) {
6b7e2d09 5178 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5179 smp_wmb();
6c142801
AK		 5180 local_irq_enable();
5181 preempt_enable();
b463a6f7 5182 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5183 r = 1;
5184 goto out;
5185 }
5186
f656ce01 5187 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5188
d6185f20
NHE		 5189 if (req_immediate_exit)
5190 smp_send_reschedule(vcpu->cpu);
5191
b6c7a5dc
HB		 5192 kvm_guest_enter();
5193
42dbaa5a 5194 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5195 set_debugreg(0, 7);
5196 set_debugreg(vcpu->arch.eff_db[0], 0);
5197 set_debugreg(vcpu->arch.eff_db[1], 1);
5198 set_debugreg(vcpu->arch.eff_db[2], 2);
5199 set_debugreg(vcpu->arch.eff_db[3], 3);
5200 }
b6c7a5dc 5201
229456fc 5202 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5203 kvm_x86_ops->run(vcpu);
b6c7a5dc 5204
24f1e32c
FW		 5205 /*
5206 * If the guest has used debug registers, at least dr7
5207 * will be disabled while returning to the host.
5208 * If we don't have active breakpoints in the host, we don't
5209 * care about the messed up debug address registers. But if
5210 * we have some of them active, restore the old state.
5211 */
59d8eb53 5212 if (hw_breakpoint_active())
24f1e32c 5213 hw_breakpoint_restore();
42dbaa5a 5214
d5c1785d 5215 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5216
6b7e2d09 5217 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5218 smp_wmb();
b6c7a5dc
HB		 5219 local_irq_enable();
5220
5221 ++vcpu->stat.exits;
5222
5223 /*
5224 * We must have an instruction between local_irq_enable() and
5225 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5226 * the interrupt shadow. The stat.exits increment will do nicely.
5227 * But we need to prevent reordering, hence this barrier():
5228 */
5229 barrier();
5230
5231 kvm_guest_exit();
5232
5233 preempt_enable();
5234
f656ce01 5235 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5236
b6c7a5dc
HB		 5237 /*
5238 * Profile KVM exit RIPs:
5239 */
5240 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5241 unsigned long rip = kvm_rip_read(vcpu);
5242 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5243 }
5244
298101da 5245
b93463aa
AK		 5246 kvm_lapic_sync_from_vapic(vcpu);
5247
851ba692 5248 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5249out:
5250 return r;
5251}
b6c7a5dc 5252
09cec754 5253
851ba692 5254static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5255{
5256 int r;
f656ce01 5257 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5258
5259 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5260 pr_debug("vcpu %d received sipi with vector # %x\n",
5261 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5262 kvm_lapic_reset(vcpu);
5f179287 5263 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5264 if (r)
5265 return r;
5266 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5267 }
5268
f656ce01 5269 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5270 vapic_enter(vcpu);
5271
5272 r = 1;
5273 while (r > 0) {
af585b92
GN		 5274 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5275 !vcpu->arch.apf.halted)
851ba692 5276 r = vcpu_enter_guest(vcpu);
d7690175 5277 else {
f656ce01 5278 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5279 kvm_vcpu_block(vcpu);
f656ce01 5280 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5281 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5282 {
5283 switch(vcpu->arch.mp_state) {
5284 case KVM_MP_STATE_HALTED:
d7690175 5285 vcpu->arch.mp_state =
09cec754
GN		 5286 KVM_MP_STATE_RUNNABLE;
5287 case KVM_MP_STATE_RUNNABLE:
af585b92 5288 vcpu->arch.apf.halted = false;
09cec754
GN		 5289 break;
5290 case KVM_MP_STATE_SIPI_RECEIVED:
5291 default:
5292 r = -EINTR;
5293 break;
5294 }
5295 }
d7690175
MT		 5296 }
5297
09cec754
GN		 5298 if (r <= 0)
5299 break;
5300
5301 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5302 if (kvm_cpu_has_pending_timer(vcpu))
5303 kvm_inject_pending_timer_irqs(vcpu);
5304
851ba692 5305 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5306 r = -EINTR;
851ba692 5307 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5308 ++vcpu->stat.request_irq_exits;
5309 }
af585b92
GN		 5310
5311 kvm_check_async_pf_completion(vcpu);
5312
09cec754
GN		 5313 if (signal_pending(current)) {
5314 r = -EINTR;
851ba692 5315 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5316 ++vcpu->stat.signal_exits;
5317 }
5318 if (need_resched()) {
f656ce01 5319 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5320 kvm_resched(vcpu);
f656ce01 5321 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5322 }
b6c7a5dc
HB		 5323 }
5324
f656ce01 5325 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5326
b93463aa
AK		 5327 vapic_exit(vcpu);
5328
b6c7a5dc
HB		 5329 return r;
5330}
5331
5287f194
AK		 5332static int complete_mmio(struct kvm_vcpu *vcpu)
5333{
5334 struct kvm_run *run = vcpu->run;
5335 int r;
5336
5337 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5338 return 1;
5339
5340 if (vcpu->mmio_needed) {
5287f194 5341 vcpu->mmio_needed = 0;
cef4dea0 5342 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5343 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5344 run->mmio.data, 8);
cef4dea0
AK		 5345 vcpu->mmio_index += 8;
5346 if (vcpu->mmio_index < vcpu->mmio_size) {
5347 run->exit_reason = KVM_EXIT_MMIO;
5348 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5349 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5350 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5351 run->mmio.is_write = vcpu->mmio_is_write;
5352 vcpu->mmio_needed = 1;
5353 return 0;
5354 }
5355 if (vcpu->mmio_is_write)
5356 return 1;
5357 vcpu->mmio_read_completed = 1;
5287f194
AK		 5358 }
5359 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5360 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5361 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5362 if (r != EMULATE_DONE)
5363 return 0;
5364 return 1;
5365}
5366
b6c7a5dc
HB		 5367int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5368{
5369 int r;
5370 sigset_t sigsaved;
5371
e5c30142
AK		 5372 if (!tsk_used_math(current) && init_fpu(current))
5373 return -ENOMEM;
5374
ac9f6dc0
AK		 5375 if (vcpu->sigset_active)
5376 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5377
a4535290 5378 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5379 kvm_vcpu_block(vcpu);
d7690175 5380 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5381 r = -EAGAIN;
5382 goto out;
b6c7a5dc
HB		 5383 }
5384
b6c7a5dc 5385 /* re-sync apic's tpr */
eea1cff9
AP		 5386 if (!irqchip_in_kernel(vcpu->kvm)) {
5387 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5388 r = -EINVAL;
5389 goto out;
5390 }
5391 }
b6c7a5dc 5392
5287f194
AK		 5393 r = complete_mmio(vcpu);
5394 if (r <= 0)
5395 goto out;
5396
851ba692 5397 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5398
5399out:
f1d86e46 5400 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5401 if (vcpu->sigset_active)
5402 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5403
b6c7a5dc
HB		 5404 return r;
5405}
5406
5407int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5408{
7ae441ea
GN		 5409 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5410 /*
5411 * We are here if userspace calls get_regs() in the middle of
5412 * instruction emulation. Registers state needs to be copied
5413 * back from emulation context to vcpu. Usrapace shouldn't do
5414 * that usually, but some bad designed PV devices (vmware
5415 * backdoor interface) need this to work
5416 */
9dac77fa
AK		 5417 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5418 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5419 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5420 }
5fdbf976
MT		 5421 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5422 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5423 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5424 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5425 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5426 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5427 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5428 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5429#ifdef CONFIG_X86_64
5fdbf976
MT		 5430 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5431 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5432 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5433 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5434 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5435 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5436 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5437 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5438#endif
5439
5fdbf976 5440 regs->rip = kvm_rip_read(vcpu);
91586a3b 5441 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5442
b6c7a5dc
HB		 5443 return 0;
5444}
5445
5446int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5447{
7ae441ea
GN		 5448 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5449 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5450
5fdbf976
MT		 5451 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5452 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5453 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5454 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5455 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5456 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5457 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5458 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5459#ifdef CONFIG_X86_64
5fdbf976
MT		 5460 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5461 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5462 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5463 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5464 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5465 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5466 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5467 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5468#endif
5469
5fdbf976 5470 kvm_rip_write(vcpu, regs->rip);
91586a3b 5471 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5472
b4f14abd
JK		 5473 vcpu->arch.exception.pending = false;
5474
3842d135
AK		 5475 kvm_make_request(KVM_REQ_EVENT, vcpu);
5476
b6c7a5dc
HB		 5477 return 0;
5478}
5479
b6c7a5dc
HB		 5480void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5481{
5482 struct kvm_segment cs;
5483
3e6e0aab 5484 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5485 *db = cs.db;
5486 *l = cs.l;
5487}
5488EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5489
5490int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5491 struct kvm_sregs *sregs)
5492{
89a27f4d 5493 struct desc_ptr dt;
b6c7a5dc 5494
3e6e0aab
GT		 5495 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5496 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5497 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5498 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5499 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5500 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5501
3e6e0aab
GT		 5502 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5503 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5504
5505 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5506 sregs->idt.limit = dt.size;
5507 sregs->idt.base = dt.address;
b6c7a5dc 5508 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5509 sregs->gdt.limit = dt.size;
5510 sregs->gdt.base = dt.address;
b6c7a5dc 5511
4d4ec087 5512 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5513 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5514 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5515 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5516 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5517 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5518 sregs->apic_base = kvm_get_apic_base(vcpu);
5519
923c61bb 5520 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5521
36752c9b 5522 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5523 set_bit(vcpu->arch.interrupt.nr,
5524 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5525
b6c7a5dc
HB		 5526 return 0;
5527}
5528
62d9f0db
MT		 5529int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5530 struct kvm_mp_state *mp_state)
5531{
62d9f0db 5532 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5533 return 0;
5534}
5535
5536int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5537 struct kvm_mp_state *mp_state)
5538{
62d9f0db 5539 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5540 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5541 return 0;
5542}
5543
e269fb21
JK		 5544int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5545 bool has_error_code, u32 error_code)
b6c7a5dc 5546{
9d74191a 5547 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5548 int ret;
e01c2426 5549
8ec4722d 5550 init_emulate_ctxt(vcpu);
c697518a 5551
9d74191a
TY		 5552 ret = emulator_task_switch(ctxt, tss_selector, reason,
5553 has_error_code, error_code);
c697518a 5554
c697518a 5555 if (ret)
19d04437 5556 return EMULATE_FAIL;
37817f29 5557
9dac77fa 5558 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5559 kvm_rip_write(vcpu, ctxt->eip);
5560 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5561 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5562 return EMULATE_DONE;
37817f29
IE		 5563}
5564EXPORT_SYMBOL_GPL(kvm_task_switch);
5565
b6c7a5dc
HB		 5566int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5567 struct kvm_sregs *sregs)
5568{
5569 int mmu_reset_needed = 0;
63f42e02 5570 int pending_vec, max_bits, idx;
89a27f4d 5571 struct desc_ptr dt;
b6c7a5dc 5572
89a27f4d
GN		 5573 dt.size = sregs->idt.limit;
5574 dt.address = sregs->idt.base;
b6c7a5dc 5575 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5576 dt.size = sregs->gdt.limit;
5577 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5578 kvm_x86_ops->set_gdt(vcpu, &dt);
5579
ad312c7c 5580 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5581 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5582 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5583 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5584
2d3ad1f4 5585 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5586
f6801dff 5587 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5588 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5589 kvm_set_apic_base(vcpu, sregs->apic_base);
5590
4d4ec087 5591 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5592 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5593 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5594
fc78f519 5595 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5596 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5597 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5598 kvm_update_cpuid(vcpu);
63f42e02
XG		 5599
5600 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5601 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5602 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5603 mmu_reset_needed = 1;
5604 }
63f42e02 5605 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5606
5607 if (mmu_reset_needed)
5608 kvm_mmu_reset_context(vcpu);
5609
923c61bb
GN		 5610 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5611 pending_vec = find_first_bit(
5612 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5613 if (pending_vec < max_bits) {
66fd3f7f 5614 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5615 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5616 }
5617
3e6e0aab
GT		 5618 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5619 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5620 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5621 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5622 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5623 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5624
3e6e0aab
GT		 5625 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5626 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5627
5f0269f5
ME		 5628 update_cr8_intercept(vcpu);
5629
9c3e4aab 5630 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5631 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5632 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5633 !is_protmode(vcpu))
9c3e4aab
MT		 5634 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5635
3842d135
AK		 5636 kvm_make_request(KVM_REQ_EVENT, vcpu);
5637
b6c7a5dc
HB		 5638 return 0;
5639}
5640
d0bfb940
JK		 5641int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5642 struct kvm_guest_debug *dbg)
b6c7a5dc 5643{
355be0b9 5644 unsigned long rflags;
ae675ef0 5645 int i, r;
b6c7a5dc 5646
4f926bf2
JK		 5647 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5648 r = -EBUSY;
5649 if (vcpu->arch.exception.pending)
2122ff5e 5650 goto out;
4f926bf2
JK		 5651 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5652 kvm_queue_exception(vcpu, DB_VECTOR);
5653 else
5654 kvm_queue_exception(vcpu, BP_VECTOR);
5655 }
5656
91586a3b
JK		 5657 /*
5658 * Read rflags as long as potentially injected trace flags are still
5659 * filtered out.
5660 */
5661 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5662
5663 vcpu->guest_debug = dbg->control;
5664 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5665 vcpu->guest_debug = 0;
5666
5667 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5668 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5669 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5670 vcpu->arch.switch_db_regs =
5671 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5672 } else {
5673 for (i = 0; i < KVM_NR_DB_REGS; i++)
5674 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5675 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5676 }
5677
f92653ee
JK		 5678 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5679 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5680 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5681
91586a3b
JK		 5682 /*
5683 * Trigger an rflags update that will inject or remove the trace
5684 * flags.
5685 */
5686 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5687
355be0b9 5688 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5689
4f926bf2 5690 r = 0;
d0bfb940 5691
2122ff5e 5692out:
b6c7a5dc
HB		 5693
5694 return r;
5695}
5696
8b006791
ZX		 5697/*
5698 * Translate a guest virtual address to a guest physical address.
5699 */
5700int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5701 struct kvm_translation *tr)
5702{
5703 unsigned long vaddr = tr->linear_address;
5704 gpa_t gpa;
f656ce01 5705 int idx;
8b006791 5706
f656ce01 5707 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5708 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5709 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5710 tr->physical_address = gpa;
5711 tr->valid = gpa != UNMAPPED_GVA;
5712 tr->writeable = 1;
5713 tr->usermode = 0;
8b006791
ZX		 5714
5715 return 0;
5716}
5717
d0752060
HB		 5718int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5719{
98918833
SY		 5720 struct i387_fxsave_struct *fxsave =
5721 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5722
d0752060
HB		 5723 memcpy(fpu->fpr, fxsave->st_space, 128);
5724 fpu->fcw = fxsave->cwd;
5725 fpu->fsw = fxsave->swd;
5726 fpu->ftwx = fxsave->twd;
5727 fpu->last_opcode = fxsave->fop;
5728 fpu->last_ip = fxsave->rip;
5729 fpu->last_dp = fxsave->rdp;
5730 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5731
d0752060
HB		 5732 return 0;
5733}
5734
5735int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5736{
98918833
SY		 5737 struct i387_fxsave_struct *fxsave =
5738 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5739
d0752060
HB		 5740 memcpy(fxsave->st_space, fpu->fpr, 128);
5741 fxsave->cwd = fpu->fcw;
5742 fxsave->swd = fpu->fsw;
5743 fxsave->twd = fpu->ftwx;
5744 fxsave->fop = fpu->last_opcode;
5745 fxsave->rip = fpu->last_ip;
5746 fxsave->rdp = fpu->last_dp;
5747 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5748
d0752060
HB		 5749 return 0;
5750}
5751
10ab25cd 5752int fx_init(struct kvm_vcpu *vcpu)
d0752060 5753{
10ab25cd
JK		 5754 int err;
5755
5756 err = fpu_alloc(&vcpu->arch.guest_fpu);
5757 if (err)
5758 return err;
5759
98918833 5760 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5761
2acf923e
DC		 5762 /*
5763 * Ensure guest xcr0 is valid for loading
5764 */
5765 vcpu->arch.xcr0 = XSTATE_FP;
5766
ad312c7c 5767 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5768
5769 return 0;
d0752060
HB		 5770}
5771EXPORT_SYMBOL_GPL(fx_init);
5772
98918833
SY		 5773static void fx_free(struct kvm_vcpu *vcpu)
5774{
5775 fpu_free(&vcpu->arch.guest_fpu);
5776}
5777
d0752060
HB		 5778void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5779{
2608d7a1 5780 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5781 return;
5782
2acf923e
DC		 5783 /*
5784 * Restore all possible states in the guest,
5785 * and assume host would use all available bits.
5786 * Guest xcr0 would be loaded later.
5787 */
5788 kvm_put_guest_xcr0(vcpu);
d0752060 5789 vcpu->guest_fpu_loaded = 1;
7cf30855 5790 unlazy_fpu(current);
98918833 5791 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5792 trace_kvm_fpu(1);
d0752060 5793}
d0752060
HB		 5794
5795void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5796{
2acf923e
DC		 5797 kvm_put_guest_xcr0(vcpu);
5798
d0752060
HB		 5799 if (!vcpu->guest_fpu_loaded)
5800 return;
5801
5802 vcpu->guest_fpu_loaded = 0;
98918833 5803 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5804 ++vcpu->stat.fpu_reload;
a8eeb04a 5805 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5806 trace_kvm_fpu(0);
d0752060 5807}
e9b11c17
ZX		 5808
5809void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5810{
12f9a48f 5811 kvmclock_reset(vcpu);
7f1ea208 5812
f5f48ee1 5813 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5814 fx_free(vcpu);
e9b11c17
ZX		 5815 kvm_x86_ops->vcpu_free(vcpu);
5816}
5817
5818struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5819 unsigned int id)
5820{
6755bae8
ZA		 5821 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5822 printk_once(KERN_WARNING
5823 "kvm: SMP vm created on host with unstable TSC; "
5824 "guest TSC will not be reliable\n");
26e5215f
AK		 5825 return kvm_x86_ops->vcpu_create(kvm, id);
5826}
e9b11c17 5827
26e5215f
AK		 5828int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5829{
5830 int r;
e9b11c17 5831
0bed3b56 5832 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5833 vcpu_load(vcpu);
5834 r = kvm_arch_vcpu_reset(vcpu);
5835 if (r == 0)
5836 r = kvm_mmu_setup(vcpu);
5837 vcpu_put(vcpu);
e9b11c17 5838
26e5215f 5839 return r;
e9b11c17
ZX		 5840}
5841
d40ccc62 5842void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5843{
344d9588
GN		 5844 vcpu->arch.apf.msr_val = 0;
5845
e9b11c17
ZX		 5846 vcpu_load(vcpu);
5847 kvm_mmu_unload(vcpu);
5848 vcpu_put(vcpu);
5849
98918833 5850 fx_free(vcpu);
e9b11c17
ZX		 5851 kvm_x86_ops->vcpu_free(vcpu);
5852}
5853
5854int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5855{
7460fb4a
AK		 5856 atomic_set(&vcpu->arch.nmi_queued, 0);
5857 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5858 vcpu->arch.nmi_injected = false;
5859
42dbaa5a
JK		 5860 vcpu->arch.switch_db_regs = 0;
5861 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5862 vcpu->arch.dr6 = DR6_FIXED_1;
5863 vcpu->arch.dr7 = DR7_FIXED_1;
5864
3842d135 5865 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5866 vcpu->arch.apf.msr_val = 0;
c9aaa895 5867 vcpu->arch.st.msr_val = 0;
3842d135 5868
12f9a48f
GC		 5869 kvmclock_reset(vcpu);
5870
af585b92
GN		 5871 kvm_clear_async_pf_completion_queue(vcpu);
5872 kvm_async_pf_hash_reset(vcpu);
5873 vcpu->arch.apf.halted = false;
3842d135 5874
f5132b01
GN		 5875 kvm_pmu_reset(vcpu);
5876
e9b11c17
ZX		 5877 return kvm_x86_ops->vcpu_reset(vcpu);
5878}
5879
10474ae8 5880int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5881{
ca84d1a2
ZA		 5882 struct kvm *kvm;
5883 struct kvm_vcpu *vcpu;
5884 int i;
18863bdd
AK		 5885
5886 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5887 list_for_each_entry(kvm, &vm_list, vm_list)
5888 kvm_for_each_vcpu(i, vcpu, kvm)
5889 if (vcpu->cpu == smp_processor_id())
c285545f 5890 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5891 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5892}
5893
5894void kvm_arch_hardware_disable(void *garbage)
5895{
5896 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5897 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5898}
5899
5900int kvm_arch_hardware_setup(void)
5901{
5902 return kvm_x86_ops->hardware_setup();
5903}
5904
5905void kvm_arch_hardware_unsetup(void)
5906{
5907 kvm_x86_ops->hardware_unsetup();
5908}
5909
5910void kvm_arch_check_processor_compat(void *rtn)
5911{
5912 kvm_x86_ops->check_processor_compatibility(rtn);
5913}
5914
5915int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5916{
5917 struct page *page;
5918 struct kvm *kvm;
5919 int r;
5920
5921 BUG_ON(vcpu->kvm == NULL);
5922 kvm = vcpu->kvm;
5923
9aabc88f 5924 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 5925 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5926 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5927 else
a4535290 5928 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5929
5930 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5931 if (!page) {
5932 r = -ENOMEM;
5933 goto fail;
5934 }
ad312c7c 5935 vcpu->arch.pio_data = page_address(page);
e9b11c17 5936
1e993611 5937 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 5938
e9b11c17
ZX		 5939 r = kvm_mmu_create(vcpu);
5940 if (r < 0)
5941 goto fail_free_pio_data;
5942
5943 if (irqchip_in_kernel(kvm)) {
5944 r = kvm_create_lapic(vcpu);
5945 if (r < 0)
5946 goto fail_mmu_destroy;
5947 }
5948
890ca9ae
HY		 5949 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5950 GFP_KERNEL);
5951 if (!vcpu->arch.mce_banks) {
5952 r = -ENOMEM;
443c39bc 5953 goto fail_free_lapic;
890ca9ae
HY		 5954 }
5955 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5956
f5f48ee1
SY		 5957 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5958 goto fail_free_mce_banks;
5959
af585b92 5960 kvm_async_pf_hash_reset(vcpu);
f5132b01 5961 kvm_pmu_init(vcpu);
af585b92 5962
e9b11c17 5963 return 0;
f5f48ee1
SY		 5964fail_free_mce_banks:
5965 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5966fail_free_lapic:
5967 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5968fail_mmu_destroy:
5969 kvm_mmu_destroy(vcpu);
5970fail_free_pio_data:
ad312c7c 5971 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5972fail:
5973 return r;
5974}
5975
5976void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5977{
f656ce01
MT		 5978 int idx;
5979
f5132b01 5980 kvm_pmu_destroy(vcpu);
36cb93fd 5981 kfree(vcpu->arch.mce_banks);
e9b11c17 5982 kvm_free_lapic(vcpu);
f656ce01 5983 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5984 kvm_mmu_destroy(vcpu);
f656ce01 5985 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5986 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5987}
d19a9cd2 5988
d89f5eff 5989int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5990{
f05e70ac 5991 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5992 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5993
5550af4d
SY		 5994 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5995 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5996
038f8c11 5997 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 5998
d89f5eff 5999 return 0;
d19a9cd2
ZX		 6000}
6001
6002static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6003{
6004 vcpu_load(vcpu);
6005 kvm_mmu_unload(vcpu);
6006 vcpu_put(vcpu);
6007}
6008
6009static void kvm_free_vcpus(struct kvm *kvm)
6010{
6011 unsigned int i;
988a2cae 6012 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6013
6014 /*
6015 * Unpin any mmu pages first.
6016 */
af585b92
GN		 6017 kvm_for_each_vcpu(i, vcpu, kvm) {
6018 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6019 kvm_unload_vcpu_mmu(vcpu);
af585b92 6020 }
988a2cae
GN		 6021 kvm_for_each_vcpu(i, vcpu, kvm)
6022 kvm_arch_vcpu_free(vcpu);
6023
6024 mutex_lock(&kvm->lock);
6025 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6026 kvm->vcpus[i] = NULL;
d19a9cd2 6027
988a2cae
GN		 6028 atomic_set(&kvm->online_vcpus, 0);
6029 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6030}
6031
ad8ba2cd
SY		 6032void kvm_arch_sync_events(struct kvm *kvm)
6033{
ba4cef31 6034 kvm_free_all_assigned_devices(kvm);
aea924f6 6035 kvm_free_pit(kvm);
ad8ba2cd
SY		 6036}
6037
d19a9cd2
ZX		 6038void kvm_arch_destroy_vm(struct kvm *kvm)
6039{
6eb55818 6040 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6041 kfree(kvm->arch.vpic);
6042 kfree(kvm->arch.vioapic);
d19a9cd2 6043 kvm_free_vcpus(kvm);
3d45830c
AK		 6044 if (kvm->arch.apic_access_page)
6045 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6046 if (kvm->arch.ept_identity_pagetable)
6047 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6048}
0de10343 6049
f7784b8e
MT		 6050int kvm_arch_prepare_memory_region(struct kvm *kvm,
6051 struct kvm_memory_slot *memslot,
0de10343 6052 struct kvm_memory_slot old,
f7784b8e 6053 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6054 int user_alloc)
6055{
f7784b8e 6056 int npages = memslot->npages;
7ac77099
AK		 6057 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6058
6059 /* Prevent internal slot pages from being moved by fork()/COW. */
6060 if (memslot->id >= KVM_MEMORY_SLOTS)
6061 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6062
6063 /*To keep backward compatibility with older userspace,
6064 *x86 needs to hanlde !user_alloc case.
6065 */
6066 if (!user_alloc) {
6067 if (npages && !old.rmap) {
604b38ac
AA		 6068 unsigned long userspace_addr;
6069
72dc67a6 6070 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6071 userspace_addr = do_mmap(NULL, 0,
6072 npages * PAGE_SIZE,
6073 PROT_READ | PROT_WRITE,
7ac77099 6074 map_flags,
604b38ac 6075 0);
72dc67a6 6076 up_write(&current->mm->mmap_sem);
0de10343 6077
604b38ac
AA		 6078 if (IS_ERR((void *)userspace_addr))
6079 return PTR_ERR((void *)userspace_addr);
6080
604b38ac 6081 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6082 }
6083 }
6084
f7784b8e
MT		 6085
6086 return 0;
6087}
6088
6089void kvm_arch_commit_memory_region(struct kvm *kvm,
6090 struct kvm_userspace_memory_region *mem,
6091 struct kvm_memory_slot old,
6092 int user_alloc)
6093{
6094
48c0e4e9 6095 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6096
6097 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6098 int ret;
6099
6100 down_write(&current->mm->mmap_sem);
6101 ret = do_munmap(current->mm, old.userspace_addr,
6102 old.npages * PAGE_SIZE);
6103 up_write(&current->mm->mmap_sem);
6104 if (ret < 0)
6105 printk(KERN_WARNING
6106 "kvm_vm_ioctl_set_memory_region: "
6107 "failed to munmap memory\n");
6108 }
6109
48c0e4e9
XG		 6110 if (!kvm->arch.n_requested_mmu_pages)
6111 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6112
7c8a83b7 6113 spin_lock(&kvm->mmu_lock);
48c0e4e9 6114 if (nr_mmu_pages)
0de10343 6115 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6116 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6117 spin_unlock(&kvm->mmu_lock);
0de10343 6118}
1d737c8a 6119
34d4cb8f
MT		 6120void kvm_arch_flush_shadow(struct kvm *kvm)
6121{
6122 kvm_mmu_zap_all(kvm);
8986ecc0 6123 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6124}
6125
1d737c8a
ZX		 6126int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6127{
af585b92
GN		 6128 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6129 !vcpu->arch.apf.halted)
6130 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6131 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6132 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6133 (kvm_arch_interrupt_allowed(vcpu) &&
6134 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6135}
5736199a 6136
5736199a
ZX		 6137void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6138{
32f88400
MT		 6139 int me;
6140 int cpu = vcpu->cpu;
5736199a
ZX		 6141
6142 if (waitqueue_active(&vcpu->wq)) {
6143 wake_up_interruptible(&vcpu->wq);
6144 ++vcpu->stat.halt_wakeup;
6145 }
32f88400
MT		 6146
6147 me = get_cpu();
6148 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6149 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6150 smp_send_reschedule(cpu);
e9571ed5 6151 put_cpu();
5736199a 6152}
78646121
GN		 6153
6154int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6155{
6156 return kvm_x86_ops->interrupt_allowed(vcpu);
6157}
229456fc 6158
f92653ee
JK		 6159bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6160{
6161 unsigned long current_rip = kvm_rip_read(vcpu) +
6162 get_segment_base(vcpu, VCPU_SREG_CS);
6163
6164 return current_rip == linear_rip;
6165}
6166EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6167
94fe45da
JK		 6168unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6169{
6170 unsigned long rflags;
6171
6172 rflags = kvm_x86_ops->get_rflags(vcpu);
6173 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6174 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6175 return rflags;
6176}
6177EXPORT_SYMBOL_GPL(kvm_get_rflags);
6178
6179void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6180{
6181 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6182 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6183 rflags |= X86_EFLAGS_TF;
94fe45da 6184 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6185 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6186}
6187EXPORT_SYMBOL_GPL(kvm_set_rflags);
6188
56028d08
GN		 6189void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6190{
6191 int r;
6192
fb67e14f 6193 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6194 is_error_page(work->page))
56028d08
GN		 6195 return;
6196
6197 r = kvm_mmu_reload(vcpu);
6198 if (unlikely(r))
6199 return;
6200
fb67e14f
XG		 6201 if (!vcpu->arch.mmu.direct_map &&
6202 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6203 return;
6204
56028d08
GN		 6205 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6206}
6207
af585b92
GN		 6208static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6209{
6210 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6211}
6212
6213static inline u32 kvm_async_pf_next_probe(u32 key)
6214{
6215 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6216}
6217
6218static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6219{
6220 u32 key = kvm_async_pf_hash_fn(gfn);
6221
6222 while (vcpu->arch.apf.gfns[key] != ~0)
6223 key = kvm_async_pf_next_probe(key);
6224
6225 vcpu->arch.apf.gfns[key] = gfn;
6226}
6227
6228static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6229{
6230 int i;
6231 u32 key = kvm_async_pf_hash_fn(gfn);
6232
6233 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6234 (vcpu->arch.apf.gfns[key] != gfn &&
6235 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6236 key = kvm_async_pf_next_probe(key);
6237
6238 return key;
6239}
6240
6241bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6242{
6243 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6244}
6245
6246static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6247{
6248 u32 i, j, k;
6249
6250 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6251 while (true) {
6252 vcpu->arch.apf.gfns[i] = ~0;
6253 do {
6254 j = kvm_async_pf_next_probe(j);
6255 if (vcpu->arch.apf.gfns[j] == ~0)
6256 return;
6257 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6258 /*
6259 * k lies cyclically in ]i,j]
6260 * | i.k.j |
6261 * |....j i.k.| or |.k..j i...|
6262 */
6263 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6264 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6265 i = j;
6266 }
6267}
6268
7c90705b
GN		 6269static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6270{
6271
6272 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6273 sizeof(val));
6274}
6275
af585b92
GN		 6276void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6277 struct kvm_async_pf *work)
6278{
6389ee94
AK		 6279 struct x86_exception fault;
6280
7c90705b 6281 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6282 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6283
6284 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6285 (vcpu->arch.apf.send_user_only &&
6286 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6287 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6288 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6289 fault.vector = PF_VECTOR;
6290 fault.error_code_valid = true;
6291 fault.error_code = 0;
6292 fault.nested_page_fault = false;
6293 fault.address = work->arch.token;
6294 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6295 }
af585b92
GN		 6296}
6297
6298void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6299 struct kvm_async_pf *work)
6300{
6389ee94
AK		 6301 struct x86_exception fault;
6302
7c90705b
GN		 6303 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6304 if (is_error_page(work->page))
6305 work->arch.token = ~0; /* broadcast wakeup */
6306 else
6307 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6308
6309 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6310 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6311 fault.vector = PF_VECTOR;
6312 fault.error_code_valid = true;
6313 fault.error_code = 0;
6314 fault.nested_page_fault = false;
6315 fault.address = work->arch.token;
6316 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6317 }
e6d53e3b 6318 vcpu->arch.apf.halted = false;
7c90705b
GN		 6319}
6320
6321bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6322{
6323 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6324 return true;
6325 else
6326 return !kvm_event_needs_reinjection(vcpu) &&
6327 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6328}
6329
229456fc
MT		 6330EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6331EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6332EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6333EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6334EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6335EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6336EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6337EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6338EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6339EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6340EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6341EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git