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KVM: nVMX: Implement reading and writing of VMX MSRs
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 349}
350
6389ee94 351void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 352{
6389ee94
AK		 353 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
354 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 355 else
6389ee94 356 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 357}
358
3419ffc8
SY		 359void kvm_inject_nmi(struct kvm_vcpu *vcpu)
360{
3842d135 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 362 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 363}
364EXPORT_SYMBOL_GPL(kvm_inject_nmi);
365
298101da
AK		 366void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
ce7ddec4 368 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 369}
370EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
371
ce7ddec4
JR		 372void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
373{
374 kvm_multiple_exception(vcpu, nr, true, error_code, true);
375}
376EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
377
0a79b009
AK		 378/*
379 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
380 * a #GP and return false.
381 */
382bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 383{
0a79b009
AK		 384 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
385 return true;
386 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
387 return false;
298101da 388}
0a79b009 389EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 390
ec92fe44
JR		 391/*
392 * This function will be used to read from the physical memory of the currently
393 * running guest. The difference to kvm_read_guest_page is that this function
394 * can read from guest physical or from the guest's guest physical memory.
395 */
396int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
397 gfn_t ngfn, void *data, int offset, int len,
398 u32 access)
399{
400 gfn_t real_gfn;
401 gpa_t ngpa;
402
403 ngpa = gfn_to_gpa(ngfn);
404 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
405 if (real_gfn == UNMAPPED_GVA)
406 return -EFAULT;
407
408 real_gfn = gpa_to_gfn(real_gfn);
409
410 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
411}
412EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
413
3d06b8bf
JR		 414int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
415 void *data, int offset, int len, u32 access)
416{
417 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
418 data, offset, len, access);
419}
420
a03490ed
CO		 421/*
422 * Load the pae pdptrs. Return true is they are all valid.
423 */
ff03a073 424int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 425{
426 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
427 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
428 int i;
429 int ret;
ff03a073 430 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 431
ff03a073
JR		 432 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
433 offset * sizeof(u64), sizeof(pdpte),
434 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 435 if (ret < 0) {
436 ret = 0;
437 goto out;
438 }
439 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 440 if (is_present_gpte(pdpte[i]) &&
20c466b5 441 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 442 ret = 0;
443 goto out;
444 }
445 }
446 ret = 1;
447
ff03a073 448 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 449 __set_bit(VCPU_EXREG_PDPTR,
450 (unsigned long *)&vcpu->arch.regs_avail);
451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 453out:
a03490ed
CO		 454
455 return ret;
456}
cc4b6871 457EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 458
d835dfec
AK		 459static bool pdptrs_changed(struct kvm_vcpu *vcpu)
460{
ff03a073 461 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 462 bool changed = true;
3d06b8bf
JR		 463 int offset;
464 gfn_t gfn;
d835dfec
AK		 465 int r;
466
467 if (is_long_mode(vcpu) || !is_pae(vcpu))
468 return false;
469
6de4f3ad
AK		 470 if (!test_bit(VCPU_EXREG_PDPTR,
471 (unsigned long *)&vcpu->arch.regs_avail))
472 return true;
473
9f8fe504
AK		 474 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
475 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 476 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
477 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 478 if (r < 0)
479 goto out;
ff03a073 480 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 481out:
d835dfec
AK		 482
483 return changed;
484}
485
49a9b07e 486int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 487{
aad82703
SY		 488 unsigned long old_cr0 = kvm_read_cr0(vcpu);
489 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
490 X86_CR0_CD | X86_CR0_NW;
491
f9a48e6a
AK		 492 cr0 |= X86_CR0_ET;
493
ab344828 494#ifdef CONFIG_X86_64
0f12244f
GN		 495 if (cr0 & 0xffffffff00000000UL)
496 return 1;
ab344828
GN		 497#endif
498
499 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
502 return 1;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
505 return 1;
a03490ed
CO		 506
507 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
508#ifdef CONFIG_X86_64
f6801dff 509 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 510 int cs_db, cs_l;
511
0f12244f
GN		 512 if (!is_pae(vcpu))
513 return 1;
a03490ed 514 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 515 if (cs_l)
516 return 1;
a03490ed
CO		 517 } else
518#endif
ff03a073 519 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 520 kvm_read_cr3(vcpu)))
0f12244f 521 return 1;
a03490ed
CO		 522 }
523
524 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 525
d170c419 526 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 527 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 528 kvm_async_pf_hash_reset(vcpu);
529 }
e5f3f027 530
aad82703
SY		 531 if ((cr0 ^ old_cr0) & update_bits)
532 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 533 return 0;
534}
2d3ad1f4 535EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 536
2d3ad1f4 537void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 538{
49a9b07e 539 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 542
2acf923e
DC		 543int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
544{
545 u64 xcr0;
546
547 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
548 if (index != XCR_XFEATURE_ENABLED_MASK)
549 return 1;
550 xcr0 = xcr;
551 if (kvm_x86_ops->get_cpl(vcpu) != 0)
552 return 1;
553 if (!(xcr0 & XSTATE_FP))
554 return 1;
555 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
556 return 1;
557 if (xcr0 & ~host_xcr0)
558 return 1;
559 vcpu->arch.xcr0 = xcr0;
560 vcpu->guest_xcr0_loaded = 0;
561 return 0;
562}
563
564int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
565{
566 if (__kvm_set_xcr(vcpu, index, xcr)) {
567 kvm_inject_gp(vcpu, 0);
568 return 1;
569 }
570 return 0;
571}
572EXPORT_SYMBOL_GPL(kvm_set_xcr);
573
574static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
580}
581
582static void update_cpuid(struct kvm_vcpu *vcpu)
583{
584 struct kvm_cpuid_entry2 *best;
585
586 best = kvm_find_cpuid_entry(vcpu, 1, 0);
587 if (!best)
588 return;
589
590 /* Update OSXSAVE bit */
591 if (cpu_has_xsave && best->function == 0x1) {
592 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
593 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
594 best->ecx |= bit(X86_FEATURE_OSXSAVE);
595 }
596}
597
a83b29c6 598int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 599{
fc78f519 600 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 601 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
602
0f12244f
GN		 603 if (cr4 & CR4_RESERVED_BITS)
604 return 1;
a03490ed 605
2acf923e
DC		 606 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
607 return 1;
608
a03490ed 609 if (is_long_mode(vcpu)) {
0f12244f
GN		 610 if (!(cr4 & X86_CR4_PAE))
611 return 1;
a2edf57f
AK		 612 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
613 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 614 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
615 kvm_read_cr3(vcpu)))
0f12244f
GN		 616 return 1;
617
5e1746d6 618 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 619 return 1;
a03490ed 620
aad82703
SY		 621 if ((cr4 ^ old_cr4) & pdptr_bits)
622 kvm_mmu_reset_context(vcpu);
0f12244f 623
2acf923e
DC		 624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
625 update_cpuid(vcpu);
626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 630
2390218b 631int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 632{
9f8fe504 633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 634 kvm_mmu_sync_roots(vcpu);
d835dfec 635 kvm_mmu_flush_tlb(vcpu);
0f12244f 636 return 0;
d835dfec
AK		 637 }
638
a03490ed 639 if (is_long_mode(vcpu)) {
0f12244f
GN		 640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
a03490ed
CO		 642 } else {
643 if (is_pae(vcpu)) {
0f12244f
GN		 644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
ff03a073
JR		 646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 648 return 1;
a03490ed
CO		 649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
a03490ed
CO		 656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 666 return 1;
667 vcpu->arch.cr3 = cr3;
aff48baa 668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 673
eea1cff9 674int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 675{
0f12244f
GN		 676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
a03490ed
CO		 678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
ad312c7c 681 vcpu->arch.cr8 = cr8;
0f12244f
GN		 682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 685
2d3ad1f4 686unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 687{
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
ad312c7c 691 return vcpu->arch.cr8;
a03490ed 692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 694
338dbc97 695static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 696{
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 case 6:
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
338dbc97
GN		 713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
020df079
GN		 715 /* fall through */
716 default: /* 7 */
338dbc97
GN		 717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
020df079
GN		 719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728}
338dbc97
GN		 729
730int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731{
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741}
020df079
GN		 742EXPORT_SYMBOL_GPL(kvm_set_dr);
743
338dbc97 744static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 745{
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
338dbc97 751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 752 return 1;
020df079
GN		 753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
338dbc97 758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 759 return 1;
020df079
GN		 760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770{
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776}
020df079
GN		 777EXPORT_SYMBOL_GPL(kvm_get_dr);
778
043405e1
CO		 779/*
780 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
781 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
782 *
783 * This list is modified at module load time to reflect the
e3267cbb
GC		 784 * capabilities of the host cpu. This capabilities test skips MSRs that are
785 * kvm-specific. Those are put in the beginning of the list.
043405e1 786 */
e3267cbb 787
344d9588 788#define KVM_SAVE_MSRS_BEGIN 8
043405e1 789static u32 msrs_to_save[] = {
e3267cbb 790 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 791 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 792 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 793 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 794 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 795 MSR_STAR,
043405e1
CO		 796#ifdef CONFIG_X86_64
797 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
798#endif
e90aa41e 799 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 800};
801
802static unsigned num_msrs_to_save;
803
804static u32 emulated_msrs[] = {
805 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
043405e1
CO		 808};
809
b69e8cae 810static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 811{
aad82703
SY		 812 u64 old_efer = vcpu->arch.efer;
813
b69e8cae
RJ		 814 if (efer & efer_reserved_bits)
815 return 1;
15c4a640
CO		 816
817 if (is_paging(vcpu)
b69e8cae
RJ		 818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
15c4a640 820
1b2fd70c
AG		 821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
1b2fd70c
AG		 827 }
828
d8017474
AG		 829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
d8017474
AG		 835 }
836
15c4a640 837 efer &= ~EFER_LMA;
f6801dff 838 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 839
a3d204e2
SY		 840 kvm_x86_ops->set_efer(vcpu, efer);
841
9645bb56 842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 843
aad82703
SY		 844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
b69e8cae 848 return 0;
15c4a640
CO		 849}
850
f2b4b7dd
JR		 851void kvm_enable_efer_bits(u64 mask)
852{
853 efer_reserved_bits &= ~mask;
854}
855EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
15c4a640
CO		 858/*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864{
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866}
867
313a3dc7
CO		 868/*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872{
873 return kvm_set_msr(vcpu, index, *data);
874}
875
18068523
GOC		 876static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877{
9ed3c444
AK		 878 int version;
879 int r;
50d0a0f9 880 struct pvclock_wall_clock wc;
923de3cf 881 struct timespec boot;
18068523
GOC		 882
883 if (!wall_clock)
884 return;
885
9ed3c444
AK		 886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
18068523 894
18068523
GOC		 895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
50d0a0f9
GH		 897 /*
898 * The guest calculates current wall clock time by adding
34c238a1 899 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
923de3cf 903 getboottime(&boot);
50d0a0f9
GH		 904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
18068523
GOC		 908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 913}
914
50d0a0f9
GH		 915static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916{
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925}
926
5f4e3f88
ZA		 927static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
50d0a0f9 929{
5f4e3f88 930 uint64_t scaled64;
50d0a0f9
GH		 931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
5f4e3f88
ZA		 935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
50933623 937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
50933623
JK		 943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
50d0a0f9
GH		 948 shift++;
949 }
950
5f4e3f88
ZA		 951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 953
5f4e3f88
ZA		 954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 956}
957
759379dd
ZA		 958static inline u64 get_kernel_ns(void)
959{
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
50d0a0f9
GH		 966}
967
c8076604 968static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 969unsigned long max_tsc_khz;
c8076604 970
8cfdc000
ZA		 971static inline int kvm_tsc_changes_freq(void)
972{
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978}
979
1e993611
JR		 980static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
981{
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
984 else
985 return __this_cpu_read(cpu_tsc_khz);
986}
987
857e4099 988static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 989{
217fc9cf
AK		 990 u64 ret;
991
759379dd
ZA		 992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 996 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 997 do_div(ret, USEC_PER_SEC);
998 return ret;
759379dd
ZA		 999}
1000
1e993611 1001static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1002{
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1007}
1008
1009static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1010{
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1014 tsc += vcpu->arch.last_tsc_write;
1015 return tsc;
1016}
1017
99e3e30a
ZA		 1018void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1019{
1020 struct kvm *kvm = vcpu->kvm;
f38e098f 1021 u64 offset, ns, elapsed;
99e3e30a 1022 unsigned long flags;
46543ba4 1023 s64 sdiff;
99e3e30a 1024
038f8c11 1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1027 ns = get_kernel_ns();
f38e098f 1028 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1029 sdiff = data - kvm->arch.last_tsc_write;
1030 if (sdiff < 0)
1031 sdiff = -sdiff;
f38e098f
ZA		 1032
1033 /*
46543ba4 1034 * Special case: close write to TSC within 5 seconds of
f38e098f 1035 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1036 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1037 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1038 *
1039 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1040 * or make a best guest using elapsed value.
f38e098f 1041 */
857e4099 1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1043 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1047 } else {
857e4099 1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1049 offset += delta;
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1051 }
1052 ns = kvm->arch.last_tsc_nsec;
1053 }
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
99e3e30a 1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1059
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1064}
1065EXPORT_SYMBOL_GPL(kvm_write_tsc);
1066
34c238a1 1067static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1068{
18068523
GOC		 1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1071 void *shared_kaddr;
463656c0 1072 unsigned long this_tsc_khz;
1d5f066e
ZA		 1073 s64 kernel_ns, max_kernel_ns;
1074 u64 tsc_timestamp;
18068523 1075
18068523
GOC		 1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
1d5f066e 1078 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1079 kernel_ns = get_kernel_ns();
1e993611 1080 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1081 if (unlikely(this_tsc_khz == 0)) {
c285545f 1082 local_irq_restore(flags);
34c238a1 1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1084 return 1;
1085 }
18068523 1086
c285545f
ZA		 1087 /*
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1095 * very slowly.
1096 */
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1102 }
50d0a0f9
GH		 1103 }
1104
18068523
GOC		 1105 local_irq_restore(flags);
1106
c285545f
ZA		 1107 if (!vcpu->time_page)
1108 return 0;
18068523 1109
1d5f066e
ZA		 1110 /*
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1123 *
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1125 *
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1130 */
1131 max_kernel_ns = 0;
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1139 }
afbcf7ab 1140
e48672fa 1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1145 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1146 }
1147
1d5f066e
ZA		 1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1150
8cfdc000 1151 /* With all the info we got, fill in the values */
1d5f066e 1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1154 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1155 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1156 vcpu->hv_clock.flags = 0;
1157
18068523
GOC		 1158 /*
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1161 * state, we just increase by 2 at the end.
18068523 1162 */
50d0a0f9 1163 vcpu->hv_clock.version += 2;
18068523
GOC		 1164
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1166
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1168 sizeof(vcpu->hv_clock));
18068523
GOC		 1169
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1171
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1173 return 0;
c8076604
GH		 1174}
1175
9ba075a6
AK		 1176static bool msr_mtrr_valid(unsigned msr)
1177{
1178 switch (msr) {
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1193 return true;
1194 case 0x2f8:
1195 return true;
1196 }
1197 return false;
1198}
1199
d6289b93
MT		 1200static bool valid_pat_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1203}
1204
1205static bool valid_mtrr_type(unsigned t)
1206{
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1208}
1209
1210static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1211{
1212 int i;
1213
1214 if (!msr_mtrr_valid(msr))
1215 return false;
1216
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 } else if (msr == MSR_MTRRdefType) {
1223 if (data & ~0xcff)
1224 return false;
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1229 return false;
1230 return true;
1231 }
1232
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1235}
1236
9ba075a6
AK		 1237static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
d6289b93 1241 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1248 p[0] = data;
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pt = data;
1268 }
1269
1270 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1271 return 0;
1272}
15c4a640 1273
890ca9ae 1274static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1275{
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1278
15c4a640 1279 switch (msr) {
15c4a640 1280 case MSR_IA32_MCG_STATUS:
890ca9ae 1281 vcpu->arch.mcg_status = data;
15c4a640 1282 break;
c7ac679c 1283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 if (data != 0 && data != ~(u64)0)
1287 return -1;
1288 vcpu->arch.mcg_ctl = data;
1289 break;
1290 default:
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1298 */
890ca9ae 1299 if ((offset & 0x3) == 0 &&
114be429 1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1301 return -1;
1302 vcpu->arch.mce_banks[offset] = data;
1303 break;
1304 }
1305 return 1;
1306 }
1307 return 0;
1308}
1309
ffde22ac
ES		 1310static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1311{
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1320 u8 *page;
1321 int r;
1322
1323 r = -E2BIG;
1324 if (page_num >= blob_size)
1325 goto out;
1326 r = -ENOMEM;
1327 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1328 if (!page)
1329 goto out;
1330 r = -EFAULT;
1331 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1332 goto out_free;
1333 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1334 goto out_free;
1335 r = 0;
1336out_free:
1337 kfree(page);
1338out:
1339 return r;
1340}
1341
55cd8e5a
GN		 1342static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1343{
1344 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1345}
1346
1347static bool kvm_hv_msr_partition_wide(u32 msr)
1348{
1349 bool r = false;
1350 switch (msr) {
1351 case HV_X64_MSR_GUEST_OS_ID:
1352 case HV_X64_MSR_HYPERCALL:
1353 r = true;
1354 break;
1355 }
1356
1357 return r;
1358}
1359
1360static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1361{
1362 struct kvm *kvm = vcpu->kvm;
1363
1364 switch (msr) {
1365 case HV_X64_MSR_GUEST_OS_ID:
1366 kvm->arch.hv_guest_os_id = data;
1367 /* setting guest os id to zero disables hypercall page */
1368 if (!kvm->arch.hv_guest_os_id)
1369 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1370 break;
1371 case HV_X64_MSR_HYPERCALL: {
1372 u64 gfn;
1373 unsigned long addr;
1374 u8 instructions[4];
1375
1376 /* if guest os id is not set hypercall should remain disabled */
1377 if (!kvm->arch.hv_guest_os_id)
1378 break;
1379 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1380 kvm->arch.hv_hypercall = data;
1381 break;
1382 }
1383 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1384 addr = gfn_to_hva(kvm, gfn);
1385 if (kvm_is_error_hva(addr))
1386 return 1;
1387 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1388 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1389 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1390 return 1;
1391 kvm->arch.hv_hypercall = data;
1392 break;
1393 }
1394 default:
1395 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1396 "data 0x%llx\n", msr, data);
1397 return 1;
1398 }
1399 return 0;
1400}
1401
1402static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1403{
10388a07
GN		 1404 switch (msr) {
1405 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1406 unsigned long addr;
55cd8e5a 1407
10388a07
GN		 1408 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1409 vcpu->arch.hv_vapic = data;
1410 break;
1411 }
1412 addr = gfn_to_hva(vcpu->kvm, data >>
1413 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1414 if (kvm_is_error_hva(addr))
1415 return 1;
8b0cedff 1416 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1417 return 1;
1418 vcpu->arch.hv_vapic = data;
1419 break;
1420 }
1421 case HV_X64_MSR_EOI:
1422 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1423 case HV_X64_MSR_ICR:
1424 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1425 case HV_X64_MSR_TPR:
1426 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1427 default:
1428 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1429 "data 0x%llx\n", msr, data);
1430 return 1;
1431 }
1432
1433 return 0;
55cd8e5a
GN		 1434}
1435
344d9588
GN		 1436static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1437{
1438 gpa_t gpa = data & ~0x3f;
1439
6adba527
GN		 1440 /* Bits 2:5 are resrved, Should be zero */
1441 if (data & 0x3c)
344d9588
GN		 1442 return 1;
1443
1444 vcpu->arch.apf.msr_val = data;
1445
1446 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1447 kvm_clear_async_pf_completion_queue(vcpu);
1448 kvm_async_pf_hash_reset(vcpu);
1449 return 0;
1450 }
1451
1452 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1453 return 1;
1454
6adba527 1455 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1456 kvm_async_pf_wakeup_all(vcpu);
1457 return 0;
1458}
1459
12f9a48f
GC		 1460static void kvmclock_reset(struct kvm_vcpu *vcpu)
1461{
1462 if (vcpu->arch.time_page) {
1463 kvm_release_page_dirty(vcpu->arch.time_page);
1464 vcpu->arch.time_page = NULL;
1465 }
1466}
1467
15c4a640
CO		 1468int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1469{
1470 switch (msr) {
15c4a640 1471 case MSR_EFER:
b69e8cae 1472 return set_efer(vcpu, data);
8f1589d9
AP		 1473 case MSR_K7_HWCR:
1474 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1475 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1476 if (data != 0) {
1477 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1478 data);
1479 return 1;
1480 }
15c4a640 1481 break;
f7c6d140
AP		 1482 case MSR_FAM10H_MMIO_CONF_BASE:
1483 if (data != 0) {
1484 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1485 "0x%llx\n", data);
1486 return 1;
1487 }
15c4a640 1488 break;
c323c0e5 1489 case MSR_AMD64_NB_CFG:
c7ac679c 1490 break;
b5e2fec0
AG		 1491 case MSR_IA32_DEBUGCTLMSR:
1492 if (!data) {
1493 /* We support the non-activated case already */
1494 break;
1495 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1496 /* Values other than LBR and BTF are vendor-specific,
1497 thus reserved and should throw a #GP */
1498 return 1;
1499 }
1500 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1501 __func__, data);
1502 break;
15c4a640
CO		 1503 case MSR_IA32_UCODE_REV:
1504 case MSR_IA32_UCODE_WRITE:
61a6bd67 1505 case MSR_VM_HSAVE_PA:
6098ca93 1506 case MSR_AMD64_PATCH_LOADER:
15c4a640 1507 break;
9ba075a6
AK		 1508 case 0x200 ... 0x2ff:
1509 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1510 case MSR_IA32_APICBASE:
1511 kvm_set_apic_base(vcpu, data);
1512 break;
0105d1a5
GN		 1513 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1514 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1515 case MSR_IA32_MISC_ENABLE:
ad312c7c 1516 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1517 break;
11c6bffa 1518 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1519 case MSR_KVM_WALL_CLOCK:
1520 vcpu->kvm->arch.wall_clock = data;
1521 kvm_write_wall_clock(vcpu->kvm, data);
1522 break;
11c6bffa 1523 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1524 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1525 kvmclock_reset(vcpu);
18068523
GOC		 1526
1527 vcpu->arch.time = data;
c285545f 1528 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1529
1530 /* we verify if the enable bit is set... */
1531 if (!(data & 1))
1532 break;
1533
1534 /* ...but clean it before doing the actual write */
1535 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1536
18068523
GOC		 1537 vcpu->arch.time_page =
1538 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1539
1540 if (is_error_page(vcpu->arch.time_page)) {
1541 kvm_release_page_clean(vcpu->arch.time_page);
1542 vcpu->arch.time_page = NULL;
1543 }
18068523
GOC		 1544 break;
1545 }
344d9588
GN		 1546 case MSR_KVM_ASYNC_PF_EN:
1547 if (kvm_pv_enable_async_pf(vcpu, data))
1548 return 1;
1549 break;
890ca9ae
HY		 1550 case MSR_IA32_MCG_CTL:
1551 case MSR_IA32_MCG_STATUS:
1552 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1553 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1554
1555 /* Performance counters are not protected by a CPUID bit,
1556 * so we should check all of them in the generic path for the sake of
1557 * cross vendor migration.
1558 * Writing a zero into the event select MSRs disables them,
1559 * which we perfectly emulate ;-). Any other value should be at least
1560 * reported, some guests depend on them.
1561 */
1562 case MSR_P6_EVNTSEL0:
1563 case MSR_P6_EVNTSEL1:
1564 case MSR_K7_EVNTSEL0:
1565 case MSR_K7_EVNTSEL1:
1566 case MSR_K7_EVNTSEL2:
1567 case MSR_K7_EVNTSEL3:
1568 if (data != 0)
1569 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1570 "0x%x data 0x%llx\n", msr, data);
1571 break;
1572 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1573 * so we ignore writes to make it happy.
1574 */
1575 case MSR_P6_PERFCTR0:
1576 case MSR_P6_PERFCTR1:
1577 case MSR_K7_PERFCTR0:
1578 case MSR_K7_PERFCTR1:
1579 case MSR_K7_PERFCTR2:
1580 case MSR_K7_PERFCTR3:
1581 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1582 "0x%x data 0x%llx\n", msr, data);
1583 break;
84e0cefa
JS		 1584 case MSR_K7_CLK_CTL:
1585 /*
1586 * Ignore all writes to this no longer documented MSR.
1587 * Writes are only relevant for old K7 processors,
1588 * all pre-dating SVM, but a recommended workaround from
1589 * AMD for these chips. It is possible to speicify the
1590 * affected processor models on the command line, hence
1591 * the need to ignore the workaround.
1592 */
1593 break;
55cd8e5a
GN		 1594 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1595 if (kvm_hv_msr_partition_wide(msr)) {
1596 int r;
1597 mutex_lock(&vcpu->kvm->lock);
1598 r = set_msr_hyperv_pw(vcpu, msr, data);
1599 mutex_unlock(&vcpu->kvm->lock);
1600 return r;
1601 } else
1602 return set_msr_hyperv(vcpu, msr, data);
1603 break;
91c9c3ed 1604 case MSR_IA32_BBL_CR_CTL3:
1605 /* Drop writes to this legacy MSR -- see rdmsr
1606 * counterpart for further detail.
1607 */
1608 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1609 break;
15c4a640 1610 default:
ffde22ac
ES		 1611 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1612 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1613 if (!ignore_msrs) {
1614 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1615 msr, data);
1616 return 1;
1617 } else {
1618 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1619 msr, data);
1620 break;
1621 }
15c4a640
CO		 1622 }
1623 return 0;
1624}
1625EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1626
1627
1628/*
1629 * Reads an msr value (of 'msr_index') into 'pdata'.
1630 * Returns 0 on success, non-0 otherwise.
1631 * Assumes vcpu_load() was already called.
1632 */
1633int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1634{
1635 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1636}
1637
9ba075a6
AK		 1638static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1639{
0bed3b56
SY		 1640 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1641
9ba075a6
AK		 1642 if (!msr_mtrr_valid(msr))
1643 return 1;
1644
0bed3b56
SY		 1645 if (msr == MSR_MTRRdefType)
1646 *pdata = vcpu->arch.mtrr_state.def_type +
1647 (vcpu->arch.mtrr_state.enabled << 10);
1648 else if (msr == MSR_MTRRfix64K_00000)
1649 *pdata = p[0];
1650 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1651 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1652 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1653 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1654 else if (msr == MSR_IA32_CR_PAT)
1655 *pdata = vcpu->arch.pat;
1656 else { /* Variable MTRRs */
1657 int idx, is_mtrr_mask;
1658 u64 *pt;
1659
1660 idx = (msr - 0x200) / 2;
1661 is_mtrr_mask = msr - 0x200 - 2 * idx;
1662 if (!is_mtrr_mask)
1663 pt =
1664 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1665 else
1666 pt =
1667 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1668 *pdata = *pt;
1669 }
1670
9ba075a6
AK		 1671 return 0;
1672}
1673
890ca9ae 1674static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1675{
1676 u64 data;
890ca9ae
HY		 1677 u64 mcg_cap = vcpu->arch.mcg_cap;
1678 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1679
1680 switch (msr) {
15c4a640
CO		 1681 case MSR_IA32_P5_MC_ADDR:
1682 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1683 data = 0;
1684 break;
15c4a640 1685 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1686 data = vcpu->arch.mcg_cap;
1687 break;
c7ac679c 1688 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1689 if (!(mcg_cap & MCG_CTL_P))
1690 return 1;
1691 data = vcpu->arch.mcg_ctl;
1692 break;
1693 case MSR_IA32_MCG_STATUS:
1694 data = vcpu->arch.mcg_status;
1695 break;
1696 default:
1697 if (msr >= MSR_IA32_MC0_CTL &&
1698 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1699 u32 offset = msr - MSR_IA32_MC0_CTL;
1700 data = vcpu->arch.mce_banks[offset];
1701 break;
1702 }
1703 return 1;
1704 }
1705 *pdata = data;
1706 return 0;
1707}
1708
55cd8e5a
GN		 1709static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1710{
1711 u64 data = 0;
1712 struct kvm *kvm = vcpu->kvm;
1713
1714 switch (msr) {
1715 case HV_X64_MSR_GUEST_OS_ID:
1716 data = kvm->arch.hv_guest_os_id;
1717 break;
1718 case HV_X64_MSR_HYPERCALL:
1719 data = kvm->arch.hv_hypercall;
1720 break;
1721 default:
1722 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1723 return 1;
1724 }
1725
1726 *pdata = data;
1727 return 0;
1728}
1729
1730static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1731{
1732 u64 data = 0;
1733
1734 switch (msr) {
1735 case HV_X64_MSR_VP_INDEX: {
1736 int r;
1737 struct kvm_vcpu *v;
1738 kvm_for_each_vcpu(r, v, vcpu->kvm)
1739 if (v == vcpu)
1740 data = r;
1741 break;
1742 }
10388a07
GN		 1743 case HV_X64_MSR_EOI:
1744 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1745 case HV_X64_MSR_ICR:
1746 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1747 case HV_X64_MSR_TPR:
1748 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1749 default:
1750 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1751 return 1;
1752 }
1753 *pdata = data;
1754 return 0;
1755}
1756
890ca9ae
HY		 1757int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1758{
1759 u64 data;
1760
1761 switch (msr) {
890ca9ae 1762 case MSR_IA32_PLATFORM_ID:
15c4a640 1763 case MSR_IA32_UCODE_REV:
15c4a640 1764 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1765 case MSR_IA32_DEBUGCTLMSR:
1766 case MSR_IA32_LASTBRANCHFROMIP:
1767 case MSR_IA32_LASTBRANCHTOIP:
1768 case MSR_IA32_LASTINTFROMIP:
1769 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1770 case MSR_K8_SYSCFG:
1771 case MSR_K7_HWCR:
61a6bd67 1772 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1773 case MSR_P6_PERFCTR0:
1774 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1775 case MSR_P6_EVNTSEL0:
1776 case MSR_P6_EVNTSEL1:
9e699624 1777 case MSR_K7_EVNTSEL0:
1f3ee616 1778 case MSR_K7_PERFCTR0:
1fdbd48c 1779 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1780 case MSR_AMD64_NB_CFG:
f7c6d140 1781 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1782 data = 0;
1783 break;
9ba075a6
AK		 1784 case MSR_MTRRcap:
1785 data = 0x500 | KVM_NR_VAR_MTRR;
1786 break;
1787 case 0x200 ... 0x2ff:
1788 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1789 case 0xcd: /* fsb frequency */
1790 data = 3;
1791 break;
7b914098
JS		 1792 /*
1793 * MSR_EBC_FREQUENCY_ID
1794 * Conservative value valid for even the basic CPU models.
1795 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1796 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1797 * and 266MHz for model 3, or 4. Set Core Clock
1798 * Frequency to System Bus Frequency Ratio to 1 (bits
1799 * 31:24) even though these are only valid for CPU
1800 * models > 2, however guests may end up dividing or
1801 * multiplying by zero otherwise.
1802 */
1803 case MSR_EBC_FREQUENCY_ID:
1804 data = 1 << 24;
1805 break;
15c4a640
CO		 1806 case MSR_IA32_APICBASE:
1807 data = kvm_get_apic_base(vcpu);
1808 break;
0105d1a5
GN		 1809 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1810 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1811 break;
15c4a640 1812 case MSR_IA32_MISC_ENABLE:
ad312c7c 1813 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1814 break;
847f0ad8
AG		 1815 case MSR_IA32_PERF_STATUS:
1816 /* TSC increment by tick */
1817 data = 1000ULL;
1818 /* CPU multiplier */
1819 data |= (((uint64_t)4ULL) << 40);
1820 break;
15c4a640 1821 case MSR_EFER:
f6801dff 1822 data = vcpu->arch.efer;
15c4a640 1823 break;
18068523 1824 case MSR_KVM_WALL_CLOCK:
11c6bffa 1825 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1826 data = vcpu->kvm->arch.wall_clock;
1827 break;
1828 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1829 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1830 data = vcpu->arch.time;
1831 break;
344d9588
GN		 1832 case MSR_KVM_ASYNC_PF_EN:
1833 data = vcpu->arch.apf.msr_val;
1834 break;
890ca9ae
HY		 1835 case MSR_IA32_P5_MC_ADDR:
1836 case MSR_IA32_P5_MC_TYPE:
1837 case MSR_IA32_MCG_CAP:
1838 case MSR_IA32_MCG_CTL:
1839 case MSR_IA32_MCG_STATUS:
1840 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1841 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1842 case MSR_K7_CLK_CTL:
1843 /*
1844 * Provide expected ramp-up count for K7. All other
1845 * are set to zero, indicating minimum divisors for
1846 * every field.
1847 *
1848 * This prevents guest kernels on AMD host with CPU
1849 * type 6, model 8 and higher from exploding due to
1850 * the rdmsr failing.
1851 */
1852 data = 0x20000000;
1853 break;
55cd8e5a
GN		 1854 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1855 if (kvm_hv_msr_partition_wide(msr)) {
1856 int r;
1857 mutex_lock(&vcpu->kvm->lock);
1858 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1859 mutex_unlock(&vcpu->kvm->lock);
1860 return r;
1861 } else
1862 return get_msr_hyperv(vcpu, msr, pdata);
1863 break;
91c9c3ed 1864 case MSR_IA32_BBL_CR_CTL3:
1865 /* This legacy MSR exists but isn't fully documented in current
1866 * silicon. It is however accessed by winxp in very narrow
1867 * scenarios where it sets bit #19, itself documented as
1868 * a "reserved" bit. Best effort attempt to source coherent
1869 * read data here should the balance of the register be
1870 * interpreted by the guest:
1871 *
1872 * L2 cache control register 3: 64GB range, 256KB size,
1873 * enabled, latency 0x1, configured
1874 */
1875 data = 0xbe702111;
1876 break;
15c4a640 1877 default:
ed85c068
AP		 1878 if (!ignore_msrs) {
1879 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1880 return 1;
1881 } else {
1882 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1883 data = 0;
1884 }
1885 break;
15c4a640
CO		 1886 }
1887 *pdata = data;
1888 return 0;
1889}
1890EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1891
313a3dc7
CO		 1892/*
1893 * Read or write a bunch of msrs. All parameters are kernel addresses.
1894 *
1895 * @return number of msrs set successfully.
1896 */
1897static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1898 struct kvm_msr_entry *entries,
1899 int (*do_msr)(struct kvm_vcpu *vcpu,
1900 unsigned index, u64 *data))
1901{
f656ce01 1902 int i, idx;
313a3dc7 1903
f656ce01 1904 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1905 for (i = 0; i < msrs->nmsrs; ++i)
1906 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1907 break;
f656ce01 1908 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1909
313a3dc7
CO		 1910 return i;
1911}
1912
1913/*
1914 * Read or write a bunch of msrs. Parameters are user addresses.
1915 *
1916 * @return number of msrs set successfully.
1917 */
1918static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1919 int (*do_msr)(struct kvm_vcpu *vcpu,
1920 unsigned index, u64 *data),
1921 int writeback)
1922{
1923 struct kvm_msrs msrs;
1924 struct kvm_msr_entry *entries;
1925 int r, n;
1926 unsigned size;
1927
1928 r = -EFAULT;
1929 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1930 goto out;
1931
1932 r = -E2BIG;
1933 if (msrs.nmsrs >= MAX_IO_MSRS)
1934 goto out;
1935
1936 r = -ENOMEM;
1937 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1938 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1939 if (!entries)
1940 goto out;
1941
1942 r = -EFAULT;
1943 if (copy_from_user(entries, user_msrs->entries, size))
1944 goto out_free;
1945
1946 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1947 if (r < 0)
1948 goto out_free;
1949
1950 r = -EFAULT;
1951 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1952 goto out_free;
1953
1954 r = n;
1955
1956out_free:
7a73c028 1957 kfree(entries);
313a3dc7
CO		 1958out:
1959 return r;
1960}
1961
018d00d2
ZX		 1962int kvm_dev_ioctl_check_extension(long ext)
1963{
1964 int r;
1965
1966 switch (ext) {
1967 case KVM_CAP_IRQCHIP:
1968 case KVM_CAP_HLT:
1969 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1970 case KVM_CAP_SET_TSS_ADDR:
07716717 1971 case KVM_CAP_EXT_CPUID:
c8076604 1972 case KVM_CAP_CLOCKSOURCE:
7837699f 1973 case KVM_CAP_PIT:
a28e4f5a 1974 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1975 case KVM_CAP_MP_STATE:
ed848624 1976 case KVM_CAP_SYNC_MMU:
a355c85c 1977 case KVM_CAP_USER_NMI:
52d939a0 1978 case KVM_CAP_REINJECT_CONTROL:
4925663a 1979 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1980 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1981 case KVM_CAP_IRQFD:
d34e6b17 1982 case KVM_CAP_IOEVENTFD:
c5ff41ce 1983 case KVM_CAP_PIT2:
e9f42757 1984 case KVM_CAP_PIT_STATE2:
b927a3ce 1985 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1986 case KVM_CAP_XEN_HVM:
afbcf7ab 1987 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1988 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1989 case KVM_CAP_HYPERV:
10388a07 1990 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1991 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1992 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1993 case KVM_CAP_DEBUGREGS:
d2be1651 1994 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1995 case KVM_CAP_XSAVE:
344d9588 1996 case KVM_CAP_ASYNC_PF:
92a1f12d 1997 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 1998 r = 1;
1999 break;
542472b5
LV		 2000 case KVM_CAP_COALESCED_MMIO:
2001 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2002 break;
774ead3a
AK		 2003 case KVM_CAP_VAPIC:
2004 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2005 break;
f725230a
AK		 2006 case KVM_CAP_NR_VCPUS:
2007 r = KVM_MAX_VCPUS;
2008 break;
a988b910
AK		 2009 case KVM_CAP_NR_MEMSLOTS:
2010 r = KVM_MEMORY_SLOTS;
2011 break;
a68a6a72
MT		 2012 case KVM_CAP_PV_MMU: /* obsolete */
2013 r = 0;
2f333bcb 2014 break;
62c476c7 2015 case KVM_CAP_IOMMU:
19de40a8 2016 r = iommu_found();
62c476c7 2017 break;
890ca9ae
HY		 2018 case KVM_CAP_MCE:
2019 r = KVM_MAX_MCE_BANKS;
2020 break;
2d5b5a66
SY		 2021 case KVM_CAP_XCRS:
2022 r = cpu_has_xsave;
2023 break;
92a1f12d
JR		 2024 case KVM_CAP_TSC_CONTROL:
2025 r = kvm_has_tsc_control;
2026 break;
018d00d2
ZX		 2027 default:
2028 r = 0;
2029 break;
2030 }
2031 return r;
2032
2033}
2034
043405e1
CO		 2035long kvm_arch_dev_ioctl(struct file *filp,
2036 unsigned int ioctl, unsigned long arg)
2037{
2038 void __user *argp = (void __user *)arg;
2039 long r;
2040
2041 switch (ioctl) {
2042 case KVM_GET_MSR_INDEX_LIST: {
2043 struct kvm_msr_list __user *user_msr_list = argp;
2044 struct kvm_msr_list msr_list;
2045 unsigned n;
2046
2047 r = -EFAULT;
2048 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2049 goto out;
2050 n = msr_list.nmsrs;
2051 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2052 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2053 goto out;
2054 r = -E2BIG;
e125e7b6 2055 if (n < msr_list.nmsrs)
043405e1
CO		 2056 goto out;
2057 r = -EFAULT;
2058 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2059 num_msrs_to_save * sizeof(u32)))
2060 goto out;
e125e7b6 2061 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2062 &emulated_msrs,
2063 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2064 goto out;
2065 r = 0;
2066 break;
2067 }
674eea0f
AK		 2068 case KVM_GET_SUPPORTED_CPUID: {
2069 struct kvm_cpuid2 __user *cpuid_arg = argp;
2070 struct kvm_cpuid2 cpuid;
2071
2072 r = -EFAULT;
2073 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2074 goto out;
2075 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2076 cpuid_arg->entries);
674eea0f
AK		 2077 if (r)
2078 goto out;
2079
2080 r = -EFAULT;
2081 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2082 goto out;
2083 r = 0;
2084 break;
2085 }
890ca9ae
HY		 2086 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2087 u64 mce_cap;
2088
2089 mce_cap = KVM_MCE_CAP_SUPPORTED;
2090 r = -EFAULT;
2091 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2092 goto out;
2093 r = 0;
2094 break;
2095 }
043405e1
CO		 2096 default:
2097 r = -EINVAL;
2098 }
2099out:
2100 return r;
2101}
2102
f5f48ee1
SY		 2103static void wbinvd_ipi(void *garbage)
2104{
2105 wbinvd();
2106}
2107
2108static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2109{
2110 return vcpu->kvm->arch.iommu_domain &&
2111 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2112}
2113
313a3dc7
CO		 2114void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2115{
f5f48ee1
SY		 2116 /* Address WBINVD may be executed by guest */
2117 if (need_emulate_wbinvd(vcpu)) {
2118 if (kvm_x86_ops->has_wbinvd_exit())
2119 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2120 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2121 smp_call_function_single(vcpu->cpu,
2122 wbinvd_ipi, NULL, 1);
2123 }
2124
313a3dc7 2125 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2126 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2127 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2128 s64 tsc_delta;
2129 u64 tsc;
2130
2131 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2132 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2133 tsc - vcpu->arch.last_guest_tsc;
2134
e48672fa
ZA		 2135 if (tsc_delta < 0)
2136 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2137 if (check_tsc_unstable()) {
e48672fa 2138 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2139 vcpu->arch.tsc_catchup = 1;
c285545f 2140 }
1aa8ceef 2141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2142 if (vcpu->cpu != cpu)
2143 kvm_migrate_timers(vcpu);
e48672fa 2144 vcpu->cpu = cpu;
6b7d7e76 2145 }
313a3dc7
CO		 2146}
2147
2148void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2149{
02daab21 2150 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2151 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2152 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2153}
2154
07716717 2155static int is_efer_nx(void)
313a3dc7 2156{
e286e86e 2157 unsigned long long efer = 0;
313a3dc7 2158
e286e86e 2159 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2160 return efer & EFER_NX;
2161}
2162
2163static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2164{
2165 int i;
2166 struct kvm_cpuid_entry2 *e, *entry;
2167
313a3dc7 2168 entry = NULL;
ad312c7c
ZX		 2169 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2170 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2171 if (e->function == 0x80000001) {
2172 entry = e;
2173 break;
2174 }
2175 }
07716717 2176 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2177 entry->edx &= ~(1 << 20);
2178 printk(KERN_INFO "kvm: guest NX capability removed\n");
2179 }
2180}
2181
07716717 2182/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2183static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2184 struct kvm_cpuid *cpuid,
2185 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2186{
2187 int r, i;
2188 struct kvm_cpuid_entry *cpuid_entries;
2189
2190 r = -E2BIG;
2191 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2192 goto out;
2193 r = -ENOMEM;
2194 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2195 if (!cpuid_entries)
2196 goto out;
2197 r = -EFAULT;
2198 if (copy_from_user(cpuid_entries, entries,
2199 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2200 goto out_free;
2201 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2202 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2203 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2204 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2205 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2206 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2207 vcpu->arch.cpuid_entries[i].index = 0;
2208 vcpu->arch.cpuid_entries[i].flags = 0;
2209 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2210 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2211 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2212 }
2213 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2214 cpuid_fix_nx_cap(vcpu);
2215 r = 0;
fc61b800 2216 kvm_apic_set_version(vcpu);
0e851880 2217 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2218 update_cpuid(vcpu);
07716717
DK		 2219
2220out_free:
2221 vfree(cpuid_entries);
2222out:
2223 return r;
2224}
2225
2226static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2227 struct kvm_cpuid2 *cpuid,
2228 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2229{
2230 int r;
2231
2232 r = -E2BIG;
2233 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2234 goto out;
2235 r = -EFAULT;
ad312c7c 2236 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2237 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2238 goto out;
ad312c7c 2239 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2240 kvm_apic_set_version(vcpu);
0e851880 2241 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2242 update_cpuid(vcpu);
313a3dc7
CO		 2243 return 0;
2244
2245out:
2246 return r;
2247}
2248
07716717 2249static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2250 struct kvm_cpuid2 *cpuid,
2251 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2252{
2253 int r;
2254
2255 r = -E2BIG;
ad312c7c 2256 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2257 goto out;
2258 r = -EFAULT;
ad312c7c 2259 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2260 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2261 goto out;
2262 return 0;
2263
2264out:
ad312c7c 2265 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2266 return r;
2267}
2268
945ee35e
AK		 2269static void cpuid_mask(u32 *word, int wordnum)
2270{
2271 *word &= boot_cpu_data.x86_capability[wordnum];
2272}
2273
07716717 2274static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2275 u32 index)
07716717
DK		 2276{
2277 entry->function = function;
2278 entry->index = index;
2279 cpuid_count(entry->function, entry->index,
19355475 2280 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2281 entry->flags = 0;
2282}
2283
24c82e57
AK		 2284static bool supported_xcr0_bit(unsigned bit)
2285{
2286 u64 mask = ((u64)1 << bit);
2287
2288 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2289}
2290
7faa4ee1
AK		 2291#define F(x) bit(X86_FEATURE_##x)
2292
07716717
DK		 2293static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2294 u32 index, int *nent, int maxnent)
2295{
7faa4ee1 2296 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2297#ifdef CONFIG_X86_64
17cc3935
SY		 2298 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2299 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2300 unsigned f_lm = F(LM);
2301#else
17cc3935 2302 unsigned f_gbpages = 0;
7faa4ee1 2303 unsigned f_lm = 0;
07716717 2304#endif
4e47c7a6 2305 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2306
2307 /* cpuid 1.edx */
2308 const u32 kvm_supported_word0_x86_features =
2309 F(FPU) | F(VME) | F(DE) | F(PSE) |
2310 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2311 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2312 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2313 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2314 0 /* Reserved, DS, ACPI */ | F(MMX) |
2315 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2316 0 /* HTT, TM, Reserved, PBE */;
2317 /* cpuid 0x80000001.edx */
2318 const u32 kvm_supported_word1_x86_features =
2319 F(FPU) | F(VME) | F(DE) | F(PSE) |
2320 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2321 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2322 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2323 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2324 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2325 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2326 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2327 /* cpuid 1.ecx */
2328 const u32 kvm_supported_word4_x86_features =
6c3f6041 2329 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2330 0 /* DS-CPL, VMX, SMX, EST */ |
2331 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2332 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2333 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2334 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2335 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2336 F(F16C);
7faa4ee1 2337 /* cpuid 0x80000001.ecx */
07716717 2338 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2339 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2340 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2341 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2342 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2343
4429d5dc
B		 2344 /* cpuid 0xC0000001.edx */
2345 const u32 kvm_supported_word5_x86_features =
2346 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2347 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2348 F(PMM) | F(PMM_EN);
2349
19355475 2350 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2351 get_cpu();
2352 do_cpuid_1_ent(entry, function, index);
2353 ++*nent;
2354
2355 switch (function) {
2356 case 0:
2acf923e 2357 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2358 break;
2359 case 1:
2360 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2361 cpuid_mask(&entry->edx, 0);
7faa4ee1 2362 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2363 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2364 /* we support x2apic emulation even if host does not support
2365 * it since we emulate x2apic in software */
2366 entry->ecx |= F(X2APIC);
07716717
DK		 2367 break;
2368 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2369 * may return different values. This forces us to get_cpu() before
2370 * issuing the first command, and also to emulate this annoying behavior
2371 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2372 case 2: {
2373 int t, times = entry->eax & 0xff;
2374
2375 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2376 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2377 for (t = 1; t < times && *nent < maxnent; ++t) {
2378 do_cpuid_1_ent(&entry[t], function, 0);
2379 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2380 ++*nent;
2381 }
2382 break;
2383 }
2384 /* function 4 and 0xb have additional index. */
2385 case 4: {
14af3f3c 2386 int i, cache_type;
07716717
DK		 2387
2388 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2389 /* read more entries until cache_type is zero */
14af3f3c
HH		 2390 for (i = 1; *nent < maxnent; ++i) {
2391 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2392 if (!cache_type)
2393 break;
14af3f3c
HH		 2394 do_cpuid_1_ent(&entry[i], function, i);
2395 entry[i].flags |=
07716717
DK		 2396 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2397 ++*nent;
2398 }
2399 break;
2400 }
24c82e57
AK		 2401 case 9:
2402 break;
07716717 2403 case 0xb: {
14af3f3c 2404 int i, level_type;
07716717
DK		 2405
2406 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2407 /* read more entries until level_type is zero */
14af3f3c 2408 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2409 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2410 if (!level_type)
2411 break;
14af3f3c
HH		 2412 do_cpuid_1_ent(&entry[i], function, i);
2413 entry[i].flags |=
07716717
DK		 2414 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2415 ++*nent;
2416 }
2417 break;
2418 }
2acf923e
DC		 2419 case 0xd: {
2420 int i;
2421
2422 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9 2423 for (i = 1; *nent < maxnent && i < 64; ++i) {
24c82e57 2424 if (entry[i].eax == 0 || !supported_xcr0_bit(i))
20800bc9 2425 continue;
2acf923e
DC		 2426 do_cpuid_1_ent(&entry[i], function, i);
2427 entry[i].flags |=
2428 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2429 ++*nent;
2430 }
2431 break;
2432 }
84478c82
GC		 2433 case KVM_CPUID_SIGNATURE: {
2434 char signature[12] = "KVMKVMKVM\0\0";
2435 u32 *sigptr = (u32 *)signature;
2436 entry->eax = 0;
2437 entry->ebx = sigptr[0];
2438 entry->ecx = sigptr[1];
2439 entry->edx = sigptr[2];
2440 break;
2441 }
2442 case KVM_CPUID_FEATURES:
2443 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2444 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2445 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2446 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2447 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2448 entry->ebx = 0;
2449 entry->ecx = 0;
2450 entry->edx = 0;
2451 break;
07716717
DK		 2452 case 0x80000000:
2453 entry->eax = min(entry->eax, 0x8000001a);
2454 break;
2455 case 0x80000001:
2456 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2457 cpuid_mask(&entry->edx, 1);
07716717 2458 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2459 cpuid_mask(&entry->ecx, 6);
07716717 2460 break;
24c82e57
AK		 2461 case 0x80000008: {
2462 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2463 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2464 unsigned phys_as = entry->eax & 0xff;
2465
2466 if (!g_phys_as)
2467 g_phys_as = phys_as;
2468 entry->eax = g_phys_as | (virt_as << 8);
2469 entry->ebx = entry->edx = 0;
2470 break;
2471 }
2472 case 0x80000019:
2473 entry->ecx = entry->edx = 0;
2474 break;
2475 case 0x8000001a:
2476 break;
2477 case 0x8000001d:
2478 break;
4429d5dc
B		 2479 /*Add support for Centaur's CPUID instruction*/
2480 case 0xC0000000:
2481 /*Just support up to 0xC0000004 now*/
2482 entry->eax = min(entry->eax, 0xC0000004);
2483 break;
2484 case 0xC0000001:
2485 entry->edx &= kvm_supported_word5_x86_features;
2486 cpuid_mask(&entry->edx, 5);
2487 break;
24c82e57
AK		 2488 case 3: /* Processor serial number */
2489 case 5: /* MONITOR/MWAIT */
2490 case 6: /* Thermal management */
2491 case 0xA: /* Architectural Performance Monitoring */
2492 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2493 case 0xC0000002:
2494 case 0xC0000003:
2495 case 0xC0000004:
24c82e57
AK		 2496 default:
2497 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2498 break;
07716717 2499 }
d4330ef2
JR		 2500
2501 kvm_x86_ops->set_supported_cpuid(function, entry);
2502
07716717
DK		 2503 put_cpu();
2504}
2505
7faa4ee1
AK		 2506#undef F
2507
674eea0f 2508static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2509 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2510{
2511 struct kvm_cpuid_entry2 *cpuid_entries;
2512 int limit, nent = 0, r = -E2BIG;
2513 u32 func;
2514
2515 if (cpuid->nent < 1)
2516 goto out;
6a544355
AK		 2517 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2518 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2519 r = -ENOMEM;
2520 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2521 if (!cpuid_entries)
2522 goto out;
2523
2524 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2525 limit = cpuid_entries[0].eax;
2526 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2527 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2528 &nent, cpuid->nent);
07716717
DK		 2529 r = -E2BIG;
2530 if (nent >= cpuid->nent)
2531 goto out_free;
2532
2533 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2534 limit = cpuid_entries[nent - 1].eax;
2535 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2536 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2537 &nent, cpuid->nent);
84478c82
GC		 2538
2539
2540
2541 r = -E2BIG;
2542 if (nent >= cpuid->nent)
2543 goto out_free;
2544
4429d5dc
B		 2545 /* Add support for Centaur's CPUID instruction. */
2546 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2547 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2548 &nent, cpuid->nent);
2549
2550 r = -E2BIG;
2551 if (nent >= cpuid->nent)
2552 goto out_free;
2553
2554 limit = cpuid_entries[nent - 1].eax;
2555 for (func = 0xC0000001;
2556 func <= limit && nent < cpuid->nent; ++func)
2557 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2558 &nent, cpuid->nent);
2559
2560 r = -E2BIG;
2561 if (nent >= cpuid->nent)
2562 goto out_free;
2563 }
2564
84478c82
GC		 2565 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2566 cpuid->nent);
2567
2568 r = -E2BIG;
2569 if (nent >= cpuid->nent)
2570 goto out_free;
2571
2572 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2573 cpuid->nent);
2574
cb007648
MM		 2575 r = -E2BIG;
2576 if (nent >= cpuid->nent)
2577 goto out_free;
2578
07716717
DK		 2579 r = -EFAULT;
2580 if (copy_to_user(entries, cpuid_entries,
19355475 2581 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2582 goto out_free;
2583 cpuid->nent = nent;
2584 r = 0;
2585
2586out_free:
2587 vfree(cpuid_entries);
2588out:
2589 return r;
2590}
2591
313a3dc7
CO		 2592static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2593 struct kvm_lapic_state *s)
2594{
ad312c7c 2595 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2596
2597 return 0;
2598}
2599
2600static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2601 struct kvm_lapic_state *s)
2602{
ad312c7c 2603 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2604 kvm_apic_post_state_restore(vcpu);
cb142eb7 2605 update_cr8_intercept(vcpu);
313a3dc7
CO		 2606
2607 return 0;
2608}
2609
f77bc6a4
ZX		 2610static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2611 struct kvm_interrupt *irq)
2612{
2613 if (irq->irq < 0 || irq->irq >= 256)
2614 return -EINVAL;
2615 if (irqchip_in_kernel(vcpu->kvm))
2616 return -ENXIO;
f77bc6a4 2617
66fd3f7f 2618 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2619 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2620
f77bc6a4
ZX		 2621 return 0;
2622}
2623
c4abb7c9
JK		 2624static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2625{
c4abb7c9 2626 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2627
2628 return 0;
2629}
2630
b209749f
AK		 2631static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2632 struct kvm_tpr_access_ctl *tac)
2633{
2634 if (tac->flags)
2635 return -EINVAL;
2636 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2637 return 0;
2638}
2639
890ca9ae
HY		 2640static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2641 u64 mcg_cap)
2642{
2643 int r;
2644 unsigned bank_num = mcg_cap & 0xff, bank;
2645
2646 r = -EINVAL;
a9e38c3e 2647 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2648 goto out;
2649 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2650 goto out;
2651 r = 0;
2652 vcpu->arch.mcg_cap = mcg_cap;
2653 /* Init IA32_MCG_CTL to all 1s */
2654 if (mcg_cap & MCG_CTL_P)
2655 vcpu->arch.mcg_ctl = ~(u64)0;
2656 /* Init IA32_MCi_CTL to all 1s */
2657 for (bank = 0; bank < bank_num; bank++)
2658 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2659out:
2660 return r;
2661}
2662
2663static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2664 struct kvm_x86_mce *mce)
2665{
2666 u64 mcg_cap = vcpu->arch.mcg_cap;
2667 unsigned bank_num = mcg_cap & 0xff;
2668 u64 *banks = vcpu->arch.mce_banks;
2669
2670 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2671 return -EINVAL;
2672 /*
2673 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2674 * reporting is disabled
2675 */
2676 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2677 vcpu->arch.mcg_ctl != ~(u64)0)
2678 return 0;
2679 banks += 4 * mce->bank;
2680 /*
2681 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2682 * reporting is disabled for the bank
2683 */
2684 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2685 return 0;
2686 if (mce->status & MCI_STATUS_UC) {
2687 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2688 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2689 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2690 return 0;
2691 }
2692 if (banks[1] & MCI_STATUS_VAL)
2693 mce->status |= MCI_STATUS_OVER;
2694 banks[2] = mce->addr;
2695 banks[3] = mce->misc;
2696 vcpu->arch.mcg_status = mce->mcg_status;
2697 banks[1] = mce->status;
2698 kvm_queue_exception(vcpu, MC_VECTOR);
2699 } else if (!(banks[1] & MCI_STATUS_VAL)
2700 || !(banks[1] & MCI_STATUS_UC)) {
2701 if (banks[1] & MCI_STATUS_VAL)
2702 mce->status |= MCI_STATUS_OVER;
2703 banks[2] = mce->addr;
2704 banks[3] = mce->misc;
2705 banks[1] = mce->status;
2706 } else
2707 banks[1] |= MCI_STATUS_OVER;
2708 return 0;
2709}
2710
3cfc3092
JK		 2711static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2712 struct kvm_vcpu_events *events)
2713{
03b82a30
JK		 2714 events->exception.injected =
2715 vcpu->arch.exception.pending &&
2716 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2717 events->exception.nr = vcpu->arch.exception.nr;
2718 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2719 events->exception.pad = 0;
3cfc3092
JK		 2720 events->exception.error_code = vcpu->arch.exception.error_code;
2721
03b82a30
JK		 2722 events->interrupt.injected =
2723 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2724 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2725 events->interrupt.soft = 0;
48005f64
JK		 2726 events->interrupt.shadow =
2727 kvm_x86_ops->get_interrupt_shadow(vcpu,
2728 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2729
2730 events->nmi.injected = vcpu->arch.nmi_injected;
2731 events->nmi.pending = vcpu->arch.nmi_pending;
2732 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2733 events->nmi.pad = 0;
3cfc3092
JK		 2734
2735 events->sipi_vector = vcpu->arch.sipi_vector;
2736
dab4b911 2737 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2738 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2739 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2740 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2741}
2742
2743static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2744 struct kvm_vcpu_events *events)
2745{
dab4b911 2746 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2747 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2748 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2749 return -EINVAL;
2750
3cfc3092
JK		 2751 vcpu->arch.exception.pending = events->exception.injected;
2752 vcpu->arch.exception.nr = events->exception.nr;
2753 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2754 vcpu->arch.exception.error_code = events->exception.error_code;
2755
2756 vcpu->arch.interrupt.pending = events->interrupt.injected;
2757 vcpu->arch.interrupt.nr = events->interrupt.nr;
2758 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2759 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2760 kvm_x86_ops->set_interrupt_shadow(vcpu,
2761 events->interrupt.shadow);
3cfc3092
JK		 2762
2763 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2764 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2765 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2766 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2767
dab4b911
JK		 2768 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2769 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2770
3842d135
AK		 2771 kvm_make_request(KVM_REQ_EVENT, vcpu);
2772
3cfc3092
JK		 2773 return 0;
2774}
2775
a1efbe77
JK		 2776static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2777 struct kvm_debugregs *dbgregs)
2778{
a1efbe77
JK		 2779 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2780 dbgregs->dr6 = vcpu->arch.dr6;
2781 dbgregs->dr7 = vcpu->arch.dr7;
2782 dbgregs->flags = 0;
97e69aa6 2783 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2784}
2785
2786static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2787 struct kvm_debugregs *dbgregs)
2788{
2789 if (dbgregs->flags)
2790 return -EINVAL;
2791
a1efbe77
JK		 2792 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2793 vcpu->arch.dr6 = dbgregs->dr6;
2794 vcpu->arch.dr7 = dbgregs->dr7;
2795
a1efbe77
JK		 2796 return 0;
2797}
2798
2d5b5a66
SY		 2799static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2800 struct kvm_xsave *guest_xsave)
2801{
2802 if (cpu_has_xsave)
2803 memcpy(guest_xsave->region,
2804 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2805 xstate_size);
2d5b5a66
SY		 2806 else {
2807 memcpy(guest_xsave->region,
2808 &vcpu->arch.guest_fpu.state->fxsave,
2809 sizeof(struct i387_fxsave_struct));
2810 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2811 XSTATE_FPSSE;
2812 }
2813}
2814
2815static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2816 struct kvm_xsave *guest_xsave)
2817{
2818 u64 xstate_bv =
2819 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2820
2821 if (cpu_has_xsave)
2822 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2823 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2824 else {
2825 if (xstate_bv & ~XSTATE_FPSSE)
2826 return -EINVAL;
2827 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2828 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2829 }
2830 return 0;
2831}
2832
2833static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2834 struct kvm_xcrs *guest_xcrs)
2835{
2836 if (!cpu_has_xsave) {
2837 guest_xcrs->nr_xcrs = 0;
2838 return;
2839 }
2840
2841 guest_xcrs->nr_xcrs = 1;
2842 guest_xcrs->flags = 0;
2843 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2844 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2845}
2846
2847static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2848 struct kvm_xcrs *guest_xcrs)
2849{
2850 int i, r = 0;
2851
2852 if (!cpu_has_xsave)
2853 return -EINVAL;
2854
2855 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2856 return -EINVAL;
2857
2858 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2859 /* Only support XCR0 currently */
2860 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2861 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2862 guest_xcrs->xcrs[0].value);
2863 break;
2864 }
2865 if (r)
2866 r = -EINVAL;
2867 return r;
2868}
2869
313a3dc7
CO		 2870long kvm_arch_vcpu_ioctl(struct file *filp,
2871 unsigned int ioctl, unsigned long arg)
2872{
2873 struct kvm_vcpu *vcpu = filp->private_data;
2874 void __user *argp = (void __user *)arg;
2875 int r;
d1ac91d8
AK		 2876 union {
2877 struct kvm_lapic_state *lapic;
2878 struct kvm_xsave *xsave;
2879 struct kvm_xcrs *xcrs;
2880 void *buffer;
2881 } u;
2882
2883 u.buffer = NULL;
313a3dc7
CO		 2884 switch (ioctl) {
2885 case KVM_GET_LAPIC: {
2204ae3c
MT		 2886 r = -EINVAL;
2887 if (!vcpu->arch.apic)
2888 goto out;
d1ac91d8 2889 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2890
b772ff36 2891 r = -ENOMEM;
d1ac91d8 2892 if (!u.lapic)
b772ff36 2893 goto out;
d1ac91d8 2894 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2895 if (r)
2896 goto out;
2897 r = -EFAULT;
d1ac91d8 2898 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2899 goto out;
2900 r = 0;
2901 break;
2902 }
2903 case KVM_SET_LAPIC: {
2204ae3c
MT		 2904 r = -EINVAL;
2905 if (!vcpu->arch.apic)
2906 goto out;
d1ac91d8 2907 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2908 r = -ENOMEM;
d1ac91d8 2909 if (!u.lapic)
b772ff36 2910 goto out;
313a3dc7 2911 r = -EFAULT;
d1ac91d8 2912 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2913 goto out;
d1ac91d8 2914 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2915 if (r)
2916 goto out;
2917 r = 0;
2918 break;
2919 }
f77bc6a4
ZX		 2920 case KVM_INTERRUPT: {
2921 struct kvm_interrupt irq;
2922
2923 r = -EFAULT;
2924 if (copy_from_user(&irq, argp, sizeof irq))
2925 goto out;
2926 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2927 if (r)
2928 goto out;
2929 r = 0;
2930 break;
2931 }
c4abb7c9
JK		 2932 case KVM_NMI: {
2933 r = kvm_vcpu_ioctl_nmi(vcpu);
2934 if (r)
2935 goto out;
2936 r = 0;
2937 break;
2938 }
313a3dc7
CO		 2939 case KVM_SET_CPUID: {
2940 struct kvm_cpuid __user *cpuid_arg = argp;
2941 struct kvm_cpuid cpuid;
2942
2943 r = -EFAULT;
2944 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2945 goto out;
2946 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2947 if (r)
2948 goto out;
2949 break;
2950 }
07716717
DK		 2951 case KVM_SET_CPUID2: {
2952 struct kvm_cpuid2 __user *cpuid_arg = argp;
2953 struct kvm_cpuid2 cpuid;
2954
2955 r = -EFAULT;
2956 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2957 goto out;
2958 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2959 cpuid_arg->entries);
07716717
DK		 2960 if (r)
2961 goto out;
2962 break;
2963 }
2964 case KVM_GET_CPUID2: {
2965 struct kvm_cpuid2 __user *cpuid_arg = argp;
2966 struct kvm_cpuid2 cpuid;
2967
2968 r = -EFAULT;
2969 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2970 goto out;
2971 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2972 cpuid_arg->entries);
07716717
DK		 2973 if (r)
2974 goto out;
2975 r = -EFAULT;
2976 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2977 goto out;
2978 r = 0;
2979 break;
2980 }
313a3dc7
CO		 2981 case KVM_GET_MSRS:
2982 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2983 break;
2984 case KVM_SET_MSRS:
2985 r = msr_io(vcpu, argp, do_set_msr, 0);
2986 break;
b209749f
AK		 2987 case KVM_TPR_ACCESS_REPORTING: {
2988 struct kvm_tpr_access_ctl tac;
2989
2990 r = -EFAULT;
2991 if (copy_from_user(&tac, argp, sizeof tac))
2992 goto out;
2993 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2994 if (r)
2995 goto out;
2996 r = -EFAULT;
2997 if (copy_to_user(argp, &tac, sizeof tac))
2998 goto out;
2999 r = 0;
3000 break;
3001 };
b93463aa
AK		 3002 case KVM_SET_VAPIC_ADDR: {
3003 struct kvm_vapic_addr va;
3004
3005 r = -EINVAL;
3006 if (!irqchip_in_kernel(vcpu->kvm))
3007 goto out;
3008 r = -EFAULT;
3009 if (copy_from_user(&va, argp, sizeof va))
3010 goto out;
3011 r = 0;
3012 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3013 break;
3014 }
890ca9ae
HY		 3015 case KVM_X86_SETUP_MCE: {
3016 u64 mcg_cap;
3017
3018 r = -EFAULT;
3019 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3020 goto out;
3021 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3022 break;
3023 }
3024 case KVM_X86_SET_MCE: {
3025 struct kvm_x86_mce mce;
3026
3027 r = -EFAULT;
3028 if (copy_from_user(&mce, argp, sizeof mce))
3029 goto out;
3030 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3031 break;
3032 }
3cfc3092
JK		 3033 case KVM_GET_VCPU_EVENTS: {
3034 struct kvm_vcpu_events events;
3035
3036 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3037
3038 r = -EFAULT;
3039 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3040 break;
3041 r = 0;
3042 break;
3043 }
3044 case KVM_SET_VCPU_EVENTS: {
3045 struct kvm_vcpu_events events;
3046
3047 r = -EFAULT;
3048 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3049 break;
3050
3051 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3052 break;
3053 }
a1efbe77
JK		 3054 case KVM_GET_DEBUGREGS: {
3055 struct kvm_debugregs dbgregs;
3056
3057 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3058
3059 r = -EFAULT;
3060 if (copy_to_user(argp, &dbgregs,
3061 sizeof(struct kvm_debugregs)))
3062 break;
3063 r = 0;
3064 break;
3065 }
3066 case KVM_SET_DEBUGREGS: {
3067 struct kvm_debugregs dbgregs;
3068
3069 r = -EFAULT;
3070 if (copy_from_user(&dbgregs, argp,
3071 sizeof(struct kvm_debugregs)))
3072 break;
3073
3074 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3075 break;
3076 }
2d5b5a66 3077 case KVM_GET_XSAVE: {
d1ac91d8 3078 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3079 r = -ENOMEM;
d1ac91d8 3080 if (!u.xsave)
2d5b5a66
SY		 3081 break;
3082
d1ac91d8 3083 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3084
3085 r = -EFAULT;
d1ac91d8 3086 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3087 break;
3088 r = 0;
3089 break;
3090 }
3091 case KVM_SET_XSAVE: {
d1ac91d8 3092 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3093 r = -ENOMEM;
d1ac91d8 3094 if (!u.xsave)
2d5b5a66
SY		 3095 break;
3096
3097 r = -EFAULT;
d1ac91d8 3098 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3099 break;
3100
d1ac91d8 3101 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3102 break;
3103 }
3104 case KVM_GET_XCRS: {
d1ac91d8 3105 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3106 r = -ENOMEM;
d1ac91d8 3107 if (!u.xcrs)
2d5b5a66
SY		 3108 break;
3109
d1ac91d8 3110 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3111
3112 r = -EFAULT;
d1ac91d8 3113 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3114 sizeof(struct kvm_xcrs)))
3115 break;
3116 r = 0;
3117 break;
3118 }
3119 case KVM_SET_XCRS: {
d1ac91d8 3120 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3121 r = -ENOMEM;
d1ac91d8 3122 if (!u.xcrs)
2d5b5a66
SY		 3123 break;
3124
3125 r = -EFAULT;
d1ac91d8 3126 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3127 sizeof(struct kvm_xcrs)))
3128 break;
3129
d1ac91d8 3130 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3131 break;
3132 }
92a1f12d
JR		 3133 case KVM_SET_TSC_KHZ: {
3134 u32 user_tsc_khz;
3135
3136 r = -EINVAL;
3137 if (!kvm_has_tsc_control)
3138 break;
3139
3140 user_tsc_khz = (u32)arg;
3141
3142 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3143 goto out;
3144
3145 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3146
3147 r = 0;
3148 goto out;
3149 }
3150 case KVM_GET_TSC_KHZ: {
3151 r = -EIO;
3152 if (check_tsc_unstable())
3153 goto out;
3154
3155 r = vcpu_tsc_khz(vcpu);
3156
3157 goto out;
3158 }
313a3dc7
CO		 3159 default:
3160 r = -EINVAL;
3161 }
3162out:
d1ac91d8 3163 kfree(u.buffer);
313a3dc7
CO		 3164 return r;
3165}
3166
1fe779f8
CO		 3167static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3168{
3169 int ret;
3170
3171 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3172 return -1;
3173 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3174 return ret;
3175}
3176
b927a3ce
SY		 3177static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3178 u64 ident_addr)
3179{
3180 kvm->arch.ept_identity_map_addr = ident_addr;
3181 return 0;
3182}
3183
1fe779f8
CO		 3184static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3185 u32 kvm_nr_mmu_pages)
3186{
3187 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3188 return -EINVAL;
3189
79fac95e 3190 mutex_lock(&kvm->slots_lock);
7c8a83b7 3191 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3192
3193 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3194 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3195
7c8a83b7 3196 spin_unlock(&kvm->mmu_lock);
79fac95e 3197 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3198 return 0;
3199}
3200
3201static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3202{
39de71ec 3203 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3204}
3205
1fe779f8
CO		 3206static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3207{
3208 int r;
3209
3210 r = 0;
3211 switch (chip->chip_id) {
3212 case KVM_IRQCHIP_PIC_MASTER:
3213 memcpy(&chip->chip.pic,
3214 &pic_irqchip(kvm)->pics[0],
3215 sizeof(struct kvm_pic_state));
3216 break;
3217 case KVM_IRQCHIP_PIC_SLAVE:
3218 memcpy(&chip->chip.pic,
3219 &pic_irqchip(kvm)->pics[1],
3220 sizeof(struct kvm_pic_state));
3221 break;
3222 case KVM_IRQCHIP_IOAPIC:
eba0226b 3223 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3224 break;
3225 default:
3226 r = -EINVAL;
3227 break;
3228 }
3229 return r;
3230}
3231
3232static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3233{
3234 int r;
3235
3236 r = 0;
3237 switch (chip->chip_id) {
3238 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3239 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3240 memcpy(&pic_irqchip(kvm)->pics[0],
3241 &chip->chip.pic,
3242 sizeof(struct kvm_pic_state));
f4f51050 3243 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3244 break;
3245 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3246 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3247 memcpy(&pic_irqchip(kvm)->pics[1],
3248 &chip->chip.pic,
3249 sizeof(struct kvm_pic_state));
f4f51050 3250 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3251 break;
3252 case KVM_IRQCHIP_IOAPIC:
eba0226b 3253 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3254 break;
3255 default:
3256 r = -EINVAL;
3257 break;
3258 }
3259 kvm_pic_update_irq(pic_irqchip(kvm));
3260 return r;
3261}
3262
e0f63cb9
SY		 3263static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3264{
3265 int r = 0;
3266
894a9c55 3267 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3268 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3269 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3270 return r;
3271}
3272
3273static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3274{
3275 int r = 0;
3276
894a9c55 3277 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3278 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3279 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3280 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3281 return r;
3282}
3283
3284static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3285{
3286 int r = 0;
3287
3288 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3289 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3290 sizeof(ps->channels));
3291 ps->flags = kvm->arch.vpit->pit_state.flags;
3292 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3293 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3294 return r;
3295}
3296
3297static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3298{
3299 int r = 0, start = 0;
3300 u32 prev_legacy, cur_legacy;
3301 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3302 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3303 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3304 if (!prev_legacy && cur_legacy)
3305 start = 1;
3306 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3307 sizeof(kvm->arch.vpit->pit_state.channels));
3308 kvm->arch.vpit->pit_state.flags = ps->flags;
3309 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3310 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3311 return r;
3312}
3313
52d939a0
MT		 3314static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3315 struct kvm_reinject_control *control)
3316{
3317 if (!kvm->arch.vpit)
3318 return -ENXIO;
894a9c55 3319 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3320 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3321 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3322 return 0;
3323}
3324
5bb064dc
ZX		 3325/*
3326 * Get (and clear) the dirty memory log for a memory slot.
3327 */
3328int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3329 struct kvm_dirty_log *log)
3330{
87bf6e7d 3331 int r, i;
5bb064dc 3332 struct kvm_memory_slot *memslot;
87bf6e7d 3333 unsigned long n;
b050b015 3334 unsigned long is_dirty = 0;
5bb064dc 3335
79fac95e 3336 mutex_lock(&kvm->slots_lock);
5bb064dc 3337
b050b015
MT		 3338 r = -EINVAL;
3339 if (log->slot >= KVM_MEMORY_SLOTS)
3340 goto out;
3341
3342 memslot = &kvm->memslots->memslots[log->slot];
3343 r = -ENOENT;
3344 if (!memslot->dirty_bitmap)
3345 goto out;
3346
87bf6e7d 3347 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3348
b050b015
MT		 3349 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3350 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3351
3352 /* If nothing is dirty, don't bother messing with page tables. */
3353 if (is_dirty) {
b050b015 3354 struct kvm_memslots *slots, *old_slots;
914ebccd 3355 unsigned long *dirty_bitmap;
b050b015 3356
515a0127
TY		 3357 dirty_bitmap = memslot->dirty_bitmap_head;
3358 if (memslot->dirty_bitmap == dirty_bitmap)
3359 dirty_bitmap += n / sizeof(long);
914ebccd 3360 memset(dirty_bitmap, 0, n);
b050b015 3361
914ebccd
TY		 3362 r = -ENOMEM;
3363 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3364 if (!slots)
914ebccd 3365 goto out;
b050b015
MT		 3366 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3367 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3368 slots->generation++;
b050b015
MT		 3369
3370 old_slots = kvm->memslots;
3371 rcu_assign_pointer(kvm->memslots, slots);
3372 synchronize_srcu_expedited(&kvm->srcu);
3373 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3374 kfree(old_slots);
914ebccd 3375
edde99ce
MT		 3376 spin_lock(&kvm->mmu_lock);
3377 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3378 spin_unlock(&kvm->mmu_lock);
3379
914ebccd 3380 r = -EFAULT;
515a0127 3381 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3382 goto out;
914ebccd
TY		 3383 } else {
3384 r = -EFAULT;
3385 if (clear_user(log->dirty_bitmap, n))
3386 goto out;
5bb064dc 3387 }
b050b015 3388
5bb064dc
ZX		 3389 r = 0;
3390out:
79fac95e 3391 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3392 return r;
3393}
3394
1fe779f8
CO		 3395long kvm_arch_vm_ioctl(struct file *filp,
3396 unsigned int ioctl, unsigned long arg)
3397{
3398 struct kvm *kvm = filp->private_data;
3399 void __user *argp = (void __user *)arg;
367e1319 3400 int r = -ENOTTY;
f0d66275
DH		 3401 /*
3402 * This union makes it completely explicit to gcc-3.x
3403 * that these two variables' stack usage should be
3404 * combined, not added together.
3405 */
3406 union {
3407 struct kvm_pit_state ps;
e9f42757 3408 struct kvm_pit_state2 ps2;
c5ff41ce 3409 struct kvm_pit_config pit_config;
f0d66275 3410 } u;
1fe779f8
CO		 3411
3412 switch (ioctl) {
3413 case KVM_SET_TSS_ADDR:
3414 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3415 if (r < 0)
3416 goto out;
3417 break;
b927a3ce
SY		 3418 case KVM_SET_IDENTITY_MAP_ADDR: {
3419 u64 ident_addr;
3420
3421 r = -EFAULT;
3422 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3423 goto out;
3424 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3425 if (r < 0)
3426 goto out;
3427 break;
3428 }
1fe779f8
CO		 3429 case KVM_SET_NR_MMU_PAGES:
3430 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3431 if (r)
3432 goto out;
3433 break;
3434 case KVM_GET_NR_MMU_PAGES:
3435 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3436 break;
3ddea128
MT		 3437 case KVM_CREATE_IRQCHIP: {
3438 struct kvm_pic *vpic;
3439
3440 mutex_lock(&kvm->lock);
3441 r = -EEXIST;
3442 if (kvm->arch.vpic)
3443 goto create_irqchip_unlock;
1fe779f8 3444 r = -ENOMEM;
3ddea128
MT		 3445 vpic = kvm_create_pic(kvm);
3446 if (vpic) {
1fe779f8
CO		 3447 r = kvm_ioapic_init(kvm);
3448 if (r) {
175504cd 3449 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3450 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3451 &vpic->dev);
175504cd 3452 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3453 kfree(vpic);
3454 goto create_irqchip_unlock;
1fe779f8
CO		 3455 }
3456 } else
3ddea128
MT		 3457 goto create_irqchip_unlock;
3458 smp_wmb();
3459 kvm->arch.vpic = vpic;
3460 smp_wmb();
399ec807
AK		 3461 r = kvm_setup_default_irq_routing(kvm);
3462 if (r) {
175504cd 3463 mutex_lock(&kvm->slots_lock);
3ddea128 3464 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3465 kvm_ioapic_destroy(kvm);
3466 kvm_destroy_pic(kvm);
3ddea128 3467 mutex_unlock(&kvm->irq_lock);
175504cd 3468 mutex_unlock(&kvm->slots_lock);
399ec807 3469 }
3ddea128
MT		 3470 create_irqchip_unlock:
3471 mutex_unlock(&kvm->lock);
1fe779f8 3472 break;
3ddea128 3473 }
7837699f 3474 case KVM_CREATE_PIT:
c5ff41ce
JK		 3475 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3476 goto create_pit;
3477 case KVM_CREATE_PIT2:
3478 r = -EFAULT;
3479 if (copy_from_user(&u.pit_config, argp,
3480 sizeof(struct kvm_pit_config)))
3481 goto out;
3482 create_pit:
79fac95e 3483 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3484 r = -EEXIST;
3485 if (kvm->arch.vpit)
3486 goto create_pit_unlock;
7837699f 3487 r = -ENOMEM;
c5ff41ce 3488 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3489 if (kvm->arch.vpit)
3490 r = 0;
269e05e4 3491 create_pit_unlock:
79fac95e 3492 mutex_unlock(&kvm->slots_lock);
7837699f 3493 break;
4925663a 3494 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3495 case KVM_IRQ_LINE: {
3496 struct kvm_irq_level irq_event;
3497
3498 r = -EFAULT;
3499 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3500 goto out;
160d2f6c 3501 r = -ENXIO;
1fe779f8 3502 if (irqchip_in_kernel(kvm)) {
4925663a 3503 __s32 status;
4925663a
GN		 3504 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3505 irq_event.irq, irq_event.level);
4925663a 3506 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3507 r = -EFAULT;
4925663a
GN		 3508 irq_event.status = status;
3509 if (copy_to_user(argp, &irq_event,
3510 sizeof irq_event))
3511 goto out;
3512 }
1fe779f8
CO		 3513 r = 0;
3514 }
3515 break;
3516 }
3517 case KVM_GET_IRQCHIP: {
3518 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3519 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3520
f0d66275
DH		 3521 r = -ENOMEM;
3522 if (!chip)
1fe779f8 3523 goto out;
f0d66275
DH		 3524 r = -EFAULT;
3525 if (copy_from_user(chip, argp, sizeof *chip))
3526 goto get_irqchip_out;
1fe779f8
CO		 3527 r = -ENXIO;
3528 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3529 goto get_irqchip_out;
3530 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3531 if (r)
f0d66275 3532 goto get_irqchip_out;
1fe779f8 3533 r = -EFAULT;
f0d66275
DH		 3534 if (copy_to_user(argp, chip, sizeof *chip))
3535 goto get_irqchip_out;
1fe779f8 3536 r = 0;
f0d66275
DH		 3537 get_irqchip_out:
3538 kfree(chip);
3539 if (r)
3540 goto out;
1fe779f8
CO		 3541 break;
3542 }
3543 case KVM_SET_IRQCHIP: {
3544 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3545 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3546
f0d66275
DH		 3547 r = -ENOMEM;
3548 if (!chip)
1fe779f8 3549 goto out;
f0d66275
DH		 3550 r = -EFAULT;
3551 if (copy_from_user(chip, argp, sizeof *chip))
3552 goto set_irqchip_out;
1fe779f8
CO		 3553 r = -ENXIO;
3554 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3555 goto set_irqchip_out;
3556 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3557 if (r)
f0d66275 3558 goto set_irqchip_out;
1fe779f8 3559 r = 0;
f0d66275
DH		 3560 set_irqchip_out:
3561 kfree(chip);
3562 if (r)
3563 goto out;
1fe779f8
CO		 3564 break;
3565 }
e0f63cb9 3566 case KVM_GET_PIT: {
e0f63cb9 3567 r = -EFAULT;
f0d66275 3568 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3569 goto out;
3570 r = -ENXIO;
3571 if (!kvm->arch.vpit)
3572 goto out;
f0d66275 3573 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3574 if (r)
3575 goto out;
3576 r = -EFAULT;
f0d66275 3577 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3578 goto out;
3579 r = 0;
3580 break;
3581 }
3582 case KVM_SET_PIT: {
e0f63cb9 3583 r = -EFAULT;
f0d66275 3584 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3585 goto out;
3586 r = -ENXIO;
3587 if (!kvm->arch.vpit)
3588 goto out;
f0d66275 3589 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3590 if (r)
3591 goto out;
3592 r = 0;
3593 break;
3594 }
e9f42757
BK		 3595 case KVM_GET_PIT2: {
3596 r = -ENXIO;
3597 if (!kvm->arch.vpit)
3598 goto out;
3599 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3600 if (r)
3601 goto out;
3602 r = -EFAULT;
3603 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3604 goto out;
3605 r = 0;
3606 break;
3607 }
3608 case KVM_SET_PIT2: {
3609 r = -EFAULT;
3610 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3611 goto out;
3612 r = -ENXIO;
3613 if (!kvm->arch.vpit)
3614 goto out;
3615 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3616 if (r)
3617 goto out;
3618 r = 0;
3619 break;
3620 }
52d939a0
MT		 3621 case KVM_REINJECT_CONTROL: {
3622 struct kvm_reinject_control control;
3623 r = -EFAULT;
3624 if (copy_from_user(&control, argp, sizeof(control)))
3625 goto out;
3626 r = kvm_vm_ioctl_reinject(kvm, &control);
3627 if (r)
3628 goto out;
3629 r = 0;
3630 break;
3631 }
ffde22ac
ES		 3632 case KVM_XEN_HVM_CONFIG: {
3633 r = -EFAULT;
3634 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3635 sizeof(struct kvm_xen_hvm_config)))
3636 goto out;
3637 r = -EINVAL;
3638 if (kvm->arch.xen_hvm_config.flags)
3639 goto out;
3640 r = 0;
3641 break;
3642 }
afbcf7ab 3643 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3644 struct kvm_clock_data user_ns;
3645 u64 now_ns;
3646 s64 delta;
3647
3648 r = -EFAULT;
3649 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3650 goto out;
3651
3652 r = -EINVAL;
3653 if (user_ns.flags)
3654 goto out;
3655
3656 r = 0;
395c6b0a 3657 local_irq_disable();
759379dd 3658 now_ns = get_kernel_ns();
afbcf7ab 3659 delta = user_ns.clock - now_ns;
395c6b0a 3660 local_irq_enable();
afbcf7ab
GC		 3661 kvm->arch.kvmclock_offset = delta;
3662 break;
3663 }
3664 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3665 struct kvm_clock_data user_ns;
3666 u64 now_ns;
3667
395c6b0a 3668 local_irq_disable();
759379dd 3669 now_ns = get_kernel_ns();
afbcf7ab 3670 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3671 local_irq_enable();
afbcf7ab 3672 user_ns.flags = 0;
97e69aa6 3673 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3674
3675 r = -EFAULT;
3676 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3677 goto out;
3678 r = 0;
3679 break;
3680 }
3681
1fe779f8
CO		 3682 default:
3683 ;
3684 }
3685out:
3686 return r;
3687}
3688
a16b043c 3689static void kvm_init_msr_list(void)
043405e1
CO		 3690{
3691 u32 dummy[2];
3692 unsigned i, j;
3693
e3267cbb
GC		 3694 /* skip the first msrs in the list. KVM-specific */
3695 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3696 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3697 continue;
3698 if (j < i)
3699 msrs_to_save[j] = msrs_to_save[i];
3700 j++;
3701 }
3702 num_msrs_to_save = j;
3703}
3704
bda9020e
MT		 3705static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3706 const void *v)
bbd9b64e 3707{
70252a10
AK		 3708 int handled = 0;
3709 int n;
3710
3711 do {
3712 n = min(len, 8);
3713 if (!(vcpu->arch.apic &&
3714 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3715 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3716 break;
3717 handled += n;
3718 addr += n;
3719 len -= n;
3720 v += n;
3721 } while (len);
bbd9b64e 3722
70252a10 3723 return handled;
bbd9b64e
CO		 3724}
3725
bda9020e 3726static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3727{
70252a10
AK		 3728 int handled = 0;
3729 int n;
3730
3731 do {
3732 n = min(len, 8);
3733 if (!(vcpu->arch.apic &&
3734 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3735 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3736 break;
3737 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3738 handled += n;
3739 addr += n;
3740 len -= n;
3741 v += n;
3742 } while (len);
bbd9b64e 3743
70252a10 3744 return handled;
bbd9b64e
CO		 3745}
3746
2dafc6c2
GN		 3747static void kvm_set_segment(struct kvm_vcpu *vcpu,
3748 struct kvm_segment *var, int seg)
3749{
3750 kvm_x86_ops->set_segment(vcpu, var, seg);
3751}
3752
3753void kvm_get_segment(struct kvm_vcpu *vcpu,
3754 struct kvm_segment *var, int seg)
3755{
3756 kvm_x86_ops->get_segment(vcpu, var, seg);
3757}
3758
c30a358d
JR		 3759static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3760{
3761 return gpa;
3762}
3763
02f59dc9
JR		 3764static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3765{
3766 gpa_t t_gpa;
ab9ae313 3767 struct x86_exception exception;
02f59dc9
JR		 3768
3769 BUG_ON(!mmu_is_nested(vcpu));
3770
3771 /* NPT walks are always user-walks */
3772 access |= PFERR_USER_MASK;
ab9ae313 3773 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3774
3775 return t_gpa;
3776}
3777
ab9ae313
AK		 3778gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3779 struct x86_exception *exception)
1871c602
GN		 3780{
3781 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3782 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3783}
3784
ab9ae313
AK		 3785 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3786 struct x86_exception *exception)
1871c602
GN		 3787{
3788 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3789 access |= PFERR_FETCH_MASK;
ab9ae313 3790 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3791}
3792
ab9ae313
AK		 3793gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3794 struct x86_exception *exception)
1871c602
GN		 3795{
3796 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3797 access |= PFERR_WRITE_MASK;
ab9ae313 3798 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3799}
3800
3801/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3802gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3803 struct x86_exception *exception)
1871c602 3804{
ab9ae313 3805 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3806}
3807
3808static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3809 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3810 struct x86_exception *exception)
bbd9b64e
CO		 3811{
3812 void *data = val;
10589a46 3813 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3814
3815 while (bytes) {
14dfe855 3816 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3817 exception);
bbd9b64e 3818 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3819 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3820 int ret;
3821
bcc55cba 3822 if (gpa == UNMAPPED_GVA)
ab9ae313 3823 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3824 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3825 if (ret < 0) {
c3cd7ffa 3826 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3827 goto out;
3828 }
bbd9b64e 3829
77c2002e
IE		 3830 bytes -= toread;
3831 data += toread;
3832 addr += toread;
bbd9b64e 3833 }
10589a46 3834out:
10589a46 3835 return r;
bbd9b64e 3836}
77c2002e 3837
1871c602 3838/* used for instruction fetching */
0f65dd70
AK		 3839static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3840 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3841 struct x86_exception *exception)
1871c602 3842{
0f65dd70 3843 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3844 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3845
1871c602 3846 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3847 access | PFERR_FETCH_MASK,
3848 exception);
1871c602
GN		 3849}
3850
0f65dd70
AK		 3851static int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3852 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3853 struct x86_exception *exception)
1871c602 3854{
0f65dd70 3855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3856 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3857
1871c602 3858 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3859 exception);
1871c602
GN		 3860}
3861
0f65dd70
AK		 3862static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3863 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3864 struct x86_exception *exception)
1871c602 3865{
0f65dd70 3866 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3867 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3868}
3869
0f65dd70
AK		 3870static int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3871 gva_t addr, void *val,
2dafc6c2 3872 unsigned int bytes,
bcc55cba 3873 struct x86_exception *exception)
77c2002e 3874{
0f65dd70 3875 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3876 void *data = val;
3877 int r = X86EMUL_CONTINUE;
3878
3879 while (bytes) {
14dfe855
JR		 3880 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3881 PFERR_WRITE_MASK,
ab9ae313 3882 exception);
77c2002e
IE		 3883 unsigned offset = addr & (PAGE_SIZE-1);
3884 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3885 int ret;
3886
bcc55cba 3887 if (gpa == UNMAPPED_GVA)
ab9ae313 3888 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3889 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3890 if (ret < 0) {
c3cd7ffa 3891 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3892 goto out;
3893 }
3894
3895 bytes -= towrite;
3896 data += towrite;
3897 addr += towrite;
3898 }
3899out:
3900 return r;
3901}
3902
0f65dd70
AK		 3903static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3904 unsigned long addr,
bbd9b64e
CO		 3905 void *val,
3906 unsigned int bytes,
0f65dd70 3907 struct x86_exception *exception)
bbd9b64e 3908{
0f65dd70 3909 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bbd9b64e 3910 gpa_t gpa;
70252a10 3911 int handled;
bbd9b64e
CO		 3912
3913 if (vcpu->mmio_read_completed) {
3914 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3915 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3916 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3917 vcpu->mmio_read_completed = 0;
3918 return X86EMUL_CONTINUE;
3919 }
3920
ab9ae313 3921 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3922
8fe681e9 3923 if (gpa == UNMAPPED_GVA)
1871c602 3924 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3925
3926 /* For APIC access vmexit */
3927 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3928 goto mmio;
3929
0f65dd70 3930 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 3931 == X86EMUL_CONTINUE)
bbd9b64e 3932 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3933
3934mmio:
3935 /*
3936 * Is this MMIO handled locally?
3937 */
70252a10
AK		 3938 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3939
3940 if (handled == bytes)
bbd9b64e 3941 return X86EMUL_CONTINUE;
70252a10
AK		 3942
3943 gpa += handled;
3944 bytes -= handled;
3945 val += handled;
aec51dc4
AK		 3946
3947 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3948
3949 vcpu->mmio_needed = 1;
411c35b7
GN		 3950 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3951 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3952 vcpu->mmio_size = bytes;
3953 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3954 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3955 vcpu->mmio_index = 0;
bbd9b64e 3956
c3cd7ffa 3957 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3958}
3959
3200f405 3960int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3961 const void *val, int bytes)
bbd9b64e
CO		 3962{
3963 int ret;
3964
3965 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3966 if (ret < 0)
bbd9b64e 3967 return 0;
ad218f85 3968 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3969 return 1;
3970}
3971
3972static int emulator_write_emulated_onepage(unsigned long addr,
3973 const void *val,
3974 unsigned int bytes,
bcc55cba 3975 struct x86_exception *exception,
bbd9b64e
CO		 3976 struct kvm_vcpu *vcpu)
3977{
10589a46 3978 gpa_t gpa;
70252a10 3979 int handled;
10589a46 3980
ab9ae313 3981 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3982
8fe681e9 3983 if (gpa == UNMAPPED_GVA)
bbd9b64e 3984 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3985
3986 /* For APIC access vmexit */
3987 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3988 goto mmio;
3989
3990 if (emulator_write_phys(vcpu, gpa, val, bytes))
3991 return X86EMUL_CONTINUE;
3992
3993mmio:
aec51dc4 3994 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3995 /*
3996 * Is this MMIO handled locally?
3997 */
70252a10
AK		 3998 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3999 if (handled == bytes)
bbd9b64e 4000 return X86EMUL_CONTINUE;
bbd9b64e 4001
70252a10
AK		 4002 gpa += handled;
4003 bytes -= handled;
4004 val += handled;
4005
bbd9b64e 4006 vcpu->mmio_needed = 1;
cef4dea0 4007 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 4008 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4009 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4010 vcpu->mmio_size = bytes;
4011 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 4012 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 4013 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4014 vcpu->mmio_index = 0;
bbd9b64e
CO		 4015
4016 return X86EMUL_CONTINUE;
4017}
4018
0f65dd70
AK		 4019int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4020 unsigned long addr,
8f6abd06
GN		 4021 const void *val,
4022 unsigned int bytes,
0f65dd70 4023 struct x86_exception *exception)
bbd9b64e 4024{
0f65dd70
AK		 4025 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4026
bbd9b64e
CO		 4027 /* Crossing a page boundary? */
4028 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4029 int rc, now;
4030
4031 now = -addr & ~PAGE_MASK;
bcc55cba 4032 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 4033 vcpu);
bbd9b64e
CO		 4034 if (rc != X86EMUL_CONTINUE)
4035 return rc;
4036 addr += now;
4037 val += now;
4038 bytes -= now;
4039 }
bcc55cba 4040 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 4041 vcpu);
bbd9b64e 4042}
bbd9b64e 4043
daea3e73
AK		 4044#define CMPXCHG_TYPE(t, ptr, old, new) \
4045 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4046
4047#ifdef CONFIG_X86_64
4048# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4049#else
4050# define CMPXCHG64(ptr, old, new) \
9749a6c0 4051 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4052#endif
4053
0f65dd70
AK		 4054static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4055 unsigned long addr,
bbd9b64e
CO		 4056 const void *old,
4057 const void *new,
4058 unsigned int bytes,
0f65dd70 4059 struct x86_exception *exception)
bbd9b64e 4060{
0f65dd70 4061 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4062 gpa_t gpa;
4063 struct page *page;
4064 char *kaddr;
4065 bool exchanged;
2bacc55c 4066
daea3e73
AK		 4067 /* guests cmpxchg8b have to be emulated atomically */
4068 if (bytes > 8 || (bytes & (bytes - 1)))
4069 goto emul_write;
10589a46 4070
daea3e73 4071 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4072
daea3e73
AK		 4073 if (gpa == UNMAPPED_GVA ||
4074 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4075 goto emul_write;
2bacc55c 4076
daea3e73
AK		 4077 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4078 goto emul_write;
72dc67a6 4079
daea3e73 4080 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4081 if (is_error_page(page)) {
4082 kvm_release_page_clean(page);
4083 goto emul_write;
4084 }
72dc67a6 4085
daea3e73
AK		 4086 kaddr = kmap_atomic(page, KM_USER0);
4087 kaddr += offset_in_page(gpa);
4088 switch (bytes) {
4089 case 1:
4090 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4091 break;
4092 case 2:
4093 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4094 break;
4095 case 4:
4096 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4097 break;
4098 case 8:
4099 exchanged = CMPXCHG64(kaddr, old, new);
4100 break;
4101 default:
4102 BUG();
2bacc55c 4103 }
daea3e73
AK		 4104 kunmap_atomic(kaddr, KM_USER0);
4105 kvm_release_page_dirty(page);
4106
4107 if (!exchanged)
4108 return X86EMUL_CMPXCHG_FAILED;
4109
8f6abd06
GN		 4110 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4111
4112 return X86EMUL_CONTINUE;
4a5f48f6 4113
3200f405 4114emul_write:
daea3e73 4115 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4116
0f65dd70 4117 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4118}
4119
cf8f70bf
GN		 4120static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4121{
4122 /* TODO: String I/O for in kernel device */
4123 int r;
4124
4125 if (vcpu->arch.pio.in)
4126 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4127 vcpu->arch.pio.size, pd);
4128 else
4129 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4130 vcpu->arch.pio.port, vcpu->arch.pio.size,
4131 pd);
4132 return r;
4133}
4134
4135
ca1d4a9e
AK		 4136static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4137 int size, unsigned short port, void *val,
4138 unsigned int count)
cf8f70bf 4139{
ca1d4a9e
AK		 4140 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4141
7972995b 4142 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4143 goto data_avail;
4144
61cfab2e 4145 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4146
4147 vcpu->arch.pio.port = port;
4148 vcpu->arch.pio.in = 1;
7972995b 4149 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4150 vcpu->arch.pio.size = size;
4151
4152 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4153 data_avail:
4154 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4155 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4156 return 1;
4157 }
4158
4159 vcpu->run->exit_reason = KVM_EXIT_IO;
4160 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4161 vcpu->run->io.size = size;
4162 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4163 vcpu->run->io.count = count;
4164 vcpu->run->io.port = port;
4165
4166 return 0;
4167}
4168
ca1d4a9e
AK		 4169static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4170 int size, unsigned short port,
4171 const void *val, unsigned int count)
cf8f70bf 4172{
ca1d4a9e
AK		 4173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4174
61cfab2e 4175 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4176
4177 vcpu->arch.pio.port = port;
4178 vcpu->arch.pio.in = 0;
7972995b 4179 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4180 vcpu->arch.pio.size = size;
4181
4182 memcpy(vcpu->arch.pio_data, val, size * count);
4183
4184 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4185 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4186 return 1;
4187 }
4188
4189 vcpu->run->exit_reason = KVM_EXIT_IO;
4190 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4191 vcpu->run->io.size = size;
4192 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4193 vcpu->run->io.count = count;
4194 vcpu->run->io.port = port;
4195
4196 return 0;
4197}
4198
bbd9b64e
CO		 4199static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4200{
4201 return kvm_x86_ops->get_segment_base(vcpu, seg);
4202}
4203
3cb16fe7 4204static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4205{
3cb16fe7 4206 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4207}
4208
f5f48ee1
SY		 4209int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4210{
4211 if (!need_emulate_wbinvd(vcpu))
4212 return X86EMUL_CONTINUE;
4213
4214 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4215 int cpu = get_cpu();
4216
4217 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4218 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4219 wbinvd_ipi, NULL, 1);
2eec7343 4220 put_cpu();
f5f48ee1 4221 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4222 } else
4223 wbinvd();
f5f48ee1
SY		 4224 return X86EMUL_CONTINUE;
4225}
4226EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4227
bcaf5cc5
AK		 4228static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4229{
4230 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4231}
4232
717746e3 4233int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4234{
717746e3 4235 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4236}
4237
717746e3 4238int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4239{
338dbc97 4240
717746e3 4241 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4242}
4243
52a46617 4244static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4245{
52a46617 4246 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4247}
4248
717746e3 4249static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4250{
717746e3 4251 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4252 unsigned long value;
4253
4254 switch (cr) {
4255 case 0:
4256 value = kvm_read_cr0(vcpu);
4257 break;
4258 case 2:
4259 value = vcpu->arch.cr2;
4260 break;
4261 case 3:
9f8fe504 4262 value = kvm_read_cr3(vcpu);
52a46617
GN		 4263 break;
4264 case 4:
4265 value = kvm_read_cr4(vcpu);
4266 break;
4267 case 8:
4268 value = kvm_get_cr8(vcpu);
4269 break;
4270 default:
4271 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4272 return 0;
4273 }
4274
4275 return value;
4276}
4277
717746e3 4278static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4279{
717746e3 4280 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4281 int res = 0;
4282
52a46617
GN		 4283 switch (cr) {
4284 case 0:
49a9b07e 4285 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4286 break;
4287 case 2:
4288 vcpu->arch.cr2 = val;
4289 break;
4290 case 3:
2390218b 4291 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4292 break;
4293 case 4:
a83b29c6 4294 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4295 break;
4296 case 8:
eea1cff9 4297 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4298 break;
4299 default:
4300 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4301 res = -1;
52a46617 4302 }
0f12244f
GN		 4303
4304 return res;
52a46617
GN		 4305}
4306
717746e3 4307static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4308{
717746e3 4309 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4310}
4311
4bff1e86 4312static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4313{
4bff1e86 4314 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4315}
4316
4bff1e86 4317static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4318{
4bff1e86 4319 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4320}
4321
1ac9d0cf
AK		 4322static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4323{
4324 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4325}
4326
4327static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4328{
4329 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4330}
4331
4bff1e86
AK		 4332static unsigned long emulator_get_cached_segment_base(
4333 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4334{
4bff1e86 4335 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4336}
4337
1aa36616
AK		 4338static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4339 struct desc_struct *desc, u32 *base3,
4340 int seg)
2dafc6c2
GN		 4341{
4342 struct kvm_segment var;
4343
4bff1e86 4344 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4345 *selector = var.selector;
2dafc6c2
GN		 4346
4347 if (var.unusable)
4348 return false;
4349
4350 if (var.g)
4351 var.limit >>= 12;
4352 set_desc_limit(desc, var.limit);
4353 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4354#ifdef CONFIG_X86_64
4355 if (base3)
4356 *base3 = var.base >> 32;
4357#endif
2dafc6c2
GN		 4358 desc->type = var.type;
4359 desc->s = var.s;
4360 desc->dpl = var.dpl;
4361 desc->p = var.present;
4362 desc->avl = var.avl;
4363 desc->l = var.l;
4364 desc->d = var.db;
4365 desc->g = var.g;
4366
4367 return true;
4368}
4369
1aa36616
AK		 4370static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4371 struct desc_struct *desc, u32 base3,
4372 int seg)
2dafc6c2 4373{
4bff1e86 4374 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4375 struct kvm_segment var;
4376
1aa36616 4377 var.selector = selector;
2dafc6c2 4378 var.base = get_desc_base(desc);
5601d05b
GN		 4379#ifdef CONFIG_X86_64
4380 var.base |= ((u64)base3) << 32;
4381#endif
2dafc6c2
GN		 4382 var.limit = get_desc_limit(desc);
4383 if (desc->g)
4384 var.limit = (var.limit << 12) | 0xfff;
4385 var.type = desc->type;
4386 var.present = desc->p;
4387 var.dpl = desc->dpl;
4388 var.db = desc->d;
4389 var.s = desc->s;
4390 var.l = desc->l;
4391 var.g = desc->g;
4392 var.avl = desc->avl;
4393 var.present = desc->p;
4394 var.unusable = !var.present;
4395 var.padding = 0;
4396
4397 kvm_set_segment(vcpu, &var, seg);
4398 return;
4399}
4400
717746e3
AK		 4401static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4402 u32 msr_index, u64 *pdata)
4403{
4404 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4405}
4406
4407static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4408 u32 msr_index, u64 data)
4409{
4410 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4411}
4412
6c3287f7
AK		 4413static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4414{
4415 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4416}
4417
5037f6f3
AK		 4418static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4419{
4420 preempt_disable();
5197b808 4421 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4422 /*
4423 * CR0.TS may reference the host fpu state, not the guest fpu state,
4424 * so it may be clear at this point.
4425 */
4426 clts();
4427}
4428
4429static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4430{
4431 preempt_enable();
4432}
4433
2953538e 4434static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4435 struct x86_instruction_info *info,
c4f035c6
AK		 4436 enum x86_intercept_stage stage)
4437{
2953538e 4438 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4439}
4440
14af3f3c 4441static struct x86_emulate_ops emulate_ops = {
1871c602 4442 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4443 .write_std = kvm_write_guest_virt_system,
1871c602 4444 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4445 .read_emulated = emulator_read_emulated,
4446 .write_emulated = emulator_write_emulated,
4447 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4448 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4449 .pio_in_emulated = emulator_pio_in_emulated,
4450 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4451 .get_segment = emulator_get_segment,
4452 .set_segment = emulator_set_segment,
5951c442 4453 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4454 .get_gdt = emulator_get_gdt,
160ce1f1 4455 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4456 .set_gdt = emulator_set_gdt,
4457 .set_idt = emulator_set_idt,
52a46617
GN		 4458 .get_cr = emulator_get_cr,
4459 .set_cr = emulator_set_cr,
9c537244 4460 .cpl = emulator_get_cpl,
35aa5375
GN		 4461 .get_dr = emulator_get_dr,
4462 .set_dr = emulator_set_dr,
717746e3
AK		 4463 .set_msr = emulator_set_msr,
4464 .get_msr = emulator_get_msr,
6c3287f7 4465 .halt = emulator_halt,
bcaf5cc5 4466 .wbinvd = emulator_wbinvd,
d6aa1000 4467 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4468 .get_fpu = emulator_get_fpu,
4469 .put_fpu = emulator_put_fpu,
c4f035c6 4470 .intercept = emulator_intercept,
bbd9b64e
CO		 4471};
4472
5fdbf976
MT		 4473static void cache_all_regs(struct kvm_vcpu *vcpu)
4474{
4475 kvm_register_read(vcpu, VCPU_REGS_RAX);
4476 kvm_register_read(vcpu, VCPU_REGS_RSP);
4477 kvm_register_read(vcpu, VCPU_REGS_RIP);
4478 vcpu->arch.regs_dirty = ~0;
4479}
4480
95cb2295
GN		 4481static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4482{
4483 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4484 /*
4485 * an sti; sti; sequence only disable interrupts for the first
4486 * instruction. So, if the last instruction, be it emulated or
4487 * not, left the system with the INT_STI flag enabled, it
4488 * means that the last instruction is an sti. We should not
4489 * leave the flag on in this case. The same goes for mov ss
4490 */
4491 if (!(int_shadow & mask))
4492 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4493}
4494
54b8486f
GN		 4495static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4496{
4497 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4498 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4499 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4500 else if (ctxt->exception.error_code_valid)
4501 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4502 ctxt->exception.error_code);
54b8486f 4503 else
da9cb575 4504 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4505}
4506
b5c9ff73
TY		 4507static void init_decode_cache(struct decode_cache *c,
4508 const unsigned long *regs)
4509{
4510 memset(c, 0, offsetof(struct decode_cache, regs));
4511 memcpy(c->regs, regs, sizeof(c->regs));
4512
4513 c->fetch.start = 0;
4514 c->fetch.end = 0;
4515 c->io_read.pos = 0;
4516 c->io_read.end = 0;
4517 c->mem_read.pos = 0;
4518 c->mem_read.end = 0;
4519}
4520
8ec4722d
MG		 4521static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4522{
adf52235
TY		 4523 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4524 struct decode_cache *c = &ctxt->decode;
8ec4722d
MG		 4525 int cs_db, cs_l;
4526
2aab2c5b
GN		 4527 /*
4528 * TODO: fix emulate.c to use guest_read/write_register
4529 * instead of direct ->regs accesses, can save hundred cycles
4530 * on Intel for instructions that don't read/change RSP, for
4531 * for example.
4532 */
8ec4722d
MG		 4533 cache_all_regs(vcpu);
4534
4535 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4536
adf52235
TY		 4537 ctxt->eflags = kvm_get_rflags(vcpu);
4538 ctxt->eip = kvm_rip_read(vcpu);
4539 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4540 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4541 cs_l ? X86EMUL_MODE_PROT64 :
4542 cs_db ? X86EMUL_MODE_PROT32 :
4543 X86EMUL_MODE_PROT16;
4544 ctxt->guest_mode = is_guest_mode(vcpu);
4545
b5c9ff73 4546 init_decode_cache(c, vcpu->arch.regs);
7ae441ea 4547 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4548}
4549
71f9833b 4550int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653
MG		 4551{
4552 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4553 int ret;
4554
4555 init_emulate_ctxt(vcpu);
4556
4557 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4558 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
71f9833b
SH		 4559 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip +
4560 inc_eip;
7b105ca2 4561 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, irq);
63995653
MG		 4562
4563 if (ret != X86EMUL_CONTINUE)
4564 return EMULATE_FAIL;
4565
4566 vcpu->arch.emulate_ctxt.eip = c->eip;
4567 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4568 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4569 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4570
4571 if (irq == NMI_VECTOR)
4572 vcpu->arch.nmi_pending = false;
4573 else
4574 vcpu->arch.interrupt.pending = false;
4575
4576 return EMULATE_DONE;
4577}
4578EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4579
6d77dbfc
GN		 4580static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4581{
fc3a9157
JR		 4582 int r = EMULATE_DONE;
4583
6d77dbfc
GN		 4584 ++vcpu->stat.insn_emulation_fail;
4585 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4586 if (!is_guest_mode(vcpu)) {
4587 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4588 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4589 vcpu->run->internal.ndata = 0;
4590 r = EMULATE_FAIL;
4591 }
6d77dbfc 4592 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4593
4594 return r;
6d77dbfc
GN		 4595}
4596
a6f177ef
GN		 4597static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4598{
4599 gpa_t gpa;
4600
68be0803
GN		 4601 if (tdp_enabled)
4602 return false;
4603
a6f177ef
GN		 4604 /*
4605 * if emulation was due to access to shadowed page table
4606 * and it failed try to unshadow page and re-entetr the
4607 * guest to let CPU execute the instruction.
4608 */
4609 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4610 return true;
4611
4612 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4613
4614 if (gpa == UNMAPPED_GVA)
4615 return true; /* let cpu generate fault */
4616
4617 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4618 return true;
4619
4620 return false;
4621}
4622
51d8b661
AP		 4623int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4624 unsigned long cr2,
dc25e89e
AP		 4625 int emulation_type,
4626 void *insn,
4627 int insn_len)
bbd9b64e 4628{
95cb2295 4629 int r;
4d2179e1 4630 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
7ae441ea 4631 bool writeback = true;
bbd9b64e 4632
26eef70c 4633 kvm_clear_exception_queue(vcpu);
8d7d8102 4634
571008da 4635 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4636 init_emulate_ctxt(vcpu);
95cb2295 4637 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4638 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4639 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4640
4005996e
AK		 4641 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4642 = emulation_type & EMULTYPE_TRAP_UD;
4643
dc25e89e 4644 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4645
e46479f8 4646 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4647 ++vcpu->stat.insn_emulation;
bbd9b64e 4648 if (r) {
4005996e
AK		 4649 if (emulation_type & EMULTYPE_TRAP_UD)
4650 return EMULATE_FAIL;
a6f177ef 4651 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4652 return EMULATE_DONE;
6d77dbfc
GN		 4653 if (emulation_type & EMULTYPE_SKIP)
4654 return EMULATE_FAIL;
4655 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4656 }
4657 }
4658
ba8afb6b
GN		 4659 if (emulation_type & EMULTYPE_SKIP) {
4660 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4661 return EMULATE_DONE;
4662 }
4663
7ae441ea 4664 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4665 changes registers values during IO operation */
7ae441ea
GN		 4666 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4667 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4668 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4669 }
4d2179e1 4670
5cd21917 4671restart:
9aabc88f 4672 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4673
775fde86
JR		 4674 if (r == EMULATION_INTERCEPTED)
4675 return EMULATE_DONE;
4676
d2ddd1c4 4677 if (r == EMULATION_FAILED) {
a6f177ef 4678 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4679 return EMULATE_DONE;
4680
6d77dbfc 4681 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4682 }
4683
da9cb575 4684 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4685 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4686 r = EMULATE_DONE;
4687 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4688 if (!vcpu->arch.pio.in)
4689 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4690 else
4691 writeback = false;
e85d28f8 4692 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4693 } else if (vcpu->mmio_needed) {
4694 if (!vcpu->mmio_is_write)
4695 writeback = false;
e85d28f8 4696 r = EMULATE_DO_MMIO;
7ae441ea 4697 } else if (r == EMULATION_RESTART)
5cd21917 4698 goto restart;
d2ddd1c4
GN		 4699 else
4700 r = EMULATE_DONE;
f850e2e6 4701
7ae441ea
GN		 4702 if (writeback) {
4703 toggle_interruptibility(vcpu,
4704 vcpu->arch.emulate_ctxt.interruptibility);
4705 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4706 kvm_make_request(KVM_REQ_EVENT, vcpu);
4707 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4708 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4709 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4710 } else
4711 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4712
4713 return r;
de7d789a 4714}
51d8b661 4715EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4716
cf8f70bf 4717int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4718{
cf8f70bf 4719 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4720 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4721 size, port, &val, 1);
cf8f70bf 4722 /* do not return to emulator after return from userspace */
7972995b 4723 vcpu->arch.pio.count = 0;
de7d789a
CO		 4724 return ret;
4725}
cf8f70bf 4726EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4727
8cfdc000
ZA		 4728static void tsc_bad(void *info)
4729{
0a3aee0d 4730 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4731}
4732
4733static void tsc_khz_changed(void *data)
c8076604 4734{
8cfdc000
ZA		 4735 struct cpufreq_freqs *freq = data;
4736 unsigned long khz = 0;
4737
4738 if (data)
4739 khz = freq->new;
4740 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4741 khz = cpufreq_quick_get(raw_smp_processor_id());
4742 if (!khz)
4743 khz = tsc_khz;
0a3aee0d 4744 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4745}
4746
c8076604
GH		 4747static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4748 void *data)
4749{
4750 struct cpufreq_freqs *freq = data;
4751 struct kvm *kvm;
4752 struct kvm_vcpu *vcpu;
4753 int i, send_ipi = 0;
4754
8cfdc000
ZA		 4755 /*
4756 * We allow guests to temporarily run on slowing clocks,
4757 * provided we notify them after, or to run on accelerating
4758 * clocks, provided we notify them before. Thus time never
4759 * goes backwards.
4760 *
4761 * However, we have a problem. We can't atomically update
4762 * the frequency of a given CPU from this function; it is
4763 * merely a notifier, which can be called from any CPU.
4764 * Changing the TSC frequency at arbitrary points in time
4765 * requires a recomputation of local variables related to
4766 * the TSC for each VCPU. We must flag these local variables
4767 * to be updated and be sure the update takes place with the
4768 * new frequency before any guests proceed.
4769 *
4770 * Unfortunately, the combination of hotplug CPU and frequency
4771 * change creates an intractable locking scenario; the order
4772 * of when these callouts happen is undefined with respect to
4773 * CPU hotplug, and they can race with each other. As such,
4774 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4775 * undefined; you can actually have a CPU frequency change take
4776 * place in between the computation of X and the setting of the
4777 * variable. To protect against this problem, all updates of
4778 * the per_cpu tsc_khz variable are done in an interrupt
4779 * protected IPI, and all callers wishing to update the value
4780 * must wait for a synchronous IPI to complete (which is trivial
4781 * if the caller is on the CPU already). This establishes the
4782 * necessary total order on variable updates.
4783 *
4784 * Note that because a guest time update may take place
4785 * anytime after the setting of the VCPU's request bit, the
4786 * correct TSC value must be set before the request. However,
4787 * to ensure the update actually makes it to any guest which
4788 * starts running in hardware virtualization between the set
4789 * and the acquisition of the spinlock, we must also ping the
4790 * CPU after setting the request bit.
4791 *
4792 */
4793
c8076604
GH		 4794 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4795 return 0;
4796 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4797 return 0;
8cfdc000
ZA		 4798
4799 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4800
e935b837 4801 raw_spin_lock(&kvm_lock);
c8076604 4802 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4803 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4804 if (vcpu->cpu != freq->cpu)
4805 continue;
c285545f 4806 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4807 if (vcpu->cpu != smp_processor_id())
8cfdc000 4808 send_ipi = 1;
c8076604
GH		 4809 }
4810 }
e935b837 4811 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4812
4813 if (freq->old < freq->new && send_ipi) {
4814 /*
4815 * We upscale the frequency. Must make the guest
4816 * doesn't see old kvmclock values while running with
4817 * the new frequency, otherwise we risk the guest sees
4818 * time go backwards.
4819 *
4820 * In case we update the frequency for another cpu
4821 * (which might be in guest context) send an interrupt
4822 * to kick the cpu out of guest context. Next time
4823 * guest context is entered kvmclock will be updated,
4824 * so the guest will not see stale values.
4825 */
8cfdc000 4826 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4827 }
4828 return 0;
4829}
4830
4831static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4832 .notifier_call = kvmclock_cpufreq_notifier
4833};
4834
4835static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4836 unsigned long action, void *hcpu)
4837{
4838 unsigned int cpu = (unsigned long)hcpu;
4839
4840 switch (action) {
4841 case CPU_ONLINE:
4842 case CPU_DOWN_FAILED:
4843 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4844 break;
4845 case CPU_DOWN_PREPARE:
4846 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4847 break;
4848 }
4849 return NOTIFY_OK;
4850}
4851
4852static struct notifier_block kvmclock_cpu_notifier_block = {
4853 .notifier_call = kvmclock_cpu_notifier,
4854 .priority = -INT_MAX
c8076604
GH		 4855};
4856
b820cc0c
ZA		 4857static void kvm_timer_init(void)
4858{
4859 int cpu;
4860
c285545f 4861 max_tsc_khz = tsc_khz;
8cfdc000 4862 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4863 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4864#ifdef CONFIG_CPU_FREQ
4865 struct cpufreq_policy policy;
4866 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4867 cpu = get_cpu();
4868 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4869 if (policy.cpuinfo.max_freq)
4870 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4871 put_cpu();
c285545f 4872#endif
b820cc0c
ZA		 4873 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4874 CPUFREQ_TRANSITION_NOTIFIER);
4875 }
c285545f 4876 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4877 for_each_online_cpu(cpu)
4878 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4879}
4880
ff9d07a0
ZY		 4881static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4882
4883static int kvm_is_in_guest(void)
4884{
4885 return percpu_read(current_vcpu) != NULL;
4886}
4887
4888static int kvm_is_user_mode(void)
4889{
4890 int user_mode = 3;
dcf46b94 4891
ff9d07a0
ZY		 4892 if (percpu_read(current_vcpu))
4893 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4894
ff9d07a0
ZY		 4895 return user_mode != 0;
4896}
4897
4898static unsigned long kvm_get_guest_ip(void)
4899{
4900 unsigned long ip = 0;
dcf46b94 4901
ff9d07a0
ZY		 4902 if (percpu_read(current_vcpu))
4903 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4904
ff9d07a0
ZY		 4905 return ip;
4906}
4907
4908static struct perf_guest_info_callbacks kvm_guest_cbs = {
4909 .is_in_guest = kvm_is_in_guest,
4910 .is_user_mode = kvm_is_user_mode,
4911 .get_guest_ip = kvm_get_guest_ip,
4912};
4913
4914void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4915{
4916 percpu_write(current_vcpu, vcpu);
4917}
4918EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4919
4920void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4921{
4922 percpu_write(current_vcpu, NULL);
4923}
4924EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4925
f8c16bba 4926int kvm_arch_init(void *opaque)
043405e1 4927{
b820cc0c 4928 int r;
f8c16bba
ZX		 4929 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4930
f8c16bba
ZX		 4931 if (kvm_x86_ops) {
4932 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4933 r = -EEXIST;
4934 goto out;
f8c16bba
ZX		 4935 }
4936
4937 if (!ops->cpu_has_kvm_support()) {
4938 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4939 r = -EOPNOTSUPP;
4940 goto out;
f8c16bba
ZX		 4941 }
4942 if (ops->disabled_by_bios()) {
4943 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4944 r = -EOPNOTSUPP;
4945 goto out;
f8c16bba
ZX		 4946 }
4947
97db56ce
AK		 4948 r = kvm_mmu_module_init();
4949 if (r)
4950 goto out;
4951
4952 kvm_init_msr_list();
4953
f8c16bba 4954 kvm_x86_ops = ops;
56c6d28a 4955 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4956 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4957 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4958
b820cc0c 4959 kvm_timer_init();
c8076604 4960
ff9d07a0
ZY		 4961 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4962
2acf923e
DC		 4963 if (cpu_has_xsave)
4964 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4965
f8c16bba 4966 return 0;
56c6d28a
ZX		 4967
4968out:
56c6d28a 4969 return r;
043405e1 4970}
8776e519 4971
f8c16bba
ZX		 4972void kvm_arch_exit(void)
4973{
ff9d07a0
ZY		 4974 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4975
888d256e
JK		 4976 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4977 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4978 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4979 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4980 kvm_x86_ops = NULL;
56c6d28a
ZX		 4981 kvm_mmu_module_exit();
4982}
f8c16bba 4983
8776e519
HB		 4984int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4985{
4986 ++vcpu->stat.halt_exits;
4987 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4988 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4989 return 1;
4990 } else {
4991 vcpu->run->exit_reason = KVM_EXIT_HLT;
4992 return 0;
4993 }
4994}
4995EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4996
2f333bcb
MT		 4997static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4998 unsigned long a1)
4999{
5000 if (is_long_mode(vcpu))
5001 return a0;
5002 else
5003 return a0 | ((gpa_t)a1 << 32);
5004}
5005
55cd8e5a
GN		 5006int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5007{
5008 u64 param, ingpa, outgpa, ret;
5009 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5010 bool fast, longmode;
5011 int cs_db, cs_l;
5012
5013 /*
5014 * hypercall generates UD from non zero cpl and real mode
5015 * per HYPER-V spec
5016 */
3eeb3288 5017 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5018 kvm_queue_exception(vcpu, UD_VECTOR);
5019 return 0;
5020 }
5021
5022 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5023 longmode = is_long_mode(vcpu) && cs_l == 1;
5024
5025 if (!longmode) {
ccd46936
GN		 5026 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5027 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5028 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5029 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5030 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5031 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5032 }
5033#ifdef CONFIG_X86_64
5034 else {
5035 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5036 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5037 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5038 }
5039#endif
5040
5041 code = param & 0xffff;
5042 fast = (param >> 16) & 0x1;
5043 rep_cnt = (param >> 32) & 0xfff;
5044 rep_idx = (param >> 48) & 0xfff;
5045
5046 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5047
c25bc163
GN		 5048 switch (code) {
5049 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5050 kvm_vcpu_on_spin(vcpu);
5051 break;
5052 default:
5053 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5054 break;
5055 }
55cd8e5a
GN		 5056
5057 ret = res | (((u64)rep_done & 0xfff) << 32);
5058 if (longmode) {
5059 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5060 } else {
5061 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5062 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5063 }
5064
5065 return 1;
5066}
5067
8776e519
HB		 5068int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5069{
5070 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5071 int r = 1;
8776e519 5072
55cd8e5a
GN		 5073 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5074 return kvm_hv_hypercall(vcpu);
5075
5fdbf976
MT		 5076 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5077 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5078 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5079 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5080 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5081
229456fc 5082 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5083
8776e519
HB		 5084 if (!is_long_mode(vcpu)) {
5085 nr &= 0xFFFFFFFF;
5086 a0 &= 0xFFFFFFFF;
5087 a1 &= 0xFFFFFFFF;
5088 a2 &= 0xFFFFFFFF;
5089 a3 &= 0xFFFFFFFF;
5090 }
5091
07708c4a
JK		 5092 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5093 ret = -KVM_EPERM;
5094 goto out;
5095 }
5096
8776e519 5097 switch (nr) {
b93463aa
AK		 5098 case KVM_HC_VAPIC_POLL_IRQ:
5099 ret = 0;
5100 break;
2f333bcb
MT		 5101 case KVM_HC_MMU_OP:
5102 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5103 break;
8776e519
HB		 5104 default:
5105 ret = -KVM_ENOSYS;
5106 break;
5107 }
07708c4a 5108out:
5fdbf976 5109 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5110 ++vcpu->stat.hypercalls;
2f333bcb 5111 return r;
8776e519
HB		 5112}
5113EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5114
d6aa1000 5115int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5116{
d6aa1000 5117 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5118 char instruction[3];
5fdbf976 5119 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5120
8776e519
HB		 5121 /*
5122 * Blow out the MMU to ensure that no other VCPU has an active mapping
5123 * to ensure that the updated hypercall appears atomically across all
5124 * VCPUs.
5125 */
5126 kvm_mmu_zap_all(vcpu->kvm);
5127
8776e519 5128 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5129
0f65dd70
AK		 5130 return emulator_write_emulated(&vcpu->arch.emulate_ctxt,
5131 rip, instruction, 3, NULL);
8776e519
HB		 5132}
5133
07716717
DK		 5134static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5135{
ad312c7c
ZX		 5136 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5137 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5138
5139 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5140 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5141 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5142 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5143 if (ej->function == e->function) {
5144 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5145 return j;
5146 }
5147 }
5148 return 0; /* silence gcc, even though control never reaches here */
5149}
5150
5151/* find an entry with matching function, matching index (if needed), and that
5152 * should be read next (if it's stateful) */
5153static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5154 u32 function, u32 index)
5155{
5156 if (e->function != function)
5157 return 0;
5158 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5159 return 0;
5160 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5161 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5162 return 0;
5163 return 1;
5164}
5165
d8017474
AG		 5166struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5167 u32 function, u32 index)
8776e519
HB		 5168{
5169 int i;
d8017474 5170 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5171
ad312c7c 5172 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5173 struct kvm_cpuid_entry2 *e;
5174
ad312c7c 5175 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5176 if (is_matching_cpuid_entry(e, function, index)) {
5177 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5178 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5179 best = e;
5180 break;
5181 }
8776e519 5182 }
d8017474
AG		 5183 return best;
5184}
0e851880 5185EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5186
82725b20
DE		 5187int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5188{
5189 struct kvm_cpuid_entry2 *best;
5190
f7a71197
AK		 5191 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5192 if (!best || best->eax < 0x80000008)
5193 goto not_found;
82725b20
DE		 5194 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5195 if (best)
5196 return best->eax & 0xff;
f7a71197 5197not_found:
82725b20
DE		 5198 return 36;
5199}
5200
bd22f5cf
AP		 5201/*
5202 * If no match is found, check whether we exceed the vCPU's limit
5203 * and return the content of the highest valid _standard_ leaf instead.
5204 * This is to satisfy the CPUID specification.
5205 */
5206static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5207 u32 function, u32 index)
5208{
5209 struct kvm_cpuid_entry2 *maxlevel;
5210
5211 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5212 if (!maxlevel || maxlevel->eax >= function)
5213 return NULL;
5214 if (function & 0x80000000) {
5215 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5216 if (!maxlevel)
5217 return NULL;
5218 }
5219 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5220}
5221
d8017474
AG		 5222void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5223{
5224 u32 function, index;
5225 struct kvm_cpuid_entry2 *best;
5226
5227 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5228 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5229 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5230 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5231 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5232 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5233 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5234
5235 if (!best)
5236 best = check_cpuid_limit(vcpu, function, index);
5237
8776e519 5238 if (best) {
5fdbf976
MT		 5239 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5240 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5241 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5242 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5243 }
8776e519 5244 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5245 trace_kvm_cpuid(function,
5246 kvm_register_read(vcpu, VCPU_REGS_RAX),
5247 kvm_register_read(vcpu, VCPU_REGS_RBX),
5248 kvm_register_read(vcpu, VCPU_REGS_RCX),
5249 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5250}
5251EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5252
b6c7a5dc
HB		 5253/*
5254 * Check if userspace requested an interrupt window, and that the
5255 * interrupt window is open.
5256 *
5257 * No need to exit to userspace if we already have an interrupt queued.
5258 */
851ba692 5259static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5260{
8061823a 5261 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5262 vcpu->run->request_interrupt_window &&
5df56646 5263 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5264}
5265
851ba692 5266static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5267{
851ba692
AK		 5268 struct kvm_run *kvm_run = vcpu->run;
5269
91586a3b 5270 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5271 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5272 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5273 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5274 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5275 else
b6c7a5dc 5276 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5277 kvm_arch_interrupt_allowed(vcpu) &&
5278 !kvm_cpu_has_interrupt(vcpu) &&
5279 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5280}
5281
b93463aa
AK		 5282static void vapic_enter(struct kvm_vcpu *vcpu)
5283{
5284 struct kvm_lapic *apic = vcpu->arch.apic;
5285 struct page *page;
5286
5287 if (!apic || !apic->vapic_addr)
5288 return;
5289
5290 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5291
5292 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5293}
5294
5295static void vapic_exit(struct kvm_vcpu *vcpu)
5296{
5297 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5298 int idx;
b93463aa
AK		 5299
5300 if (!apic || !apic->vapic_addr)
5301 return;
5302
f656ce01 5303 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5304 kvm_release_page_dirty(apic->vapic_page);
5305 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5306 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5307}
5308
95ba8273
GN		 5309static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5310{
5311 int max_irr, tpr;
5312
5313 if (!kvm_x86_ops->update_cr8_intercept)
5314 return;
5315
88c808fd
AK		 5316 if (!vcpu->arch.apic)
5317 return;
5318
8db3baa2
GN		 5319 if (!vcpu->arch.apic->vapic_addr)
5320 max_irr = kvm_lapic_find_highest_irr(vcpu);
5321 else
5322 max_irr = -1;
95ba8273
GN		 5323
5324 if (max_irr != -1)
5325 max_irr >>= 4;
5326
5327 tpr = kvm_lapic_get_cr8(vcpu);
5328
5329 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5330}
5331
851ba692 5332static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5333{
5334 /* try to reinject previous events if any */
b59bb7bd 5335 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5336 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5337 vcpu->arch.exception.has_error_code,
5338 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5339 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5340 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5341 vcpu->arch.exception.error_code,
5342 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5343 return;
5344 }
5345
95ba8273
GN		 5346 if (vcpu->arch.nmi_injected) {
5347 kvm_x86_ops->set_nmi(vcpu);
5348 return;
5349 }
5350
5351 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5352 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5353 return;
5354 }
5355
5356 /* try to inject new event if pending */
5357 if (vcpu->arch.nmi_pending) {
5358 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5359 vcpu->arch.nmi_pending = false;
5360 vcpu->arch.nmi_injected = true;
5361 kvm_x86_ops->set_nmi(vcpu);
5362 }
5363 } else if (kvm_cpu_has_interrupt(vcpu)) {
5364 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5365 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5366 false);
5367 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5368 }
5369 }
5370}
5371
2acf923e
DC		 5372static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5373{
5374 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5375 !vcpu->guest_xcr0_loaded) {
5376 /* kvm_set_xcr() also depends on this */
5377 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5378 vcpu->guest_xcr0_loaded = 1;
5379 }
5380}
5381
5382static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5383{
5384 if (vcpu->guest_xcr0_loaded) {
5385 if (vcpu->arch.xcr0 != host_xcr0)
5386 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5387 vcpu->guest_xcr0_loaded = 0;
5388 }
5389}
5390
851ba692 5391static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5392{
5393 int r;
1499e54a 5394 bool nmi_pending;
6a8b1d13 5395 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5396 vcpu->run->request_interrupt_window;
b6c7a5dc 5397
3e007509 5398 if (vcpu->requests) {
a8eeb04a 5399 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5400 kvm_mmu_unload(vcpu);
a8eeb04a 5401 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5402 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5403 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5404 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5405 if (unlikely(r))
5406 goto out;
5407 }
a8eeb04a 5408 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5409 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5410 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5411 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5412 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5413 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5414 r = 0;
5415 goto out;
5416 }
a8eeb04a 5417 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5418 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5419 r = 0;
5420 goto out;
5421 }
a8eeb04a 5422 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5423 vcpu->fpu_active = 0;
5424 kvm_x86_ops->fpu_deactivate(vcpu);
5425 }
af585b92
GN		 5426 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5427 /* Page is swapped out. Do synthetic halt */
5428 vcpu->arch.apf.halted = true;
5429 r = 1;
5430 goto out;
5431 }
2f52d58c 5432 }
b93463aa 5433
3e007509
AK		 5434 r = kvm_mmu_reload(vcpu);
5435 if (unlikely(r))
5436 goto out;
5437
1499e54a
GN		 5438 /*
5439 * An NMI can be injected between local nmi_pending read and
5440 * vcpu->arch.nmi_pending read inside inject_pending_event().
5441 * But in that case, KVM_REQ_EVENT will be set, which makes
5442 * the race described above benign.
5443 */
5444 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5445
b463a6f7
AK		 5446 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5447 inject_pending_event(vcpu);
5448
5449 /* enable NMI/IRQ window open exits if needed */
1499e54a 5450 if (nmi_pending)
b463a6f7
AK		 5451 kvm_x86_ops->enable_nmi_window(vcpu);
5452 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5453 kvm_x86_ops->enable_irq_window(vcpu);
5454
5455 if (kvm_lapic_enabled(vcpu)) {
5456 update_cr8_intercept(vcpu);
5457 kvm_lapic_sync_to_vapic(vcpu);
5458 }
5459 }
5460
b6c7a5dc
HB		 5461 preempt_disable();
5462
5463 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5464 if (vcpu->fpu_active)
5465 kvm_load_guest_fpu(vcpu);
2acf923e 5466 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5467
6b7e2d09
XG		 5468 vcpu->mode = IN_GUEST_MODE;
5469
5470 /* We should set ->mode before check ->requests,
5471 * see the comment in make_all_cpus_request.
5472 */
5473 smp_mb();
b6c7a5dc 5474
d94e1dc9 5475 local_irq_disable();
32f88400 5476
6b7e2d09 5477 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5478 || need_resched() || signal_pending(current)) {
6b7e2d09 5479 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5480 smp_wmb();
6c142801
AK		 5481 local_irq_enable();
5482 preempt_enable();
b463a6f7 5483 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5484 r = 1;
5485 goto out;
5486 }
5487
f656ce01 5488 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5489
b6c7a5dc
HB		 5490 kvm_guest_enter();
5491
42dbaa5a 5492 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5493 set_debugreg(0, 7);
5494 set_debugreg(vcpu->arch.eff_db[0], 0);
5495 set_debugreg(vcpu->arch.eff_db[1], 1);
5496 set_debugreg(vcpu->arch.eff_db[2], 2);
5497 set_debugreg(vcpu->arch.eff_db[3], 3);
5498 }
b6c7a5dc 5499
229456fc 5500 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5501 kvm_x86_ops->run(vcpu);
b6c7a5dc 5502
24f1e32c
FW		 5503 /*
5504 * If the guest has used debug registers, at least dr7
5505 * will be disabled while returning to the host.
5506 * If we don't have active breakpoints in the host, we don't
5507 * care about the messed up debug address registers. But if
5508 * we have some of them active, restore the old state.
5509 */
59d8eb53 5510 if (hw_breakpoint_active())
24f1e32c 5511 hw_breakpoint_restore();
42dbaa5a 5512
1d5f066e
ZA		 5513 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5514
6b7e2d09 5515 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5516 smp_wmb();
b6c7a5dc
HB		 5517 local_irq_enable();
5518
5519 ++vcpu->stat.exits;
5520
5521 /*
5522 * We must have an instruction between local_irq_enable() and
5523 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5524 * the interrupt shadow. The stat.exits increment will do nicely.
5525 * But we need to prevent reordering, hence this barrier():
5526 */
5527 barrier();
5528
5529 kvm_guest_exit();
5530
5531 preempt_enable();
5532
f656ce01 5533 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5534
b6c7a5dc
HB		 5535 /*
5536 * Profile KVM exit RIPs:
5537 */
5538 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5539 unsigned long rip = kvm_rip_read(vcpu);
5540 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5541 }
5542
298101da 5543
b93463aa
AK		 5544 kvm_lapic_sync_from_vapic(vcpu);
5545
851ba692 5546 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5547out:
5548 return r;
5549}
b6c7a5dc 5550
09cec754 5551
851ba692 5552static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5553{
5554 int r;
f656ce01 5555 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5556
5557 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5558 pr_debug("vcpu %d received sipi with vector # %x\n",
5559 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5560 kvm_lapic_reset(vcpu);
5f179287 5561 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5562 if (r)
5563 return r;
5564 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5565 }
5566
f656ce01 5567 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5568 vapic_enter(vcpu);
5569
5570 r = 1;
5571 while (r > 0) {
af585b92
GN		 5572 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5573 !vcpu->arch.apf.halted)
851ba692 5574 r = vcpu_enter_guest(vcpu);
d7690175 5575 else {
f656ce01 5576 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5577 kvm_vcpu_block(vcpu);
f656ce01 5578 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5579 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5580 {
5581 switch(vcpu->arch.mp_state) {
5582 case KVM_MP_STATE_HALTED:
d7690175 5583 vcpu->arch.mp_state =
09cec754
GN		 5584 KVM_MP_STATE_RUNNABLE;
5585 case KVM_MP_STATE_RUNNABLE:
af585b92 5586 vcpu->arch.apf.halted = false;
09cec754
GN		 5587 break;
5588 case KVM_MP_STATE_SIPI_RECEIVED:
5589 default:
5590 r = -EINTR;
5591 break;
5592 }
5593 }
d7690175
MT		 5594 }
5595
09cec754
GN		 5596 if (r <= 0)
5597 break;
5598
5599 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5600 if (kvm_cpu_has_pending_timer(vcpu))
5601 kvm_inject_pending_timer_irqs(vcpu);
5602
851ba692 5603 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5604 r = -EINTR;
851ba692 5605 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5606 ++vcpu->stat.request_irq_exits;
5607 }
af585b92
GN		 5608
5609 kvm_check_async_pf_completion(vcpu);
5610
09cec754
GN		 5611 if (signal_pending(current)) {
5612 r = -EINTR;
851ba692 5613 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5614 ++vcpu->stat.signal_exits;
5615 }
5616 if (need_resched()) {
f656ce01 5617 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5618 kvm_resched(vcpu);
f656ce01 5619 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5620 }
b6c7a5dc
HB		 5621 }
5622
f656ce01 5623 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5624
b93463aa
AK		 5625 vapic_exit(vcpu);
5626
b6c7a5dc
HB		 5627 return r;
5628}
5629
5287f194
AK		 5630static int complete_mmio(struct kvm_vcpu *vcpu)
5631{
5632 struct kvm_run *run = vcpu->run;
5633 int r;
5634
5635 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5636 return 1;
5637
5638 if (vcpu->mmio_needed) {
5287f194 5639 vcpu->mmio_needed = 0;
cef4dea0 5640 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5641 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5642 run->mmio.data, 8);
cef4dea0
AK		 5643 vcpu->mmio_index += 8;
5644 if (vcpu->mmio_index < vcpu->mmio_size) {
5645 run->exit_reason = KVM_EXIT_MMIO;
5646 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5647 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5648 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5649 run->mmio.is_write = vcpu->mmio_is_write;
5650 vcpu->mmio_needed = 1;
5651 return 0;
5652 }
5653 if (vcpu->mmio_is_write)
5654 return 1;
5655 vcpu->mmio_read_completed = 1;
5287f194
AK		 5656 }
5657 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5658 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5659 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5660 if (r != EMULATE_DONE)
5661 return 0;
5662 return 1;
5663}
5664
b6c7a5dc
HB		 5665int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5666{
5667 int r;
5668 sigset_t sigsaved;
5669
e5c30142
AK		 5670 if (!tsk_used_math(current) && init_fpu(current))
5671 return -ENOMEM;
5672
ac9f6dc0
AK		 5673 if (vcpu->sigset_active)
5674 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5675
a4535290 5676 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5677 kvm_vcpu_block(vcpu);
d7690175 5678 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5679 r = -EAGAIN;
5680 goto out;
b6c7a5dc
HB		 5681 }
5682
b6c7a5dc 5683 /* re-sync apic's tpr */
eea1cff9
AP		 5684 if (!irqchip_in_kernel(vcpu->kvm)) {
5685 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5686 r = -EINVAL;
5687 goto out;
5688 }
5689 }
b6c7a5dc 5690
5287f194
AK		 5691 r = complete_mmio(vcpu);
5692 if (r <= 0)
5693 goto out;
5694
5fdbf976
MT		 5695 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5696 kvm_register_write(vcpu, VCPU_REGS_RAX,
5697 kvm_run->hypercall.ret);
b6c7a5dc 5698
851ba692 5699 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5700
5701out:
f1d86e46 5702 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5703 if (vcpu->sigset_active)
5704 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5705
b6c7a5dc
HB		 5706 return r;
5707}
5708
5709int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5710{
7ae441ea
GN		 5711 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5712 /*
5713 * We are here if userspace calls get_regs() in the middle of
5714 * instruction emulation. Registers state needs to be copied
5715 * back from emulation context to vcpu. Usrapace shouldn't do
5716 * that usually, but some bad designed PV devices (vmware
5717 * backdoor interface) need this to work
5718 */
5719 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5720 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5721 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5722 }
5fdbf976
MT		 5723 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5724 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5725 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5726 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5727 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5728 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5729 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5730 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5731#ifdef CONFIG_X86_64
5fdbf976
MT		 5732 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5733 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5734 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5735 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5736 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5737 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5738 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5739 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5740#endif
5741
5fdbf976 5742 regs->rip = kvm_rip_read(vcpu);
91586a3b 5743 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5744
b6c7a5dc
HB		 5745 return 0;
5746}
5747
5748int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5749{
7ae441ea
GN		 5750 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5751 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5752
5fdbf976
MT		 5753 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5754 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5755 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5756 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5757 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5758 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5759 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5760 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5761#ifdef CONFIG_X86_64
5fdbf976
MT		 5762 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5763 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5764 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5765 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5766 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5767 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5768 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5769 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5770#endif
5771
5fdbf976 5772 kvm_rip_write(vcpu, regs->rip);
91586a3b 5773 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5774
b4f14abd
JK		 5775 vcpu->arch.exception.pending = false;
5776
3842d135
AK		 5777 kvm_make_request(KVM_REQ_EVENT, vcpu);
5778
b6c7a5dc
HB		 5779 return 0;
5780}
5781
b6c7a5dc
HB		 5782void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5783{
5784 struct kvm_segment cs;
5785
3e6e0aab 5786 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5787 *db = cs.db;
5788 *l = cs.l;
5789}
5790EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5791
5792int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5793 struct kvm_sregs *sregs)
5794{
89a27f4d 5795 struct desc_ptr dt;
b6c7a5dc 5796
3e6e0aab
GT		 5797 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5798 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5799 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5800 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5801 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5802 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5803
3e6e0aab
GT		 5804 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5805 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5806
5807 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5808 sregs->idt.limit = dt.size;
5809 sregs->idt.base = dt.address;
b6c7a5dc 5810 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5811 sregs->gdt.limit = dt.size;
5812 sregs->gdt.base = dt.address;
b6c7a5dc 5813
4d4ec087 5814 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5815 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5816 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5817 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5818 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5819 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5820 sregs->apic_base = kvm_get_apic_base(vcpu);
5821
923c61bb 5822 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5823
36752c9b 5824 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5825 set_bit(vcpu->arch.interrupt.nr,
5826 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5827
b6c7a5dc
HB		 5828 return 0;
5829}
5830
62d9f0db
MT		 5831int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5832 struct kvm_mp_state *mp_state)
5833{
62d9f0db 5834 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5835 return 0;
5836}
5837
5838int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5839 struct kvm_mp_state *mp_state)
5840{
62d9f0db 5841 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5842 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5843 return 0;
5844}
5845
e269fb21
JK		 5846int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5847 bool has_error_code, u32 error_code)
b6c7a5dc 5848{
4d2179e1 5849 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5850 int ret;
e01c2426 5851
8ec4722d 5852 init_emulate_ctxt(vcpu);
c697518a 5853
9aabc88f 5854 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5855 tss_selector, reason, has_error_code,
5856 error_code);
c697518a 5857
c697518a 5858 if (ret)
19d04437 5859 return EMULATE_FAIL;
37817f29 5860
4d2179e1 5861 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5862 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5863 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5864 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5865 return EMULATE_DONE;
37817f29
IE		 5866}
5867EXPORT_SYMBOL_GPL(kvm_task_switch);
5868
b6c7a5dc
HB		 5869int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5870 struct kvm_sregs *sregs)
5871{
5872 int mmu_reset_needed = 0;
63f42e02 5873 int pending_vec, max_bits, idx;
89a27f4d 5874 struct desc_ptr dt;
b6c7a5dc 5875
89a27f4d
GN		 5876 dt.size = sregs->idt.limit;
5877 dt.address = sregs->idt.base;
b6c7a5dc 5878 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5879 dt.size = sregs->gdt.limit;
5880 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5881 kvm_x86_ops->set_gdt(vcpu, &dt);
5882
ad312c7c 5883 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5884 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5885 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5886 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5887
2d3ad1f4 5888 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5889
f6801dff 5890 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5891 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5892 kvm_set_apic_base(vcpu, sregs->apic_base);
5893
4d4ec087 5894 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5895 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5896 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5897
fc78f519 5898 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5899 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5900 if (sregs->cr4 & X86_CR4_OSXSAVE)
5901 update_cpuid(vcpu);
63f42e02
XG		 5902
5903 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5904 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5905 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5906 mmu_reset_needed = 1;
5907 }
63f42e02 5908 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5909
5910 if (mmu_reset_needed)
5911 kvm_mmu_reset_context(vcpu);
5912
923c61bb
GN		 5913 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5914 pending_vec = find_first_bit(
5915 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5916 if (pending_vec < max_bits) {
66fd3f7f 5917 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5918 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5919 }
5920
3e6e0aab
GT		 5921 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5922 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5923 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5924 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5925 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5926 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5927
3e6e0aab
GT		 5928 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5929 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5930
5f0269f5
ME		 5931 update_cr8_intercept(vcpu);
5932
9c3e4aab 5933 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5934 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5935 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5936 !is_protmode(vcpu))
9c3e4aab
MT		 5937 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5938
3842d135
AK		 5939 kvm_make_request(KVM_REQ_EVENT, vcpu);
5940
b6c7a5dc
HB		 5941 return 0;
5942}
5943
d0bfb940
JK		 5944int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5945 struct kvm_guest_debug *dbg)
b6c7a5dc 5946{
355be0b9 5947 unsigned long rflags;
ae675ef0 5948 int i, r;
b6c7a5dc 5949
4f926bf2
JK		 5950 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5951 r = -EBUSY;
5952 if (vcpu->arch.exception.pending)
2122ff5e 5953 goto out;
4f926bf2
JK		 5954 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5955 kvm_queue_exception(vcpu, DB_VECTOR);
5956 else
5957 kvm_queue_exception(vcpu, BP_VECTOR);
5958 }
5959
91586a3b
JK		 5960 /*
5961 * Read rflags as long as potentially injected trace flags are still
5962 * filtered out.
5963 */
5964 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5965
5966 vcpu->guest_debug = dbg->control;
5967 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5968 vcpu->guest_debug = 0;
5969
5970 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5971 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5972 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5973 vcpu->arch.switch_db_regs =
5974 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5975 } else {
5976 for (i = 0; i < KVM_NR_DB_REGS; i++)
5977 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5978 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5979 }
5980
f92653ee
JK		 5981 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5982 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5983 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5984
91586a3b
JK		 5985 /*
5986 * Trigger an rflags update that will inject or remove the trace
5987 * flags.
5988 */
5989 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5990
355be0b9 5991 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5992
4f926bf2 5993 r = 0;
d0bfb940 5994
2122ff5e 5995out:
b6c7a5dc
HB		 5996
5997 return r;
5998}
5999
8b006791
ZX		 6000/*
6001 * Translate a guest virtual address to a guest physical address.
6002 */
6003int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6004 struct kvm_translation *tr)
6005{
6006 unsigned long vaddr = tr->linear_address;
6007 gpa_t gpa;
f656ce01 6008 int idx;
8b006791 6009
f656ce01 6010 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6011 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6012 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6013 tr->physical_address = gpa;
6014 tr->valid = gpa != UNMAPPED_GVA;
6015 tr->writeable = 1;
6016 tr->usermode = 0;
8b006791
ZX		 6017
6018 return 0;
6019}
6020
d0752060
HB		 6021int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6022{
98918833
SY		 6023 struct i387_fxsave_struct *fxsave =
6024 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6025
d0752060
HB		 6026 memcpy(fpu->fpr, fxsave->st_space, 128);
6027 fpu->fcw = fxsave->cwd;
6028 fpu->fsw = fxsave->swd;
6029 fpu->ftwx = fxsave->twd;
6030 fpu->last_opcode = fxsave->fop;
6031 fpu->last_ip = fxsave->rip;
6032 fpu->last_dp = fxsave->rdp;
6033 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6034
d0752060
HB		 6035 return 0;
6036}
6037
6038int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6039{
98918833
SY		 6040 struct i387_fxsave_struct *fxsave =
6041 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6042
d0752060
HB		 6043 memcpy(fxsave->st_space, fpu->fpr, 128);
6044 fxsave->cwd = fpu->fcw;
6045 fxsave->swd = fpu->fsw;
6046 fxsave->twd = fpu->ftwx;
6047 fxsave->fop = fpu->last_opcode;
6048 fxsave->rip = fpu->last_ip;
6049 fxsave->rdp = fpu->last_dp;
6050 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6051
d0752060
HB		 6052 return 0;
6053}
6054
10ab25cd 6055int fx_init(struct kvm_vcpu *vcpu)
d0752060 6056{
10ab25cd
JK		 6057 int err;
6058
6059 err = fpu_alloc(&vcpu->arch.guest_fpu);
6060 if (err)
6061 return err;
6062
98918833 6063 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6064
2acf923e
DC		 6065 /*
6066 * Ensure guest xcr0 is valid for loading
6067 */
6068 vcpu->arch.xcr0 = XSTATE_FP;
6069
ad312c7c 6070 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6071
6072 return 0;
d0752060
HB		 6073}
6074EXPORT_SYMBOL_GPL(fx_init);
6075
98918833
SY		 6076static void fx_free(struct kvm_vcpu *vcpu)
6077{
6078 fpu_free(&vcpu->arch.guest_fpu);
6079}
6080
d0752060
HB		 6081void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6082{
2608d7a1 6083 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6084 return;
6085
2acf923e
DC		 6086 /*
6087 * Restore all possible states in the guest,
6088 * and assume host would use all available bits.
6089 * Guest xcr0 would be loaded later.
6090 */
6091 kvm_put_guest_xcr0(vcpu);
d0752060 6092 vcpu->guest_fpu_loaded = 1;
7cf30855 6093 unlazy_fpu(current);
98918833 6094 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6095 trace_kvm_fpu(1);
d0752060 6096}
d0752060
HB		 6097
6098void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6099{
2acf923e
DC		 6100 kvm_put_guest_xcr0(vcpu);
6101
d0752060
HB		 6102 if (!vcpu->guest_fpu_loaded)
6103 return;
6104
6105 vcpu->guest_fpu_loaded = 0;
98918833 6106 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6107 ++vcpu->stat.fpu_reload;
a8eeb04a 6108 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6109 trace_kvm_fpu(0);
d0752060 6110}
e9b11c17
ZX		 6111
6112void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6113{
12f9a48f 6114 kvmclock_reset(vcpu);
7f1ea208 6115
f5f48ee1 6116 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6117 fx_free(vcpu);
e9b11c17
ZX		 6118 kvm_x86_ops->vcpu_free(vcpu);
6119}
6120
6121struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6122 unsigned int id)
6123{
6755bae8
ZA		 6124 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6125 printk_once(KERN_WARNING
6126 "kvm: SMP vm created on host with unstable TSC; "
6127 "guest TSC will not be reliable\n");
26e5215f
AK		 6128 return kvm_x86_ops->vcpu_create(kvm, id);
6129}
e9b11c17 6130
26e5215f
AK		 6131int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6132{
6133 int r;
e9b11c17 6134
0bed3b56 6135 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6136 vcpu_load(vcpu);
6137 r = kvm_arch_vcpu_reset(vcpu);
6138 if (r == 0)
6139 r = kvm_mmu_setup(vcpu);
6140 vcpu_put(vcpu);
e9b11c17 6141
26e5215f 6142 return r;
e9b11c17
ZX		 6143}
6144
d40ccc62 6145void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6146{
344d9588
GN		 6147 vcpu->arch.apf.msr_val = 0;
6148
e9b11c17
ZX		 6149 vcpu_load(vcpu);
6150 kvm_mmu_unload(vcpu);
6151 vcpu_put(vcpu);
6152
98918833 6153 fx_free(vcpu);
e9b11c17
ZX		 6154 kvm_x86_ops->vcpu_free(vcpu);
6155}
6156
6157int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6158{
448fa4a9
JK		 6159 vcpu->arch.nmi_pending = false;
6160 vcpu->arch.nmi_injected = false;
6161
42dbaa5a
JK		 6162 vcpu->arch.switch_db_regs = 0;
6163 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6164 vcpu->arch.dr6 = DR6_FIXED_1;
6165 vcpu->arch.dr7 = DR7_FIXED_1;
6166
3842d135 6167 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6168 vcpu->arch.apf.msr_val = 0;
3842d135 6169
12f9a48f
GC		 6170 kvmclock_reset(vcpu);
6171
af585b92
GN		 6172 kvm_clear_async_pf_completion_queue(vcpu);
6173 kvm_async_pf_hash_reset(vcpu);
6174 vcpu->arch.apf.halted = false;
3842d135 6175
e9b11c17
ZX		 6176 return kvm_x86_ops->vcpu_reset(vcpu);
6177}
6178
10474ae8 6179int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6180{
ca84d1a2
ZA		 6181 struct kvm *kvm;
6182 struct kvm_vcpu *vcpu;
6183 int i;
18863bdd
AK		 6184
6185 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6186 list_for_each_entry(kvm, &vm_list, vm_list)
6187 kvm_for_each_vcpu(i, vcpu, kvm)
6188 if (vcpu->cpu == smp_processor_id())
c285545f 6189 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6190 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6191}
6192
6193void kvm_arch_hardware_disable(void *garbage)
6194{
6195 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6196 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6197}
6198
6199int kvm_arch_hardware_setup(void)
6200{
6201 return kvm_x86_ops->hardware_setup();
6202}
6203
6204void kvm_arch_hardware_unsetup(void)
6205{
6206 kvm_x86_ops->hardware_unsetup();
6207}
6208
6209void kvm_arch_check_processor_compat(void *rtn)
6210{
6211 kvm_x86_ops->check_processor_compatibility(rtn);
6212}
6213
6214int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6215{
6216 struct page *page;
6217 struct kvm *kvm;
6218 int r;
6219
6220 BUG_ON(vcpu->kvm == NULL);
6221 kvm = vcpu->kvm;
6222
9aabc88f 6223 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6224 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6225 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6226 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6227 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6228 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6229 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6230 else
a4535290 6231 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6232
6233 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6234 if (!page) {
6235 r = -ENOMEM;
6236 goto fail;
6237 }
ad312c7c 6238 vcpu->arch.pio_data = page_address(page);
e9b11c17 6239
1e993611 6240 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6241
e9b11c17
ZX		 6242 r = kvm_mmu_create(vcpu);
6243 if (r < 0)
6244 goto fail_free_pio_data;
6245
6246 if (irqchip_in_kernel(kvm)) {
6247 r = kvm_create_lapic(vcpu);
6248 if (r < 0)
6249 goto fail_mmu_destroy;
6250 }
6251
890ca9ae
HY		 6252 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6253 GFP_KERNEL);
6254 if (!vcpu->arch.mce_banks) {
6255 r = -ENOMEM;
443c39bc 6256 goto fail_free_lapic;
890ca9ae
HY		 6257 }
6258 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6259
f5f48ee1
SY		 6260 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6261 goto fail_free_mce_banks;
6262
af585b92
GN		 6263 kvm_async_pf_hash_reset(vcpu);
6264
e9b11c17 6265 return 0;
f5f48ee1
SY		 6266fail_free_mce_banks:
6267 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6268fail_free_lapic:
6269 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6270fail_mmu_destroy:
6271 kvm_mmu_destroy(vcpu);
6272fail_free_pio_data:
ad312c7c 6273 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6274fail:
6275 return r;
6276}
6277
6278void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6279{
f656ce01
MT		 6280 int idx;
6281
36cb93fd 6282 kfree(vcpu->arch.mce_banks);
e9b11c17 6283 kvm_free_lapic(vcpu);
f656ce01 6284 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6285 kvm_mmu_destroy(vcpu);
f656ce01 6286 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6287 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6288}
d19a9cd2 6289
d89f5eff 6290int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6291{
f05e70ac 6292 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6293 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6294
5550af4d
SY		 6295 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6296 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6297
038f8c11 6298 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6299
d89f5eff 6300 return 0;
d19a9cd2
ZX		 6301}
6302
6303static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6304{
6305 vcpu_load(vcpu);
6306 kvm_mmu_unload(vcpu);
6307 vcpu_put(vcpu);
6308}
6309
6310static void kvm_free_vcpus(struct kvm *kvm)
6311{
6312 unsigned int i;
988a2cae 6313 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6314
6315 /*
6316 * Unpin any mmu pages first.
6317 */
af585b92
GN		 6318 kvm_for_each_vcpu(i, vcpu, kvm) {
6319 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6320 kvm_unload_vcpu_mmu(vcpu);
af585b92 6321 }
988a2cae
GN		 6322 kvm_for_each_vcpu(i, vcpu, kvm)
6323 kvm_arch_vcpu_free(vcpu);
6324
6325 mutex_lock(&kvm->lock);
6326 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6327 kvm->vcpus[i] = NULL;
d19a9cd2 6328
988a2cae
GN		 6329 atomic_set(&kvm->online_vcpus, 0);
6330 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6331}
6332
ad8ba2cd
SY		 6333void kvm_arch_sync_events(struct kvm *kvm)
6334{
ba4cef31 6335 kvm_free_all_assigned_devices(kvm);
aea924f6 6336 kvm_free_pit(kvm);
ad8ba2cd
SY		 6337}
6338
d19a9cd2
ZX		 6339void kvm_arch_destroy_vm(struct kvm *kvm)
6340{
6eb55818 6341 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6342 kfree(kvm->arch.vpic);
6343 kfree(kvm->arch.vioapic);
d19a9cd2 6344 kvm_free_vcpus(kvm);
3d45830c
AK		 6345 if (kvm->arch.apic_access_page)
6346 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6347 if (kvm->arch.ept_identity_pagetable)
6348 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6349}
0de10343 6350
f7784b8e
MT		 6351int kvm_arch_prepare_memory_region(struct kvm *kvm,
6352 struct kvm_memory_slot *memslot,
0de10343 6353 struct kvm_memory_slot old,
f7784b8e 6354 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6355 int user_alloc)
6356{
f7784b8e 6357 int npages = memslot->npages;
7ac77099
AK		 6358 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6359
6360 /* Prevent internal slot pages from being moved by fork()/COW. */
6361 if (memslot->id >= KVM_MEMORY_SLOTS)
6362 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6363
6364 /*To keep backward compatibility with older userspace,
6365 *x86 needs to hanlde !user_alloc case.
6366 */
6367 if (!user_alloc) {
6368 if (npages && !old.rmap) {
604b38ac
AA		 6369 unsigned long userspace_addr;
6370
72dc67a6 6371 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6372 userspace_addr = do_mmap(NULL, 0,
6373 npages * PAGE_SIZE,
6374 PROT_READ | PROT_WRITE,
7ac77099 6375 map_flags,
604b38ac 6376 0);
72dc67a6 6377 up_write(&current->mm->mmap_sem);
0de10343 6378
604b38ac
AA		 6379 if (IS_ERR((void *)userspace_addr))
6380 return PTR_ERR((void *)userspace_addr);
6381
604b38ac 6382 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6383 }
6384 }
6385
f7784b8e
MT		 6386
6387 return 0;
6388}
6389
6390void kvm_arch_commit_memory_region(struct kvm *kvm,
6391 struct kvm_userspace_memory_region *mem,
6392 struct kvm_memory_slot old,
6393 int user_alloc)
6394{
6395
48c0e4e9 6396 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6397
6398 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6399 int ret;
6400
6401 down_write(&current->mm->mmap_sem);
6402 ret = do_munmap(current->mm, old.userspace_addr,
6403 old.npages * PAGE_SIZE);
6404 up_write(&current->mm->mmap_sem);
6405 if (ret < 0)
6406 printk(KERN_WARNING
6407 "kvm_vm_ioctl_set_memory_region: "
6408 "failed to munmap memory\n");
6409 }
6410
48c0e4e9
XG		 6411 if (!kvm->arch.n_requested_mmu_pages)
6412 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6413
7c8a83b7 6414 spin_lock(&kvm->mmu_lock);
48c0e4e9 6415 if (nr_mmu_pages)
0de10343 6416 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6417 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6418 spin_unlock(&kvm->mmu_lock);
0de10343 6419}
1d737c8a 6420
34d4cb8f
MT		 6421void kvm_arch_flush_shadow(struct kvm *kvm)
6422{
6423 kvm_mmu_zap_all(kvm);
8986ecc0 6424 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6425}
6426
1d737c8a
ZX		 6427int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6428{
af585b92
GN		 6429 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6430 !vcpu->arch.apf.halted)
6431 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6432 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6433 || vcpu->arch.nmi_pending ||
6434 (kvm_arch_interrupt_allowed(vcpu) &&
6435 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6436}
5736199a 6437
5736199a
ZX		 6438void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6439{
32f88400
MT		 6440 int me;
6441 int cpu = vcpu->cpu;
5736199a
ZX		 6442
6443 if (waitqueue_active(&vcpu->wq)) {
6444 wake_up_interruptible(&vcpu->wq);
6445 ++vcpu->stat.halt_wakeup;
6446 }
32f88400
MT		 6447
6448 me = get_cpu();
6449 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6450 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6451 smp_send_reschedule(cpu);
e9571ed5 6452 put_cpu();
5736199a 6453}
78646121
GN		 6454
6455int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6456{
6457 return kvm_x86_ops->interrupt_allowed(vcpu);
6458}
229456fc 6459
f92653ee
JK		 6460bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6461{
6462 unsigned long current_rip = kvm_rip_read(vcpu) +
6463 get_segment_base(vcpu, VCPU_SREG_CS);
6464
6465 return current_rip == linear_rip;
6466}
6467EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6468
94fe45da
JK		 6469unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6470{
6471 unsigned long rflags;
6472
6473 rflags = kvm_x86_ops->get_rflags(vcpu);
6474 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6475 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6476 return rflags;
6477}
6478EXPORT_SYMBOL_GPL(kvm_get_rflags);
6479
6480void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6481{
6482 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6483 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6484 rflags |= X86_EFLAGS_TF;
94fe45da 6485 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6486 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6487}
6488EXPORT_SYMBOL_GPL(kvm_set_rflags);
6489
56028d08
GN		 6490void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6491{
6492 int r;
6493
fb67e14f 6494 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6495 is_error_page(work->page))
56028d08
GN		 6496 return;
6497
6498 r = kvm_mmu_reload(vcpu);
6499 if (unlikely(r))
6500 return;
6501
fb67e14f
XG		 6502 if (!vcpu->arch.mmu.direct_map &&
6503 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6504 return;
6505
56028d08
GN		 6506 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6507}
6508
af585b92
GN		 6509static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6510{
6511 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6512}
6513
6514static inline u32 kvm_async_pf_next_probe(u32 key)
6515{
6516 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6517}
6518
6519static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6520{
6521 u32 key = kvm_async_pf_hash_fn(gfn);
6522
6523 while (vcpu->arch.apf.gfns[key] != ~0)
6524 key = kvm_async_pf_next_probe(key);
6525
6526 vcpu->arch.apf.gfns[key] = gfn;
6527}
6528
6529static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6530{
6531 int i;
6532 u32 key = kvm_async_pf_hash_fn(gfn);
6533
6534 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6535 (vcpu->arch.apf.gfns[key] != gfn &&
6536 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6537 key = kvm_async_pf_next_probe(key);
6538
6539 return key;
6540}
6541
6542bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6543{
6544 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6545}
6546
6547static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6548{
6549 u32 i, j, k;
6550
6551 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6552 while (true) {
6553 vcpu->arch.apf.gfns[i] = ~0;
6554 do {
6555 j = kvm_async_pf_next_probe(j);
6556 if (vcpu->arch.apf.gfns[j] == ~0)
6557 return;
6558 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6559 /*
6560 * k lies cyclically in ]i,j]
6561 * | i.k.j |
6562 * |....j i.k.| or |.k..j i...|
6563 */
6564 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6565 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6566 i = j;
6567 }
6568}
6569
7c90705b
GN		 6570static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6571{
6572
6573 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6574 sizeof(val));
6575}
6576
af585b92
GN		 6577void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6578 struct kvm_async_pf *work)
6579{
6389ee94
AK		 6580 struct x86_exception fault;
6581
7c90705b 6582 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6583 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6584
6585 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6586 (vcpu->arch.apf.send_user_only &&
6587 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6588 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6589 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6590 fault.vector = PF_VECTOR;
6591 fault.error_code_valid = true;
6592 fault.error_code = 0;
6593 fault.nested_page_fault = false;
6594 fault.address = work->arch.token;
6595 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6596 }
af585b92
GN		 6597}
6598
6599void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6600 struct kvm_async_pf *work)
6601{
6389ee94
AK		 6602 struct x86_exception fault;
6603
7c90705b
GN		 6604 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6605 if (is_error_page(work->page))
6606 work->arch.token = ~0; /* broadcast wakeup */
6607 else
6608 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6609
6610 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6611 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6612 fault.vector = PF_VECTOR;
6613 fault.error_code_valid = true;
6614 fault.error_code = 0;
6615 fault.nested_page_fault = false;
6616 fault.address = work->arch.token;
6617 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6618 }
e6d53e3b 6619 vcpu->arch.apf.halted = false;
7c90705b
GN		 6620}
6621
6622bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6623{
6624 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6625 return true;
6626 else
6627 return !kvm_event_needs_reinjection(vcpu) &&
6628 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6629}
6630
229456fc
MT		 6631EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6632EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6633EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6634EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6635EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6636EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6637EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6638EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git