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KVM: SVM: init_vmcb should reset vcpu->efer
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
287 if (!vcpu->arch.exception.pending) {
288 queue:
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
3f0fd292 293 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 294 return;
295 }
296
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
a8eeb04a 301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 302 return;
303 }
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
313 } else
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
316 exception */
317 goto queue;
318}
319
298101da
AK		 320void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
321{
ce7ddec4 322 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 323}
324EXPORT_SYMBOL_GPL(kvm_queue_exception);
325
ce7ddec4
JR		 326void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327{
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
329}
330EXPORT_SYMBOL_GPL(kvm_requeue_exception);
331
c3c91fee
AK		 332void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
333 u32 error_code)
334{
335 ++vcpu->stat.pf_guest;
ad312c7c 336 vcpu->arch.cr2 = addr;
c3c91fee
AK		 337 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
338}
339
3419ffc8
SY		 340void kvm_inject_nmi(struct kvm_vcpu *vcpu)
341{
342 vcpu->arch.nmi_pending = 1;
343}
344EXPORT_SYMBOL_GPL(kvm_inject_nmi);
345
298101da
AK		 346void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
347{
ce7ddec4 348 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 349}
350EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
351
ce7ddec4
JR		 352void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
354 kvm_multiple_exception(vcpu, nr, true, error_code, true);
355}
356EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
49a9b07e 430int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
aad82703
SY		 432 unsigned long old_cr0 = kvm_read_cr0(vcpu);
433 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
434 X86_CR0_CD | X86_CR0_NW;
435
f9a48e6a
AK		 436 cr0 |= X86_CR0_ET;
437
ab344828 438#ifdef CONFIG_X86_64
0f12244f
GN		 439 if (cr0 & 0xffffffff00000000UL)
440 return 1;
ab344828
GN		 441#endif
442
443 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 444
0f12244f
GN		 445 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
446 return 1;
a03490ed 447
0f12244f
GN		 448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
449 return 1;
a03490ed
CO		 450
451 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
452#ifdef CONFIG_X86_64
f6801dff 453 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 454 int cs_db, cs_l;
455
0f12244f
GN		 456 if (!is_pae(vcpu))
457 return 1;
a03490ed 458 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 459 if (cs_l)
460 return 1;
a03490ed
CO		 461 } else
462#endif
0f12244f
GN		 463 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
464 return 1;
a03490ed
CO		 465 }
466
467 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 468
aad82703
SY		 469 if ((cr0 ^ old_cr0) & update_bits)
470 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 471 return 0;
472}
2d3ad1f4 473EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 474
2d3ad1f4 475void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 476{
49a9b07e 477 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 478}
2d3ad1f4 479EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 480
2acf923e
DC		 481int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
482{
483 u64 xcr0;
484
485 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
486 if (index != XCR_XFEATURE_ENABLED_MASK)
487 return 1;
488 xcr0 = xcr;
489 if (kvm_x86_ops->get_cpl(vcpu) != 0)
490 return 1;
491 if (!(xcr0 & XSTATE_FP))
492 return 1;
493 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
494 return 1;
495 if (xcr0 & ~host_xcr0)
496 return 1;
497 vcpu->arch.xcr0 = xcr0;
498 vcpu->guest_xcr0_loaded = 0;
499 return 0;
500}
501
502int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
503{
504 if (__kvm_set_xcr(vcpu, index, xcr)) {
505 kvm_inject_gp(vcpu, 0);
506 return 1;
507 }
508 return 0;
509}
510EXPORT_SYMBOL_GPL(kvm_set_xcr);
511
512static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
513{
514 struct kvm_cpuid_entry2 *best;
515
516 best = kvm_find_cpuid_entry(vcpu, 1, 0);
517 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
518}
519
520static void update_cpuid(struct kvm_vcpu *vcpu)
521{
522 struct kvm_cpuid_entry2 *best;
523
524 best = kvm_find_cpuid_entry(vcpu, 1, 0);
525 if (!best)
526 return;
527
528 /* Update OSXSAVE bit */
529 if (cpu_has_xsave && best->function == 0x1) {
530 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
531 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
532 best->ecx |= bit(X86_FEATURE_OSXSAVE);
533 }
534}
535
a83b29c6 536int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 537{
fc78f519 538 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 539 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
540
0f12244f
GN		 541 if (cr4 & CR4_RESERVED_BITS)
542 return 1;
a03490ed 543
2acf923e
DC		 544 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
545 return 1;
546
a03490ed 547 if (is_long_mode(vcpu)) {
0f12244f
GN		 548 if (!(cr4 & X86_CR4_PAE))
549 return 1;
a2edf57f
AK		 550 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
551 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 552 && !load_pdptrs(vcpu, vcpu->arch.cr3))
553 return 1;
554
555 if (cr4 & X86_CR4_VMXE)
556 return 1;
a03490ed 557
a03490ed 558 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 559
aad82703
SY		 560 if ((cr4 ^ old_cr4) & pdptr_bits)
561 kvm_mmu_reset_context(vcpu);
0f12244f 562
2acf923e
DC		 563 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
564 update_cpuid(vcpu);
565
0f12244f
GN		 566 return 0;
567}
2d3ad1f4 568EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 569
2390218b 570int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 571{
ad312c7c 572 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 573 kvm_mmu_sync_roots(vcpu);
d835dfec 574 kvm_mmu_flush_tlb(vcpu);
0f12244f 575 return 0;
d835dfec
AK		 576 }
577
a03490ed 578 if (is_long_mode(vcpu)) {
0f12244f
GN		 579 if (cr3 & CR3_L_MODE_RESERVED_BITS)
580 return 1;
a03490ed
CO		 581 } else {
582 if (is_pae(vcpu)) {
0f12244f
GN		 583 if (cr3 & CR3_PAE_RESERVED_BITS)
584 return 1;
585 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
586 return 1;
a03490ed
CO		 587 }
588 /*
589 * We don't check reserved bits in nonpae mode, because
590 * this isn't enforced, and VMware depends on this.
591 */
592 }
593
a03490ed
CO		 594 /*
595 * Does the new cr3 value map to physical memory? (Note, we
596 * catch an invalid cr3 even in real-mode, because it would
597 * cause trouble later on when we turn on paging anyway.)
598 *
599 * A real CPU would silently accept an invalid cr3 and would
600 * attempt to use it - with largely undefined (and often hard
601 * to debug) behavior on the guest side.
602 */
603 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 604 return 1;
605 vcpu->arch.cr3 = cr3;
606 vcpu->arch.mmu.new_cr3(vcpu);
607 return 0;
608}
2d3ad1f4 609EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 610
0f12244f 611int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 612{
0f12244f
GN		 613 if (cr8 & CR8_RESERVED_BITS)
614 return 1;
a03490ed
CO		 615 if (irqchip_in_kernel(vcpu->kvm))
616 kvm_lapic_set_tpr(vcpu, cr8);
617 else
ad312c7c 618 vcpu->arch.cr8 = cr8;
0f12244f
GN		 619 return 0;
620}
621
622void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
623{
624 if (__kvm_set_cr8(vcpu, cr8))
625 kvm_inject_gp(vcpu, 0);
a03490ed 626}
2d3ad1f4 627EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 628
2d3ad1f4 629unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 630{
631 if (irqchip_in_kernel(vcpu->kvm))
632 return kvm_lapic_get_cr8(vcpu);
633 else
ad312c7c 634 return vcpu->arch.cr8;
a03490ed 635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 637
338dbc97 638static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 639{
640 switch (dr) {
641 case 0 ... 3:
642 vcpu->arch.db[dr] = val;
643 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
644 vcpu->arch.eff_db[dr] = val;
645 break;
646 case 4:
338dbc97
GN		 647 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
648 return 1; /* #UD */
020df079
GN		 649 /* fall through */
650 case 6:
338dbc97
GN		 651 if (val & 0xffffffff00000000ULL)
652 return -1; /* #GP */
020df079
GN		 653 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
654 break;
655 case 5:
338dbc97
GN		 656 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
657 return 1; /* #UD */
020df079
GN		 658 /* fall through */
659 default: /* 7 */
338dbc97
GN		 660 if (val & 0xffffffff00000000ULL)
661 return -1; /* #GP */
020df079
GN		 662 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
663 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
664 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
665 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
666 }
667 break;
668 }
669
670 return 0;
671}
338dbc97
GN		 672
673int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
674{
675 int res;
676
677 res = __kvm_set_dr(vcpu, dr, val);
678 if (res > 0)
679 kvm_queue_exception(vcpu, UD_VECTOR);
680 else if (res < 0)
681 kvm_inject_gp(vcpu, 0);
682
683 return res;
684}
020df079
GN		 685EXPORT_SYMBOL_GPL(kvm_set_dr);
686
338dbc97 687static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 688{
689 switch (dr) {
690 case 0 ... 3:
691 *val = vcpu->arch.db[dr];
692 break;
693 case 4:
338dbc97 694 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 695 return 1;
020df079
GN		 696 /* fall through */
697 case 6:
698 *val = vcpu->arch.dr6;
699 break;
700 case 5:
338dbc97 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 702 return 1;
020df079
GN		 703 /* fall through */
704 default: /* 7 */
705 *val = vcpu->arch.dr7;
706 break;
707 }
708
709 return 0;
710}
338dbc97
GN		 711
712int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
713{
714 if (_kvm_get_dr(vcpu, dr, val)) {
715 kvm_queue_exception(vcpu, UD_VECTOR);
716 return 1;
717 }
718 return 0;
719}
020df079
GN		 720EXPORT_SYMBOL_GPL(kvm_get_dr);
721
043405e1
CO		 722/*
723 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
724 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
725 *
726 * This list is modified at module load time to reflect the
e3267cbb
GC		 727 * capabilities of the host cpu. This capabilities test skips MSRs that are
728 * kvm-specific. Those are put in the beginning of the list.
043405e1 729 */
e3267cbb 730
11c6bffa 731#define KVM_SAVE_MSRS_BEGIN 7
043405e1 732static u32 msrs_to_save[] = {
e3267cbb 733 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 734 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 735 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 736 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 737 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 738 MSR_STAR,
043405e1
CO		 739#ifdef CONFIG_X86_64
740 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
741#endif
e3267cbb 742 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 743};
744
745static unsigned num_msrs_to_save;
746
747static u32 emulated_msrs[] = {
748 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 749 MSR_IA32_MCG_STATUS,
750 MSR_IA32_MCG_CTL,
043405e1
CO		 751};
752
b69e8cae 753static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 754{
aad82703
SY		 755 u64 old_efer = vcpu->arch.efer;
756
b69e8cae
RJ		 757 if (efer & efer_reserved_bits)
758 return 1;
15c4a640
CO		 759
760 if (is_paging(vcpu)
b69e8cae
RJ		 761 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
762 return 1;
15c4a640 763
1b2fd70c
AG		 764 if (efer & EFER_FFXSR) {
765 struct kvm_cpuid_entry2 *feat;
766
767 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 768 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
769 return 1;
1b2fd70c
AG		 770 }
771
d8017474
AG		 772 if (efer & EFER_SVME) {
773 struct kvm_cpuid_entry2 *feat;
774
775 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 776 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
777 return 1;
d8017474
AG		 778 }
779
15c4a640 780 efer &= ~EFER_LMA;
f6801dff 781 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 782
a3d204e2
SY		 783 kvm_x86_ops->set_efer(vcpu, efer);
784
9645bb56
AK		 785 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
786 kvm_mmu_reset_context(vcpu);
b69e8cae 787
aad82703
SY		 788 /* Update reserved bits */
789 if ((efer ^ old_efer) & EFER_NX)
790 kvm_mmu_reset_context(vcpu);
791
b69e8cae 792 return 0;
15c4a640
CO		 793}
794
f2b4b7dd
JR		 795void kvm_enable_efer_bits(u64 mask)
796{
797 efer_reserved_bits &= ~mask;
798}
799EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
800
801
15c4a640
CO		 802/*
803 * Writes msr value into into the appropriate "register".
804 * Returns 0 on success, non-0 otherwise.
805 * Assumes vcpu_load() was already called.
806 */
807int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
808{
809 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
810}
811
313a3dc7
CO		 812/*
813 * Adapt set_msr() to msr_io()'s calling convention
814 */
815static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
816{
817 return kvm_set_msr(vcpu, index, *data);
818}
819
18068523
GOC		 820static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
821{
9ed3c444
AK		 822 int version;
823 int r;
50d0a0f9 824 struct pvclock_wall_clock wc;
923de3cf 825 struct timespec boot;
18068523
GOC		 826
827 if (!wall_clock)
828 return;
829
9ed3c444
AK		 830 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
831 if (r)
832 return;
833
834 if (version & 1)
835 ++version; /* first time write, random junk */
836
837 ++version;
18068523 838
18068523
GOC		 839 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
840
50d0a0f9
GH		 841 /*
842 * The guest calculates current wall clock time by adding
843 * system time (updated by kvm_write_guest_time below) to the
844 * wall clock specified here. guest system time equals host
845 * system time for us, thus we must fill in host boot time here.
846 */
923de3cf 847 getboottime(&boot);
50d0a0f9
GH		 848
849 wc.sec = boot.tv_sec;
850 wc.nsec = boot.tv_nsec;
851 wc.version = version;
18068523
GOC		 852
853 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
854
855 version++;
856 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 857}
858
50d0a0f9
GH		 859static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
860{
861 uint32_t quotient, remainder;
862
863 /* Don't try to replace with do_div(), this one calculates
864 * "(dividend << 32) / divisor" */
865 __asm__ ( "divl %4"
866 : "=a" (quotient), "=d" (remainder)
867 : "0" (0), "1" (dividend), "r" (divisor) );
868 return quotient;
869}
870
871static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
872{
873 uint64_t nsecs = 1000000000LL;
874 int32_t shift = 0;
875 uint64_t tps64;
876 uint32_t tps32;
877
878 tps64 = tsc_khz * 1000LL;
879 while (tps64 > nsecs*2) {
880 tps64 >>= 1;
881 shift--;
882 }
883
884 tps32 = (uint32_t)tps64;
885 while (tps32 <= (uint32_t)nsecs) {
886 tps32 <<= 1;
887 shift++;
888 }
889
890 hv_clock->tsc_shift = shift;
891 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
892
893 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 894 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 895 hv_clock->tsc_to_system_mul);
896}
897
759379dd
ZA		 898static inline u64 get_kernel_ns(void)
899{
900 struct timespec ts;
901
902 WARN_ON(preemptible());
903 ktime_get_ts(&ts);
904 monotonic_to_bootbased(&ts);
905 return timespec_to_ns(&ts);
906}
907
c8076604
GH		 908static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
909
8cfdc000
ZA		 910static inline int kvm_tsc_changes_freq(void)
911{
912 int cpu = get_cpu();
913 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
914 cpufreq_quick_get(cpu) != 0;
915 put_cpu();
916 return ret;
917}
918
759379dd
ZA		 919static inline u64 nsec_to_cycles(u64 nsec)
920{
217fc9cf
AK		 921 u64 ret;
922
759379dd
ZA		 923 WARN_ON(preemptible());
924 if (kvm_tsc_changes_freq())
925 printk_once(KERN_WARNING
926 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 927 ret = nsec * __get_cpu_var(cpu_tsc_khz);
928 do_div(ret, USEC_PER_SEC);
929 return ret;
759379dd
ZA		 930}
931
99e3e30a
ZA		 932void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
933{
934 struct kvm *kvm = vcpu->kvm;
f38e098f 935 u64 offset, ns, elapsed;
99e3e30a 936 unsigned long flags;
46543ba4 937 s64 sdiff;
99e3e30a
ZA		 938
939 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
940 offset = data - native_read_tsc();
759379dd 941 ns = get_kernel_ns();
f38e098f 942 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 943 sdiff = data - kvm->arch.last_tsc_write;
944 if (sdiff < 0)
945 sdiff = -sdiff;
f38e098f
ZA		 946
947 /*
46543ba4 948 * Special case: close write to TSC within 5 seconds of
f38e098f 949 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 950 * The 5 seconds is to accomodate host load / swapping as
951 * well as any reset of TSC during the boot process.
f38e098f
ZA		 952 *
953 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 954 * or make a best guest using elapsed value.
f38e098f 955 */
46543ba4
ZA		 956 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
957 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 958 if (!check_tsc_unstable()) {
959 offset = kvm->arch.last_tsc_offset;
960 pr_debug("kvm: matched tsc offset for %llu\n", data);
961 } else {
759379dd
ZA		 962 u64 delta = nsec_to_cycles(elapsed);
963 offset += delta;
964 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 965 }
966 ns = kvm->arch.last_tsc_nsec;
967 }
968 kvm->arch.last_tsc_nsec = ns;
969 kvm->arch.last_tsc_write = data;
970 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 971 kvm_x86_ops->write_tsc_offset(vcpu, offset);
972 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
973
974 /* Reset of TSC must disable overshoot protection below */
975 vcpu->arch.hv_clock.tsc_timestamp = 0;
976}
977EXPORT_SYMBOL_GPL(kvm_write_tsc);
978
8cfdc000 979static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 980{
18068523
GOC		 981 unsigned long flags;
982 struct kvm_vcpu_arch *vcpu = &v->arch;
983 void *shared_kaddr;
463656c0 984 unsigned long this_tsc_khz;
1d5f066e
ZA		 985 s64 kernel_ns, max_kernel_ns;
986 u64 tsc_timestamp;
18068523
GOC		 987
988 if ((!vcpu->time_page))
8cfdc000 989 return 0;
50d0a0f9 990
18068523
GOC		 991 /* Keep irq disabled to prevent changes to the clock */
992 local_irq_save(flags);
1d5f066e 993 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 994 kernel_ns = get_kernel_ns();
8cfdc000 995 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 996 local_irq_restore(flags);
997
8cfdc000
ZA		 998 if (unlikely(this_tsc_khz == 0)) {
999 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1000 return 1;
1001 }
18068523 1002
1d5f066e
ZA		 1003 /*
1004 * Time as measured by the TSC may go backwards when resetting the base
1005 * tsc_timestamp. The reason for this is that the TSC resolution is
1006 * higher than the resolution of the other clock scales. Thus, many
1007 * possible measurments of the TSC correspond to one measurement of any
1008 * other clock, and so a spread of values is possible. This is not a
1009 * problem for the computation of the nanosecond clock; with TSC rates
1010 * around 1GHZ, there can only be a few cycles which correspond to one
1011 * nanosecond value, and any path through this code will inevitably
1012 * take longer than that. However, with the kernel_ns value itself,
1013 * the precision may be much lower, down to HZ granularity. If the
1014 * first sampling of TSC against kernel_ns ends in the low part of the
1015 * range, and the second in the high end of the range, we can get:
1016 *
1017 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1018 *
1019 * As the sampling errors potentially range in the thousands of cycles,
1020 * it is possible such a time value has already been observed by the
1021 * guest. To protect against this, we must compute the system time as
1022 * observed by the guest and ensure the new system time is greater.
1023 */
1024 max_kernel_ns = 0;
1025 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1026 max_kernel_ns = vcpu->last_guest_tsc -
1027 vcpu->hv_clock.tsc_timestamp;
1028 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1029 vcpu->hv_clock.tsc_to_system_mul,
1030 vcpu->hv_clock.tsc_shift);
1031 max_kernel_ns += vcpu->last_kernel_ns;
1032 }
1033
e48672fa 1034 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1035 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1036 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1037 }
1038
1d5f066e
ZA		 1039 if (max_kernel_ns > kernel_ns)
1040 kernel_ns = max_kernel_ns;
1041
8cfdc000 1042 /* With all the info we got, fill in the values */
1d5f066e 1043 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1044 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1045 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1046 vcpu->hv_clock.flags = 0;
1047
18068523
GOC		 1048 /*
1049 * The interface expects us to write an even number signaling that the
1050 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1051 * state, we just increase by 2 at the end.
18068523 1052 */
50d0a0f9 1053 vcpu->hv_clock.version += 2;
18068523
GOC		 1054
1055 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1056
1057 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1058 sizeof(vcpu->hv_clock));
18068523
GOC		 1059
1060 kunmap_atomic(shared_kaddr, KM_USER0);
1061
1062 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1063 return 0;
18068523
GOC		 1064}
1065
c8076604
GH		 1066static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1067{
1068 struct kvm_vcpu_arch *vcpu = &v->arch;
1069
1070 if (!vcpu->time_page)
1071 return 0;
a8eeb04a 1072 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1073 return 1;
1074}
1075
9ba075a6
AK		 1076static bool msr_mtrr_valid(unsigned msr)
1077{
1078 switch (msr) {
1079 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1080 case MSR_MTRRfix64K_00000:
1081 case MSR_MTRRfix16K_80000:
1082 case MSR_MTRRfix16K_A0000:
1083 case MSR_MTRRfix4K_C0000:
1084 case MSR_MTRRfix4K_C8000:
1085 case MSR_MTRRfix4K_D0000:
1086 case MSR_MTRRfix4K_D8000:
1087 case MSR_MTRRfix4K_E0000:
1088 case MSR_MTRRfix4K_E8000:
1089 case MSR_MTRRfix4K_F0000:
1090 case MSR_MTRRfix4K_F8000:
1091 case MSR_MTRRdefType:
1092 case MSR_IA32_CR_PAT:
1093 return true;
1094 case 0x2f8:
1095 return true;
1096 }
1097 return false;
1098}
1099
d6289b93
MT		 1100static bool valid_pat_type(unsigned t)
1101{
1102 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1103}
1104
1105static bool valid_mtrr_type(unsigned t)
1106{
1107 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1108}
1109
1110static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1111{
1112 int i;
1113
1114 if (!msr_mtrr_valid(msr))
1115 return false;
1116
1117 if (msr == MSR_IA32_CR_PAT) {
1118 for (i = 0; i < 8; i++)
1119 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1120 return false;
1121 return true;
1122 } else if (msr == MSR_MTRRdefType) {
1123 if (data & ~0xcff)
1124 return false;
1125 return valid_mtrr_type(data & 0xff);
1126 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1127 for (i = 0; i < 8 ; i++)
1128 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1129 return false;
1130 return true;
1131 }
1132
1133 /* variable MTRRs */
1134 return valid_mtrr_type(data & 0xff);
1135}
1136
9ba075a6
AK		 1137static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1138{
0bed3b56
SY		 1139 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1140
d6289b93 1141 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1142 return 1;
1143
0bed3b56
SY		 1144 if (msr == MSR_MTRRdefType) {
1145 vcpu->arch.mtrr_state.def_type = data;
1146 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1147 } else if (msr == MSR_MTRRfix64K_00000)
1148 p[0] = data;
1149 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1150 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1151 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1152 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1153 else if (msr == MSR_IA32_CR_PAT)
1154 vcpu->arch.pat = data;
1155 else { /* Variable MTRRs */
1156 int idx, is_mtrr_mask;
1157 u64 *pt;
1158
1159 idx = (msr - 0x200) / 2;
1160 is_mtrr_mask = msr - 0x200 - 2 * idx;
1161 if (!is_mtrr_mask)
1162 pt =
1163 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1164 else
1165 pt =
1166 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1167 *pt = data;
1168 }
1169
1170 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1171 return 0;
1172}
15c4a640 1173
890ca9ae 1174static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1175{
890ca9ae
HY		 1176 u64 mcg_cap = vcpu->arch.mcg_cap;
1177 unsigned bank_num = mcg_cap & 0xff;
1178
15c4a640 1179 switch (msr) {
15c4a640 1180 case MSR_IA32_MCG_STATUS:
890ca9ae 1181 vcpu->arch.mcg_status = data;
15c4a640 1182 break;
c7ac679c 1183 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1184 if (!(mcg_cap & MCG_CTL_P))
1185 return 1;
1186 if (data != 0 && data != ~(u64)0)
1187 return -1;
1188 vcpu->arch.mcg_ctl = data;
1189 break;
1190 default:
1191 if (msr >= MSR_IA32_MC0_CTL &&
1192 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1193 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1194 /* only 0 or all 1s can be written to IA32_MCi_CTL
1195 * some Linux kernels though clear bit 10 in bank 4 to
1196 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1197 * this to avoid an uncatched #GP in the guest
1198 */
890ca9ae 1199 if ((offset & 0x3) == 0 &&
114be429 1200 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1201 return -1;
1202 vcpu->arch.mce_banks[offset] = data;
1203 break;
1204 }
1205 return 1;
1206 }
1207 return 0;
1208}
1209
ffde22ac
ES		 1210static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1211{
1212 struct kvm *kvm = vcpu->kvm;
1213 int lm = is_long_mode(vcpu);
1214 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1215 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1216 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1217 : kvm->arch.xen_hvm_config.blob_size_32;
1218 u32 page_num = data & ~PAGE_MASK;
1219 u64 page_addr = data & PAGE_MASK;
1220 u8 *page;
1221 int r;
1222
1223 r = -E2BIG;
1224 if (page_num >= blob_size)
1225 goto out;
1226 r = -ENOMEM;
1227 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1228 if (!page)
1229 goto out;
1230 r = -EFAULT;
1231 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1232 goto out_free;
1233 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1234 goto out_free;
1235 r = 0;
1236out_free:
1237 kfree(page);
1238out:
1239 return r;
1240}
1241
55cd8e5a
GN		 1242static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1243{
1244 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1245}
1246
1247static bool kvm_hv_msr_partition_wide(u32 msr)
1248{
1249 bool r = false;
1250 switch (msr) {
1251 case HV_X64_MSR_GUEST_OS_ID:
1252 case HV_X64_MSR_HYPERCALL:
1253 r = true;
1254 break;
1255 }
1256
1257 return r;
1258}
1259
1260static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1261{
1262 struct kvm *kvm = vcpu->kvm;
1263
1264 switch (msr) {
1265 case HV_X64_MSR_GUEST_OS_ID:
1266 kvm->arch.hv_guest_os_id = data;
1267 /* setting guest os id to zero disables hypercall page */
1268 if (!kvm->arch.hv_guest_os_id)
1269 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1270 break;
1271 case HV_X64_MSR_HYPERCALL: {
1272 u64 gfn;
1273 unsigned long addr;
1274 u8 instructions[4];
1275
1276 /* if guest os id is not set hypercall should remain disabled */
1277 if (!kvm->arch.hv_guest_os_id)
1278 break;
1279 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1280 kvm->arch.hv_hypercall = data;
1281 break;
1282 }
1283 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1284 addr = gfn_to_hva(kvm, gfn);
1285 if (kvm_is_error_hva(addr))
1286 return 1;
1287 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1288 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1289 if (copy_to_user((void __user *)addr, instructions, 4))
1290 return 1;
1291 kvm->arch.hv_hypercall = data;
1292 break;
1293 }
1294 default:
1295 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1296 "data 0x%llx\n", msr, data);
1297 return 1;
1298 }
1299 return 0;
1300}
1301
1302static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1303{
10388a07
GN		 1304 switch (msr) {
1305 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1306 unsigned long addr;
55cd8e5a 1307
10388a07
GN		 1308 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1309 vcpu->arch.hv_vapic = data;
1310 break;
1311 }
1312 addr = gfn_to_hva(vcpu->kvm, data >>
1313 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1314 if (kvm_is_error_hva(addr))
1315 return 1;
1316 if (clear_user((void __user *)addr, PAGE_SIZE))
1317 return 1;
1318 vcpu->arch.hv_vapic = data;
1319 break;
1320 }
1321 case HV_X64_MSR_EOI:
1322 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1323 case HV_X64_MSR_ICR:
1324 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1325 case HV_X64_MSR_TPR:
1326 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1327 default:
1328 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1329 "data 0x%llx\n", msr, data);
1330 return 1;
1331 }
1332
1333 return 0;
55cd8e5a
GN		 1334}
1335
15c4a640
CO		 1336int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1337{
1338 switch (msr) {
15c4a640 1339 case MSR_EFER:
b69e8cae 1340 return set_efer(vcpu, data);
8f1589d9
AP		 1341 case MSR_K7_HWCR:
1342 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1343 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1344 if (data != 0) {
1345 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1346 data);
1347 return 1;
1348 }
15c4a640 1349 break;
f7c6d140
AP		 1350 case MSR_FAM10H_MMIO_CONF_BASE:
1351 if (data != 0) {
1352 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1353 "0x%llx\n", data);
1354 return 1;
1355 }
15c4a640 1356 break;
c323c0e5 1357 case MSR_AMD64_NB_CFG:
c7ac679c 1358 break;
b5e2fec0
AG		 1359 case MSR_IA32_DEBUGCTLMSR:
1360 if (!data) {
1361 /* We support the non-activated case already */
1362 break;
1363 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1364 /* Values other than LBR and BTF are vendor-specific,
1365 thus reserved and should throw a #GP */
1366 return 1;
1367 }
1368 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1369 __func__, data);
1370 break;
15c4a640
CO		 1371 case MSR_IA32_UCODE_REV:
1372 case MSR_IA32_UCODE_WRITE:
61a6bd67 1373 case MSR_VM_HSAVE_PA:
6098ca93 1374 case MSR_AMD64_PATCH_LOADER:
15c4a640 1375 break;
9ba075a6
AK		 1376 case 0x200 ... 0x2ff:
1377 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1378 case MSR_IA32_APICBASE:
1379 kvm_set_apic_base(vcpu, data);
1380 break;
0105d1a5
GN		 1381 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1382 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1383 case MSR_IA32_MISC_ENABLE:
ad312c7c 1384 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1385 break;
11c6bffa 1386 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1387 case MSR_KVM_WALL_CLOCK:
1388 vcpu->kvm->arch.wall_clock = data;
1389 kvm_write_wall_clock(vcpu->kvm, data);
1390 break;
11c6bffa 1391 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1392 case MSR_KVM_SYSTEM_TIME: {
1393 if (vcpu->arch.time_page) {
1394 kvm_release_page_dirty(vcpu->arch.time_page);
1395 vcpu->arch.time_page = NULL;
1396 }
1397
1398 vcpu->arch.time = data;
1399
1400 /* we verify if the enable bit is set... */
1401 if (!(data & 1))
1402 break;
1403
1404 /* ...but clean it before doing the actual write */
1405 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1406
18068523
GOC		 1407 vcpu->arch.time_page =
1408 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1409
1410 if (is_error_page(vcpu->arch.time_page)) {
1411 kvm_release_page_clean(vcpu->arch.time_page);
1412 vcpu->arch.time_page = NULL;
1413 }
1414
c8076604 1415 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1416 break;
1417 }
890ca9ae
HY		 1418 case MSR_IA32_MCG_CTL:
1419 case MSR_IA32_MCG_STATUS:
1420 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1421 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1422
1423 /* Performance counters are not protected by a CPUID bit,
1424 * so we should check all of them in the generic path for the sake of
1425 * cross vendor migration.
1426 * Writing a zero into the event select MSRs disables them,
1427 * which we perfectly emulate ;-). Any other value should be at least
1428 * reported, some guests depend on them.
1429 */
1430 case MSR_P6_EVNTSEL0:
1431 case MSR_P6_EVNTSEL1:
1432 case MSR_K7_EVNTSEL0:
1433 case MSR_K7_EVNTSEL1:
1434 case MSR_K7_EVNTSEL2:
1435 case MSR_K7_EVNTSEL3:
1436 if (data != 0)
1437 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1438 "0x%x data 0x%llx\n", msr, data);
1439 break;
1440 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1441 * so we ignore writes to make it happy.
1442 */
1443 case MSR_P6_PERFCTR0:
1444 case MSR_P6_PERFCTR1:
1445 case MSR_K7_PERFCTR0:
1446 case MSR_K7_PERFCTR1:
1447 case MSR_K7_PERFCTR2:
1448 case MSR_K7_PERFCTR3:
1449 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1450 "0x%x data 0x%llx\n", msr, data);
1451 break;
55cd8e5a
GN		 1452 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1453 if (kvm_hv_msr_partition_wide(msr)) {
1454 int r;
1455 mutex_lock(&vcpu->kvm->lock);
1456 r = set_msr_hyperv_pw(vcpu, msr, data);
1457 mutex_unlock(&vcpu->kvm->lock);
1458 return r;
1459 } else
1460 return set_msr_hyperv(vcpu, msr, data);
1461 break;
15c4a640 1462 default:
ffde22ac
ES		 1463 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1464 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1465 if (!ignore_msrs) {
1466 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1467 msr, data);
1468 return 1;
1469 } else {
1470 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1471 msr, data);
1472 break;
1473 }
15c4a640
CO		 1474 }
1475 return 0;
1476}
1477EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1478
1479
1480/*
1481 * Reads an msr value (of 'msr_index') into 'pdata'.
1482 * Returns 0 on success, non-0 otherwise.
1483 * Assumes vcpu_load() was already called.
1484 */
1485int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1486{
1487 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1488}
1489
9ba075a6
AK		 1490static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1491{
0bed3b56
SY		 1492 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1493
9ba075a6
AK		 1494 if (!msr_mtrr_valid(msr))
1495 return 1;
1496
0bed3b56
SY		 1497 if (msr == MSR_MTRRdefType)
1498 *pdata = vcpu->arch.mtrr_state.def_type +
1499 (vcpu->arch.mtrr_state.enabled << 10);
1500 else if (msr == MSR_MTRRfix64K_00000)
1501 *pdata = p[0];
1502 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1503 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1504 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1505 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1506 else if (msr == MSR_IA32_CR_PAT)
1507 *pdata = vcpu->arch.pat;
1508 else { /* Variable MTRRs */
1509 int idx, is_mtrr_mask;
1510 u64 *pt;
1511
1512 idx = (msr - 0x200) / 2;
1513 is_mtrr_mask = msr - 0x200 - 2 * idx;
1514 if (!is_mtrr_mask)
1515 pt =
1516 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1517 else
1518 pt =
1519 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1520 *pdata = *pt;
1521 }
1522
9ba075a6
AK		 1523 return 0;
1524}
1525
890ca9ae 1526static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1527{
1528 u64 data;
890ca9ae
HY		 1529 u64 mcg_cap = vcpu->arch.mcg_cap;
1530 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1531
1532 switch (msr) {
15c4a640
CO		 1533 case MSR_IA32_P5_MC_ADDR:
1534 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1535 data = 0;
1536 break;
15c4a640 1537 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1538 data = vcpu->arch.mcg_cap;
1539 break;
c7ac679c 1540 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1541 if (!(mcg_cap & MCG_CTL_P))
1542 return 1;
1543 data = vcpu->arch.mcg_ctl;
1544 break;
1545 case MSR_IA32_MCG_STATUS:
1546 data = vcpu->arch.mcg_status;
1547 break;
1548 default:
1549 if (msr >= MSR_IA32_MC0_CTL &&
1550 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1551 u32 offset = msr - MSR_IA32_MC0_CTL;
1552 data = vcpu->arch.mce_banks[offset];
1553 break;
1554 }
1555 return 1;
1556 }
1557 *pdata = data;
1558 return 0;
1559}
1560
55cd8e5a
GN		 1561static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1562{
1563 u64 data = 0;
1564 struct kvm *kvm = vcpu->kvm;
1565
1566 switch (msr) {
1567 case HV_X64_MSR_GUEST_OS_ID:
1568 data = kvm->arch.hv_guest_os_id;
1569 break;
1570 case HV_X64_MSR_HYPERCALL:
1571 data = kvm->arch.hv_hypercall;
1572 break;
1573 default:
1574 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1575 return 1;
1576 }
1577
1578 *pdata = data;
1579 return 0;
1580}
1581
1582static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1583{
1584 u64 data = 0;
1585
1586 switch (msr) {
1587 case HV_X64_MSR_VP_INDEX: {
1588 int r;
1589 struct kvm_vcpu *v;
1590 kvm_for_each_vcpu(r, v, vcpu->kvm)
1591 if (v == vcpu)
1592 data = r;
1593 break;
1594 }
10388a07
GN		 1595 case HV_X64_MSR_EOI:
1596 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1597 case HV_X64_MSR_ICR:
1598 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1599 case HV_X64_MSR_TPR:
1600 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1601 default:
1602 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1603 return 1;
1604 }
1605 *pdata = data;
1606 return 0;
1607}
1608
890ca9ae
HY		 1609int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1610{
1611 u64 data;
1612
1613 switch (msr) {
890ca9ae 1614 case MSR_IA32_PLATFORM_ID:
15c4a640 1615 case MSR_IA32_UCODE_REV:
15c4a640 1616 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1617 case MSR_IA32_DEBUGCTLMSR:
1618 case MSR_IA32_LASTBRANCHFROMIP:
1619 case MSR_IA32_LASTBRANCHTOIP:
1620 case MSR_IA32_LASTINTFROMIP:
1621 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1622 case MSR_K8_SYSCFG:
1623 case MSR_K7_HWCR:
61a6bd67 1624 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1625 case MSR_P6_PERFCTR0:
1626 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1627 case MSR_P6_EVNTSEL0:
1628 case MSR_P6_EVNTSEL1:
9e699624 1629 case MSR_K7_EVNTSEL0:
1f3ee616 1630 case MSR_K7_PERFCTR0:
1fdbd48c 1631 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1632 case MSR_AMD64_NB_CFG:
f7c6d140 1633 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1634 data = 0;
1635 break;
9ba075a6
AK		 1636 case MSR_MTRRcap:
1637 data = 0x500 | KVM_NR_VAR_MTRR;
1638 break;
1639 case 0x200 ... 0x2ff:
1640 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1641 case 0xcd: /* fsb frequency */
1642 data = 3;
1643 break;
1644 case MSR_IA32_APICBASE:
1645 data = kvm_get_apic_base(vcpu);
1646 break;
0105d1a5
GN		 1647 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1648 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1649 break;
15c4a640 1650 case MSR_IA32_MISC_ENABLE:
ad312c7c 1651 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1652 break;
847f0ad8
AG		 1653 case MSR_IA32_PERF_STATUS:
1654 /* TSC increment by tick */
1655 data = 1000ULL;
1656 /* CPU multiplier */
1657 data |= (((uint64_t)4ULL) << 40);
1658 break;
15c4a640 1659 case MSR_EFER:
f6801dff 1660 data = vcpu->arch.efer;
15c4a640 1661 break;
18068523 1662 case MSR_KVM_WALL_CLOCK:
11c6bffa 1663 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1664 data = vcpu->kvm->arch.wall_clock;
1665 break;
1666 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1667 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1668 data = vcpu->arch.time;
1669 break;
890ca9ae
HY		 1670 case MSR_IA32_P5_MC_ADDR:
1671 case MSR_IA32_P5_MC_TYPE:
1672 case MSR_IA32_MCG_CAP:
1673 case MSR_IA32_MCG_CTL:
1674 case MSR_IA32_MCG_STATUS:
1675 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1676 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1677 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1678 if (kvm_hv_msr_partition_wide(msr)) {
1679 int r;
1680 mutex_lock(&vcpu->kvm->lock);
1681 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1682 mutex_unlock(&vcpu->kvm->lock);
1683 return r;
1684 } else
1685 return get_msr_hyperv(vcpu, msr, pdata);
1686 break;
15c4a640 1687 default:
ed85c068
AP		 1688 if (!ignore_msrs) {
1689 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1690 return 1;
1691 } else {
1692 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1693 data = 0;
1694 }
1695 break;
15c4a640
CO		 1696 }
1697 *pdata = data;
1698 return 0;
1699}
1700EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1701
313a3dc7
CO		 1702/*
1703 * Read or write a bunch of msrs. All parameters are kernel addresses.
1704 *
1705 * @return number of msrs set successfully.
1706 */
1707static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1708 struct kvm_msr_entry *entries,
1709 int (*do_msr)(struct kvm_vcpu *vcpu,
1710 unsigned index, u64 *data))
1711{
f656ce01 1712 int i, idx;
313a3dc7 1713
f656ce01 1714 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1715 for (i = 0; i < msrs->nmsrs; ++i)
1716 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1717 break;
f656ce01 1718 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1719
313a3dc7
CO		 1720 return i;
1721}
1722
1723/*
1724 * Read or write a bunch of msrs. Parameters are user addresses.
1725 *
1726 * @return number of msrs set successfully.
1727 */
1728static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1729 int (*do_msr)(struct kvm_vcpu *vcpu,
1730 unsigned index, u64 *data),
1731 int writeback)
1732{
1733 struct kvm_msrs msrs;
1734 struct kvm_msr_entry *entries;
1735 int r, n;
1736 unsigned size;
1737
1738 r = -EFAULT;
1739 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1740 goto out;
1741
1742 r = -E2BIG;
1743 if (msrs.nmsrs >= MAX_IO_MSRS)
1744 goto out;
1745
1746 r = -ENOMEM;
1747 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1748 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1749 if (!entries)
1750 goto out;
1751
1752 r = -EFAULT;
1753 if (copy_from_user(entries, user_msrs->entries, size))
1754 goto out_free;
1755
1756 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1757 if (r < 0)
1758 goto out_free;
1759
1760 r = -EFAULT;
1761 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1762 goto out_free;
1763
1764 r = n;
1765
1766out_free:
7a73c028 1767 kfree(entries);
313a3dc7
CO		 1768out:
1769 return r;
1770}
1771
018d00d2
ZX		 1772int kvm_dev_ioctl_check_extension(long ext)
1773{
1774 int r;
1775
1776 switch (ext) {
1777 case KVM_CAP_IRQCHIP:
1778 case KVM_CAP_HLT:
1779 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1780 case KVM_CAP_SET_TSS_ADDR:
07716717 1781 case KVM_CAP_EXT_CPUID:
c8076604 1782 case KVM_CAP_CLOCKSOURCE:
7837699f 1783 case KVM_CAP_PIT:
a28e4f5a 1784 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1785 case KVM_CAP_MP_STATE:
ed848624 1786 case KVM_CAP_SYNC_MMU:
52d939a0 1787 case KVM_CAP_REINJECT_CONTROL:
4925663a 1788 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1789 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1790 case KVM_CAP_IRQFD:
d34e6b17 1791 case KVM_CAP_IOEVENTFD:
c5ff41ce 1792 case KVM_CAP_PIT2:
e9f42757 1793 case KVM_CAP_PIT_STATE2:
b927a3ce 1794 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1795 case KVM_CAP_XEN_HVM:
afbcf7ab 1796 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1797 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1798 case KVM_CAP_HYPERV:
10388a07 1799 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1800 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1801 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1802 case KVM_CAP_DEBUGREGS:
d2be1651 1803 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1804 case KVM_CAP_XSAVE:
018d00d2
ZX		 1805 r = 1;
1806 break;
542472b5
LV		 1807 case KVM_CAP_COALESCED_MMIO:
1808 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1809 break;
774ead3a
AK		 1810 case KVM_CAP_VAPIC:
1811 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1812 break;
f725230a
AK		 1813 case KVM_CAP_NR_VCPUS:
1814 r = KVM_MAX_VCPUS;
1815 break;
a988b910
AK		 1816 case KVM_CAP_NR_MEMSLOTS:
1817 r = KVM_MEMORY_SLOTS;
1818 break;
a68a6a72
MT		 1819 case KVM_CAP_PV_MMU: /* obsolete */
1820 r = 0;
2f333bcb 1821 break;
62c476c7 1822 case KVM_CAP_IOMMU:
19de40a8 1823 r = iommu_found();
62c476c7 1824 break;
890ca9ae
HY		 1825 case KVM_CAP_MCE:
1826 r = KVM_MAX_MCE_BANKS;
1827 break;
2d5b5a66
SY		 1828 case KVM_CAP_XCRS:
1829 r = cpu_has_xsave;
1830 break;
018d00d2
ZX		 1831 default:
1832 r = 0;
1833 break;
1834 }
1835 return r;
1836
1837}
1838
043405e1
CO		 1839long kvm_arch_dev_ioctl(struct file *filp,
1840 unsigned int ioctl, unsigned long arg)
1841{
1842 void __user *argp = (void __user *)arg;
1843 long r;
1844
1845 switch (ioctl) {
1846 case KVM_GET_MSR_INDEX_LIST: {
1847 struct kvm_msr_list __user *user_msr_list = argp;
1848 struct kvm_msr_list msr_list;
1849 unsigned n;
1850
1851 r = -EFAULT;
1852 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1853 goto out;
1854 n = msr_list.nmsrs;
1855 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1856 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1857 goto out;
1858 r = -E2BIG;
e125e7b6 1859 if (n < msr_list.nmsrs)
043405e1
CO		 1860 goto out;
1861 r = -EFAULT;
1862 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1863 num_msrs_to_save * sizeof(u32)))
1864 goto out;
e125e7b6 1865 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1866 &emulated_msrs,
1867 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1868 goto out;
1869 r = 0;
1870 break;
1871 }
674eea0f
AK		 1872 case KVM_GET_SUPPORTED_CPUID: {
1873 struct kvm_cpuid2 __user *cpuid_arg = argp;
1874 struct kvm_cpuid2 cpuid;
1875
1876 r = -EFAULT;
1877 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1878 goto out;
1879 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1880 cpuid_arg->entries);
674eea0f
AK		 1881 if (r)
1882 goto out;
1883
1884 r = -EFAULT;
1885 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1886 goto out;
1887 r = 0;
1888 break;
1889 }
890ca9ae
HY		 1890 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1891 u64 mce_cap;
1892
1893 mce_cap = KVM_MCE_CAP_SUPPORTED;
1894 r = -EFAULT;
1895 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1896 goto out;
1897 r = 0;
1898 break;
1899 }
043405e1
CO		 1900 default:
1901 r = -EINVAL;
1902 }
1903out:
1904 return r;
1905}
1906
f5f48ee1
SY		 1907static void wbinvd_ipi(void *garbage)
1908{
1909 wbinvd();
1910}
1911
1912static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1913{
1914 return vcpu->kvm->arch.iommu_domain &&
1915 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1916}
1917
313a3dc7
CO		 1918void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1919{
f5f48ee1
SY		 1920 /* Address WBINVD may be executed by guest */
1921 if (need_emulate_wbinvd(vcpu)) {
1922 if (kvm_x86_ops->has_wbinvd_exit())
1923 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1924 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1925 smp_call_function_single(vcpu->cpu,
1926 wbinvd_ipi, NULL, 1);
1927 }
1928
313a3dc7 1929 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 1930 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 1931 /* Make sure TSC doesn't go backwards */
1932 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
1933 native_read_tsc() - vcpu->arch.last_host_tsc;
1934 if (tsc_delta < 0)
1935 mark_tsc_unstable("KVM discovered backwards TSC");
1936 if (check_tsc_unstable())
1937 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
1938 kvm_migrate_timers(vcpu);
1939 vcpu->cpu = cpu;
1940 }
313a3dc7
CO		 1941}
1942
1943void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1944{
02daab21 1945 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1946 kvm_put_guest_fpu(vcpu);
e48672fa 1947 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 1948}
1949
07716717 1950static int is_efer_nx(void)
313a3dc7 1951{
e286e86e 1952 unsigned long long efer = 0;
313a3dc7 1953
e286e86e 1954 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1955 return efer & EFER_NX;
1956}
1957
1958static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1959{
1960 int i;
1961 struct kvm_cpuid_entry2 *e, *entry;
1962
313a3dc7 1963 entry = NULL;
ad312c7c
ZX		 1964 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1965 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1966 if (e->function == 0x80000001) {
1967 entry = e;
1968 break;
1969 }
1970 }
07716717 1971 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1972 entry->edx &= ~(1 << 20);
1973 printk(KERN_INFO "kvm: guest NX capability removed\n");
1974 }
1975}
1976
07716717 1977/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1978static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1979 struct kvm_cpuid *cpuid,
1980 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1981{
1982 int r, i;
1983 struct kvm_cpuid_entry *cpuid_entries;
1984
1985 r = -E2BIG;
1986 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1987 goto out;
1988 r = -ENOMEM;
1989 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1990 if (!cpuid_entries)
1991 goto out;
1992 r = -EFAULT;
1993 if (copy_from_user(cpuid_entries, entries,
1994 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1995 goto out_free;
1996 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1997 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1998 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1999 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2000 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2001 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2002 vcpu->arch.cpuid_entries[i].index = 0;
2003 vcpu->arch.cpuid_entries[i].flags = 0;
2004 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2005 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2006 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2007 }
2008 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2009 cpuid_fix_nx_cap(vcpu);
2010 r = 0;
fc61b800 2011 kvm_apic_set_version(vcpu);
0e851880 2012 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2013 update_cpuid(vcpu);
07716717
DK		 2014
2015out_free:
2016 vfree(cpuid_entries);
2017out:
2018 return r;
2019}
2020
2021static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2022 struct kvm_cpuid2 *cpuid,
2023 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2024{
2025 int r;
2026
2027 r = -E2BIG;
2028 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2029 goto out;
2030 r = -EFAULT;
ad312c7c 2031 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2032 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2033 goto out;
ad312c7c 2034 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2035 kvm_apic_set_version(vcpu);
0e851880 2036 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2037 update_cpuid(vcpu);
313a3dc7
CO		 2038 return 0;
2039
2040out:
2041 return r;
2042}
2043
07716717 2044static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2045 struct kvm_cpuid2 *cpuid,
2046 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2047{
2048 int r;
2049
2050 r = -E2BIG;
ad312c7c 2051 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2052 goto out;
2053 r = -EFAULT;
ad312c7c 2054 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2055 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2056 goto out;
2057 return 0;
2058
2059out:
ad312c7c 2060 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2061 return r;
2062}
2063
07716717 2064static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2065 u32 index)
07716717
DK		 2066{
2067 entry->function = function;
2068 entry->index = index;
2069 cpuid_count(entry->function, entry->index,
19355475 2070 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2071 entry->flags = 0;
2072}
2073
7faa4ee1
AK		 2074#define F(x) bit(X86_FEATURE_##x)
2075
07716717
DK		 2076static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2077 u32 index, int *nent, int maxnent)
2078{
7faa4ee1 2079 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2080#ifdef CONFIG_X86_64
17cc3935
SY		 2081 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2082 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2083 unsigned f_lm = F(LM);
2084#else
17cc3935 2085 unsigned f_gbpages = 0;
7faa4ee1 2086 unsigned f_lm = 0;
07716717 2087#endif
4e47c7a6 2088 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2089
2090 /* cpuid 1.edx */
2091 const u32 kvm_supported_word0_x86_features =
2092 F(FPU) | F(VME) | F(DE) | F(PSE) |
2093 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2094 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2095 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2096 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2097 0 /* Reserved, DS, ACPI */ | F(MMX) |
2098 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2099 0 /* HTT, TM, Reserved, PBE */;
2100 /* cpuid 0x80000001.edx */
2101 const u32 kvm_supported_word1_x86_features =
2102 F(FPU) | F(VME) | F(DE) | F(PSE) |
2103 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2104 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2105 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2106 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2107 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2108 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2109 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2110 /* cpuid 1.ecx */
2111 const u32 kvm_supported_word4_x86_features =
6c3f6041 2112 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2113 0 /* DS-CPL, VMX, SMX, EST */ |
2114 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2115 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2116 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2117 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2118 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2119 /* cpuid 0x80000001.ecx */
07716717 2120 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2121 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2122 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2123 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2124 0 /* SKINIT */ | 0 /* WDT */;
07716717 2125
19355475 2126 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2127 get_cpu();
2128 do_cpuid_1_ent(entry, function, index);
2129 ++*nent;
2130
2131 switch (function) {
2132 case 0:
2acf923e 2133 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2134 break;
2135 case 1:
2136 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2137 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2138 /* we support x2apic emulation even if host does not support
2139 * it since we emulate x2apic in software */
2140 entry->ecx |= F(X2APIC);
07716717
DK		 2141 break;
2142 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2143 * may return different values. This forces us to get_cpu() before
2144 * issuing the first command, and also to emulate this annoying behavior
2145 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2146 case 2: {
2147 int t, times = entry->eax & 0xff;
2148
2149 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2150 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2151 for (t = 1; t < times && *nent < maxnent; ++t) {
2152 do_cpuid_1_ent(&entry[t], function, 0);
2153 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2154 ++*nent;
2155 }
2156 break;
2157 }
2158 /* function 4 and 0xb have additional index. */
2159 case 4: {
14af3f3c 2160 int i, cache_type;
07716717
DK		 2161
2162 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2163 /* read more entries until cache_type is zero */
14af3f3c
HH		 2164 for (i = 1; *nent < maxnent; ++i) {
2165 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2166 if (!cache_type)
2167 break;
14af3f3c
HH		 2168 do_cpuid_1_ent(&entry[i], function, i);
2169 entry[i].flags |=
07716717
DK		 2170 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2171 ++*nent;
2172 }
2173 break;
2174 }
2175 case 0xb: {
14af3f3c 2176 int i, level_type;
07716717
DK		 2177
2178 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2179 /* read more entries until level_type is zero */
14af3f3c 2180 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2181 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2182 if (!level_type)
2183 break;
14af3f3c
HH		 2184 do_cpuid_1_ent(&entry[i], function, i);
2185 entry[i].flags |=
07716717
DK		 2186 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2187 ++*nent;
2188 }
2189 break;
2190 }
2acf923e
DC		 2191 case 0xd: {
2192 int i;
2193
2194 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2195 for (i = 1; *nent < maxnent; ++i) {
2196 if (entry[i - 1].eax == 0 && i != 2)
2197 break;
2198 do_cpuid_1_ent(&entry[i], function, i);
2199 entry[i].flags |=
2200 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2201 ++*nent;
2202 }
2203 break;
2204 }
84478c82
GC		 2205 case KVM_CPUID_SIGNATURE: {
2206 char signature[12] = "KVMKVMKVM\0\0";
2207 u32 *sigptr = (u32 *)signature;
2208 entry->eax = 0;
2209 entry->ebx = sigptr[0];
2210 entry->ecx = sigptr[1];
2211 entry->edx = sigptr[2];
2212 break;
2213 }
2214 case KVM_CPUID_FEATURES:
2215 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2216 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2217 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2218 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2219 entry->ebx = 0;
2220 entry->ecx = 0;
2221 entry->edx = 0;
2222 break;
07716717
DK		 2223 case 0x80000000:
2224 entry->eax = min(entry->eax, 0x8000001a);
2225 break;
2226 case 0x80000001:
2227 entry->edx &= kvm_supported_word1_x86_features;
2228 entry->ecx &= kvm_supported_word6_x86_features;
2229 break;
2230 }
d4330ef2
JR		 2231
2232 kvm_x86_ops->set_supported_cpuid(function, entry);
2233
07716717
DK		 2234 put_cpu();
2235}
2236
7faa4ee1
AK		 2237#undef F
2238
674eea0f 2239static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2240 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2241{
2242 struct kvm_cpuid_entry2 *cpuid_entries;
2243 int limit, nent = 0, r = -E2BIG;
2244 u32 func;
2245
2246 if (cpuid->nent < 1)
2247 goto out;
6a544355
AK		 2248 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2249 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2250 r = -ENOMEM;
2251 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2252 if (!cpuid_entries)
2253 goto out;
2254
2255 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2256 limit = cpuid_entries[0].eax;
2257 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2258 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2259 &nent, cpuid->nent);
07716717
DK		 2260 r = -E2BIG;
2261 if (nent >= cpuid->nent)
2262 goto out_free;
2263
2264 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2265 limit = cpuid_entries[nent - 1].eax;
2266 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2267 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2268 &nent, cpuid->nent);
84478c82
GC		 2269
2270
2271
2272 r = -E2BIG;
2273 if (nent >= cpuid->nent)
2274 goto out_free;
2275
2276 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2277 cpuid->nent);
2278
2279 r = -E2BIG;
2280 if (nent >= cpuid->nent)
2281 goto out_free;
2282
2283 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2284 cpuid->nent);
2285
cb007648
MM		 2286 r = -E2BIG;
2287 if (nent >= cpuid->nent)
2288 goto out_free;
2289
07716717
DK		 2290 r = -EFAULT;
2291 if (copy_to_user(entries, cpuid_entries,
19355475 2292 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2293 goto out_free;
2294 cpuid->nent = nent;
2295 r = 0;
2296
2297out_free:
2298 vfree(cpuid_entries);
2299out:
2300 return r;
2301}
2302
313a3dc7
CO		 2303static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2304 struct kvm_lapic_state *s)
2305{
ad312c7c 2306 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2307
2308 return 0;
2309}
2310
2311static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2312 struct kvm_lapic_state *s)
2313{
ad312c7c 2314 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2315 kvm_apic_post_state_restore(vcpu);
cb142eb7 2316 update_cr8_intercept(vcpu);
313a3dc7
CO		 2317
2318 return 0;
2319}
2320
f77bc6a4
ZX		 2321static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2322 struct kvm_interrupt *irq)
2323{
2324 if (irq->irq < 0 || irq->irq >= 256)
2325 return -EINVAL;
2326 if (irqchip_in_kernel(vcpu->kvm))
2327 return -ENXIO;
f77bc6a4 2328
66fd3f7f 2329 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2330
f77bc6a4
ZX		 2331 return 0;
2332}
2333
c4abb7c9
JK		 2334static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2335{
c4abb7c9 2336 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2337
2338 return 0;
2339}
2340
b209749f
AK		 2341static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2342 struct kvm_tpr_access_ctl *tac)
2343{
2344 if (tac->flags)
2345 return -EINVAL;
2346 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2347 return 0;
2348}
2349
890ca9ae
HY		 2350static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2351 u64 mcg_cap)
2352{
2353 int r;
2354 unsigned bank_num = mcg_cap & 0xff, bank;
2355
2356 r = -EINVAL;
a9e38c3e 2357 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2358 goto out;
2359 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2360 goto out;
2361 r = 0;
2362 vcpu->arch.mcg_cap = mcg_cap;
2363 /* Init IA32_MCG_CTL to all 1s */
2364 if (mcg_cap & MCG_CTL_P)
2365 vcpu->arch.mcg_ctl = ~(u64)0;
2366 /* Init IA32_MCi_CTL to all 1s */
2367 for (bank = 0; bank < bank_num; bank++)
2368 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2369out:
2370 return r;
2371}
2372
2373static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2374 struct kvm_x86_mce *mce)
2375{
2376 u64 mcg_cap = vcpu->arch.mcg_cap;
2377 unsigned bank_num = mcg_cap & 0xff;
2378 u64 *banks = vcpu->arch.mce_banks;
2379
2380 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2381 return -EINVAL;
2382 /*
2383 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2384 * reporting is disabled
2385 */
2386 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2387 vcpu->arch.mcg_ctl != ~(u64)0)
2388 return 0;
2389 banks += 4 * mce->bank;
2390 /*
2391 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2392 * reporting is disabled for the bank
2393 */
2394 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2395 return 0;
2396 if (mce->status & MCI_STATUS_UC) {
2397 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2398 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2399 printk(KERN_DEBUG "kvm: set_mce: "
2400 "injects mce exception while "
2401 "previous one is in progress!\n");
a8eeb04a 2402 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2403 return 0;
2404 }
2405 if (banks[1] & MCI_STATUS_VAL)
2406 mce->status |= MCI_STATUS_OVER;
2407 banks[2] = mce->addr;
2408 banks[3] = mce->misc;
2409 vcpu->arch.mcg_status = mce->mcg_status;
2410 banks[1] = mce->status;
2411 kvm_queue_exception(vcpu, MC_VECTOR);
2412 } else if (!(banks[1] & MCI_STATUS_VAL)
2413 || !(banks[1] & MCI_STATUS_UC)) {
2414 if (banks[1] & MCI_STATUS_VAL)
2415 mce->status |= MCI_STATUS_OVER;
2416 banks[2] = mce->addr;
2417 banks[3] = mce->misc;
2418 banks[1] = mce->status;
2419 } else
2420 banks[1] |= MCI_STATUS_OVER;
2421 return 0;
2422}
2423
3cfc3092
JK		 2424static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2425 struct kvm_vcpu_events *events)
2426{
03b82a30
JK		 2427 events->exception.injected =
2428 vcpu->arch.exception.pending &&
2429 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2430 events->exception.nr = vcpu->arch.exception.nr;
2431 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2432 events->exception.error_code = vcpu->arch.exception.error_code;
2433
03b82a30
JK		 2434 events->interrupt.injected =
2435 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2436 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2437 events->interrupt.soft = 0;
48005f64
JK		 2438 events->interrupt.shadow =
2439 kvm_x86_ops->get_interrupt_shadow(vcpu,
2440 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2441
2442 events->nmi.injected = vcpu->arch.nmi_injected;
2443 events->nmi.pending = vcpu->arch.nmi_pending;
2444 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2445
2446 events->sipi_vector = vcpu->arch.sipi_vector;
2447
dab4b911 2448 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2449 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2450 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2451}
2452
2453static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2454 struct kvm_vcpu_events *events)
2455{
dab4b911 2456 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2457 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2458 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2459 return -EINVAL;
2460
3cfc3092
JK		 2461 vcpu->arch.exception.pending = events->exception.injected;
2462 vcpu->arch.exception.nr = events->exception.nr;
2463 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2464 vcpu->arch.exception.error_code = events->exception.error_code;
2465
2466 vcpu->arch.interrupt.pending = events->interrupt.injected;
2467 vcpu->arch.interrupt.nr = events->interrupt.nr;
2468 vcpu->arch.interrupt.soft = events->interrupt.soft;
2469 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2470 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2471 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2472 kvm_x86_ops->set_interrupt_shadow(vcpu,
2473 events->interrupt.shadow);
3cfc3092
JK		 2474
2475 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2476 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2477 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2478 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2479
dab4b911
JK		 2480 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2481 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2482
3cfc3092
JK		 2483 return 0;
2484}
2485
a1efbe77
JK		 2486static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2487 struct kvm_debugregs *dbgregs)
2488{
a1efbe77
JK		 2489 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2490 dbgregs->dr6 = vcpu->arch.dr6;
2491 dbgregs->dr7 = vcpu->arch.dr7;
2492 dbgregs->flags = 0;
a1efbe77
JK		 2493}
2494
2495static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2496 struct kvm_debugregs *dbgregs)
2497{
2498 if (dbgregs->flags)
2499 return -EINVAL;
2500
a1efbe77
JK		 2501 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2502 vcpu->arch.dr6 = dbgregs->dr6;
2503 vcpu->arch.dr7 = dbgregs->dr7;
2504
a1efbe77
JK		 2505 return 0;
2506}
2507
2d5b5a66
SY		 2508static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2509 struct kvm_xsave *guest_xsave)
2510{
2511 if (cpu_has_xsave)
2512 memcpy(guest_xsave->region,
2513 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2514 xstate_size);
2d5b5a66
SY		 2515 else {
2516 memcpy(guest_xsave->region,
2517 &vcpu->arch.guest_fpu.state->fxsave,
2518 sizeof(struct i387_fxsave_struct));
2519 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2520 XSTATE_FPSSE;
2521 }
2522}
2523
2524static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2525 struct kvm_xsave *guest_xsave)
2526{
2527 u64 xstate_bv =
2528 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2529
2530 if (cpu_has_xsave)
2531 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2532 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2533 else {
2534 if (xstate_bv & ~XSTATE_FPSSE)
2535 return -EINVAL;
2536 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2537 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2538 }
2539 return 0;
2540}
2541
2542static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2543 struct kvm_xcrs *guest_xcrs)
2544{
2545 if (!cpu_has_xsave) {
2546 guest_xcrs->nr_xcrs = 0;
2547 return;
2548 }
2549
2550 guest_xcrs->nr_xcrs = 1;
2551 guest_xcrs->flags = 0;
2552 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2553 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2554}
2555
2556static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2557 struct kvm_xcrs *guest_xcrs)
2558{
2559 int i, r = 0;
2560
2561 if (!cpu_has_xsave)
2562 return -EINVAL;
2563
2564 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2565 return -EINVAL;
2566
2567 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2568 /* Only support XCR0 currently */
2569 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2570 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2571 guest_xcrs->xcrs[0].value);
2572 break;
2573 }
2574 if (r)
2575 r = -EINVAL;
2576 return r;
2577}
2578
313a3dc7
CO		 2579long kvm_arch_vcpu_ioctl(struct file *filp,
2580 unsigned int ioctl, unsigned long arg)
2581{
2582 struct kvm_vcpu *vcpu = filp->private_data;
2583 void __user *argp = (void __user *)arg;
2584 int r;
d1ac91d8
AK		 2585 union {
2586 struct kvm_lapic_state *lapic;
2587 struct kvm_xsave *xsave;
2588 struct kvm_xcrs *xcrs;
2589 void *buffer;
2590 } u;
2591
2592 u.buffer = NULL;
313a3dc7
CO		 2593 switch (ioctl) {
2594 case KVM_GET_LAPIC: {
2204ae3c
MT		 2595 r = -EINVAL;
2596 if (!vcpu->arch.apic)
2597 goto out;
d1ac91d8 2598 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2599
b772ff36 2600 r = -ENOMEM;
d1ac91d8 2601 if (!u.lapic)
b772ff36 2602 goto out;
d1ac91d8 2603 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2604 if (r)
2605 goto out;
2606 r = -EFAULT;
d1ac91d8 2607 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2608 goto out;
2609 r = 0;
2610 break;
2611 }
2612 case KVM_SET_LAPIC: {
2204ae3c
MT		 2613 r = -EINVAL;
2614 if (!vcpu->arch.apic)
2615 goto out;
d1ac91d8 2616 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2617 r = -ENOMEM;
d1ac91d8 2618 if (!u.lapic)
b772ff36 2619 goto out;
313a3dc7 2620 r = -EFAULT;
d1ac91d8 2621 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2622 goto out;
d1ac91d8 2623 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2624 if (r)
2625 goto out;
2626 r = 0;
2627 break;
2628 }
f77bc6a4
ZX		 2629 case KVM_INTERRUPT: {
2630 struct kvm_interrupt irq;
2631
2632 r = -EFAULT;
2633 if (copy_from_user(&irq, argp, sizeof irq))
2634 goto out;
2635 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2636 if (r)
2637 goto out;
2638 r = 0;
2639 break;
2640 }
c4abb7c9
JK		 2641 case KVM_NMI: {
2642 r = kvm_vcpu_ioctl_nmi(vcpu);
2643 if (r)
2644 goto out;
2645 r = 0;
2646 break;
2647 }
313a3dc7
CO		 2648 case KVM_SET_CPUID: {
2649 struct kvm_cpuid __user *cpuid_arg = argp;
2650 struct kvm_cpuid cpuid;
2651
2652 r = -EFAULT;
2653 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2654 goto out;
2655 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2656 if (r)
2657 goto out;
2658 break;
2659 }
07716717
DK		 2660 case KVM_SET_CPUID2: {
2661 struct kvm_cpuid2 __user *cpuid_arg = argp;
2662 struct kvm_cpuid2 cpuid;
2663
2664 r = -EFAULT;
2665 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2666 goto out;
2667 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2668 cpuid_arg->entries);
07716717
DK		 2669 if (r)
2670 goto out;
2671 break;
2672 }
2673 case KVM_GET_CPUID2: {
2674 struct kvm_cpuid2 __user *cpuid_arg = argp;
2675 struct kvm_cpuid2 cpuid;
2676
2677 r = -EFAULT;
2678 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2679 goto out;
2680 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2681 cpuid_arg->entries);
07716717
DK		 2682 if (r)
2683 goto out;
2684 r = -EFAULT;
2685 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2686 goto out;
2687 r = 0;
2688 break;
2689 }
313a3dc7
CO		 2690 case KVM_GET_MSRS:
2691 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2692 break;
2693 case KVM_SET_MSRS:
2694 r = msr_io(vcpu, argp, do_set_msr, 0);
2695 break;
b209749f
AK		 2696 case KVM_TPR_ACCESS_REPORTING: {
2697 struct kvm_tpr_access_ctl tac;
2698
2699 r = -EFAULT;
2700 if (copy_from_user(&tac, argp, sizeof tac))
2701 goto out;
2702 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2703 if (r)
2704 goto out;
2705 r = -EFAULT;
2706 if (copy_to_user(argp, &tac, sizeof tac))
2707 goto out;
2708 r = 0;
2709 break;
2710 };
b93463aa
AK		 2711 case KVM_SET_VAPIC_ADDR: {
2712 struct kvm_vapic_addr va;
2713
2714 r = -EINVAL;
2715 if (!irqchip_in_kernel(vcpu->kvm))
2716 goto out;
2717 r = -EFAULT;
2718 if (copy_from_user(&va, argp, sizeof va))
2719 goto out;
2720 r = 0;
2721 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2722 break;
2723 }
890ca9ae
HY		 2724 case KVM_X86_SETUP_MCE: {
2725 u64 mcg_cap;
2726
2727 r = -EFAULT;
2728 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2729 goto out;
2730 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2731 break;
2732 }
2733 case KVM_X86_SET_MCE: {
2734 struct kvm_x86_mce mce;
2735
2736 r = -EFAULT;
2737 if (copy_from_user(&mce, argp, sizeof mce))
2738 goto out;
2739 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2740 break;
2741 }
3cfc3092
JK		 2742 case KVM_GET_VCPU_EVENTS: {
2743 struct kvm_vcpu_events events;
2744
2745 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2746
2747 r = -EFAULT;
2748 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2749 break;
2750 r = 0;
2751 break;
2752 }
2753 case KVM_SET_VCPU_EVENTS: {
2754 struct kvm_vcpu_events events;
2755
2756 r = -EFAULT;
2757 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2758 break;
2759
2760 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2761 break;
2762 }
a1efbe77
JK		 2763 case KVM_GET_DEBUGREGS: {
2764 struct kvm_debugregs dbgregs;
2765
2766 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2767
2768 r = -EFAULT;
2769 if (copy_to_user(argp, &dbgregs,
2770 sizeof(struct kvm_debugregs)))
2771 break;
2772 r = 0;
2773 break;
2774 }
2775 case KVM_SET_DEBUGREGS: {
2776 struct kvm_debugregs dbgregs;
2777
2778 r = -EFAULT;
2779 if (copy_from_user(&dbgregs, argp,
2780 sizeof(struct kvm_debugregs)))
2781 break;
2782
2783 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2784 break;
2785 }
2d5b5a66 2786 case KVM_GET_XSAVE: {
d1ac91d8 2787 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2788 r = -ENOMEM;
d1ac91d8 2789 if (!u.xsave)
2d5b5a66
SY		 2790 break;
2791
d1ac91d8 2792 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2793
2794 r = -EFAULT;
d1ac91d8 2795 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2796 break;
2797 r = 0;
2798 break;
2799 }
2800 case KVM_SET_XSAVE: {
d1ac91d8 2801 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2802 r = -ENOMEM;
d1ac91d8 2803 if (!u.xsave)
2d5b5a66
SY		 2804 break;
2805
2806 r = -EFAULT;
d1ac91d8 2807 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2808 break;
2809
d1ac91d8 2810 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2811 break;
2812 }
2813 case KVM_GET_XCRS: {
d1ac91d8 2814 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2815 r = -ENOMEM;
d1ac91d8 2816 if (!u.xcrs)
2d5b5a66
SY		 2817 break;
2818
d1ac91d8 2819 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2820
2821 r = -EFAULT;
d1ac91d8 2822 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2823 sizeof(struct kvm_xcrs)))
2824 break;
2825 r = 0;
2826 break;
2827 }
2828 case KVM_SET_XCRS: {
d1ac91d8 2829 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2830 r = -ENOMEM;
d1ac91d8 2831 if (!u.xcrs)
2d5b5a66
SY		 2832 break;
2833
2834 r = -EFAULT;
d1ac91d8 2835 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2836 sizeof(struct kvm_xcrs)))
2837 break;
2838
d1ac91d8 2839 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2840 break;
2841 }
313a3dc7
CO		 2842 default:
2843 r = -EINVAL;
2844 }
2845out:
d1ac91d8 2846 kfree(u.buffer);
313a3dc7
CO		 2847 return r;
2848}
2849
1fe779f8
CO		 2850static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2851{
2852 int ret;
2853
2854 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2855 return -1;
2856 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2857 return ret;
2858}
2859
b927a3ce
SY		 2860static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2861 u64 ident_addr)
2862{
2863 kvm->arch.ept_identity_map_addr = ident_addr;
2864 return 0;
2865}
2866
1fe779f8
CO		 2867static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2868 u32 kvm_nr_mmu_pages)
2869{
2870 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2871 return -EINVAL;
2872
79fac95e 2873 mutex_lock(&kvm->slots_lock);
7c8a83b7 2874 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2875
2876 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2877 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2878
7c8a83b7 2879 spin_unlock(&kvm->mmu_lock);
79fac95e 2880 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2881 return 0;
2882}
2883
2884static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2885{
39de71ec 2886 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2887}
2888
1fe779f8
CO		 2889static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2890{
2891 int r;
2892
2893 r = 0;
2894 switch (chip->chip_id) {
2895 case KVM_IRQCHIP_PIC_MASTER:
2896 memcpy(&chip->chip.pic,
2897 &pic_irqchip(kvm)->pics[0],
2898 sizeof(struct kvm_pic_state));
2899 break;
2900 case KVM_IRQCHIP_PIC_SLAVE:
2901 memcpy(&chip->chip.pic,
2902 &pic_irqchip(kvm)->pics[1],
2903 sizeof(struct kvm_pic_state));
2904 break;
2905 case KVM_IRQCHIP_IOAPIC:
eba0226b 2906 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2907 break;
2908 default:
2909 r = -EINVAL;
2910 break;
2911 }
2912 return r;
2913}
2914
2915static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2916{
2917 int r;
2918
2919 r = 0;
2920 switch (chip->chip_id) {
2921 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2922 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2923 memcpy(&pic_irqchip(kvm)->pics[0],
2924 &chip->chip.pic,
2925 sizeof(struct kvm_pic_state));
fa8273e9 2926 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2927 break;
2928 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2929 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2930 memcpy(&pic_irqchip(kvm)->pics[1],
2931 &chip->chip.pic,
2932 sizeof(struct kvm_pic_state));
fa8273e9 2933 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2934 break;
2935 case KVM_IRQCHIP_IOAPIC:
eba0226b 2936 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2937 break;
2938 default:
2939 r = -EINVAL;
2940 break;
2941 }
2942 kvm_pic_update_irq(pic_irqchip(kvm));
2943 return r;
2944}
2945
e0f63cb9
SY		 2946static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2947{
2948 int r = 0;
2949
894a9c55 2950 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2951 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2952 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2953 return r;
2954}
2955
2956static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2957{
2958 int r = 0;
2959
894a9c55 2960 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2961 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2962 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2963 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2964 return r;
2965}
2966
2967static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2968{
2969 int r = 0;
2970
2971 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2972 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2973 sizeof(ps->channels));
2974 ps->flags = kvm->arch.vpit->pit_state.flags;
2975 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2976 return r;
2977}
2978
2979static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2980{
2981 int r = 0, start = 0;
2982 u32 prev_legacy, cur_legacy;
2983 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2984 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2985 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2986 if (!prev_legacy && cur_legacy)
2987 start = 1;
2988 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2989 sizeof(kvm->arch.vpit->pit_state.channels));
2990 kvm->arch.vpit->pit_state.flags = ps->flags;
2991 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2992 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2993 return r;
2994}
2995
52d939a0
MT		 2996static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2997 struct kvm_reinject_control *control)
2998{
2999 if (!kvm->arch.vpit)
3000 return -ENXIO;
894a9c55 3001 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3002 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3003 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3004 return 0;
3005}
3006
5bb064dc
ZX		 3007/*
3008 * Get (and clear) the dirty memory log for a memory slot.
3009 */
3010int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3011 struct kvm_dirty_log *log)
3012{
87bf6e7d 3013 int r, i;
5bb064dc 3014 struct kvm_memory_slot *memslot;
87bf6e7d 3015 unsigned long n;
b050b015 3016 unsigned long is_dirty = 0;
5bb064dc 3017
79fac95e 3018 mutex_lock(&kvm->slots_lock);
5bb064dc 3019
b050b015
MT		 3020 r = -EINVAL;
3021 if (log->slot >= KVM_MEMORY_SLOTS)
3022 goto out;
3023
3024 memslot = &kvm->memslots->memslots[log->slot];
3025 r = -ENOENT;
3026 if (!memslot->dirty_bitmap)
3027 goto out;
3028
87bf6e7d 3029 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3030
b050b015
MT		 3031 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3032 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3033
3034 /* If nothing is dirty, don't bother messing with page tables. */
3035 if (is_dirty) {
b050b015 3036 struct kvm_memslots *slots, *old_slots;
914ebccd 3037 unsigned long *dirty_bitmap;
b050b015 3038
7c8a83b7 3039 spin_lock(&kvm->mmu_lock);
5bb064dc 3040 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3041 spin_unlock(&kvm->mmu_lock);
b050b015 3042
914ebccd
TY		 3043 r = -ENOMEM;
3044 dirty_bitmap = vmalloc(n);
3045 if (!dirty_bitmap)
3046 goto out;
3047 memset(dirty_bitmap, 0, n);
b050b015 3048
914ebccd
TY		 3049 r = -ENOMEM;
3050 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3051 if (!slots) {
3052 vfree(dirty_bitmap);
3053 goto out;
3054 }
b050b015
MT		 3055 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3056 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3057
3058 old_slots = kvm->memslots;
3059 rcu_assign_pointer(kvm->memslots, slots);
3060 synchronize_srcu_expedited(&kvm->srcu);
3061 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3062 kfree(old_slots);
914ebccd
TY		 3063
3064 r = -EFAULT;
3065 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3066 vfree(dirty_bitmap);
3067 goto out;
3068 }
3069 vfree(dirty_bitmap);
3070 } else {
3071 r = -EFAULT;
3072 if (clear_user(log->dirty_bitmap, n))
3073 goto out;
5bb064dc 3074 }
b050b015 3075
5bb064dc
ZX		 3076 r = 0;
3077out:
79fac95e 3078 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3079 return r;
3080}
3081
1fe779f8
CO		 3082long kvm_arch_vm_ioctl(struct file *filp,
3083 unsigned int ioctl, unsigned long arg)
3084{
3085 struct kvm *kvm = filp->private_data;
3086 void __user *argp = (void __user *)arg;
367e1319 3087 int r = -ENOTTY;
f0d66275
DH		 3088 /*
3089 * This union makes it completely explicit to gcc-3.x
3090 * that these two variables' stack usage should be
3091 * combined, not added together.
3092 */
3093 union {
3094 struct kvm_pit_state ps;
e9f42757 3095 struct kvm_pit_state2 ps2;
c5ff41ce 3096 struct kvm_pit_config pit_config;
f0d66275 3097 } u;
1fe779f8
CO		 3098
3099 switch (ioctl) {
3100 case KVM_SET_TSS_ADDR:
3101 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3102 if (r < 0)
3103 goto out;
3104 break;
b927a3ce
SY		 3105 case KVM_SET_IDENTITY_MAP_ADDR: {
3106 u64 ident_addr;
3107
3108 r = -EFAULT;
3109 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3110 goto out;
3111 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3112 if (r < 0)
3113 goto out;
3114 break;
3115 }
1fe779f8
CO		 3116 case KVM_SET_NR_MMU_PAGES:
3117 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3118 if (r)
3119 goto out;
3120 break;
3121 case KVM_GET_NR_MMU_PAGES:
3122 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3123 break;
3ddea128
MT		 3124 case KVM_CREATE_IRQCHIP: {
3125 struct kvm_pic *vpic;
3126
3127 mutex_lock(&kvm->lock);
3128 r = -EEXIST;
3129 if (kvm->arch.vpic)
3130 goto create_irqchip_unlock;
1fe779f8 3131 r = -ENOMEM;
3ddea128
MT		 3132 vpic = kvm_create_pic(kvm);
3133 if (vpic) {
1fe779f8
CO		 3134 r = kvm_ioapic_init(kvm);
3135 if (r) {
72bb2fcd
WY		 3136 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3137 &vpic->dev);
3ddea128
MT		 3138 kfree(vpic);
3139 goto create_irqchip_unlock;
1fe779f8
CO		 3140 }
3141 } else
3ddea128
MT		 3142 goto create_irqchip_unlock;
3143 smp_wmb();
3144 kvm->arch.vpic = vpic;
3145 smp_wmb();
399ec807
AK		 3146 r = kvm_setup_default_irq_routing(kvm);
3147 if (r) {
3ddea128 3148 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3149 kvm_ioapic_destroy(kvm);
3150 kvm_destroy_pic(kvm);
3ddea128 3151 mutex_unlock(&kvm->irq_lock);
399ec807 3152 }
3ddea128
MT		 3153 create_irqchip_unlock:
3154 mutex_unlock(&kvm->lock);
1fe779f8 3155 break;
3ddea128 3156 }
7837699f 3157 case KVM_CREATE_PIT:
c5ff41ce
JK		 3158 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3159 goto create_pit;
3160 case KVM_CREATE_PIT2:
3161 r = -EFAULT;
3162 if (copy_from_user(&u.pit_config, argp,
3163 sizeof(struct kvm_pit_config)))
3164 goto out;
3165 create_pit:
79fac95e 3166 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3167 r = -EEXIST;
3168 if (kvm->arch.vpit)
3169 goto create_pit_unlock;
7837699f 3170 r = -ENOMEM;
c5ff41ce 3171 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3172 if (kvm->arch.vpit)
3173 r = 0;
269e05e4 3174 create_pit_unlock:
79fac95e 3175 mutex_unlock(&kvm->slots_lock);
7837699f 3176 break;
4925663a 3177 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3178 case KVM_IRQ_LINE: {
3179 struct kvm_irq_level irq_event;
3180
3181 r = -EFAULT;
3182 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3183 goto out;
160d2f6c 3184 r = -ENXIO;
1fe779f8 3185 if (irqchip_in_kernel(kvm)) {
4925663a 3186 __s32 status;
4925663a
GN		 3187 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3188 irq_event.irq, irq_event.level);
4925663a 3189 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3190 r = -EFAULT;
4925663a
GN		 3191 irq_event.status = status;
3192 if (copy_to_user(argp, &irq_event,
3193 sizeof irq_event))
3194 goto out;
3195 }
1fe779f8
CO		 3196 r = 0;
3197 }
3198 break;
3199 }
3200 case KVM_GET_IRQCHIP: {
3201 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3202 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3203
f0d66275
DH		 3204 r = -ENOMEM;
3205 if (!chip)
1fe779f8 3206 goto out;
f0d66275
DH		 3207 r = -EFAULT;
3208 if (copy_from_user(chip, argp, sizeof *chip))
3209 goto get_irqchip_out;
1fe779f8
CO		 3210 r = -ENXIO;
3211 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3212 goto get_irqchip_out;
3213 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3214 if (r)
f0d66275 3215 goto get_irqchip_out;
1fe779f8 3216 r = -EFAULT;
f0d66275
DH		 3217 if (copy_to_user(argp, chip, sizeof *chip))
3218 goto get_irqchip_out;
1fe779f8 3219 r = 0;
f0d66275
DH		 3220 get_irqchip_out:
3221 kfree(chip);
3222 if (r)
3223 goto out;
1fe779f8
CO		 3224 break;
3225 }
3226 case KVM_SET_IRQCHIP: {
3227 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3228 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3229
f0d66275
DH		 3230 r = -ENOMEM;
3231 if (!chip)
1fe779f8 3232 goto out;
f0d66275
DH		 3233 r = -EFAULT;
3234 if (copy_from_user(chip, argp, sizeof *chip))
3235 goto set_irqchip_out;
1fe779f8
CO		 3236 r = -ENXIO;
3237 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3238 goto set_irqchip_out;
3239 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3240 if (r)
f0d66275 3241 goto set_irqchip_out;
1fe779f8 3242 r = 0;
f0d66275
DH		 3243 set_irqchip_out:
3244 kfree(chip);
3245 if (r)
3246 goto out;
1fe779f8
CO		 3247 break;
3248 }
e0f63cb9 3249 case KVM_GET_PIT: {
e0f63cb9 3250 r = -EFAULT;
f0d66275 3251 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3252 goto out;
3253 r = -ENXIO;
3254 if (!kvm->arch.vpit)
3255 goto out;
f0d66275 3256 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3257 if (r)
3258 goto out;
3259 r = -EFAULT;
f0d66275 3260 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3261 goto out;
3262 r = 0;
3263 break;
3264 }
3265 case KVM_SET_PIT: {
e0f63cb9 3266 r = -EFAULT;
f0d66275 3267 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3268 goto out;
3269 r = -ENXIO;
3270 if (!kvm->arch.vpit)
3271 goto out;
f0d66275 3272 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3273 if (r)
3274 goto out;
3275 r = 0;
3276 break;
3277 }
e9f42757
BK		 3278 case KVM_GET_PIT2: {
3279 r = -ENXIO;
3280 if (!kvm->arch.vpit)
3281 goto out;
3282 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3283 if (r)
3284 goto out;
3285 r = -EFAULT;
3286 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3287 goto out;
3288 r = 0;
3289 break;
3290 }
3291 case KVM_SET_PIT2: {
3292 r = -EFAULT;
3293 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3294 goto out;
3295 r = -ENXIO;
3296 if (!kvm->arch.vpit)
3297 goto out;
3298 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3299 if (r)
3300 goto out;
3301 r = 0;
3302 break;
3303 }
52d939a0
MT		 3304 case KVM_REINJECT_CONTROL: {
3305 struct kvm_reinject_control control;
3306 r = -EFAULT;
3307 if (copy_from_user(&control, argp, sizeof(control)))
3308 goto out;
3309 r = kvm_vm_ioctl_reinject(kvm, &control);
3310 if (r)
3311 goto out;
3312 r = 0;
3313 break;
3314 }
ffde22ac
ES		 3315 case KVM_XEN_HVM_CONFIG: {
3316 r = -EFAULT;
3317 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3318 sizeof(struct kvm_xen_hvm_config)))
3319 goto out;
3320 r = -EINVAL;
3321 if (kvm->arch.xen_hvm_config.flags)
3322 goto out;
3323 r = 0;
3324 break;
3325 }
afbcf7ab 3326 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3327 struct kvm_clock_data user_ns;
3328 u64 now_ns;
3329 s64 delta;
3330
3331 r = -EFAULT;
3332 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3333 goto out;
3334
3335 r = -EINVAL;
3336 if (user_ns.flags)
3337 goto out;
3338
3339 r = 0;
759379dd 3340 now_ns = get_kernel_ns();
afbcf7ab
GC		 3341 delta = user_ns.clock - now_ns;
3342 kvm->arch.kvmclock_offset = delta;
3343 break;
3344 }
3345 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3346 struct kvm_clock_data user_ns;
3347 u64 now_ns;
3348
759379dd 3349 now_ns = get_kernel_ns();
afbcf7ab
GC		 3350 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3351 user_ns.flags = 0;
3352
3353 r = -EFAULT;
3354 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3355 goto out;
3356 r = 0;
3357 break;
3358 }
3359
1fe779f8
CO		 3360 default:
3361 ;
3362 }
3363out:
3364 return r;
3365}
3366
a16b043c 3367static void kvm_init_msr_list(void)
043405e1
CO		 3368{
3369 u32 dummy[2];
3370 unsigned i, j;
3371
e3267cbb
GC		 3372 /* skip the first msrs in the list. KVM-specific */
3373 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3374 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3375 continue;
3376 if (j < i)
3377 msrs_to_save[j] = msrs_to_save[i];
3378 j++;
3379 }
3380 num_msrs_to_save = j;
3381}
3382
bda9020e
MT		 3383static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3384 const void *v)
bbd9b64e 3385{
bda9020e
MT		 3386 if (vcpu->arch.apic &&
3387 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3388 return 0;
bbd9b64e 3389
e93f8a0f 3390 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3391}
3392
bda9020e 3393static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3394{
bda9020e
MT		 3395 if (vcpu->arch.apic &&
3396 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3397 return 0;
bbd9b64e 3398
e93f8a0f 3399 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3400}
3401
2dafc6c2
GN		 3402static void kvm_set_segment(struct kvm_vcpu *vcpu,
3403 struct kvm_segment *var, int seg)
3404{
3405 kvm_x86_ops->set_segment(vcpu, var, seg);
3406}
3407
3408void kvm_get_segment(struct kvm_vcpu *vcpu,
3409 struct kvm_segment *var, int seg)
3410{
3411 kvm_x86_ops->get_segment(vcpu, var, seg);
3412}
3413
1871c602
GN		 3414gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3415{
3416 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3417 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3418}
3419
3420 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3421{
3422 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3423 access |= PFERR_FETCH_MASK;
3424 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3425}
3426
3427gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3428{
3429 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3430 access |= PFERR_WRITE_MASK;
3431 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3432}
3433
3434/* uses this to access any guest's mapped memory without checking CPL */
3435gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3436{
3437 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3438}
3439
3440static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3441 struct kvm_vcpu *vcpu, u32 access,
3442 u32 *error)
bbd9b64e
CO		 3443{
3444 void *data = val;
10589a46 3445 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3446
3447 while (bytes) {
1871c602 3448 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3449 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3450 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3451 int ret;
3452
10589a46
MT		 3453 if (gpa == UNMAPPED_GVA) {
3454 r = X86EMUL_PROPAGATE_FAULT;
3455 goto out;
3456 }
77c2002e 3457 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3458 if (ret < 0) {
c3cd7ffa 3459 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3460 goto out;
3461 }
bbd9b64e 3462
77c2002e
IE		 3463 bytes -= toread;
3464 data += toread;
3465 addr += toread;
bbd9b64e 3466 }
10589a46 3467out:
10589a46 3468 return r;
bbd9b64e 3469}
77c2002e 3470
1871c602
GN		 3471/* used for instruction fetching */
3472static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3473 struct kvm_vcpu *vcpu, u32 *error)
3474{
3475 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3476 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3477 access | PFERR_FETCH_MASK, error);
3478}
3479
3480static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3481 struct kvm_vcpu *vcpu, u32 *error)
3482{
3483 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3484 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3485 error);
3486}
3487
3488static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3489 struct kvm_vcpu *vcpu, u32 *error)
3490{
3491 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3492}
3493
7972995b 3494static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3495 unsigned int bytes,
7972995b 3496 struct kvm_vcpu *vcpu,
2dafc6c2 3497 u32 *error)
77c2002e
IE		 3498{
3499 void *data = val;
3500 int r = X86EMUL_CONTINUE;
3501
3502 while (bytes) {
7972995b
GN		 3503 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3504 PFERR_WRITE_MASK, error);
77c2002e
IE		 3505 unsigned offset = addr & (PAGE_SIZE-1);
3506 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3507 int ret;
3508
3509 if (gpa == UNMAPPED_GVA) {
3510 r = X86EMUL_PROPAGATE_FAULT;
3511 goto out;
3512 }
3513 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3514 if (ret < 0) {
c3cd7ffa 3515 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3516 goto out;
3517 }
3518
3519 bytes -= towrite;
3520 data += towrite;
3521 addr += towrite;
3522 }
3523out:
3524 return r;
3525}
3526
bbd9b64e
CO		 3527static int emulator_read_emulated(unsigned long addr,
3528 void *val,
3529 unsigned int bytes,
8fe681e9 3530 unsigned int *error_code,
bbd9b64e
CO		 3531 struct kvm_vcpu *vcpu)
3532{
bbd9b64e
CO		 3533 gpa_t gpa;
3534
3535 if (vcpu->mmio_read_completed) {
3536 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3537 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3538 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3539 vcpu->mmio_read_completed = 0;
3540 return X86EMUL_CONTINUE;
3541 }
3542
8fe681e9 3543 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3544
8fe681e9 3545 if (gpa == UNMAPPED_GVA)
1871c602 3546 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3547
3548 /* For APIC access vmexit */
3549 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3550 goto mmio;
3551
1871c602 3552 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3553 == X86EMUL_CONTINUE)
bbd9b64e 3554 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3555
3556mmio:
3557 /*
3558 * Is this MMIO handled locally?
3559 */
aec51dc4
AK		 3560 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3561 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3562 return X86EMUL_CONTINUE;
3563 }
aec51dc4
AK		 3564
3565 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3566
3567 vcpu->mmio_needed = 1;
411c35b7
GN		 3568 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3569 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3570 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3571 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3572
c3cd7ffa 3573 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3574}
3575
3200f405 3576int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3577 const void *val, int bytes)
bbd9b64e
CO		 3578{
3579 int ret;
3580
3581 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3582 if (ret < 0)
bbd9b64e 3583 return 0;
ad218f85 3584 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3585 return 1;
3586}
3587
3588static int emulator_write_emulated_onepage(unsigned long addr,
3589 const void *val,
3590 unsigned int bytes,
8fe681e9 3591 unsigned int *error_code,
bbd9b64e
CO		 3592 struct kvm_vcpu *vcpu)
3593{
10589a46
MT		 3594 gpa_t gpa;
3595
8fe681e9 3596 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3597
8fe681e9 3598 if (gpa == UNMAPPED_GVA)
bbd9b64e 3599 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3600
3601 /* For APIC access vmexit */
3602 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3603 goto mmio;
3604
3605 if (emulator_write_phys(vcpu, gpa, val, bytes))
3606 return X86EMUL_CONTINUE;
3607
3608mmio:
aec51dc4 3609 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3610 /*
3611 * Is this MMIO handled locally?
3612 */
bda9020e 3613 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3614 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3615
3616 vcpu->mmio_needed = 1;
411c35b7
GN		 3617 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3618 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3619 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3620 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3621 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3622
3623 return X86EMUL_CONTINUE;
3624}
3625
3626int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3627 const void *val,
3628 unsigned int bytes,
8fe681e9 3629 unsigned int *error_code,
8f6abd06 3630 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3631{
3632 /* Crossing a page boundary? */
3633 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3634 int rc, now;
3635
3636 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3637 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3638 vcpu);
bbd9b64e
CO		 3639 if (rc != X86EMUL_CONTINUE)
3640 return rc;
3641 addr += now;
3642 val += now;
3643 bytes -= now;
3644 }
8fe681e9
GN		 3645 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3646 vcpu);
bbd9b64e 3647}
bbd9b64e 3648
daea3e73
AK		 3649#define CMPXCHG_TYPE(t, ptr, old, new) \
3650 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3651
3652#ifdef CONFIG_X86_64
3653# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3654#else
3655# define CMPXCHG64(ptr, old, new) \
9749a6c0 3656 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3657#endif
3658
bbd9b64e
CO		 3659static int emulator_cmpxchg_emulated(unsigned long addr,
3660 const void *old,
3661 const void *new,
3662 unsigned int bytes,
8fe681e9 3663 unsigned int *error_code,
bbd9b64e
CO		 3664 struct kvm_vcpu *vcpu)
3665{
daea3e73
AK		 3666 gpa_t gpa;
3667 struct page *page;
3668 char *kaddr;
3669 bool exchanged;
2bacc55c 3670
daea3e73
AK		 3671 /* guests cmpxchg8b have to be emulated atomically */
3672 if (bytes > 8 || (bytes & (bytes - 1)))
3673 goto emul_write;
10589a46 3674
daea3e73 3675 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3676
daea3e73
AK		 3677 if (gpa == UNMAPPED_GVA ||
3678 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3679 goto emul_write;
2bacc55c 3680
daea3e73
AK		 3681 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3682 goto emul_write;
72dc67a6 3683
daea3e73 3684 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3685 if (is_error_page(page)) {
3686 kvm_release_page_clean(page);
3687 goto emul_write;
3688 }
72dc67a6 3689
daea3e73
AK		 3690 kaddr = kmap_atomic(page, KM_USER0);
3691 kaddr += offset_in_page(gpa);
3692 switch (bytes) {
3693 case 1:
3694 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3695 break;
3696 case 2:
3697 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3698 break;
3699 case 4:
3700 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3701 break;
3702 case 8:
3703 exchanged = CMPXCHG64(kaddr, old, new);
3704 break;
3705 default:
3706 BUG();
2bacc55c 3707 }
daea3e73
AK		 3708 kunmap_atomic(kaddr, KM_USER0);
3709 kvm_release_page_dirty(page);
3710
3711 if (!exchanged)
3712 return X86EMUL_CMPXCHG_FAILED;
3713
8f6abd06
GN		 3714 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3715
3716 return X86EMUL_CONTINUE;
4a5f48f6 3717
3200f405 3718emul_write:
daea3e73 3719 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3720
8fe681e9 3721 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3722}
3723
cf8f70bf
GN		 3724static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3725{
3726 /* TODO: String I/O for in kernel device */
3727 int r;
3728
3729 if (vcpu->arch.pio.in)
3730 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3731 vcpu->arch.pio.size, pd);
3732 else
3733 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3734 vcpu->arch.pio.port, vcpu->arch.pio.size,
3735 pd);
3736 return r;
3737}
3738
3739
3740static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3741 unsigned int count, struct kvm_vcpu *vcpu)
3742{
7972995b 3743 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3744 goto data_avail;
3745
c41a15dd 3746 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3747
3748 vcpu->arch.pio.port = port;
3749 vcpu->arch.pio.in = 1;
7972995b 3750 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3751 vcpu->arch.pio.size = size;
3752
3753 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3754 data_avail:
3755 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3756 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3757 return 1;
3758 }
3759
3760 vcpu->run->exit_reason = KVM_EXIT_IO;
3761 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3762 vcpu->run->io.size = size;
3763 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3764 vcpu->run->io.count = count;
3765 vcpu->run->io.port = port;
3766
3767 return 0;
3768}
3769
3770static int emulator_pio_out_emulated(int size, unsigned short port,
3771 const void *val, unsigned int count,
3772 struct kvm_vcpu *vcpu)
3773{
c41a15dd 3774 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3775
3776 vcpu->arch.pio.port = port;
3777 vcpu->arch.pio.in = 0;
7972995b 3778 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3779 vcpu->arch.pio.size = size;
3780
3781 memcpy(vcpu->arch.pio_data, val, size * count);
3782
3783 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3784 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3785 return 1;
3786 }
3787
3788 vcpu->run->exit_reason = KVM_EXIT_IO;
3789 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3790 vcpu->run->io.size = size;
3791 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3792 vcpu->run->io.count = count;
3793 vcpu->run->io.port = port;
3794
3795 return 0;
3796}
3797
bbd9b64e
CO		 3798static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3799{
3800 return kvm_x86_ops->get_segment_base(vcpu, seg);
3801}
3802
3803int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3804{
a7052897 3805 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3806 return X86EMUL_CONTINUE;
3807}
3808
f5f48ee1
SY		 3809int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3810{
3811 if (!need_emulate_wbinvd(vcpu))
3812 return X86EMUL_CONTINUE;
3813
3814 if (kvm_x86_ops->has_wbinvd_exit()) {
3815 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3816 wbinvd_ipi, NULL, 1);
3817 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3818 }
3819 wbinvd();
3820 return X86EMUL_CONTINUE;
3821}
3822EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3823
bbd9b64e
CO		 3824int emulate_clts(struct kvm_vcpu *vcpu)
3825{
4d4ec087 3826 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3827 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3828 return X86EMUL_CONTINUE;
3829}
3830
35aa5375 3831int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3832{
338dbc97 3833 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3834}
3835
35aa5375 3836int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3837{
338dbc97
GN		 3838
3839 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3840}
3841
52a46617 3842static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3843{
52a46617 3844 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3845}
3846
52a46617 3847static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3848{
52a46617
GN		 3849 unsigned long value;
3850
3851 switch (cr) {
3852 case 0:
3853 value = kvm_read_cr0(vcpu);
3854 break;
3855 case 2:
3856 value = vcpu->arch.cr2;
3857 break;
3858 case 3:
3859 value = vcpu->arch.cr3;
3860 break;
3861 case 4:
3862 value = kvm_read_cr4(vcpu);
3863 break;
3864 case 8:
3865 value = kvm_get_cr8(vcpu);
3866 break;
3867 default:
3868 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3869 return 0;
3870 }
3871
3872 return value;
3873}
3874
0f12244f 3875static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3876{
0f12244f
GN		 3877 int res = 0;
3878
52a46617
GN		 3879 switch (cr) {
3880 case 0:
49a9b07e 3881 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3882 break;
3883 case 2:
3884 vcpu->arch.cr2 = val;
3885 break;
3886 case 3:
2390218b 3887 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3888 break;
3889 case 4:
a83b29c6 3890 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3891 break;
3892 case 8:
0f12244f 3893 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3894 break;
3895 default:
3896 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3897 res = -1;
52a46617 3898 }
0f12244f
GN		 3899
3900 return res;
52a46617
GN		 3901}
3902
9c537244
GN		 3903static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3904{
3905 return kvm_x86_ops->get_cpl(vcpu);
3906}
3907
2dafc6c2
GN		 3908static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3909{
3910 kvm_x86_ops->get_gdt(vcpu, dt);
3911}
3912
160ce1f1
MG		 3913static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3914{
3915 kvm_x86_ops->get_idt(vcpu, dt);
3916}
3917
5951c442
GN		 3918static unsigned long emulator_get_cached_segment_base(int seg,
3919 struct kvm_vcpu *vcpu)
3920{
3921 return get_segment_base(vcpu, seg);
3922}
3923
2dafc6c2
GN		 3924static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3925 struct kvm_vcpu *vcpu)
3926{
3927 struct kvm_segment var;
3928
3929 kvm_get_segment(vcpu, &var, seg);
3930
3931 if (var.unusable)
3932 return false;
3933
3934 if (var.g)
3935 var.limit >>= 12;
3936 set_desc_limit(desc, var.limit);
3937 set_desc_base(desc, (unsigned long)var.base);
3938 desc->type = var.type;
3939 desc->s = var.s;
3940 desc->dpl = var.dpl;
3941 desc->p = var.present;
3942 desc->avl = var.avl;
3943 desc->l = var.l;
3944 desc->d = var.db;
3945 desc->g = var.g;
3946
3947 return true;
3948}
3949
3950static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3951 struct kvm_vcpu *vcpu)
3952{
3953 struct kvm_segment var;
3954
3955 /* needed to preserve selector */
3956 kvm_get_segment(vcpu, &var, seg);
3957
3958 var.base = get_desc_base(desc);
3959 var.limit = get_desc_limit(desc);
3960 if (desc->g)
3961 var.limit = (var.limit << 12) | 0xfff;
3962 var.type = desc->type;
3963 var.present = desc->p;
3964 var.dpl = desc->dpl;
3965 var.db = desc->d;
3966 var.s = desc->s;
3967 var.l = desc->l;
3968 var.g = desc->g;
3969 var.avl = desc->avl;
3970 var.present = desc->p;
3971 var.unusable = !var.present;
3972 var.padding = 0;
3973
3974 kvm_set_segment(vcpu, &var, seg);
3975 return;
3976}
3977
3978static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3979{
3980 struct kvm_segment kvm_seg;
3981
3982 kvm_get_segment(vcpu, &kvm_seg, seg);
3983 return kvm_seg.selector;
3984}
3985
3986static void emulator_set_segment_selector(u16 sel, int seg,
3987 struct kvm_vcpu *vcpu)
3988{
3989 struct kvm_segment kvm_seg;
3990
3991 kvm_get_segment(vcpu, &kvm_seg, seg);
3992 kvm_seg.selector = sel;
3993 kvm_set_segment(vcpu, &kvm_seg, seg);
3994}
3995
14af3f3c 3996static struct x86_emulate_ops emulate_ops = {
1871c602 3997 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3998 .write_std = kvm_write_guest_virt_system,
1871c602 3999 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4000 .read_emulated = emulator_read_emulated,
4001 .write_emulated = emulator_write_emulated,
4002 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4003 .pio_in_emulated = emulator_pio_in_emulated,
4004 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4005 .get_cached_descriptor = emulator_get_cached_descriptor,
4006 .set_cached_descriptor = emulator_set_cached_descriptor,
4007 .get_segment_selector = emulator_get_segment_selector,
4008 .set_segment_selector = emulator_set_segment_selector,
5951c442 4009 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4010 .get_gdt = emulator_get_gdt,
160ce1f1 4011 .get_idt = emulator_get_idt,
52a46617
GN		 4012 .get_cr = emulator_get_cr,
4013 .set_cr = emulator_set_cr,
9c537244 4014 .cpl = emulator_get_cpl,
35aa5375
GN		 4015 .get_dr = emulator_get_dr,
4016 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4017 .set_msr = kvm_set_msr,
4018 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4019};
4020
5fdbf976
MT		 4021static void cache_all_regs(struct kvm_vcpu *vcpu)
4022{
4023 kvm_register_read(vcpu, VCPU_REGS_RAX);
4024 kvm_register_read(vcpu, VCPU_REGS_RSP);
4025 kvm_register_read(vcpu, VCPU_REGS_RIP);
4026 vcpu->arch.regs_dirty = ~0;
4027}
4028
95cb2295
GN		 4029static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4030{
4031 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4032 /*
4033 * an sti; sti; sequence only disable interrupts for the first
4034 * instruction. So, if the last instruction, be it emulated or
4035 * not, left the system with the INT_STI flag enabled, it
4036 * means that the last instruction is an sti. We should not
4037 * leave the flag on in this case. The same goes for mov ss
4038 */
4039 if (!(int_shadow & mask))
4040 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4041}
4042
54b8486f
GN		 4043static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4044{
4045 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4046 if (ctxt->exception == PF_VECTOR)
4047 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
4048 else if (ctxt->error_code_valid)
4049 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4050 else
4051 kvm_queue_exception(vcpu, ctxt->exception);
4052}
4053
8ec4722d
MG		 4054static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4055{
4056 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4057 int cs_db, cs_l;
4058
4059 cache_all_regs(vcpu);
4060
4061 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4062
4063 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4064 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4065 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4066 vcpu->arch.emulate_ctxt.mode =
4067 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4068 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4069 ? X86EMUL_MODE_VM86 : cs_l
4070 ? X86EMUL_MODE_PROT64 : cs_db
4071 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4072 memset(c, 0, sizeof(struct decode_cache));
4073 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4074}
4075
6d77dbfc
GN		 4076static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4077{
6d77dbfc
GN		 4078 ++vcpu->stat.insn_emulation_fail;
4079 trace_kvm_emulate_insn_failed(vcpu);
4080 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4081 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4082 vcpu->run->internal.ndata = 0;
4083 kvm_queue_exception(vcpu, UD_VECTOR);
4084 return EMULATE_FAIL;
4085}
4086
a6f177ef
GN		 4087static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4088{
4089 gpa_t gpa;
4090
68be0803
GN		 4091 if (tdp_enabled)
4092 return false;
4093
a6f177ef
GN		 4094 /*
4095 * if emulation was due to access to shadowed page table
4096 * and it failed try to unshadow page and re-entetr the
4097 * guest to let CPU execute the instruction.
4098 */
4099 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4100 return true;
4101
4102 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4103
4104 if (gpa == UNMAPPED_GVA)
4105 return true; /* let cpu generate fault */
4106
4107 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4108 return true;
4109
4110 return false;
4111}
4112
bbd9b64e 4113int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4114 unsigned long cr2,
4115 u16 error_code,
571008da 4116 int emulation_type)
bbd9b64e 4117{
95cb2295 4118 int r;
4d2179e1 4119 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4120
26eef70c 4121 kvm_clear_exception_queue(vcpu);
ad312c7c 4122 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4123 /*
56e82318 4124 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4125 * instead of direct ->regs accesses, can save hundred cycles
4126 * on Intel for instructions that don't read/change RSP, for
4127 * for example.
4128 */
4129 cache_all_regs(vcpu);
bbd9b64e 4130
571008da 4131 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4132 init_emulate_ctxt(vcpu);
95cb2295 4133 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4134 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4135 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4136
9aabc88f 4137 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
e46479f8 4138 trace_kvm_emulate_insn_start(vcpu);
571008da 4139
0cb5762e
AP		 4140 /* Only allow emulation of specific instructions on #UD
4141 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4142 if (emulation_type & EMULTYPE_TRAP_UD) {
4143 if (!c->twobyte)
4144 return EMULATE_FAIL;
4145 switch (c->b) {
4146 case 0x01: /* VMMCALL */
4147 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4148 return EMULATE_FAIL;
4149 break;
4150 case 0x34: /* sysenter */
4151 case 0x35: /* sysexit */
4152 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4153 return EMULATE_FAIL;
4154 break;
4155 case 0x05: /* syscall */
4156 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4157 return EMULATE_FAIL;
4158 break;
4159 default:
4160 return EMULATE_FAIL;
4161 }
4162
4163 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4164 return EMULATE_FAIL;
4165 }
571008da 4166
f2b5756b 4167 ++vcpu->stat.insn_emulation;
bbd9b64e 4168 if (r) {
a6f177ef 4169 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4170 return EMULATE_DONE;
6d77dbfc
GN		 4171 if (emulation_type & EMULTYPE_SKIP)
4172 return EMULATE_FAIL;
4173 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4174 }
4175 }
4176
ba8afb6b
GN		 4177 if (emulation_type & EMULTYPE_SKIP) {
4178 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4179 return EMULATE_DONE;
4180 }
4181
4d2179e1
GN		 4182 /* this is needed for vmware backdor interface to work since it
4183 changes registers values during IO operation */
4184 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4185
5cd21917 4186restart:
9aabc88f 4187 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4188
d2ddd1c4 4189 if (r == EMULATION_FAILED) {
a6f177ef 4190 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4191 return EMULATE_DONE;
4192
6d77dbfc 4193 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4194 }
4195
d2ddd1c4 4196 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4197 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4198 r = EMULATE_DONE;
4199 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4200 if (!vcpu->arch.pio.in)
4201 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4202 r = EMULATE_DO_MMIO;
4203 } else if (vcpu->mmio_needed) {
3457e419
GN		 4204 if (vcpu->mmio_is_write)
4205 vcpu->mmio_needed = 0;
e85d28f8 4206 r = EMULATE_DO_MMIO;
d2ddd1c4 4207 } else if (r == EMULATION_RESTART)
5cd21917 4208 goto restart;
d2ddd1c4
GN		 4209 else
4210 r = EMULATE_DONE;
f850e2e6 4211
e85d28f8
GN		 4212 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4213 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4214 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4215 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4216
4217 return r;
de7d789a 4218}
bbd9b64e 4219EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4220
cf8f70bf 4221int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4222{
cf8f70bf
GN		 4223 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4224 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4225 /* do not return to emulator after return from userspace */
7972995b 4226 vcpu->arch.pio.count = 0;
de7d789a
CO		 4227 return ret;
4228}
cf8f70bf 4229EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4230
8cfdc000
ZA		 4231static void tsc_bad(void *info)
4232{
4233 __get_cpu_var(cpu_tsc_khz) = 0;
4234}
4235
4236static void tsc_khz_changed(void *data)
c8076604 4237{
8cfdc000
ZA		 4238 struct cpufreq_freqs *freq = data;
4239 unsigned long khz = 0;
4240
4241 if (data)
4242 khz = freq->new;
4243 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4244 khz = cpufreq_quick_get(raw_smp_processor_id());
4245 if (!khz)
4246 khz = tsc_khz;
4247 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4248}
4249
c8076604
GH		 4250static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4251 void *data)
4252{
4253 struct cpufreq_freqs *freq = data;
4254 struct kvm *kvm;
4255 struct kvm_vcpu *vcpu;
4256 int i, send_ipi = 0;
4257
8cfdc000
ZA		 4258 /*
4259 * We allow guests to temporarily run on slowing clocks,
4260 * provided we notify them after, or to run on accelerating
4261 * clocks, provided we notify them before. Thus time never
4262 * goes backwards.
4263 *
4264 * However, we have a problem. We can't atomically update
4265 * the frequency of a given CPU from this function; it is
4266 * merely a notifier, which can be called from any CPU.
4267 * Changing the TSC frequency at arbitrary points in time
4268 * requires a recomputation of local variables related to
4269 * the TSC for each VCPU. We must flag these local variables
4270 * to be updated and be sure the update takes place with the
4271 * new frequency before any guests proceed.
4272 *
4273 * Unfortunately, the combination of hotplug CPU and frequency
4274 * change creates an intractable locking scenario; the order
4275 * of when these callouts happen is undefined with respect to
4276 * CPU hotplug, and they can race with each other. As such,
4277 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4278 * undefined; you can actually have a CPU frequency change take
4279 * place in between the computation of X and the setting of the
4280 * variable. To protect against this problem, all updates of
4281 * the per_cpu tsc_khz variable are done in an interrupt
4282 * protected IPI, and all callers wishing to update the value
4283 * must wait for a synchronous IPI to complete (which is trivial
4284 * if the caller is on the CPU already). This establishes the
4285 * necessary total order on variable updates.
4286 *
4287 * Note that because a guest time update may take place
4288 * anytime after the setting of the VCPU's request bit, the
4289 * correct TSC value must be set before the request. However,
4290 * to ensure the update actually makes it to any guest which
4291 * starts running in hardware virtualization between the set
4292 * and the acquisition of the spinlock, we must also ping the
4293 * CPU after setting the request bit.
4294 *
4295 */
4296
c8076604
GH		 4297 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4298 return 0;
4299 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4300 return 0;
8cfdc000
ZA		 4301
4302 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4303
4304 spin_lock(&kvm_lock);
4305 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4306 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4307 if (vcpu->cpu != freq->cpu)
4308 continue;
4309 if (!kvm_request_guest_time_update(vcpu))
4310 continue;
4311 if (vcpu->cpu != smp_processor_id())
8cfdc000 4312 send_ipi = 1;
c8076604
GH		 4313 }
4314 }
4315 spin_unlock(&kvm_lock);
4316
4317 if (freq->old < freq->new && send_ipi) {
4318 /*
4319 * We upscale the frequency. Must make the guest
4320 * doesn't see old kvmclock values while running with
4321 * the new frequency, otherwise we risk the guest sees
4322 * time go backwards.
4323 *
4324 * In case we update the frequency for another cpu
4325 * (which might be in guest context) send an interrupt
4326 * to kick the cpu out of guest context. Next time
4327 * guest context is entered kvmclock will be updated,
4328 * so the guest will not see stale values.
4329 */
8cfdc000 4330 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4331 }
4332 return 0;
4333}
4334
4335static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4336 .notifier_call = kvmclock_cpufreq_notifier
4337};
4338
4339static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4340 unsigned long action, void *hcpu)
4341{
4342 unsigned int cpu = (unsigned long)hcpu;
4343
4344 switch (action) {
4345 case CPU_ONLINE:
4346 case CPU_DOWN_FAILED:
4347 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4348 break;
4349 case CPU_DOWN_PREPARE:
4350 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4351 break;
4352 }
4353 return NOTIFY_OK;
4354}
4355
4356static struct notifier_block kvmclock_cpu_notifier_block = {
4357 .notifier_call = kvmclock_cpu_notifier,
4358 .priority = -INT_MAX
c8076604
GH		 4359};
4360
b820cc0c
ZA		 4361static void kvm_timer_init(void)
4362{
4363 int cpu;
4364
8cfdc000 4365 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4366 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4367 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4368 CPUFREQ_TRANSITION_NOTIFIER);
4369 }
8cfdc000
ZA		 4370 for_each_online_cpu(cpu)
4371 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4372}
4373
ff9d07a0
ZY		 4374static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4375
4376static int kvm_is_in_guest(void)
4377{
4378 return percpu_read(current_vcpu) != NULL;
4379}
4380
4381static int kvm_is_user_mode(void)
4382{
4383 int user_mode = 3;
dcf46b94 4384
ff9d07a0
ZY		 4385 if (percpu_read(current_vcpu))
4386 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4387
ff9d07a0
ZY		 4388 return user_mode != 0;
4389}
4390
4391static unsigned long kvm_get_guest_ip(void)
4392{
4393 unsigned long ip = 0;
dcf46b94 4394
ff9d07a0
ZY		 4395 if (percpu_read(current_vcpu))
4396 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4397
ff9d07a0
ZY		 4398 return ip;
4399}
4400
4401static struct perf_guest_info_callbacks kvm_guest_cbs = {
4402 .is_in_guest = kvm_is_in_guest,
4403 .is_user_mode = kvm_is_user_mode,
4404 .get_guest_ip = kvm_get_guest_ip,
4405};
4406
4407void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4408{
4409 percpu_write(current_vcpu, vcpu);
4410}
4411EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4412
4413void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4414{
4415 percpu_write(current_vcpu, NULL);
4416}
4417EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4418
f8c16bba 4419int kvm_arch_init(void *opaque)
043405e1 4420{
b820cc0c 4421 int r;
f8c16bba
ZX		 4422 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4423
f8c16bba
ZX		 4424 if (kvm_x86_ops) {
4425 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4426 r = -EEXIST;
4427 goto out;
f8c16bba
ZX		 4428 }
4429
4430 if (!ops->cpu_has_kvm_support()) {
4431 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4432 r = -EOPNOTSUPP;
4433 goto out;
f8c16bba
ZX		 4434 }
4435 if (ops->disabled_by_bios()) {
4436 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4437 r = -EOPNOTSUPP;
4438 goto out;
f8c16bba
ZX		 4439 }
4440
97db56ce
AK		 4441 r = kvm_mmu_module_init();
4442 if (r)
4443 goto out;
4444
4445 kvm_init_msr_list();
4446
f8c16bba 4447 kvm_x86_ops = ops;
56c6d28a 4448 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4449 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4450 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4451 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4452
b820cc0c 4453 kvm_timer_init();
c8076604 4454
ff9d07a0
ZY		 4455 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4456
2acf923e
DC		 4457 if (cpu_has_xsave)
4458 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4459
f8c16bba 4460 return 0;
56c6d28a
ZX		 4461
4462out:
56c6d28a 4463 return r;
043405e1 4464}
8776e519 4465
f8c16bba
ZX		 4466void kvm_arch_exit(void)
4467{
ff9d07a0
ZY		 4468 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4469
888d256e
JK		 4470 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4471 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4472 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4473 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4474 kvm_x86_ops = NULL;
56c6d28a
ZX		 4475 kvm_mmu_module_exit();
4476}
f8c16bba 4477
8776e519
HB		 4478int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4479{
4480 ++vcpu->stat.halt_exits;
4481 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4482 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4483 return 1;
4484 } else {
4485 vcpu->run->exit_reason = KVM_EXIT_HLT;
4486 return 0;
4487 }
4488}
4489EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4490
2f333bcb
MT		 4491static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4492 unsigned long a1)
4493{
4494 if (is_long_mode(vcpu))
4495 return a0;
4496 else
4497 return a0 | ((gpa_t)a1 << 32);
4498}
4499
55cd8e5a
GN		 4500int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4501{
4502 u64 param, ingpa, outgpa, ret;
4503 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4504 bool fast, longmode;
4505 int cs_db, cs_l;
4506
4507 /*
4508 * hypercall generates UD from non zero cpl and real mode
4509 * per HYPER-V spec
4510 */
3eeb3288 4511 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4512 kvm_queue_exception(vcpu, UD_VECTOR);
4513 return 0;
4514 }
4515
4516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4517 longmode = is_long_mode(vcpu) && cs_l == 1;
4518
4519 if (!longmode) {
ccd46936
GN		 4520 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4521 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4522 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4523 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4524 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4525 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4526 }
4527#ifdef CONFIG_X86_64
4528 else {
4529 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4530 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4531 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4532 }
4533#endif
4534
4535 code = param & 0xffff;
4536 fast = (param >> 16) & 0x1;
4537 rep_cnt = (param >> 32) & 0xfff;
4538 rep_idx = (param >> 48) & 0xfff;
4539
4540 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4541
c25bc163
GN		 4542 switch (code) {
4543 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4544 kvm_vcpu_on_spin(vcpu);
4545 break;
4546 default:
4547 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4548 break;
4549 }
55cd8e5a
GN		 4550
4551 ret = res | (((u64)rep_done & 0xfff) << 32);
4552 if (longmode) {
4553 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4554 } else {
4555 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4556 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4557 }
4558
4559 return 1;
4560}
4561
8776e519
HB		 4562int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4563{
4564 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4565 int r = 1;
8776e519 4566
55cd8e5a
GN		 4567 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4568 return kvm_hv_hypercall(vcpu);
4569
5fdbf976
MT		 4570 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4571 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4572 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4573 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4574 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4575
229456fc 4576 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4577
8776e519
HB		 4578 if (!is_long_mode(vcpu)) {
4579 nr &= 0xFFFFFFFF;
4580 a0 &= 0xFFFFFFFF;
4581 a1 &= 0xFFFFFFFF;
4582 a2 &= 0xFFFFFFFF;
4583 a3 &= 0xFFFFFFFF;
4584 }
4585
07708c4a
JK		 4586 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4587 ret = -KVM_EPERM;
4588 goto out;
4589 }
4590
8776e519 4591 switch (nr) {
b93463aa
AK		 4592 case KVM_HC_VAPIC_POLL_IRQ:
4593 ret = 0;
4594 break;
2f333bcb
MT		 4595 case KVM_HC_MMU_OP:
4596 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4597 break;
8776e519
HB		 4598 default:
4599 ret = -KVM_ENOSYS;
4600 break;
4601 }
07708c4a 4602out:
5fdbf976 4603 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4604 ++vcpu->stat.hypercalls;
2f333bcb 4605 return r;
8776e519
HB		 4606}
4607EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4608
4609int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4610{
4611 char instruction[3];
5fdbf976 4612 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4613
8776e519
HB		 4614 /*
4615 * Blow out the MMU to ensure that no other VCPU has an active mapping
4616 * to ensure that the updated hypercall appears atomically across all
4617 * VCPUs.
4618 */
4619 kvm_mmu_zap_all(vcpu->kvm);
4620
8776e519 4621 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4622
8fe681e9 4623 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4624}
4625
8776e519
HB		 4626void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4627{
89a27f4d 4628 struct desc_ptr dt = { limit, base };
8776e519
HB		 4629
4630 kvm_x86_ops->set_gdt(vcpu, &dt);
4631}
4632
4633void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4634{
89a27f4d 4635 struct desc_ptr dt = { limit, base };
8776e519
HB		 4636
4637 kvm_x86_ops->set_idt(vcpu, &dt);
4638}
4639
07716717
DK		 4640static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4641{
ad312c7c
ZX		 4642 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4643 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4644
4645 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4646 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4647 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4648 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4649 if (ej->function == e->function) {
4650 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4651 return j;
4652 }
4653 }
4654 return 0; /* silence gcc, even though control never reaches here */
4655}
4656
4657/* find an entry with matching function, matching index (if needed), and that
4658 * should be read next (if it's stateful) */
4659static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4660 u32 function, u32 index)
4661{
4662 if (e->function != function)
4663 return 0;
4664 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4665 return 0;
4666 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4667 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4668 return 0;
4669 return 1;
4670}
4671
d8017474
AG		 4672struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4673 u32 function, u32 index)
8776e519
HB		 4674{
4675 int i;
d8017474 4676 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4677
ad312c7c 4678 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4679 struct kvm_cpuid_entry2 *e;
4680
ad312c7c 4681 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4682 if (is_matching_cpuid_entry(e, function, index)) {
4683 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4684 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4685 best = e;
4686 break;
4687 }
4688 /*
4689 * Both basic or both extended?
4690 */
4691 if (((e->function ^ function) & 0x80000000) == 0)
4692 if (!best || e->function > best->function)
4693 best = e;
4694 }
d8017474
AG		 4695 return best;
4696}
0e851880 4697EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4698
82725b20
DE		 4699int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4700{
4701 struct kvm_cpuid_entry2 *best;
4702
f7a71197
AK		 4703 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4704 if (!best || best->eax < 0x80000008)
4705 goto not_found;
82725b20
DE		 4706 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4707 if (best)
4708 return best->eax & 0xff;
f7a71197 4709not_found:
82725b20
DE		 4710 return 36;
4711}
4712
d8017474
AG		 4713void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4714{
4715 u32 function, index;
4716 struct kvm_cpuid_entry2 *best;
4717
4718 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4719 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4720 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4721 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4722 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4723 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4724 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4725 if (best) {
5fdbf976
MT		 4726 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4727 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4728 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4729 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4730 }
8776e519 4731 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4732 trace_kvm_cpuid(function,
4733 kvm_register_read(vcpu, VCPU_REGS_RAX),
4734 kvm_register_read(vcpu, VCPU_REGS_RBX),
4735 kvm_register_read(vcpu, VCPU_REGS_RCX),
4736 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4737}
4738EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4739
b6c7a5dc
HB		 4740/*
4741 * Check if userspace requested an interrupt window, and that the
4742 * interrupt window is open.
4743 *
4744 * No need to exit to userspace if we already have an interrupt queued.
4745 */
851ba692 4746static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4747{
8061823a 4748 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4749 vcpu->run->request_interrupt_window &&
5df56646 4750 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4751}
4752
851ba692 4753static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4754{
851ba692
AK		 4755 struct kvm_run *kvm_run = vcpu->run;
4756
91586a3b 4757 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4758 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4759 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4760 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4761 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4762 else
b6c7a5dc 4763 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4764 kvm_arch_interrupt_allowed(vcpu) &&
4765 !kvm_cpu_has_interrupt(vcpu) &&
4766 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4767}
4768
b93463aa
AK		 4769static void vapic_enter(struct kvm_vcpu *vcpu)
4770{
4771 struct kvm_lapic *apic = vcpu->arch.apic;
4772 struct page *page;
4773
4774 if (!apic || !apic->vapic_addr)
4775 return;
4776
4777 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4778
4779 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4780}
4781
4782static void vapic_exit(struct kvm_vcpu *vcpu)
4783{
4784 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4785 int idx;
b93463aa
AK		 4786
4787 if (!apic || !apic->vapic_addr)
4788 return;
4789
f656ce01 4790 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4791 kvm_release_page_dirty(apic->vapic_page);
4792 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4793 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4794}
4795
95ba8273
GN		 4796static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4797{
4798 int max_irr, tpr;
4799
4800 if (!kvm_x86_ops->update_cr8_intercept)
4801 return;
4802
88c808fd
AK		 4803 if (!vcpu->arch.apic)
4804 return;
4805
8db3baa2
GN		 4806 if (!vcpu->arch.apic->vapic_addr)
4807 max_irr = kvm_lapic_find_highest_irr(vcpu);
4808 else
4809 max_irr = -1;
95ba8273
GN		 4810
4811 if (max_irr != -1)
4812 max_irr >>= 4;
4813
4814 tpr = kvm_lapic_get_cr8(vcpu);
4815
4816 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4817}
4818
851ba692 4819static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4820{
4821 /* try to reinject previous events if any */
b59bb7bd 4822 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4823 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4824 vcpu->arch.exception.has_error_code,
4825 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4826 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4827 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4828 vcpu->arch.exception.error_code,
4829 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4830 return;
4831 }
4832
95ba8273
GN		 4833 if (vcpu->arch.nmi_injected) {
4834 kvm_x86_ops->set_nmi(vcpu);
4835 return;
4836 }
4837
4838 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4839 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4840 return;
4841 }
4842
4843 /* try to inject new event if pending */
4844 if (vcpu->arch.nmi_pending) {
4845 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4846 vcpu->arch.nmi_pending = false;
4847 vcpu->arch.nmi_injected = true;
4848 kvm_x86_ops->set_nmi(vcpu);
4849 }
4850 } else if (kvm_cpu_has_interrupt(vcpu)) {
4851 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4852 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4853 false);
4854 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4855 }
4856 }
4857}
4858
2acf923e
DC		 4859static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4860{
4861 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4862 !vcpu->guest_xcr0_loaded) {
4863 /* kvm_set_xcr() also depends on this */
4864 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4865 vcpu->guest_xcr0_loaded = 1;
4866 }
4867}
4868
4869static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4870{
4871 if (vcpu->guest_xcr0_loaded) {
4872 if (vcpu->arch.xcr0 != host_xcr0)
4873 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4874 vcpu->guest_xcr0_loaded = 0;
4875 }
4876}
4877
851ba692 4878static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4879{
4880 int r;
6a8b1d13 4881 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4882 vcpu->run->request_interrupt_window;
b6c7a5dc 4883
3e007509 4884 if (vcpu->requests) {
a8eeb04a 4885 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4886 kvm_mmu_unload(vcpu);
a8eeb04a 4887 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4888 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 4889 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
4890 r = kvm_write_guest_time(vcpu);
4891 if (unlikely(r))
4892 goto out;
4893 }
a8eeb04a 4894 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4895 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4896 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4897 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4898 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4899 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4900 r = 0;
4901 goto out;
4902 }
a8eeb04a 4903 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4904 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4905 r = 0;
4906 goto out;
4907 }
a8eeb04a 4908 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4909 vcpu->fpu_active = 0;
4910 kvm_x86_ops->fpu_deactivate(vcpu);
4911 }
2f52d58c 4912 }
b93463aa 4913
3e007509
AK		 4914 r = kvm_mmu_reload(vcpu);
4915 if (unlikely(r))
4916 goto out;
4917
b6c7a5dc
HB		 4918 preempt_disable();
4919
4920 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4921 if (vcpu->fpu_active)
4922 kvm_load_guest_fpu(vcpu);
2acf923e 4923 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4924
d94e1dc9
AK		 4925 atomic_set(&vcpu->guest_mode, 1);
4926 smp_wmb();
b6c7a5dc 4927
d94e1dc9 4928 local_irq_disable();
32f88400 4929
d94e1dc9
AK		 4930 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4931 || need_resched() || signal_pending(current)) {
4932 atomic_set(&vcpu->guest_mode, 0);
4933 smp_wmb();
6c142801
AK		 4934 local_irq_enable();
4935 preempt_enable();
4936 r = 1;
4937 goto out;
4938 }
4939
851ba692 4940 inject_pending_event(vcpu);
b6c7a5dc 4941
6a8b1d13
GN		 4942 /* enable NMI/IRQ window open exits if needed */
4943 if (vcpu->arch.nmi_pending)
4944 kvm_x86_ops->enable_nmi_window(vcpu);
4945 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4946 kvm_x86_ops->enable_irq_window(vcpu);
4947
95ba8273 4948 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4949 update_cr8_intercept(vcpu);
4950 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4951 }
b93463aa 4952
f656ce01 4953 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4954
b6c7a5dc
HB		 4955 kvm_guest_enter();
4956
42dbaa5a 4957 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4958 set_debugreg(0, 7);
4959 set_debugreg(vcpu->arch.eff_db[0], 0);
4960 set_debugreg(vcpu->arch.eff_db[1], 1);
4961 set_debugreg(vcpu->arch.eff_db[2], 2);
4962 set_debugreg(vcpu->arch.eff_db[3], 3);
4963 }
b6c7a5dc 4964
229456fc 4965 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4966 kvm_x86_ops->run(vcpu);
b6c7a5dc 4967
24f1e32c
FW		 4968 /*
4969 * If the guest has used debug registers, at least dr7
4970 * will be disabled while returning to the host.
4971 * If we don't have active breakpoints in the host, we don't
4972 * care about the messed up debug address registers. But if
4973 * we have some of them active, restore the old state.
4974 */
59d8eb53 4975 if (hw_breakpoint_active())
24f1e32c 4976 hw_breakpoint_restore();
42dbaa5a 4977
1d5f066e
ZA		 4978 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
4979
d94e1dc9
AK		 4980 atomic_set(&vcpu->guest_mode, 0);
4981 smp_wmb();
b6c7a5dc
HB		 4982 local_irq_enable();
4983
4984 ++vcpu->stat.exits;
4985
4986 /*
4987 * We must have an instruction between local_irq_enable() and
4988 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4989 * the interrupt shadow. The stat.exits increment will do nicely.
4990 * But we need to prevent reordering, hence this barrier():
4991 */
4992 barrier();
4993
4994 kvm_guest_exit();
4995
4996 preempt_enable();
4997
f656ce01 4998 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4999
b6c7a5dc
HB		 5000 /*
5001 * Profile KVM exit RIPs:
5002 */
5003 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5004 unsigned long rip = kvm_rip_read(vcpu);
5005 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5006 }
5007
298101da 5008
b93463aa
AK		 5009 kvm_lapic_sync_from_vapic(vcpu);
5010
851ba692 5011 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5012out:
5013 return r;
5014}
b6c7a5dc 5015
09cec754 5016
851ba692 5017static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5018{
5019 int r;
f656ce01 5020 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5021
5022 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5023 pr_debug("vcpu %d received sipi with vector # %x\n",
5024 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5025 kvm_lapic_reset(vcpu);
5f179287 5026 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5027 if (r)
5028 return r;
5029 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5030 }
5031
f656ce01 5032 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5033 vapic_enter(vcpu);
5034
5035 r = 1;
5036 while (r > 0) {
af2152f5 5037 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5038 r = vcpu_enter_guest(vcpu);
d7690175 5039 else {
f656ce01 5040 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5041 kvm_vcpu_block(vcpu);
f656ce01 5042 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5043 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5044 {
5045 switch(vcpu->arch.mp_state) {
5046 case KVM_MP_STATE_HALTED:
d7690175 5047 vcpu->arch.mp_state =
09cec754
GN		 5048 KVM_MP_STATE_RUNNABLE;
5049 case KVM_MP_STATE_RUNNABLE:
5050 break;
5051 case KVM_MP_STATE_SIPI_RECEIVED:
5052 default:
5053 r = -EINTR;
5054 break;
5055 }
5056 }
d7690175
MT		 5057 }
5058
09cec754
GN		 5059 if (r <= 0)
5060 break;
5061
5062 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5063 if (kvm_cpu_has_pending_timer(vcpu))
5064 kvm_inject_pending_timer_irqs(vcpu);
5065
851ba692 5066 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5067 r = -EINTR;
851ba692 5068 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5069 ++vcpu->stat.request_irq_exits;
5070 }
5071 if (signal_pending(current)) {
5072 r = -EINTR;
851ba692 5073 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5074 ++vcpu->stat.signal_exits;
5075 }
5076 if (need_resched()) {
f656ce01 5077 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5078 kvm_resched(vcpu);
f656ce01 5079 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5080 }
b6c7a5dc
HB		 5081 }
5082
f656ce01 5083 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5084
b93463aa
AK		 5085 vapic_exit(vcpu);
5086
b6c7a5dc
HB		 5087 return r;
5088}
5089
5090int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5091{
5092 int r;
5093 sigset_t sigsaved;
5094
ac9f6dc0
AK		 5095 if (vcpu->sigset_active)
5096 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5097
a4535290 5098 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5099 kvm_vcpu_block(vcpu);
d7690175 5100 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5101 r = -EAGAIN;
5102 goto out;
b6c7a5dc
HB		 5103 }
5104
b6c7a5dc
HB		 5105 /* re-sync apic's tpr */
5106 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5107 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5108
d2ddd1c4 5109 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5110 if (vcpu->mmio_needed) {
5111 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5112 vcpu->mmio_read_completed = 1;
5113 vcpu->mmio_needed = 0;
b6c7a5dc 5114 }
f656ce01 5115 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5116 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5117 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5118 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5119 r = 0;
5120 goto out;
5121 }
5122 }
5fdbf976
MT		 5123 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5124 kvm_register_write(vcpu, VCPU_REGS_RAX,
5125 kvm_run->hypercall.ret);
b6c7a5dc 5126
851ba692 5127 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5128
5129out:
f1d86e46 5130 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5131 if (vcpu->sigset_active)
5132 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5133
b6c7a5dc
HB		 5134 return r;
5135}
5136
5137int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5138{
5fdbf976
MT		 5139 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5140 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5141 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5142 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5143 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5144 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5145 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5146 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5147#ifdef CONFIG_X86_64
5fdbf976
MT		 5148 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5149 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5150 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5151 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5152 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5153 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5154 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5155 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5156#endif
5157
5fdbf976 5158 regs->rip = kvm_rip_read(vcpu);
91586a3b 5159 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5160
b6c7a5dc
HB		 5161 return 0;
5162}
5163
5164int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5165{
5fdbf976
MT		 5166 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5167 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5168 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5169 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5170 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5171 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5172 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5173 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5174#ifdef CONFIG_X86_64
5fdbf976
MT		 5175 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5176 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5177 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5178 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5179 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5180 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5181 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5182 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5183#endif
5184
5fdbf976 5185 kvm_rip_write(vcpu, regs->rip);
91586a3b 5186 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5187
b4f14abd
JK		 5188 vcpu->arch.exception.pending = false;
5189
b6c7a5dc
HB		 5190 return 0;
5191}
5192
b6c7a5dc
HB		 5193void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5194{
5195 struct kvm_segment cs;
5196
3e6e0aab 5197 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5198 *db = cs.db;
5199 *l = cs.l;
5200}
5201EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5202
5203int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5204 struct kvm_sregs *sregs)
5205{
89a27f4d 5206 struct desc_ptr dt;
b6c7a5dc 5207
3e6e0aab
GT		 5208 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5209 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5210 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5211 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5212 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5213 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5214
3e6e0aab
GT		 5215 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5216 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5217
5218 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5219 sregs->idt.limit = dt.size;
5220 sregs->idt.base = dt.address;
b6c7a5dc 5221 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5222 sregs->gdt.limit = dt.size;
5223 sregs->gdt.base = dt.address;
b6c7a5dc 5224
4d4ec087 5225 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5226 sregs->cr2 = vcpu->arch.cr2;
5227 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5228 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5229 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5230 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5231 sregs->apic_base = kvm_get_apic_base(vcpu);
5232
923c61bb 5233 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5234
36752c9b 5235 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5236 set_bit(vcpu->arch.interrupt.nr,
5237 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5238
b6c7a5dc
HB		 5239 return 0;
5240}
5241
62d9f0db
MT		 5242int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5243 struct kvm_mp_state *mp_state)
5244{
62d9f0db 5245 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5246 return 0;
5247}
5248
5249int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5250 struct kvm_mp_state *mp_state)
5251{
62d9f0db 5252 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5253 return 0;
5254}
5255
e269fb21
JK		 5256int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5257 bool has_error_code, u32 error_code)
b6c7a5dc 5258{
4d2179e1 5259 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5260 int ret;
e01c2426 5261
8ec4722d 5262 init_emulate_ctxt(vcpu);
c697518a 5263
9aabc88f 5264 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5265 tss_selector, reason, has_error_code,
5266 error_code);
c697518a 5267
c697518a 5268 if (ret)
19d04437 5269 return EMULATE_FAIL;
37817f29 5270
4d2179e1 5271 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5272 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5273 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5274 return EMULATE_DONE;
37817f29
IE		 5275}
5276EXPORT_SYMBOL_GPL(kvm_task_switch);
5277
b6c7a5dc
HB		 5278int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5279 struct kvm_sregs *sregs)
5280{
5281 int mmu_reset_needed = 0;
923c61bb 5282 int pending_vec, max_bits;
89a27f4d 5283 struct desc_ptr dt;
b6c7a5dc 5284
89a27f4d
GN		 5285 dt.size = sregs->idt.limit;
5286 dt.address = sregs->idt.base;
b6c7a5dc 5287 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5288 dt.size = sregs->gdt.limit;
5289 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5290 kvm_x86_ops->set_gdt(vcpu, &dt);
5291
ad312c7c
ZX		 5292 vcpu->arch.cr2 = sregs->cr2;
5293 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5294 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5295
2d3ad1f4 5296 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5297
f6801dff 5298 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5299 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5300 kvm_set_apic_base(vcpu, sregs->apic_base);
5301
4d4ec087 5302 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5303 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5304 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5305
fc78f519 5306 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5307 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5308 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5309 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5310 mmu_reset_needed = 1;
5311 }
b6c7a5dc
HB		 5312
5313 if (mmu_reset_needed)
5314 kvm_mmu_reset_context(vcpu);
5315
923c61bb
GN		 5316 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5317 pending_vec = find_first_bit(
5318 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5319 if (pending_vec < max_bits) {
66fd3f7f 5320 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5321 pr_debug("Set back pending irq %d\n", pending_vec);
5322 if (irqchip_in_kernel(vcpu->kvm))
5323 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5324 }
5325
3e6e0aab
GT		 5326 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5327 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5328 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5329 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5330 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5331 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5332
3e6e0aab
GT		 5333 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5334 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5335
5f0269f5
ME		 5336 update_cr8_intercept(vcpu);
5337
9c3e4aab 5338 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5339 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5340 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5341 !is_protmode(vcpu))
9c3e4aab
MT		 5342 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5343
b6c7a5dc
HB		 5344 return 0;
5345}
5346
d0bfb940
JK		 5347int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5348 struct kvm_guest_debug *dbg)
b6c7a5dc 5349{
355be0b9 5350 unsigned long rflags;
ae675ef0 5351 int i, r;
b6c7a5dc 5352
4f926bf2
JK		 5353 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5354 r = -EBUSY;
5355 if (vcpu->arch.exception.pending)
2122ff5e 5356 goto out;
4f926bf2
JK		 5357 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5358 kvm_queue_exception(vcpu, DB_VECTOR);
5359 else
5360 kvm_queue_exception(vcpu, BP_VECTOR);
5361 }
5362
91586a3b
JK		 5363 /*
5364 * Read rflags as long as potentially injected trace flags are still
5365 * filtered out.
5366 */
5367 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5368
5369 vcpu->guest_debug = dbg->control;
5370 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5371 vcpu->guest_debug = 0;
5372
5373 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5374 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5375 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5376 vcpu->arch.switch_db_regs =
5377 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5378 } else {
5379 for (i = 0; i < KVM_NR_DB_REGS; i++)
5380 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5381 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5382 }
5383
f92653ee
JK		 5384 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5385 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5386 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5387
91586a3b
JK		 5388 /*
5389 * Trigger an rflags update that will inject or remove the trace
5390 * flags.
5391 */
5392 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5393
355be0b9 5394 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5395
4f926bf2 5396 r = 0;
d0bfb940 5397
2122ff5e 5398out:
b6c7a5dc
HB		 5399
5400 return r;
5401}
5402
8b006791
ZX		 5403/*
5404 * Translate a guest virtual address to a guest physical address.
5405 */
5406int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5407 struct kvm_translation *tr)
5408{
5409 unsigned long vaddr = tr->linear_address;
5410 gpa_t gpa;
f656ce01 5411 int idx;
8b006791 5412
f656ce01 5413 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5414 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5415 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5416 tr->physical_address = gpa;
5417 tr->valid = gpa != UNMAPPED_GVA;
5418 tr->writeable = 1;
5419 tr->usermode = 0;
8b006791
ZX		 5420
5421 return 0;
5422}
5423
d0752060
HB		 5424int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5425{
98918833
SY		 5426 struct i387_fxsave_struct *fxsave =
5427 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5428
d0752060
HB		 5429 memcpy(fpu->fpr, fxsave->st_space, 128);
5430 fpu->fcw = fxsave->cwd;
5431 fpu->fsw = fxsave->swd;
5432 fpu->ftwx = fxsave->twd;
5433 fpu->last_opcode = fxsave->fop;
5434 fpu->last_ip = fxsave->rip;
5435 fpu->last_dp = fxsave->rdp;
5436 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5437
d0752060
HB		 5438 return 0;
5439}
5440
5441int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5442{
98918833
SY		 5443 struct i387_fxsave_struct *fxsave =
5444 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5445
d0752060
HB		 5446 memcpy(fxsave->st_space, fpu->fpr, 128);
5447 fxsave->cwd = fpu->fcw;
5448 fxsave->swd = fpu->fsw;
5449 fxsave->twd = fpu->ftwx;
5450 fxsave->fop = fpu->last_opcode;
5451 fxsave->rip = fpu->last_ip;
5452 fxsave->rdp = fpu->last_dp;
5453 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5454
d0752060
HB		 5455 return 0;
5456}
5457
10ab25cd 5458int fx_init(struct kvm_vcpu *vcpu)
d0752060 5459{
10ab25cd
JK		 5460 int err;
5461
5462 err = fpu_alloc(&vcpu->arch.guest_fpu);
5463 if (err)
5464 return err;
5465
98918833 5466 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5467
2acf923e
DC		 5468 /*
5469 * Ensure guest xcr0 is valid for loading
5470 */
5471 vcpu->arch.xcr0 = XSTATE_FP;
5472
ad312c7c 5473 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5474
5475 return 0;
d0752060
HB		 5476}
5477EXPORT_SYMBOL_GPL(fx_init);
5478
98918833
SY		 5479static void fx_free(struct kvm_vcpu *vcpu)
5480{
5481 fpu_free(&vcpu->arch.guest_fpu);
5482}
5483
d0752060
HB		 5484void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5485{
2608d7a1 5486 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5487 return;
5488
2acf923e
DC		 5489 /*
5490 * Restore all possible states in the guest,
5491 * and assume host would use all available bits.
5492 * Guest xcr0 would be loaded later.
5493 */
5494 kvm_put_guest_xcr0(vcpu);
d0752060 5495 vcpu->guest_fpu_loaded = 1;
7cf30855 5496 unlazy_fpu(current);
98918833 5497 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5498 trace_kvm_fpu(1);
d0752060 5499}
d0752060
HB		 5500
5501void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5502{
2acf923e
DC		 5503 kvm_put_guest_xcr0(vcpu);
5504
d0752060
HB		 5505 if (!vcpu->guest_fpu_loaded)
5506 return;
5507
5508 vcpu->guest_fpu_loaded = 0;
98918833 5509 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5510 ++vcpu->stat.fpu_reload;
a8eeb04a 5511 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5512 trace_kvm_fpu(0);
d0752060 5513}
e9b11c17
ZX		 5514
5515void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5516{
7f1ea208
JR		 5517 if (vcpu->arch.time_page) {
5518 kvm_release_page_dirty(vcpu->arch.time_page);
5519 vcpu->arch.time_page = NULL;
5520 }
5521
f5f48ee1 5522 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5523 fx_free(vcpu);
e9b11c17
ZX		 5524 kvm_x86_ops->vcpu_free(vcpu);
5525}
5526
5527struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5528 unsigned int id)
5529{
6755bae8
ZA		 5530 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5531 printk_once(KERN_WARNING
5532 "kvm: SMP vm created on host with unstable TSC; "
5533 "guest TSC will not be reliable\n");
26e5215f
AK		 5534 return kvm_x86_ops->vcpu_create(kvm, id);
5535}
e9b11c17 5536
26e5215f
AK		 5537int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5538{
5539 int r;
e9b11c17 5540
0bed3b56 5541 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5542 vcpu_load(vcpu);
5543 r = kvm_arch_vcpu_reset(vcpu);
5544 if (r == 0)
5545 r = kvm_mmu_setup(vcpu);
5546 vcpu_put(vcpu);
5547 if (r < 0)
5548 goto free_vcpu;
5549
26e5215f 5550 return 0;
e9b11c17
ZX		 5551free_vcpu:
5552 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5553 return r;
e9b11c17
ZX		 5554}
5555
d40ccc62 5556void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5557{
5558 vcpu_load(vcpu);
5559 kvm_mmu_unload(vcpu);
5560 vcpu_put(vcpu);
5561
98918833 5562 fx_free(vcpu);
e9b11c17
ZX		 5563 kvm_x86_ops->vcpu_free(vcpu);
5564}
5565
5566int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5567{
448fa4a9
JK		 5568 vcpu->arch.nmi_pending = false;
5569 vcpu->arch.nmi_injected = false;
5570
42dbaa5a
JK		 5571 vcpu->arch.switch_db_regs = 0;
5572 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5573 vcpu->arch.dr6 = DR6_FIXED_1;
5574 vcpu->arch.dr7 = DR7_FIXED_1;
5575
e9b11c17
ZX		 5576 return kvm_x86_ops->vcpu_reset(vcpu);
5577}
5578
10474ae8 5579int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5580{
ca84d1a2
ZA		 5581 struct kvm *kvm;
5582 struct kvm_vcpu *vcpu;
5583 int i;
5584
18863bdd 5585 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5586 list_for_each_entry(kvm, &vm_list, vm_list)
5587 kvm_for_each_vcpu(i, vcpu, kvm)
5588 if (vcpu->cpu == smp_processor_id())
5589 kvm_request_guest_time_update(vcpu);
10474ae8 5590 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5591}
5592
5593void kvm_arch_hardware_disable(void *garbage)
5594{
5595 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5596 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5597}
5598
5599int kvm_arch_hardware_setup(void)
5600{
5601 return kvm_x86_ops->hardware_setup();
5602}
5603
5604void kvm_arch_hardware_unsetup(void)
5605{
5606 kvm_x86_ops->hardware_unsetup();
5607}
5608
5609void kvm_arch_check_processor_compat(void *rtn)
5610{
5611 kvm_x86_ops->check_processor_compatibility(rtn);
5612}
5613
5614int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5615{
5616 struct page *page;
5617 struct kvm *kvm;
5618 int r;
5619
5620 BUG_ON(vcpu->kvm == NULL);
5621 kvm = vcpu->kvm;
5622
9aabc88f 5623 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
ad312c7c 5624 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5625 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5626 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5627 else
a4535290 5628 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5629
5630 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5631 if (!page) {
5632 r = -ENOMEM;
5633 goto fail;
5634 }
ad312c7c 5635 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5636
5637 r = kvm_mmu_create(vcpu);
5638 if (r < 0)
5639 goto fail_free_pio_data;
5640
5641 if (irqchip_in_kernel(kvm)) {
5642 r = kvm_create_lapic(vcpu);
5643 if (r < 0)
5644 goto fail_mmu_destroy;
5645 }
5646
890ca9ae
HY		 5647 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5648 GFP_KERNEL);
5649 if (!vcpu->arch.mce_banks) {
5650 r = -ENOMEM;
443c39bc 5651 goto fail_free_lapic;
890ca9ae
HY		 5652 }
5653 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5654
f5f48ee1
SY		 5655 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5656 goto fail_free_mce_banks;
5657
e9b11c17 5658 return 0;
f5f48ee1
SY		 5659fail_free_mce_banks:
5660 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5661fail_free_lapic:
5662 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5663fail_mmu_destroy:
5664 kvm_mmu_destroy(vcpu);
5665fail_free_pio_data:
ad312c7c 5666 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5667fail:
5668 return r;
5669}
5670
5671void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5672{
f656ce01
MT		 5673 int idx;
5674
36cb93fd 5675 kfree(vcpu->arch.mce_banks);
e9b11c17 5676 kvm_free_lapic(vcpu);
f656ce01 5677 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5678 kvm_mmu_destroy(vcpu);
f656ce01 5679 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5680 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5681}
d19a9cd2
ZX		 5682
5683struct kvm *kvm_arch_create_vm(void)
5684{
5685 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5686
5687 if (!kvm)
5688 return ERR_PTR(-ENOMEM);
5689
f05e70ac 5690 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5691 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5692
5550af4d
SY		 5693 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5694 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5695
99e3e30a
ZA		 5696 spin_lock_init(&kvm->arch.tsc_write_lock);
5697
d19a9cd2
ZX		 5698 return kvm;
5699}
5700
5701static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5702{
5703 vcpu_load(vcpu);
5704 kvm_mmu_unload(vcpu);
5705 vcpu_put(vcpu);
5706}
5707
5708static void kvm_free_vcpus(struct kvm *kvm)
5709{
5710 unsigned int i;
988a2cae 5711 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5712
5713 /*
5714 * Unpin any mmu pages first.
5715 */
988a2cae
GN		 5716 kvm_for_each_vcpu(i, vcpu, kvm)
5717 kvm_unload_vcpu_mmu(vcpu);
5718 kvm_for_each_vcpu(i, vcpu, kvm)
5719 kvm_arch_vcpu_free(vcpu);
5720
5721 mutex_lock(&kvm->lock);
5722 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5723 kvm->vcpus[i] = NULL;
d19a9cd2 5724
988a2cae
GN		 5725 atomic_set(&kvm->online_vcpus, 0);
5726 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5727}
5728
ad8ba2cd
SY		 5729void kvm_arch_sync_events(struct kvm *kvm)
5730{
ba4cef31 5731 kvm_free_all_assigned_devices(kvm);
aea924f6 5732 kvm_free_pit(kvm);
ad8ba2cd
SY		 5733}
5734
d19a9cd2
ZX		 5735void kvm_arch_destroy_vm(struct kvm *kvm)
5736{
6eb55818 5737 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5738 kfree(kvm->arch.vpic);
5739 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5740 kvm_free_vcpus(kvm);
5741 kvm_free_physmem(kvm);
3d45830c
AK		 5742 if (kvm->arch.apic_access_page)
5743 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5744 if (kvm->arch.ept_identity_pagetable)
5745 put_page(kvm->arch.ept_identity_pagetable);
64749204 5746 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5747 kfree(kvm);
5748}
0de10343 5749
f7784b8e
MT		 5750int kvm_arch_prepare_memory_region(struct kvm *kvm,
5751 struct kvm_memory_slot *memslot,
0de10343 5752 struct kvm_memory_slot old,
f7784b8e 5753 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5754 int user_alloc)
5755{
f7784b8e 5756 int npages = memslot->npages;
7ac77099
AK		 5757 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5758
5759 /* Prevent internal slot pages from being moved by fork()/COW. */
5760 if (memslot->id >= KVM_MEMORY_SLOTS)
5761 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5762
5763 /*To keep backward compatibility with older userspace,
5764 *x86 needs to hanlde !user_alloc case.
5765 */
5766 if (!user_alloc) {
5767 if (npages && !old.rmap) {
604b38ac
AA		 5768 unsigned long userspace_addr;
5769
72dc67a6 5770 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5771 userspace_addr = do_mmap(NULL, 0,
5772 npages * PAGE_SIZE,
5773 PROT_READ | PROT_WRITE,
7ac77099 5774 map_flags,
604b38ac 5775 0);
72dc67a6 5776 up_write(&current->mm->mmap_sem);
0de10343 5777
604b38ac
AA		 5778 if (IS_ERR((void *)userspace_addr))
5779 return PTR_ERR((void *)userspace_addr);
5780
604b38ac 5781 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5782 }
5783 }
5784
f7784b8e
MT		 5785
5786 return 0;
5787}
5788
5789void kvm_arch_commit_memory_region(struct kvm *kvm,
5790 struct kvm_userspace_memory_region *mem,
5791 struct kvm_memory_slot old,
5792 int user_alloc)
5793{
5794
5795 int npages = mem->memory_size >> PAGE_SHIFT;
5796
5797 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5798 int ret;
5799
5800 down_write(&current->mm->mmap_sem);
5801 ret = do_munmap(current->mm, old.userspace_addr,
5802 old.npages * PAGE_SIZE);
5803 up_write(&current->mm->mmap_sem);
5804 if (ret < 0)
5805 printk(KERN_WARNING
5806 "kvm_vm_ioctl_set_memory_region: "
5807 "failed to munmap memory\n");
5808 }
5809
7c8a83b7 5810 spin_lock(&kvm->mmu_lock);
f05e70ac 5811 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5812 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5813 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5814 }
5815
5816 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5817 spin_unlock(&kvm->mmu_lock);
0de10343 5818}
1d737c8a 5819
34d4cb8f
MT		 5820void kvm_arch_flush_shadow(struct kvm *kvm)
5821{
5822 kvm_mmu_zap_all(kvm);
8986ecc0 5823 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5824}
5825
1d737c8a
ZX		 5826int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5827{
a4535290 5828 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5829 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5830 || vcpu->arch.nmi_pending ||
5831 (kvm_arch_interrupt_allowed(vcpu) &&
5832 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5833}
5736199a 5834
5736199a
ZX		 5835void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5836{
32f88400
MT		 5837 int me;
5838 int cpu = vcpu->cpu;
5736199a
ZX		 5839
5840 if (waitqueue_active(&vcpu->wq)) {
5841 wake_up_interruptible(&vcpu->wq);
5842 ++vcpu->stat.halt_wakeup;
5843 }
32f88400
MT		 5844
5845 me = get_cpu();
5846 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5847 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5848 smp_send_reschedule(cpu);
e9571ed5 5849 put_cpu();
5736199a 5850}
78646121
GN		 5851
5852int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5853{
5854 return kvm_x86_ops->interrupt_allowed(vcpu);
5855}
229456fc 5856
f92653ee
JK		 5857bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5858{
5859 unsigned long current_rip = kvm_rip_read(vcpu) +
5860 get_segment_base(vcpu, VCPU_SREG_CS);
5861
5862 return current_rip == linear_rip;
5863}
5864EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5865
94fe45da
JK		 5866unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5867{
5868 unsigned long rflags;
5869
5870 rflags = kvm_x86_ops->get_rflags(vcpu);
5871 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5872 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5873 return rflags;
5874}
5875EXPORT_SYMBOL_GPL(kvm_get_rflags);
5876
5877void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5878{
5879 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5880 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5881 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5882 kvm_x86_ops->set_rflags(vcpu, rflags);
5883}
5884EXPORT_SYMBOL_GPL(kvm_set_rflags);
5885
229456fc
MT		 5886EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5887EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5888EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5889EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5890EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5891EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5892EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5893EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5894EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5895EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5896EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5897EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git