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252b5132 1/* 32-bit ELF support for ARM
2571583a 2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0
TP		 3569 /* Force return logic to be reviewed for each new architecture. */
3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3571 || arch == TAG_CPU_ARCH_V8M_BASE
3572 || arch == TAG_CPU_ARCH_V8M_MAIN);
3573
2fd158eb
TP		 3574 if (arch == TAG_CPU_ARCH_V6_M
3575 || arch == TAG_CPU_ARCH_V6S_M
3576 || arch == TAG_CPU_ARCH_V7E_M
3577 || arch == TAG_CPU_ARCH_V8M_BASE
3578 || arch == TAG_CPU_ARCH_V8M_MAIN)
3579 return TRUE;
eed94f8f 3580
2fd158eb 3581 return FALSE;
eed94f8f
NC		 3582}
3583
3584/* Determine if we're dealing with a Thumb-2 object. */
3585
3586static bfd_boolean
3587using_thumb2 (struct elf32_arm_link_hash_table *globals)
3588{
60a019a0
TP		 3589 int arch;
3590 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3591 Tag_THUMB_ISA_use);
3592
3593 if (thumb_isa)
3594 return thumb_isa == 2;
3595
3596 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3597
3598 /* Force return logic to be reviewed for each new architecture. */
3599 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3600 || arch == TAG_CPU_ARCH_V8M_BASE
3601 || arch == TAG_CPU_ARCH_V8M_MAIN);
3602
3603 return (arch == TAG_CPU_ARCH_V6T2
3604 || arch == TAG_CPU_ARCH_V7
3605 || arch == TAG_CPU_ARCH_V7E_M
3606 || arch == TAG_CPU_ARCH_V8
3607 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3608}
3609
5e866f5a
TP		 3610/* Determine whether Thumb-2 BL instruction is available. */
3611
3612static bfd_boolean
3613using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3614{
3615 int arch =
3616 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3617
3618 /* Force return logic to be reviewed for each new architecture. */
3619 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3620 || arch == TAG_CPU_ARCH_V8M_BASE
3621 || arch == TAG_CPU_ARCH_V8M_MAIN);
3622
3623 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3624 return (arch == TAG_CPU_ARCH_V6T2
3625 || arch >= TAG_CPU_ARCH_V7);
3626}
3627
00a97672
RS		 3628/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3629 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3630 hash table. */
3631
3632static bfd_boolean
57e8b36a 3633elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3634{
3635 struct elf32_arm_link_hash_table *htab;
3636
3637 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3638 if (htab == NULL)
3639 return FALSE;
3640
362d30a1 3641 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3642 return FALSE;
3643
3644 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3645 return FALSE;
3646
00a97672
RS		 3647 if (htab->vxworks_p)
3648 {
3649 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3650 return FALSE;
3651
0e1862bb 3652 if (bfd_link_pic (info))
00a97672
RS		 3653 {
3654 htab->plt_header_size = 0;
3655 htab->plt_entry_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3657 }
3658 else
3659 {
3660 htab->plt_header_size
3661 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3662 htab->plt_entry_size
3663 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3664 }
aebf9be7
NC		 3665
3666 if (elf_elfheader (dynobj))
3667 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3668 }
eed94f8f
NC		 3669 else
3670 {
3671 /* PR ld/16017
3672 Test for thumb only architectures. Note - we cannot just call
3673 using_thumb_only() as the attributes in the output bfd have not been
3674 initialised at this point, so instead we use the input bfd. */
3675 bfd * saved_obfd = htab->obfd;
3676
3677 htab->obfd = dynobj;
3678 if (using_thumb_only (htab))
3679 {
3680 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3681 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3682 }
3683 htab->obfd = saved_obfd;
3684 }
5e681ec4 3685
362d30a1
RS		 3686 if (!htab->root.splt
3687 || !htab->root.srelplt
9d19e4fd
AM		 3688 || !htab->root.sdynbss
3689 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3690 abort ();
3691
3692 return TRUE;
3693}
3694
906e58ca
NC		 3695/* Copy the extra info we tack onto an elf_link_hash_entry. */
3696
3697static void
3698elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3699 struct elf_link_hash_entry *dir,
3700 struct elf_link_hash_entry *ind)
3701{
3702 struct elf32_arm_link_hash_entry *edir, *eind;
3703
3704 edir = (struct elf32_arm_link_hash_entry *) dir;
3705 eind = (struct elf32_arm_link_hash_entry *) ind;
3706
0bdcacaf 3707 if (eind->dyn_relocs != NULL)
906e58ca 3708 {
0bdcacaf 3709 if (edir->dyn_relocs != NULL)
906e58ca 3710 {
0bdcacaf
RS		 3711 struct elf_dyn_relocs **pp;
3712 struct elf_dyn_relocs *p;
906e58ca
NC		 3713
3714 /* Add reloc counts against the indirect sym to the direct sym
3715 list. Merge any entries against the same section. */
0bdcacaf 3716 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3717 {
0bdcacaf 3718 struct elf_dyn_relocs *q;
906e58ca 3719
0bdcacaf
RS		 3720 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3721 if (q->sec == p->sec)
906e58ca
NC		 3722 {
3723 q->pc_count += p->pc_count;
3724 q->count += p->count;
3725 *pp = p->next;
3726 break;
3727 }
3728 if (q == NULL)
3729 pp = &p->next;
3730 }
0bdcacaf 3731 *pp = edir->dyn_relocs;
906e58ca
NC		 3732 }
3733
0bdcacaf
RS		 3734 edir->dyn_relocs = eind->dyn_relocs;
3735 eind->dyn_relocs = NULL;
906e58ca
NC		 3736 }
3737
3738 if (ind->root.type == bfd_link_hash_indirect)
3739 {
3740 /* Copy over PLT info. */
34e77a92
RS		 3741 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3742 eind->plt.thumb_refcount = 0;
3743 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3744 eind->plt.maybe_thumb_refcount = 0;
3745 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3746 eind->plt.noncall_refcount = 0;
3747
3748 /* We should only allocate a function to .iplt once the final
3749 symbol information is known. */
3750 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3751
3752 if (dir->got.refcount <= 0)
3753 {
3754 edir->tls_type = eind->tls_type;
3755 eind->tls_type = GOT_UNKNOWN;
3756 }
3757 }
3758
3759 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3760}
3761
68faa637
AM		 3762/* Destroy an ARM elf linker hash table. */
3763
3764static void
d495ab0d 3765elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3766{
3767 struct elf32_arm_link_hash_table *ret
d495ab0d 3768 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3769
3770 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3771 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3772}
3773
906e58ca
NC		 3774/* Create an ARM elf linker hash table. */
3775
3776static struct bfd_link_hash_table *
3777elf32_arm_link_hash_table_create (bfd *abfd)
3778{
3779 struct elf32_arm_link_hash_table *ret;
3780 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3781
7bf52ea2 3782 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3783 if (ret == NULL)
3784 return NULL;
3785
3786 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3787 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3788 sizeof (struct elf32_arm_link_hash_entry),
3789 ARM_ELF_DATA))
906e58ca
NC		 3790 {
3791 free (ret);
3792 return NULL;
3793 }
3794
906e58ca 3795 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3796 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3797#ifdef FOUR_WORD_PLT
3798 ret->plt_header_size = 16;
3799 ret->plt_entry_size = 16;
3800#else
3801 ret->plt_header_size = 20;
1db37fe6 3802 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3803#endif
906e58ca 3804 ret->use_rel = 1;
906e58ca 3805 ret->obfd = abfd;
906e58ca
NC		 3806
3807 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3808 sizeof (struct elf32_arm_stub_hash_entry)))
3809 {
d495ab0d 3810 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3811 return NULL;
3812 }
d495ab0d 3813 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3814
3815 return &ret->root.root;
3816}
3817
cd1dac3d
DG		 3818/* Determine what kind of NOPs are available. */
3819
3820static bfd_boolean
3821arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3822{
3823 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3824 Tag_CPU_arch);
cd1dac3d 3825
60a019a0
TP		 3826 /* Force return logic to be reviewed for each new architecture. */
3827 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8M_BASE
3829 || arch == TAG_CPU_ARCH_V8M_MAIN);
3830
3831 return (arch == TAG_CPU_ARCH_V6T2
3832 || arch == TAG_CPU_ARCH_V6K
3833 || arch == TAG_CPU_ARCH_V7
3834 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3835}
3836
f4ac8484
DJ		 3837static bfd_boolean
3838arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3839{
3840 switch (stub_type)
3841 {
fea2b4d6 3842 case arm_stub_long_branch_thumb_only:
80c135e5 3843 case arm_stub_long_branch_thumb2_only:
d5a67c02 3844 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3845 case arm_stub_long_branch_v4t_thumb_arm:
3846 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3847 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3848 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3849 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3850 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3851 return TRUE;
3852 case arm_stub_none:
3853 BFD_FAIL ();
3854 return FALSE;
3855 break;
3856 default:
3857 return FALSE;
3858 }
3859}
3860
906e58ca
NC		 3861/* Determine the type of stub needed, if any, for a call. */
3862
3863static enum elf32_arm_stub_type
3864arm_type_of_stub (struct bfd_link_info *info,
3865 asection *input_sec,
3866 const Elf_Internal_Rela *rel,
34e77a92 3867 unsigned char st_type,
35fc36a8 3868 enum arm_st_branch_type *actual_branch_type,
906e58ca 3869 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3870 bfd_vma destination,
3871 asection *sym_sec,
3872 bfd *input_bfd,
3873 const char *name)
906e58ca
NC		 3874{
3875 bfd_vma location;
3876 bfd_signed_vma branch_offset;
3877 unsigned int r_type;
3878 struct elf32_arm_link_hash_table * globals;
5e866f5a 3879 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3880 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3881 int use_plt = 0;
35fc36a8 3882 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3883 union gotplt_union *root_plt;
3884 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3885 int arch;
3886 int thumb2_movw;
906e58ca 3887
35fc36a8 3888 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3889 return stub_type;
3890
906e58ca 3891 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3892 if (globals == NULL)
3893 return stub_type;
906e58ca
NC		 3894
3895 thumb_only = using_thumb_only (globals);
906e58ca 3896 thumb2 = using_thumb2 (globals);
5e866f5a 3897 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3898
d5a67c02
AV		 3899 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3900
3901 /* True for architectures that implement the thumb2 movw instruction. */
3902 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3903
906e58ca
NC		 3904 /* Determine where the call point is. */
3905 location = (input_sec->output_offset
3906 + input_sec->output_section->vma
3907 + rel->r_offset);
3908
906e58ca
NC		 3909 r_type = ELF32_R_TYPE (rel->r_info);
3910
39f21624
NC		 3911 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3912 are considering a function call relocation. */
c5423981
TG		 3913 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3914 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3915 && branch_type == ST_BRANCH_TO_ARM)
3916 branch_type = ST_BRANCH_TO_THUMB;
3917
34e77a92
RS		 3918 /* For TLS call relocs, it is the caller's responsibility to provide
3919 the address of the appropriate trampoline. */
3920 if (r_type != R_ARM_TLS_CALL
3921 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3922 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3923 ELF32_R_SYM (rel->r_info), &root_plt,
3924 &arm_plt)
34e77a92 3925 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3926 {
34e77a92 3927 asection *splt;
fe33d2fa 3928
34e77a92
RS		 3929 if (hash == NULL || hash->is_iplt)
3930 splt = globals->root.iplt;
3931 else
3932 splt = globals->root.splt;
3933 if (splt != NULL)
b38cadfb 3934 {
34e77a92
RS		 3935 use_plt = 1;
3936
3937 /* Note when dealing with PLT entries: the main PLT stub is in
3938 ARM mode, so if the branch is in Thumb mode, another
3939 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3940 PLT stub. If a long branch stub is needed, we'll add a
3941 Thumb->Arm one and branch directly to the ARM PLT entry.
3942 Here, we have to check if a pre-PLT Thumb->ARM stub
3943 is needed and if it will be close enough. */
34e77a92
RS		 3944
3945 destination = (splt->output_section->vma
3946 + splt->output_offset
3947 + root_plt->offset);
3948 st_type = STT_FUNC;
2df2751d
CL		 3949
3950 /* Thumb branch/call to PLT: it can become a branch to ARM
3951 or to Thumb. We must perform the same checks and
3952 corrections as in elf32_arm_final_link_relocate. */
3953 if ((r_type == R_ARM_THM_CALL)
3954 || (r_type == R_ARM_THM_JUMP24))
3955 {
3956 if (globals->use_blx
3957 && r_type == R_ARM_THM_CALL
3958 && !thumb_only)
3959 {
3960 /* If the Thumb BLX instruction is available, convert
3961 the BL to a BLX instruction to call the ARM-mode
3962 PLT entry. */
3963 branch_type = ST_BRANCH_TO_ARM;
3964 }
3965 else
3966 {
3967 if (!thumb_only)
3968 /* Target the Thumb stub before the ARM PLT entry. */
3969 destination -= PLT_THUMB_STUB_SIZE;
3970 branch_type = ST_BRANCH_TO_THUMB;
3971 }
3972 }
3973 else
3974 {
3975 branch_type = ST_BRANCH_TO_ARM;
3976 }
34e77a92 3977 }
5fa9e92f 3978 }
34e77a92
RS		 3979 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3980 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3981
fe33d2fa
CL		 3982 branch_offset = (bfd_signed_vma)(destination - location);
3983
0855e32b 3984 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3985 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3986 {
5fa9e92f
CL		 3987 /* Handle cases where:
3988 - this call goes too far (different Thumb/Thumb2 max
99059e56 3989 distance)
155d87d7 3990 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3991 Thumb->Arm branch (not bl). A stub is needed in this case,
3992 but only if this call is not through a PLT entry. Indeed,
695344c0 3993 PLT stubs handle mode switching already. */
5e866f5a 3994 if ((!thumb2_bl
906e58ca
NC		 3995 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3996 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3997 || (thumb2_bl
906e58ca
NC		 3998 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3999 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4000 || (thumb2
4001 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4002 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4003 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4004 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4005 && (((r_type == R_ARM_THM_CALL
4006 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4007 || (r_type == R_ARM_THM_JUMP24)
4008 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4009 && !use_plt))
906e58ca 4010 {
2df2751d
CL		 4011 /* If we need to insert a Thumb-Thumb long branch stub to a
4012 PLT, use one that branches directly to the ARM PLT
4013 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4014 stub, undo this now. */
695344c0
NC		 4015 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4016 {
4017 branch_type = ST_BRANCH_TO_ARM;
4018 branch_offset += PLT_THUMB_STUB_SIZE;
4019 }
2df2751d 4020
35fc36a8 4021 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4022 {
4023 /* Thumb to thumb. */
4024 if (!thumb_only)
4025 {
d5a67c02 4026 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4027 _bfd_error_handler
4028 (_("%B(%A): warning: long branch veneers used in"
4029 " section with SHF_ARM_PURECODE section"
4030 " attribute is only supported for M-profile"
4031 " targets that implement the movw instruction."),
4032 input_bfd, input_sec);
d5a67c02 4033
0e1862bb 4034 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4035 /* PIC stubs. */
155d87d7 4036 ? ((globals->use_blx
9553db3c 4037 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4038 /* V5T and above. Stub starts with ARM code, so
4039 we must be able to switch mode before
4040 reaching it, which is only possible for 'bl'
4041 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4042 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4043 /* On V4T, use Thumb code only. */
d3626fb0 4044 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4045
4046 /* non-PIC stubs. */
155d87d7 4047 : ((globals->use_blx
9553db3c 4048 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4049 /* V5T and above. */
4050 ? arm_stub_long_branch_any_any
4051 /* V4T. */
d3626fb0 4052 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4053 }
4054 else
4055 {
d5a67c02
AV		 4056 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4057 stub_type = arm_stub_long_branch_thumb2_only_pure;
4058 else
4059 {
4060 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4061 _bfd_error_handler
4062 (_("%B(%A): warning: long branch veneers used in"
4063 " section with SHF_ARM_PURECODE section"
4064 " attribute is only supported for M-profile"
4065 " targets that implement the movw instruction."),
4066 input_bfd, input_sec);
d5a67c02
AV		 4067
4068 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4069 /* PIC stub. */
4070 ? arm_stub_long_branch_thumb_only_pic
4071 /* non-PIC stub. */
4072 : (thumb2 ? arm_stub_long_branch_thumb2_only
4073 : arm_stub_long_branch_thumb_only);
4074 }
906e58ca
NC		 4075 }
4076 }
4077 else
4078 {
d5a67c02 4079 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4080 _bfd_error_handler
4081 (_("%B(%A): warning: long branch veneers used in"
4082 " section with SHF_ARM_PURECODE section"
4083 " attribute is only supported" " for M-profile"
4084 " targets that implement the movw instruction."),
4085 input_bfd, input_sec);
d5a67c02 4086
906e58ca 4087 /* Thumb to arm. */
c820be07
NC		 4088 if (sym_sec != NULL
4089 && sym_sec->owner != NULL
4090 && !INTERWORK_FLAG (sym_sec->owner))
4091 {
4eca0228 4092 _bfd_error_handler
c820be07
NC		 4093 (_("%B(%s): warning: interworking not enabled.\n"
4094 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 4095 sym_sec->owner, name, input_bfd);
c820be07
NC		 4096 }
4097
0855e32b 4098 stub_type =
0e1862bb 4099 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4100 /* PIC stubs. */
0855e32b 4101 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4102 /* TLS PIC stubs. */
0855e32b
NS		 4103 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4104 : arm_stub_long_branch_v4t_thumb_tls_pic)
4105 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4106 /* V5T PIC and above. */
4107 ? arm_stub_long_branch_any_arm_pic
4108 /* V4T PIC stub. */
4109 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4110
4111 /* non-PIC stubs. */
0855e32b 4112 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4113 /* V5T and above. */
4114 ? arm_stub_long_branch_any_any
4115 /* V4T. */
4116 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4117
4118 /* Handle v4t short branches. */
fea2b4d6 4119 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4120 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4121 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4122 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4123 }
4124 }
4125 }
fe33d2fa
CL		 4126 else if (r_type == R_ARM_CALL
4127 || r_type == R_ARM_JUMP24
0855e32b
NS		 4128 || r_type == R_ARM_PLT32
4129 || r_type == R_ARM_TLS_CALL)
906e58ca 4130 {
d5a67c02 4131 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4132 _bfd_error_handler
4133 (_("%B(%A): warning: long branch veneers used in"
4134 " section with SHF_ARM_PURECODE section"
4135 " attribute is only supported for M-profile"
4136 " targets that implement the movw instruction."),
4137 input_bfd, input_sec);
35fc36a8 4138 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4139 {
4140 /* Arm to thumb. */
c820be07
NC		 4141
4142 if (sym_sec != NULL
4143 && sym_sec->owner != NULL
4144 && !INTERWORK_FLAG (sym_sec->owner))
4145 {
4eca0228 4146 _bfd_error_handler
c820be07 4147 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4148 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4149 sym_sec->owner, input_bfd, name);
4150 }
4151
4152 /* We have an extra 2-bytes reach because of
4153 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4154 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4155 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4156 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4157 || (r_type == R_ARM_JUMP24)
4158 || (r_type == R_ARM_PLT32))
906e58ca 4159 {
0e1862bb 4160 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4161 /* PIC stubs. */
ebe24dd4
CL		 4162 ? ((globals->use_blx)
4163 /* V5T and above. */
4164 ? arm_stub_long_branch_any_thumb_pic
4165 /* V4T stub. */
4166 : arm_stub_long_branch_v4t_arm_thumb_pic)
4167
c2b4a39d
CL		 4168 /* non-PIC stubs. */
4169 : ((globals->use_blx)
4170 /* V5T and above. */
4171 ? arm_stub_long_branch_any_any
4172 /* V4T. */
4173 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4174 }
4175 }
4176 else
4177 {
4178 /* Arm to arm. */
4179 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4180 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4181 {
0855e32b 4182 stub_type =
0e1862bb 4183 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4184 /* PIC stubs. */
0855e32b 4185 ? (r_type == R_ARM_TLS_CALL
6a631e86 4186 /* TLS PIC Stub. */
0855e32b 4187 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4188 : (globals->nacl_p
4189 ? arm_stub_long_branch_arm_nacl_pic
4190 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4191 /* non-PIC stubs. */
7a89b94e
NC		 4192 : (globals->nacl_p
4193 ? arm_stub_long_branch_arm_nacl
4194 : arm_stub_long_branch_any_any);
906e58ca
NC		 4195 }
4196 }
4197 }
4198
fe33d2fa
CL		 4199 /* If a stub is needed, record the actual destination type. */
4200 if (stub_type != arm_stub_none)
35fc36a8 4201 *actual_branch_type = branch_type;
fe33d2fa 4202
906e58ca
NC		 4203 return stub_type;
4204}
4205
4206/* Build a name for an entry in the stub hash table. */
4207
4208static char *
4209elf32_arm_stub_name (const asection *input_section,
4210 const asection *sym_sec,
4211 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4212 const Elf_Internal_Rela *rel,
4213 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4214{
4215 char *stub_name;
4216 bfd_size_type len;
4217
4218 if (hash)
4219 {
fe33d2fa 4220 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4221 stub_name = (char *) bfd_malloc (len);
906e58ca 4222 if (stub_name != NULL)
fe33d2fa 4223 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4224 input_section->id & 0xffffffff,
4225 hash->root.root.root.string,
fe33d2fa
CL		 4226 (int) rel->r_addend & 0xffffffff,
4227 (int) stub_type);
906e58ca
NC		 4228 }
4229 else
4230 {
fe33d2fa 4231 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4232 stub_name = (char *) bfd_malloc (len);
906e58ca 4233 if (stub_name != NULL)
fe33d2fa 4234 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4235 input_section->id & 0xffffffff,
4236 sym_sec->id & 0xffffffff,
0855e32b
NS		 4237 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4238 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4239 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4240 (int) rel->r_addend & 0xffffffff,
4241 (int) stub_type);
906e58ca
NC		 4242 }
4243
4244 return stub_name;
4245}
4246
4247/* Look up an entry in the stub hash. Stub entries are cached because
4248 creating the stub name takes a bit of time. */
4249
4250static struct elf32_arm_stub_hash_entry *
4251elf32_arm_get_stub_entry (const asection *input_section,
4252 const asection *sym_sec,
4253 struct elf_link_hash_entry *hash,
4254 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4255 struct elf32_arm_link_hash_table *htab,
4256 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4257{
4258 struct elf32_arm_stub_hash_entry *stub_entry;
4259 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4260 const asection *id_sec;
4261
4262 if ((input_section->flags & SEC_CODE) == 0)
4263 return NULL;
4264
4265 /* If this input section is part of a group of sections sharing one
4266 stub section, then use the id of the first section in the group.
4267 Stub names need to include a section id, as there may well be
4268 more than one stub used to reach say, printf, and we need to
4269 distinguish between them. */
c2abbbeb 4270 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4271 id_sec = htab->stub_group[input_section->id].link_sec;
4272
4273 if (h != NULL && h->stub_cache != NULL
4274 && h->stub_cache->h == h
fe33d2fa
CL		 4275 && h->stub_cache->id_sec == id_sec
4276 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4277 {
4278 stub_entry = h->stub_cache;
4279 }
4280 else
4281 {
4282 char *stub_name;
4283
fe33d2fa 4284 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4285 if (stub_name == NULL)
4286 return NULL;
4287
4288 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4289 stub_name, FALSE, FALSE);
4290 if (h != NULL)
4291 h->stub_cache = stub_entry;
4292
4293 free (stub_name);
4294 }
4295
4296 return stub_entry;
4297}
4298
daa4adae
TP		 4299/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4300 section. */
4301
4302static bfd_boolean
4303arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4304{
4305 if (stub_type >= max_stub_type)
4306 abort (); /* Should be unreachable. */
4307
4ba2ef8f
TP		 4308 switch (stub_type)
4309 {
4310 case arm_stub_cmse_branch_thumb_only:
4311 return TRUE;
4312
4313 default:
4314 return FALSE;
4315 }
4316
4317 abort (); /* Should be unreachable. */
daa4adae
TP		 4318}
4319
4320/* Required alignment (as a power of 2) for the dedicated section holding
4321 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4322 with input sections. */
4323
4324static int
4325arm_dedicated_stub_output_section_required_alignment
4326 (enum elf32_arm_stub_type stub_type)
4327{
4328 if (stub_type >= max_stub_type)
4329 abort (); /* Should be unreachable. */
4330
4ba2ef8f
TP		 4331 switch (stub_type)
4332 {
4333 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4334 boundary. */
4335 case arm_stub_cmse_branch_thumb_only:
4336 return 5;
4337
4338 default:
4339 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4340 return 0;
4341 }
4342
4343 abort (); /* Should be unreachable. */
daa4adae
TP		 4344}
4345
4346/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4347 NULL if veneers of this type are interspersed with input sections. */
4348
4349static const char *
4350arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4351{
4352 if (stub_type >= max_stub_type)
4353 abort (); /* Should be unreachable. */
4354
4ba2ef8f
TP		 4355 switch (stub_type)
4356 {
4357 case arm_stub_cmse_branch_thumb_only:
4358 return ".gnu.sgstubs";
4359
4360 default:
4361 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4362 return NULL;
4363 }
4364
4365 abort (); /* Should be unreachable. */
daa4adae
TP		 4366}
4367
4368/* If veneers of type STUB_TYPE should go in a dedicated output section,
4369 returns the address of the hash table field in HTAB holding a pointer to the
4370 corresponding input section. Otherwise, returns NULL. */
4371
4372static asection **
4ba2ef8f
TP		 4373arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4374 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4375{
4376 if (stub_type >= max_stub_type)
4377 abort (); /* Should be unreachable. */
4378
4ba2ef8f
TP		 4379 switch (stub_type)
4380 {
4381 case arm_stub_cmse_branch_thumb_only:
4382 return &htab->cmse_stub_sec;
4383
4384 default:
4385 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4386 return NULL;
4387 }
4388
4389 abort (); /* Should be unreachable. */
daa4adae
TP		 4390}
4391
4392/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4393 is the section that branch into veneer and can be NULL if stub should go in
4394 a dedicated output section. Returns a pointer to the stub section, and the
4395 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4396 LINK_SEC_P may be NULL. */
906e58ca 4397
48229727
JB		 4398static asection *
4399elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4400 struct elf32_arm_link_hash_table *htab,
4401 enum elf32_arm_stub_type stub_type)
906e58ca 4402{
daa4adae
TP		 4403 asection *link_sec, *out_sec, **stub_sec_p;
4404 const char *stub_sec_prefix;
4405 bfd_boolean dedicated_output_section =
4406 arm_dedicated_stub_output_section_required (stub_type);
4407 int align;
906e58ca 4408
daa4adae 4409 if (dedicated_output_section)
906e58ca 4410 {
daa4adae
TP		 4411 bfd *output_bfd = htab->obfd;
4412 const char *out_sec_name =
4413 arm_dedicated_stub_output_section_name (stub_type);
4414 link_sec = NULL;
4415 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4416 stub_sec_prefix = out_sec_name;
4417 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4418 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4419 if (out_sec == NULL)
906e58ca 4420 {
4eca0228
AM		 4421 _bfd_error_handler (_("No address assigned to the veneers output "
4422 "section %s"), out_sec_name);
daa4adae 4423 return NULL;
906e58ca 4424 }
daa4adae
TP		 4425 }
4426 else
4427 {
c2abbbeb 4428 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4429 link_sec = htab->stub_group[section->id].link_sec;
4430 BFD_ASSERT (link_sec != NULL);
4431 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4432 if (*stub_sec_p == NULL)
4433 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4434 stub_sec_prefix = link_sec->name;
4435 out_sec = link_sec->output_section;
4436 align = htab->nacl_p ? 4 : 3;
906e58ca 4437 }
b38cadfb 4438
daa4adae
TP		 4439 if (*stub_sec_p == NULL)
4440 {
4441 size_t namelen;
4442 bfd_size_type len;
4443 char *s_name;
4444
4445 namelen = strlen (stub_sec_prefix);
4446 len = namelen + sizeof (STUB_SUFFIX);
4447 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4448 if (s_name == NULL)
4449 return NULL;
4450
4451 memcpy (s_name, stub_sec_prefix, namelen);
4452 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4453 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4454 align);
4455 if (*stub_sec_p == NULL)
4456 return NULL;
4457
4458 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4459 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4460 | SEC_KEEP;
4461 }
4462
4463 if (!dedicated_output_section)
4464 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4465
48229727
JB		 4466 if (link_sec_p)
4467 *link_sec_p = link_sec;
b38cadfb 4468
daa4adae 4469 return *stub_sec_p;
48229727
JB		 4470}
4471
4472/* Add a new stub entry to the stub hash. Not all fields of the new
4473 stub entry are initialised. */
4474
4475static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4476elf32_arm_add_stub (const char *stub_name, asection *section,
4477 struct elf32_arm_link_hash_table *htab,
4478 enum elf32_arm_stub_type stub_type)
48229727
JB		 4479{
4480 asection *link_sec;
4481 asection *stub_sec;
4482 struct elf32_arm_stub_hash_entry *stub_entry;
4483
daa4adae
TP		 4484 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4485 stub_type);
48229727
JB		 4486 if (stub_sec == NULL)
4487 return NULL;
906e58ca
NC		 4488
4489 /* Enter this entry into the linker stub hash table. */
4490 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4491 TRUE, FALSE);
4492 if (stub_entry == NULL)
4493 {
6bde4c52
TP		 4494 if (section == NULL)
4495 section = stub_sec;
dae82561 4496 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 4497 section->owner, stub_name);
906e58ca
NC		 4498 return NULL;
4499 }
4500
4501 stub_entry->stub_sec = stub_sec;
0955507f 4502 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4503 stub_entry->id_sec = link_sec;
4504
906e58ca
NC		 4505 return stub_entry;
4506}
4507
4508/* Store an Arm insn into an output section not processed by
4509 elf32_arm_write_section. */
4510
4511static void
8029a119
NC		 4512put_arm_insn (struct elf32_arm_link_hash_table * htab,
4513 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4514{
4515 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4516 bfd_putl32 (val, ptr);
4517 else
4518 bfd_putb32 (val, ptr);
4519}
4520
4521/* Store a 16-bit Thumb insn into an output section not processed by
4522 elf32_arm_write_section. */
4523
4524static void
8029a119
NC		 4525put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4526 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4527{
4528 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4529 bfd_putl16 (val, ptr);
4530 else
4531 bfd_putb16 (val, ptr);
4532}
4533
a504d23a
LA		 4534/* Store a Thumb2 insn into an output section not processed by
4535 elf32_arm_write_section. */
4536
4537static void
4538put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4539 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4540{
4541 /* T2 instructions are 16-bit streamed. */
4542 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4543 {
4544 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4545 bfd_putl16 ((val & 0xffff), ptr + 2);
4546 }
4547 else
4548 {
4549 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4550 bfd_putb16 ((val & 0xffff), ptr + 2);
4551 }
4552}
4553
0855e32b
NS		 4554/* If it's possible to change R_TYPE to a more efficient access
4555 model, return the new reloc type. */
4556
4557static unsigned
b38cadfb 4558elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4559 struct elf_link_hash_entry *h)
4560{
4561 int is_local = (h == NULL);
4562
0e1862bb
L		 4563 if (bfd_link_pic (info)
4564 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4565 return r_type;
4566
b38cadfb 4567 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4568 switch (r_type)
4569 {
4570 case R_ARM_TLS_GOTDESC:
4571 case R_ARM_TLS_CALL:
4572 case R_ARM_THM_TLS_CALL:
4573 case R_ARM_TLS_DESCSEQ:
4574 case R_ARM_THM_TLS_DESCSEQ:
4575 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4576 }
4577
4578 return r_type;
4579}
4580
48229727
JB		 4581static bfd_reloc_status_type elf32_arm_final_link_relocate
4582 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4583 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4584 const char *, unsigned char, enum arm_st_branch_type,
4585 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4586
4563a860
JB		 4587static unsigned int
4588arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4589{
4590 switch (stub_type)
4591 {
4592 case arm_stub_a8_veneer_b_cond:
4593 case arm_stub_a8_veneer_b:
4594 case arm_stub_a8_veneer_bl:
4595 return 2;
4596
4597 case arm_stub_long_branch_any_any:
4598 case arm_stub_long_branch_v4t_arm_thumb:
4599 case arm_stub_long_branch_thumb_only:
80c135e5 4600 case arm_stub_long_branch_thumb2_only:
d5a67c02 4601 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4602 case arm_stub_long_branch_v4t_thumb_thumb:
4603 case arm_stub_long_branch_v4t_thumb_arm:
4604 case arm_stub_short_branch_v4t_thumb_arm:
4605 case arm_stub_long_branch_any_arm_pic:
4606 case arm_stub_long_branch_any_thumb_pic:
4607 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4608 case arm_stub_long_branch_v4t_arm_thumb_pic:
4609 case arm_stub_long_branch_v4t_thumb_arm_pic:
4610 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4611 case arm_stub_long_branch_any_tls_pic:
4612 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4613 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4614 case arm_stub_a8_veneer_blx:
4615 return 4;
b38cadfb 4616
7a89b94e
NC		 4617 case arm_stub_long_branch_arm_nacl:
4618 case arm_stub_long_branch_arm_nacl_pic:
4619 return 16;
4620
4563a860
JB		 4621 default:
4622 abort (); /* Should be unreachable. */
4623 }
4624}
4625
4f4faa4d
TP		 4626/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4627 veneering (TRUE) or have their own symbol (FALSE). */
4628
4629static bfd_boolean
4630arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4631{
4632 if (stub_type >= max_stub_type)
4633 abort (); /* Should be unreachable. */
4634
4ba2ef8f
TP		 4635 switch (stub_type)
4636 {
4637 case arm_stub_cmse_branch_thumb_only:
4638 return TRUE;
4639
4640 default:
4641 return FALSE;
4642 }
4643
4644 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4645}
4646
d7c5bd02
TP		 4647/* Returns the padding needed for the dedicated section used stubs of type
4648 STUB_TYPE. */
4649
4650static int
4651arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4652{
4653 if (stub_type >= max_stub_type)
4654 abort (); /* Should be unreachable. */
4655
4ba2ef8f
TP		 4656 switch (stub_type)
4657 {
4658 case arm_stub_cmse_branch_thumb_only:
4659 return 32;
4660
4661 default:
4662 return 0;
4663 }
4664
4665 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4666}
4667
0955507f
TP		 4668/* If veneers of type STUB_TYPE should go in a dedicated output section,
4669 returns the address of the hash table field in HTAB holding the offset at
4670 which new veneers should be layed out in the stub section. */
4671
4672static bfd_vma*
4673arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4674 enum elf32_arm_stub_type stub_type)
4675{
4676 switch (stub_type)
4677 {
4678 case arm_stub_cmse_branch_thumb_only:
4679 return &htab->new_cmse_stub_offset;
4680
4681 default:
4682 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4683 return NULL;
4684 }
4685}
4686
906e58ca
NC		 4687static bfd_boolean
4688arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4689 void * in_arg)
4690{
7a89b94e 4691#define MAXRELOCS 3
0955507f 4692 bfd_boolean removed_sg_veneer;
906e58ca 4693 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4694 struct elf32_arm_link_hash_table *globals;
906e58ca 4695 struct bfd_link_info *info;
906e58ca
NC		 4696 asection *stub_sec;
4697 bfd *stub_bfd;
906e58ca
NC		 4698 bfd_byte *loc;
4699 bfd_vma sym_value;
4700 int template_size;
4701 int size;
d3ce72d0 4702 const insn_sequence *template_sequence;
906e58ca 4703 int i;
48229727
JB		 4704 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4705 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4706 int nrelocs = 0;
0955507f 4707 int just_allocated = 0;
906e58ca
NC		 4708
4709 /* Massage our args to the form they really have. */
4710 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4711 info = (struct bfd_link_info *) in_arg;
4712
4713 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4714 if (globals == NULL)
4715 return FALSE;
906e58ca 4716
906e58ca
NC		 4717 stub_sec = stub_entry->stub_sec;
4718
4dfe6ac6 4719 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4720 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4721 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4722 return TRUE;
fe33d2fa 4723
0955507f
TP		 4724 /* Assign a slot at the end of section if none assigned yet. */
4725 if (stub_entry->stub_offset == (bfd_vma) -1)
4726 {
4727 stub_entry->stub_offset = stub_sec->size;
4728 just_allocated = 1;
4729 }
906e58ca
NC		 4730 loc = stub_sec->contents + stub_entry->stub_offset;
4731
4732 stub_bfd = stub_sec->owner;
4733
906e58ca
NC		 4734 /* This is the address of the stub destination. */
4735 sym_value = (stub_entry->target_value
4736 + stub_entry->target_section->output_offset
4737 + stub_entry->target_section->output_section->vma);
4738
d3ce72d0 4739 template_sequence = stub_entry->stub_template;
461a49ca 4740 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4741
4742 size = 0;
461a49ca 4743 for (i = 0; i < template_size; i++)
906e58ca 4744 {
d3ce72d0 4745 switch (template_sequence[i].type)
461a49ca
DJ		 4746 {
4747 case THUMB16_TYPE:
48229727 4748 {
d3ce72d0
NC		 4749 bfd_vma data = (bfd_vma) template_sequence[i].data;
4750 if (template_sequence[i].reloc_addend != 0)
48229727 4751 {
99059e56
RM		 4752 /* We've borrowed the reloc_addend field to mean we should
4753 insert a condition code into this (Thumb-1 branch)
4754 instruction. See THUMB16_BCOND_INSN. */
4755 BFD_ASSERT ((data & 0xff00) == 0xd000);
4756 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4757 }
fe33d2fa 4758 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4759 size += 2;
4760 }
461a49ca 4761 break;
906e58ca 4762
48229727 4763 case THUMB32_TYPE:
fe33d2fa
CL		 4764 bfd_put_16 (stub_bfd,
4765 (template_sequence[i].data >> 16) & 0xffff,
4766 loc + size);
4767 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4768 loc + size + 2);
99059e56
RM		 4769 if (template_sequence[i].r_type != R_ARM_NONE)
4770 {
4771 stub_reloc_idx[nrelocs] = i;
4772 stub_reloc_offset[nrelocs++] = size;
4773 }
4774 size += 4;
4775 break;
48229727 4776
461a49ca 4777 case ARM_TYPE:
fe33d2fa
CL		 4778 bfd_put_32 (stub_bfd, template_sequence[i].data,
4779 loc + size);
461a49ca
DJ		 4780 /* Handle cases where the target is encoded within the
4781 instruction. */
d3ce72d0 4782 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4783 {
48229727
JB		 4784 stub_reloc_idx[nrelocs] = i;
4785 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4786 }
4787 size += 4;
4788 break;
4789
4790 case DATA_TYPE:
d3ce72d0 4791 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4792 stub_reloc_idx[nrelocs] = i;
4793 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4794 size += 4;
4795 break;
4796
4797 default:
4798 BFD_FAIL ();
4799 return FALSE;
4800 }
906e58ca 4801 }
461a49ca 4802
0955507f
TP		 4803 if (just_allocated)
4804 stub_sec->size += size;
906e58ca 4805
461a49ca
DJ		 4806 /* Stub size has already been computed in arm_size_one_stub. Check
4807 consistency. */
4808 BFD_ASSERT (size == stub_entry->stub_size);
4809
906e58ca 4810 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4811 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4812 sym_value |= 1;
4813
0955507f
TP		 4814 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4815 to relocate in each stub. */
4816 removed_sg_veneer =
4817 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4818 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4819
48229727 4820 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4821 {
4822 Elf_Internal_Rela rel;
4823 bfd_boolean unresolved_reloc;
4824 char *error_message;
4825 bfd_vma points_to =
4826 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4827
4828 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4829 rel.r_info = ELF32_R_INFO (0,
4830 template_sequence[stub_reloc_idx[i]].r_type);
4831 rel.r_addend = 0;
4832
4833 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4834 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4835 template should refer back to the instruction after the original
4836 branch. We use target_section as Cortex-A8 erratum workaround stubs
4837 are only generated when both source and target are in the same
4838 section. */
4839 points_to = stub_entry->target_section->output_section->vma
4840 + stub_entry->target_section->output_offset
4841 + stub_entry->source_value;
4842
4843 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4844 (template_sequence[stub_reloc_idx[i]].r_type),
4845 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4846 points_to, info, stub_entry->target_section, "", STT_FUNC,
4847 stub_entry->branch_type,
4848 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4849 &error_message);
4850 }
906e58ca
NC		 4851
4852 return TRUE;
48229727 4853#undef MAXRELOCS
906e58ca
NC		 4854}
4855
48229727
JB		 4856/* Calculate the template, template size and instruction size for a stub.
4857 Return value is the instruction size. */
906e58ca 4858
48229727
JB		 4859static unsigned int
4860find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4861 const insn_sequence **stub_template,
4862 int *stub_template_size)
906e58ca 4863{
d3ce72d0 4864 const insn_sequence *template_sequence = NULL;
48229727
JB		 4865 int template_size = 0, i;
4866 unsigned int size;
906e58ca 4867
d3ce72d0 4868 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4869 if (stub_template)
4870 *stub_template = template_sequence;
4871
48229727 4872 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4873 if (stub_template_size)
4874 *stub_template_size = template_size;
906e58ca
NC		 4875
4876 size = 0;
461a49ca
DJ		 4877 for (i = 0; i < template_size; i++)
4878 {
d3ce72d0 4879 switch (template_sequence[i].type)
461a49ca
DJ		 4880 {
4881 case THUMB16_TYPE:
4882 size += 2;
4883 break;
4884
4885 case ARM_TYPE:
48229727 4886 case THUMB32_TYPE:
461a49ca
DJ		 4887 case DATA_TYPE:
4888 size += 4;
4889 break;
4890
4891 default:
4892 BFD_FAIL ();
2a229407 4893 return 0;
461a49ca
DJ		 4894 }
4895 }
4896
48229727
JB		 4897 return size;
4898}
4899
4900/* As above, but don't actually build the stub. Just bump offset so
4901 we know stub section sizes. */
4902
4903static bfd_boolean
4904arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4905 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4906{
4907 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4908 const insn_sequence *template_sequence;
48229727
JB		 4909 int template_size, size;
4910
4911 /* Massage our args to the form they really have. */
4912 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4913
4914 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4915 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4916
d3ce72d0 4917 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4918 &template_size);
4919
0955507f
TP		 4920 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4921 if (stub_entry->stub_template_size)
4922 {
4923 stub_entry->stub_size = size;
4924 stub_entry->stub_template = template_sequence;
4925 stub_entry->stub_template_size = template_size;
4926 }
4927
4928 /* Already accounted for. */
4929 if (stub_entry->stub_offset != (bfd_vma) -1)
4930 return TRUE;
461a49ca 4931
906e58ca
NC		 4932 size = (size + 7) & ~7;
4933 stub_entry->stub_sec->size += size;
461a49ca 4934
906e58ca
NC		 4935 return TRUE;
4936}
4937
4938/* External entry points for sizing and building linker stubs. */
4939
4940/* Set up various things so that we can make a list of input sections
4941 for each output section included in the link. Returns -1 on error,
4942 0 when no stubs will be needed, and 1 on success. */
4943
4944int
4945elf32_arm_setup_section_lists (bfd *output_bfd,
4946 struct bfd_link_info *info)
4947{
4948 bfd *input_bfd;
4949 unsigned int bfd_count;
7292b3ac 4950 unsigned int top_id, top_index;
906e58ca
NC		 4951 asection *section;
4952 asection **input_list, **list;
4953 bfd_size_type amt;
4954 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4955
4dfe6ac6
NC		 4956 if (htab == NULL)
4957 return 0;
906e58ca
NC		 4958 if (! is_elf_hash_table (htab))
4959 return 0;
4960
4961 /* Count the number of input BFDs and find the top input section id. */
4962 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4963 input_bfd != NULL;
c72f2fb2 4964 input_bfd = input_bfd->link.next)
906e58ca
NC		 4965 {
4966 bfd_count += 1;
4967 for (section = input_bfd->sections;
4968 section != NULL;
4969 section = section->next)
4970 {
4971 if (top_id < section->id)
4972 top_id = section->id;
4973 }
4974 }
4975 htab->bfd_count = bfd_count;
4976
4977 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4978 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4979 if (htab->stub_group == NULL)
4980 return -1;
fe33d2fa 4981 htab->top_id = top_id;
906e58ca
NC		 4982
4983 /* We can't use output_bfd->section_count here to find the top output
4984 section index as some sections may have been removed, and
4985 _bfd_strip_section_from_output doesn't renumber the indices. */
4986 for (section = output_bfd->sections, top_index = 0;
4987 section != NULL;
4988 section = section->next)
4989 {
4990 if (top_index < section->index)
4991 top_index = section->index;
4992 }
4993
4994 htab->top_index = top_index;
4995 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4996 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4997 htab->input_list = input_list;
4998 if (input_list == NULL)
4999 return -1;
5000
5001 /* For sections we aren't interested in, mark their entries with a
5002 value we can check later. */
5003 list = input_list + top_index;
5004 do
5005 *list = bfd_abs_section_ptr;
5006 while (list-- != input_list);
5007
5008 for (section = output_bfd->sections;
5009 section != NULL;
5010 section = section->next)
5011 {
5012 if ((section->flags & SEC_CODE) != 0)
5013 input_list[section->index] = NULL;
5014 }
5015
5016 return 1;
5017}
5018
5019/* The linker repeatedly calls this function for each input section,
5020 in the order that input sections are linked into output sections.
5021 Build lists of input sections to determine groupings between which
5022 we may insert linker stubs. */
5023
5024void
5025elf32_arm_next_input_section (struct bfd_link_info *info,
5026 asection *isec)
5027{
5028 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5029
4dfe6ac6
NC		 5030 if (htab == NULL)
5031 return;
5032
906e58ca
NC		 5033 if (isec->output_section->index <= htab->top_index)
5034 {
5035 asection **list = htab->input_list + isec->output_section->index;
5036
a7470592 5037 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5038 {
5039 /* Steal the link_sec pointer for our list. */
5040#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5041 /* This happens to make the list in reverse order,
07d72278 5042 which we reverse later. */
906e58ca
NC		 5043 PREV_SEC (isec) = *list;
5044 *list = isec;
5045 }
5046 }
5047}
5048
5049/* See whether we can group stub sections together. Grouping stub
5050 sections may result in fewer stubs. More importantly, we need to
07d72278 5051 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5052 .fini output sections respectively, because glibc splits the
5053 _init and _fini functions into multiple parts. Putting a stub in
5054 the middle of a function is not a good idea. */
5055
5056static void
5057group_sections (struct elf32_arm_link_hash_table *htab,
5058 bfd_size_type stub_group_size,
07d72278 5059 bfd_boolean stubs_always_after_branch)
906e58ca 5060{
07d72278 5061 asection **list = htab->input_list;
906e58ca
NC		 5062
5063 do
5064 {
5065 asection *tail = *list;
07d72278 5066 asection *head;
906e58ca
NC		 5067
5068 if (tail == bfd_abs_section_ptr)
5069 continue;
5070
07d72278
DJ		 5071 /* Reverse the list: we must avoid placing stubs at the
5072 beginning of the section because the beginning of the text
5073 section may be required for an interrupt vector in bare metal
5074 code. */
5075#define NEXT_SEC PREV_SEC
e780aef2
CL		 5076 head = NULL;
5077 while (tail != NULL)
99059e56
RM		 5078 {
5079 /* Pop from tail. */
5080 asection *item = tail;
5081 tail = PREV_SEC (item);
e780aef2 5082
99059e56
RM		 5083 /* Push on head. */
5084 NEXT_SEC (item) = head;
5085 head = item;
5086 }
07d72278
DJ		 5087
5088 while (head != NULL)
906e58ca
NC		 5089 {
5090 asection *curr;
07d72278 5091 asection *next;
e780aef2
CL		 5092 bfd_vma stub_group_start = head->output_offset;
5093 bfd_vma end_of_next;
906e58ca 5094
07d72278 5095 curr = head;
e780aef2 5096 while (NEXT_SEC (curr) != NULL)
8cd931b7 5097 {
e780aef2
CL		 5098 next = NEXT_SEC (curr);
5099 end_of_next = next->output_offset + next->size;
5100 if (end_of_next - stub_group_start >= stub_group_size)
5101 /* End of NEXT is too far from start, so stop. */
8cd931b7 5102 break;
e780aef2
CL		 5103 /* Add NEXT to the group. */
5104 curr = next;
8cd931b7 5105 }
906e58ca 5106
07d72278 5107 /* OK, the size from the start to the start of CURR is less
906e58ca 5108 than stub_group_size and thus can be handled by one stub
07d72278 5109 section. (Or the head section is itself larger than
906e58ca
NC		 5110 stub_group_size, in which case we may be toast.)
5111 We should really be keeping track of the total size of
5112 stubs added here, as stubs contribute to the final output
7fb9f789 5113 section size. */
906e58ca
NC		 5114 do
5115 {
07d72278 5116 next = NEXT_SEC (head);
906e58ca 5117 /* Set up this stub group. */
07d72278 5118 htab->stub_group[head->id].link_sec = curr;
906e58ca 5119 }
07d72278 5120 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5121
5122 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5123 bytes after the stub section can be handled by it too. */
5124 if (!stubs_always_after_branch)
906e58ca 5125 {
e780aef2
CL		 5126 stub_group_start = curr->output_offset + curr->size;
5127
8cd931b7 5128 while (next != NULL)
906e58ca 5129 {
e780aef2
CL		 5130 end_of_next = next->output_offset + next->size;
5131 if (end_of_next - stub_group_start >= stub_group_size)
5132 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5133 break;
e780aef2 5134 /* Add NEXT to the stub group. */
07d72278
DJ		 5135 head = next;
5136 next = NEXT_SEC (head);
5137 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5138 }
5139 }
07d72278 5140 head = next;
906e58ca
NC		 5141 }
5142 }
07d72278 5143 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5144
5145 free (htab->input_list);
5146#undef PREV_SEC
07d72278 5147#undef NEXT_SEC
906e58ca
NC		 5148}
5149
48229727
JB		 5150/* Comparison function for sorting/searching relocations relating to Cortex-A8
5151 erratum fix. */
5152
5153static int
5154a8_reloc_compare (const void *a, const void *b)
5155{
21d799b5
NC		 5156 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5157 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5158
5159 if (ra->from < rb->from)
5160 return -1;
5161 else if (ra->from > rb->from)
5162 return 1;
5163 else
5164 return 0;
5165}
5166
5167static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5168 const char *, char **);
5169
5170/* Helper function to scan code for sequences which might trigger the Cortex-A8
5171 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5172 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5173 otherwise. */
5174
81694485
NC		 5175static bfd_boolean
5176cortex_a8_erratum_scan (bfd *input_bfd,
5177 struct bfd_link_info *info,
48229727
JB		 5178 struct a8_erratum_fix **a8_fixes_p,
5179 unsigned int *num_a8_fixes_p,
5180 unsigned int *a8_fix_table_size_p,
5181 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5182 unsigned int num_a8_relocs,
5183 unsigned prev_num_a8_fixes,
5184 bfd_boolean *stub_changed_p)
48229727
JB		 5185{
5186 asection *section;
5187 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5188 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5189 unsigned int num_a8_fixes = *num_a8_fixes_p;
5190 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5191
4dfe6ac6
NC		 5192 if (htab == NULL)
5193 return FALSE;
5194
48229727
JB		 5195 for (section = input_bfd->sections;
5196 section != NULL;
5197 section = section->next)
5198 {
5199 bfd_byte *contents = NULL;
5200 struct _arm_elf_section_data *sec_data;
5201 unsigned int span;
5202 bfd_vma base_vma;
5203
5204 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5205 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5206 || (section->flags & SEC_EXCLUDE) != 0
5207 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5208 || (section->output_section == bfd_abs_section_ptr))
5209 continue;
48229727
JB		 5210
5211 base_vma = section->output_section->vma + section->output_offset;
5212
5213 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5214 contents = elf_section_data (section)->this_hdr.contents;
48229727 5215 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5216 return TRUE;
48229727
JB		 5217
5218 sec_data = elf32_arm_section_data (section);
5219
5220 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5221 {
5222 unsigned int span_start = sec_data->map[span].vma;
5223 unsigned int span_end = (span == sec_data->mapcount - 1)
5224 ? section->size : sec_data->map[span + 1].vma;
5225 unsigned int i;
5226 char span_type = sec_data->map[span].type;
5227 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5228
5229 if (span_type != 't')
5230 continue;
5231
5232 /* Span is entirely within a single 4KB region: skip scanning. */
5233 if (((base_vma + span_start) & ~0xfff)
48229727 5234 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5235 continue;
5236
5237 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5238
5239 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5240 * The branch target is in the same 4KB region as the
5241 first half of the branch.
5242 * The instruction before the branch is a 32-bit
5243 length non-branch instruction. */
5244 for (i = span_start; i < span_end;)
5245 {
5246 unsigned int insn = bfd_getl16 (&contents[i]);
5247 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5248 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5249
99059e56
RM		 5250 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5251 insn_32bit = TRUE;
48229727
JB		 5252
5253 if (insn_32bit)
99059e56
RM		 5254 {
5255 /* Load the rest of the insn (in manual-friendly order). */
5256 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5257
5258 /* Encoding T4: B<c>.W. */
5259 is_b = (insn & 0xf800d000) == 0xf0009000;
5260 /* Encoding T1: BL<c>.W. */
5261 is_bl = (insn & 0xf800d000) == 0xf000d000;
5262 /* Encoding T2: BLX<c>.W. */
5263 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5264 /* Encoding T3: B<c>.W (not permitted in IT block). */
5265 is_bcc = (insn & 0xf800d000) == 0xf0008000
5266 && (insn & 0x07f00000) != 0x03800000;
5267 }
5268
5269 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5270
99059e56 5271 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5272 && insn_32bit
5273 && is_32bit_branch
5274 && last_was_32bit
5275 && ! last_was_branch)
99059e56
RM		 5276 {
5277 bfd_signed_vma offset = 0;
5278 bfd_boolean force_target_arm = FALSE;
48229727 5279 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5280 bfd_vma target;
5281 enum elf32_arm_stub_type stub_type = arm_stub_none;
5282 struct a8_erratum_reloc key, *found;
5283 bfd_boolean use_plt = FALSE;
48229727 5284
99059e56
RM		 5285 key.from = base_vma + i;
5286 found = (struct a8_erratum_reloc *)
5287 bsearch (&key, a8_relocs, num_a8_relocs,
5288 sizeof (struct a8_erratum_reloc),
5289 &a8_reloc_compare);
48229727
JB		 5290
5291 if (found)
5292 {
5293 char *error_message = NULL;
5294 struct elf_link_hash_entry *entry;
5295
5296 /* We don't care about the error returned from this
99059e56 5297 function, only if there is glue or not. */
48229727
JB		 5298 entry = find_thumb_glue (info, found->sym_name,
5299 &error_message);
5300
5301 if (entry)
5302 found->non_a8_stub = TRUE;
5303
92750f34 5304 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5305 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5306 && found->hash->root.plt.offset != (bfd_vma) -1)
5307 use_plt = TRUE;
5308
5309 if (found->r_type == R_ARM_THM_CALL)
5310 {
35fc36a8
RS		 5311 if (found->branch_type == ST_BRANCH_TO_ARM
5312 || use_plt)
92750f34
DJ		 5313 force_target_arm = TRUE;
5314 else
5315 force_target_thumb = TRUE;
5316 }
48229727
JB		 5317 }
5318
99059e56 5319 /* Check if we have an offending branch instruction. */
48229727
JB		 5320
5321 if (found && found->non_a8_stub)
5322 /* We've already made a stub for this instruction, e.g.
5323 it's a long branch or a Thumb->ARM stub. Assume that
5324 stub will suffice to work around the A8 erratum (see
5325 setting of always_after_branch above). */
5326 ;
99059e56
RM		 5327 else if (is_bcc)
5328 {
5329 offset = (insn & 0x7ff) << 1;
5330 offset |= (insn & 0x3f0000) >> 4;
5331 offset |= (insn & 0x2000) ? 0x40000 : 0;
5332 offset |= (insn & 0x800) ? 0x80000 : 0;
5333 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5334 if (offset & 0x100000)
5335 offset |= ~ ((bfd_signed_vma) 0xfffff);
5336 stub_type = arm_stub_a8_veneer_b_cond;
5337 }
5338 else if (is_b || is_bl || is_blx)
5339 {
5340 int s = (insn & 0x4000000) != 0;
5341 int j1 = (insn & 0x2000) != 0;
5342 int j2 = (insn & 0x800) != 0;
5343 int i1 = !(j1 ^ s);
5344 int i2 = !(j2 ^ s);
5345
5346 offset = (insn & 0x7ff) << 1;
5347 offset |= (insn & 0x3ff0000) >> 4;
5348 offset |= i2 << 22;
5349 offset |= i1 << 23;
5350 offset |= s << 24;
5351 if (offset & 0x1000000)
5352 offset |= ~ ((bfd_signed_vma) 0xffffff);
5353
5354 if (is_blx)
5355 offset &= ~ ((bfd_signed_vma) 3);
5356
5357 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5358 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5359 }
5360
5361 if (stub_type != arm_stub_none)
5362 {
5363 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5364
5365 /* The original instruction is a BL, but the target is
99059e56 5366 an ARM instruction. If we were not making a stub,
48229727
JB		 5367 the BL would have been converted to a BLX. Use the
5368 BLX stub instead in that case. */
5369 if (htab->use_blx && force_target_arm
5370 && stub_type == arm_stub_a8_veneer_bl)
5371 {
5372 stub_type = arm_stub_a8_veneer_blx;
5373 is_blx = TRUE;
5374 is_bl = FALSE;
5375 }
5376 /* Conversely, if the original instruction was
5377 BLX but the target is Thumb mode, use the BL
5378 stub. */
5379 else if (force_target_thumb
5380 && stub_type == arm_stub_a8_veneer_blx)
5381 {
5382 stub_type = arm_stub_a8_veneer_bl;
5383 is_blx = FALSE;
5384 is_bl = TRUE;
5385 }
5386
99059e56
RM		 5387 if (is_blx)
5388 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5389
99059e56
RM		 5390 /* If we found a relocation, use the proper destination,
5391 not the offset in the (unrelocated) instruction.
48229727
JB		 5392 Note this is always done if we switched the stub type
5393 above. */
99059e56
RM		 5394 if (found)
5395 offset =
81694485 5396 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5397
99059e56
RM		 5398 /* If the stub will use a Thumb-mode branch to a
5399 PLT target, redirect it to the preceding Thumb
5400 entry point. */
5401 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5402 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5403
99059e56 5404 target = pc_for_insn + offset;
48229727 5405
99059e56
RM		 5406 /* The BLX stub is ARM-mode code. Adjust the offset to
5407 take the different PC value (+8 instead of +4) into
48229727 5408 account. */
99059e56
RM		 5409 if (stub_type == arm_stub_a8_veneer_blx)
5410 offset += 4;
5411
5412 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5413 {
5414 char *stub_name = NULL;
5415
5416 if (num_a8_fixes == a8_fix_table_size)
5417 {
5418 a8_fix_table_size *= 2;
5419 a8_fixes = (struct a8_erratum_fix *)
5420 bfd_realloc (a8_fixes,
5421 sizeof (struct a8_erratum_fix)
5422 * a8_fix_table_size);
5423 }
48229727 5424
eb7c4339
NS		 5425 if (num_a8_fixes < prev_num_a8_fixes)
5426 {
5427 /* If we're doing a subsequent scan,
5428 check if we've found the same fix as
5429 before, and try and reuse the stub
5430 name. */
5431 stub_name = a8_fixes[num_a8_fixes].stub_name;
5432 if ((a8_fixes[num_a8_fixes].section != section)
5433 || (a8_fixes[num_a8_fixes].offset != i))
5434 {
5435 free (stub_name);
5436 stub_name = NULL;
5437 *stub_changed_p = TRUE;
5438 }
5439 }
5440
5441 if (!stub_name)
5442 {
21d799b5 5443 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5444 if (stub_name != NULL)
5445 sprintf (stub_name, "%x:%x", section->id, i);
5446 }
48229727 5447
99059e56
RM		 5448 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5449 a8_fixes[num_a8_fixes].section = section;
5450 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5451 a8_fixes[num_a8_fixes].target_offset =
5452 target - base_vma;
99059e56
RM		 5453 a8_fixes[num_a8_fixes].orig_insn = insn;
5454 a8_fixes[num_a8_fixes].stub_name = stub_name;
5455 a8_fixes[num_a8_fixes].stub_type = stub_type;
5456 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5457 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5458
99059e56
RM		 5459 num_a8_fixes++;
5460 }
5461 }
5462 }
48229727 5463
99059e56
RM		 5464 i += insn_32bit ? 4 : 2;
5465 last_was_32bit = insn_32bit;
48229727 5466 last_was_branch = is_32bit_branch;
99059e56
RM		 5467 }
5468 }
48229727
JB		 5469
5470 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5471 free (contents);
48229727 5472 }
fe33d2fa 5473
48229727
JB		 5474 *a8_fixes_p = a8_fixes;
5475 *num_a8_fixes_p = num_a8_fixes;
5476 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5477
81694485 5478 return FALSE;
48229727
JB		 5479}
5480
b715f643
TP		 5481/* Create or update a stub entry depending on whether the stub can already be
5482 found in HTAB. The stub is identified by:
5483 - its type STUB_TYPE
5484 - its source branch (note that several can share the same stub) whose
5485 section and relocation (if any) are given by SECTION and IRELA
5486 respectively
5487 - its target symbol whose input section, hash, name, value and branch type
5488 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5489 respectively
5490
5491 If found, the value of the stub's target symbol is updated from SYM_VALUE
5492 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5493 TRUE and the stub entry is initialized.
5494
0955507f
TP		 5495 Returns the stub that was created or updated, or NULL if an error
5496 occurred. */
b715f643 5497
0955507f 5498static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5499elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5500 enum elf32_arm_stub_type stub_type, asection *section,
5501 Elf_Internal_Rela *irela, asection *sym_sec,
5502 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5503 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5504 bfd_boolean *new_stub)
5505{
5506 const asection *id_sec;
5507 char *stub_name;
5508 struct elf32_arm_stub_hash_entry *stub_entry;
5509 unsigned int r_type;
4f4faa4d 5510 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5511
5512 BFD_ASSERT (stub_type != arm_stub_none);
5513 *new_stub = FALSE;
5514
4f4faa4d
TP		 5515 if (sym_claimed)
5516 stub_name = sym_name;
5517 else
5518 {
5519 BFD_ASSERT (irela);
5520 BFD_ASSERT (section);
c2abbbeb 5521 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5522
4f4faa4d
TP		 5523 /* Support for grouping stub sections. */
5524 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5525
4f4faa4d
TP		 5526 /* Get the name of this stub. */
5527 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5528 stub_type);
5529 if (!stub_name)
0955507f 5530 return NULL;
4f4faa4d 5531 }
b715f643
TP		 5532
5533 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5534 FALSE);
5535 /* The proper stub has already been created, just update its value. */
5536 if (stub_entry != NULL)
5537 {
4f4faa4d
TP		 5538 if (!sym_claimed)
5539 free (stub_name);
b715f643 5540 stub_entry->target_value = sym_value;
0955507f 5541 return stub_entry;
b715f643
TP		 5542 }
5543
daa4adae 5544 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5545 if (stub_entry == NULL)
5546 {
4f4faa4d
TP		 5547 if (!sym_claimed)
5548 free (stub_name);
0955507f 5549 return NULL;
b715f643
TP		 5550 }
5551
5552 stub_entry->target_value = sym_value;
5553 stub_entry->target_section = sym_sec;
5554 stub_entry->stub_type = stub_type;
5555 stub_entry->h = hash;
5556 stub_entry->branch_type = branch_type;
5557
4f4faa4d
TP		 5558 if (sym_claimed)
5559 stub_entry->output_name = sym_name;
5560 else
b715f643 5561 {
4f4faa4d
TP		 5562 if (sym_name == NULL)
5563 sym_name = "unnamed";
5564 stub_entry->output_name = (char *)
5565 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5566 + strlen (sym_name));
5567 if (stub_entry->output_name == NULL)
5568 {
5569 free (stub_name);
0955507f 5570 return NULL;
4f4faa4d 5571 }
b715f643 5572
4f4faa4d
TP		 5573 /* For historical reasons, use the existing names for ARM-to-Thumb and
5574 Thumb-to-ARM stubs. */
5575 r_type = ELF32_R_TYPE (irela->r_info);
5576 if ((r_type == (unsigned int) R_ARM_THM_CALL
5577 || r_type == (unsigned int) R_ARM_THM_JUMP24
5578 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5579 && branch_type == ST_BRANCH_TO_ARM)
5580 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5581 else if ((r_type == (unsigned int) R_ARM_CALL
5582 || r_type == (unsigned int) R_ARM_JUMP24)
5583 && branch_type == ST_BRANCH_TO_THUMB)
5584 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5585 else
5586 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5587 }
b715f643
TP		 5588
5589 *new_stub = TRUE;
0955507f 5590 return stub_entry;
b715f643
TP		 5591}
5592
4ba2ef8f
TP		 5593/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5594 gateway veneer to transition from non secure to secure state and create them
5595 accordingly.
5596
5597 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5598 defines the conditions that govern Secure Gateway veneer creation for a
5599 given symbol <SYM> as follows:
5600 - it has function type
5601 - it has non local binding
5602 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5603 same type, binding and value as <SYM> (called normal symbol).
5604 An entry function can handle secure state transition itself in which case
5605 its special symbol would have a different value from the normal symbol.
5606
5607 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5608 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5609 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5610 created.
4ba2ef8f 5611
0955507f 5612 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5613
5614static bfd_boolean
5615cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5616 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5617 int *cmse_stub_created)
4ba2ef8f
TP		 5618{
5619 const struct elf_backend_data *bed;
5620 Elf_Internal_Shdr *symtab_hdr;
5621 unsigned i, j, sym_count, ext_start;
5622 Elf_Internal_Sym *cmse_sym, *local_syms;
5623 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5624 enum arm_st_branch_type branch_type;
5625 char *sym_name, *lsym_name;
5626 bfd_vma sym_value;
5627 asection *section;
0955507f
TP		 5628 struct elf32_arm_stub_hash_entry *stub_entry;
5629 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5630
5631 bed = get_elf_backend_data (input_bfd);
5632 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5633 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5634 ext_start = symtab_hdr->sh_info;
5635 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5636 && out_attr[Tag_CPU_arch_profile].i == 'M');
5637
5638 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5639 if (local_syms == NULL)
5640 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5641 symtab_hdr->sh_info, 0, NULL, NULL,
5642 NULL);
5643 if (symtab_hdr->sh_info && local_syms == NULL)
5644 return FALSE;
5645
5646 /* Scan symbols. */
5647 for (i = 0; i < sym_count; i++)
5648 {
5649 cmse_invalid = FALSE;
5650
5651 if (i < ext_start)
5652 {
5653 cmse_sym = &local_syms[i];
5654 /* Not a special symbol. */
5655 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5656 continue;
5657 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5658 symtab_hdr->sh_link,
5659 cmse_sym->st_name);
5660 /* Special symbol with local binding. */
5661 cmse_invalid = TRUE;
5662 }
5663 else
5664 {
5665 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5666 sym_name = (char *) cmse_hash->root.root.root.string;
5667
5668 /* Not a special symbol. */
5669 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5670 continue;
5671
5672 /* Special symbol has incorrect binding or type. */
5673 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5674 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5675 || cmse_hash->root.type != STT_FUNC)
5676 cmse_invalid = TRUE;
5677 }
5678
5679 if (!is_v8m)
5680 {
4eca0228
AM		 5681 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5682 "ARMv8-M architecture or later."),
5683 input_bfd, sym_name);
4ba2ef8f
TP		 5684 is_v8m = TRUE; /* Avoid multiple warning. */
5685 ret = FALSE;
5686 }
5687
5688 if (cmse_invalid)
5689 {
4eca0228
AM		 5690 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5691 input_bfd, sym_name);
5692 _bfd_error_handler (_("It must be a global or weak function "
5693 "symbol."));
4ba2ef8f
TP		 5694 ret = FALSE;
5695 if (i < ext_start)
5696 continue;
5697 }
5698
5699 sym_name += strlen (CMSE_PREFIX);
5700 hash = (struct elf32_arm_link_hash_entry *)
5701 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5702
5703 /* No associated normal symbol or it is neither global nor weak. */
5704 if (!hash
5705 || (hash->root.root.type != bfd_link_hash_defined
5706 && hash->root.root.type != bfd_link_hash_defweak)
5707 || hash->root.type != STT_FUNC)
5708 {
5709 /* Initialize here to avoid warning about use of possibly
5710 uninitialized variable. */
5711 j = 0;
5712
5713 if (!hash)
5714 {
5715 /* Searching for a normal symbol with local binding. */
5716 for (; j < ext_start; j++)
5717 {
5718 lsym_name =
5719 bfd_elf_string_from_elf_section (input_bfd,
5720 symtab_hdr->sh_link,
5721 local_syms[j].st_name);
5722 if (!strcmp (sym_name, lsym_name))
5723 break;
5724 }
5725 }
5726
5727 if (hash || j < ext_start)
5728 {
4eca0228 5729 _bfd_error_handler
4ba2ef8f 5730 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5731 _bfd_error_handler
4ba2ef8f
TP		 5732 (_("It must be a global or weak function symbol."));
5733 }
5734 else
4eca0228 5735 _bfd_error_handler
4ba2ef8f
TP		 5736 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5737 ret = FALSE;
5738 if (!hash)
5739 continue;
5740 }
5741
5742 sym_value = hash->root.root.u.def.value;
5743 section = hash->root.root.u.def.section;
5744
5745 if (cmse_hash->root.root.u.def.section != section)
5746 {
4eca0228 5747 _bfd_error_handler
4ba2ef8f
TP		 5748 (_("%B: `%s' and its special symbol are in different sections."),
5749 input_bfd, sym_name);
5750 ret = FALSE;
5751 }
5752 if (cmse_hash->root.root.u.def.value != sym_value)
5753 continue; /* Ignore: could be an entry function starting with SG. */
5754
5755 /* If this section is a link-once section that will be discarded, then
5756 don't create any stubs. */
5757 if (section->output_section == NULL)
5758 {
4eca0228 5759 _bfd_error_handler
4ba2ef8f
TP		 5760 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5761 continue;
5762 }
5763
5764 if (hash->root.size == 0)
5765 {
4eca0228 5766 _bfd_error_handler
4ba2ef8f
TP		 5767 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5768 ret = FALSE;
5769 }
5770
5771 if (!ret)
5772 continue;
5773 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5774 stub_entry
4ba2ef8f
TP		 5775 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5776 NULL, NULL, section, hash, sym_name,
5777 sym_value, branch_type, &new_stub);
5778
0955507f 5779 if (stub_entry == NULL)
4ba2ef8f
TP		 5780 ret = FALSE;
5781 else
5782 {
5783 BFD_ASSERT (new_stub);
0955507f 5784 (*cmse_stub_created)++;
4ba2ef8f
TP		 5785 }
5786 }
5787
5788 if (!symtab_hdr->contents)
5789 free (local_syms);
5790 return ret;
5791}
5792
0955507f
TP		 5793/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5794 code entry function, ie can be called from non secure code without using a
5795 veneer. */
5796
5797static bfd_boolean
5798cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5799{
42484486 5800 bfd_byte contents[4];
0955507f
TP		 5801 uint32_t first_insn;
5802 asection *section;
5803 file_ptr offset;
5804 bfd *abfd;
5805
5806 /* Defined symbol of function type. */
5807 if (hash->root.root.type != bfd_link_hash_defined
5808 && hash->root.root.type != bfd_link_hash_defweak)
5809 return FALSE;
5810 if (hash->root.type != STT_FUNC)
5811 return FALSE;
5812
5813 /* Read first instruction. */
5814 section = hash->root.root.u.def.section;
5815 abfd = section->owner;
5816 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5817 if (!bfd_get_section_contents (abfd, section, contents, offset,
5818 sizeof (contents)))
0955507f
TP		 5819 return FALSE;
5820
42484486
TP		 5821 first_insn = bfd_get_32 (abfd, contents);
5822
5823 /* Starts by SG instruction. */
0955507f
TP		 5824 return first_insn == 0xe97fe97f;
5825}
5826
5827/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5828 secure gateway veneers (ie. the veneers was not in the input import library)
5829 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5830
5831static bfd_boolean
5832arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5833{
5834 struct elf32_arm_stub_hash_entry *stub_entry;
5835 struct bfd_link_info *info;
5836
5837 /* Massage our args to the form they really have. */
5838 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5839 info = (struct bfd_link_info *) gen_info;
5840
5841 if (info->out_implib_bfd)
5842 return TRUE;
5843
5844 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5845 return TRUE;
5846
5847 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5848 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5849
5850 return TRUE;
5851}
5852
5853/* Set offset of each secure gateway veneers so that its address remain
5854 identical to the one in the input import library referred by
5855 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5856 (present in input import library but absent from the executable being
5857 linked) or if new veneers appeared and there is no output import library
5858 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5859 number of secure gateway veneers found in the input import library.
5860
5861 The function returns whether an error occurred. If no error occurred,
5862 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5863 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5864 veneer observed set for new veneers to be layed out after. */
5865
5866static bfd_boolean
5867set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5868 struct elf32_arm_link_hash_table *htab,
5869 int *cmse_stub_created)
5870{
5871 long symsize;
5872 char *sym_name;
5873 flagword flags;
5874 long i, symcount;
5875 bfd *in_implib_bfd;
5876 asection *stub_out_sec;
5877 bfd_boolean ret = TRUE;
5878 Elf_Internal_Sym *intsym;
5879 const char *out_sec_name;
5880 bfd_size_type cmse_stub_size;
5881 asymbol **sympp = NULL, *sym;
5882 struct elf32_arm_link_hash_entry *hash;
5883 const insn_sequence *cmse_stub_template;
5884 struct elf32_arm_stub_hash_entry *stub_entry;
5885 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5886 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5887 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5888
5889 /* No input secure gateway import library. */
5890 if (!htab->in_implib_bfd)
5891 return TRUE;
5892
5893 in_implib_bfd = htab->in_implib_bfd;
5894 if (!htab->cmse_implib)
5895 {
4eca0228
AM		 5896 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5897 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5898 return FALSE;
5899 }
5900
5901 /* Get symbol table size. */
5902 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5903 if (symsize < 0)
5904 return FALSE;
5905
5906 /* Read in the input secure gateway import library's symbol table. */
5907 sympp = (asymbol **) xmalloc (symsize);
5908 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5909 if (symcount < 0)
5910 {
5911 ret = FALSE;
5912 goto free_sym_buf;
5913 }
5914
5915 htab->new_cmse_stub_offset = 0;
5916 cmse_stub_size =
5917 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5918 &cmse_stub_template,
5919 &cmse_stub_template_size);
5920 out_sec_name =
5921 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5922 stub_out_sec =
5923 bfd_get_section_by_name (htab->obfd, out_sec_name);
5924 if (stub_out_sec != NULL)
5925 cmse_stub_sec_vma = stub_out_sec->vma;
5926
5927 /* Set addresses of veneers mentionned in input secure gateway import
5928 library's symbol table. */
5929 for (i = 0; i < symcount; i++)
5930 {
5931 sym = sympp[i];
5932 flags = sym->flags;
5933 sym_name = (char *) bfd_asymbol_name (sym);
5934 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5935
5936 if (sym->section != bfd_abs_section_ptr
5937 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5938 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5939 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5940 != ST_BRANCH_TO_THUMB))
5941 {
4eca0228
AM		 5942 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5943 in_implib_bfd, sym_name);
5944 _bfd_error_handler (_("Symbol should be absolute, global and "
5945 "refer to Thumb functions."));
0955507f
TP		 5946 ret = FALSE;
5947 continue;
5948 }
5949
5950 veneer_value = bfd_asymbol_value (sym);
5951 stub_offset = veneer_value - cmse_stub_sec_vma;
5952 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5953 FALSE, FALSE);
5954 hash = (struct elf32_arm_link_hash_entry *)
5955 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5956
5957 /* Stub entry should have been created by cmse_scan or the symbol be of
5958 a secure function callable from non secure code. */
5959 if (!stub_entry && !hash)
5960 {
5961 bfd_boolean new_stub;
5962
4eca0228 5963 _bfd_error_handler
0955507f
TP		 5964 (_("Entry function `%s' disappeared from secure code."), sym_name);
5965 hash = (struct elf32_arm_link_hash_entry *)
5966 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5967 stub_entry
5968 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5969 NULL, NULL, bfd_abs_section_ptr, hash,
5970 sym_name, veneer_value,
5971 ST_BRANCH_TO_THUMB, &new_stub);
5972 if (stub_entry == NULL)
5973 ret = FALSE;
5974 else
5975 {
5976 BFD_ASSERT (new_stub);
5977 new_cmse_stubs_created++;
5978 (*cmse_stub_created)++;
5979 }
5980 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5981 stub_entry->stub_offset = stub_offset;
5982 }
5983 /* Symbol found is not callable from non secure code. */
5984 else if (!stub_entry)
5985 {
5986 if (!cmse_entry_fct_p (hash))
5987 {
4eca0228
AM		 5988 _bfd_error_handler (_("`%s' refers to a non entry function."),
5989 sym_name);
0955507f
TP		 5990 ret = FALSE;
5991 }
5992 continue;
5993 }
5994 else
5995 {
5996 /* Only stubs for SG veneers should have been created. */
5997 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5998
5999 /* Check visibility hasn't changed. */
6000 if (!!(flags & BSF_GLOBAL)
6001 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6002 _bfd_error_handler
0955507f
TP		 6003 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6004 sym_name);
6005
6006 stub_entry->stub_offset = stub_offset;
6007 }
6008
6009 /* Size should match that of a SG veneer. */
6010 if (intsym->st_size != cmse_stub_size)
6011 {
4eca0228
AM		 6012 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6013 in_implib_bfd, sym_name);
0955507f
TP		 6014 ret = FALSE;
6015 }
6016
6017 /* Previous veneer address is before current SG veneer section. */
6018 if (veneer_value < cmse_stub_sec_vma)
6019 {
6020 /* Avoid offset underflow. */
6021 if (stub_entry)
6022 stub_entry->stub_offset = 0;
6023 stub_offset = 0;
6024 ret = FALSE;
6025 }
6026
6027 /* Complain if stub offset not a multiple of stub size. */
6028 if (stub_offset % cmse_stub_size)
6029 {
4eca0228 6030 _bfd_error_handler
0955507f
TP		 6031 (_("Offset of veneer for entry function `%s' not a multiple of "
6032 "its size."), sym_name);
6033 ret = FALSE;
6034 }
6035
6036 if (!ret)
6037 continue;
6038
6039 new_cmse_stubs_created--;
6040 if (veneer_value < cmse_stub_array_start)
6041 cmse_stub_array_start = veneer_value;
6042 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6043 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6044 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6045 }
6046
6047 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6048 {
6049 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6050 _bfd_error_handler
0955507f
TP		 6051 (_("new entry function(s) introduced but no output import library "
6052 "specified:"));
6053 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6054 }
6055
6056 if (cmse_stub_array_start != cmse_stub_sec_vma)
6057 {
4eca0228 6058 _bfd_error_handler
0955507f
TP		 6059 (_("Start address of `%s' is different from previous link."),
6060 out_sec_name);
6061 ret = FALSE;
6062 }
6063
6064free_sym_buf:
6065 free (sympp);
6066 return ret;
6067}
6068
906e58ca
NC		 6069/* Determine and set the size of the stub section for a final link.
6070
6071 The basic idea here is to examine all the relocations looking for
6072 PC-relative calls to a target that is unreachable with a "bl"
6073 instruction. */
6074
6075bfd_boolean
6076elf32_arm_size_stubs (bfd *output_bfd,
6077 bfd *stub_bfd,
6078 struct bfd_link_info *info,
6079 bfd_signed_vma group_size,
7a89b94e 6080 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6081 asection *,
7a89b94e 6082 unsigned int),
906e58ca
NC		 6083 void (*layout_sections_again) (void))
6084{
0955507f 6085 bfd_boolean ret = TRUE;
4ba2ef8f 6086 obj_attribute *out_attr;
0955507f 6087 int cmse_stub_created = 0;
906e58ca 6088 bfd_size_type stub_group_size;
4ba2ef8f 6089 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6090 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6091 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6092 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6093 struct a8_erratum_reloc *a8_relocs = NULL;
6094 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6095
4dfe6ac6
NC		 6096 if (htab == NULL)
6097 return FALSE;
6098
48229727
JB		 6099 if (htab->fix_cortex_a8)
6100 {
21d799b5 6101 a8_fixes = (struct a8_erratum_fix *)
99059e56 6102 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6103 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6104 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6105 }
906e58ca
NC		 6106
6107 /* Propagate mach to stub bfd, because it may not have been
6108 finalized when we created stub_bfd. */
6109 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6110 bfd_get_mach (output_bfd));
6111
6112 /* Stash our params away. */
6113 htab->stub_bfd = stub_bfd;
6114 htab->add_stub_section = add_stub_section;
6115 htab->layout_sections_again = layout_sections_again;
07d72278 6116 stubs_always_after_branch = group_size < 0;
48229727 6117
4ba2ef8f
TP		 6118 out_attr = elf_known_obj_attributes_proc (output_bfd);
6119 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6120
48229727
JB		 6121 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6122 as the first half of a 32-bit branch straddling two 4K pages. This is a
6123 crude way of enforcing that. */
6124 if (htab->fix_cortex_a8)
6125 stubs_always_after_branch = 1;
6126
906e58ca
NC		 6127 if (group_size < 0)
6128 stub_group_size = -group_size;
6129 else
6130 stub_group_size = group_size;
6131
6132 if (stub_group_size == 1)
6133 {
6134 /* Default values. */
6135 /* Thumb branch range is +-4MB has to be used as the default
6136 maximum size (a given section can contain both ARM and Thumb
6137 code, so the worst case has to be taken into account).
6138
6139 This value is 24K less than that, which allows for 2025
6140 12-byte stubs. If we exceed that, then we will fail to link.
6141 The user will have to relink with an explicit group size
6142 option. */
6143 stub_group_size = 4170000;
6144 }
6145
07d72278 6146 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6147
3ae046cc
NS		 6148 /* If we're applying the cortex A8 fix, we need to determine the
6149 program header size now, because we cannot change it later --
6150 that could alter section placements. Notice the A8 erratum fix
6151 ends up requiring the section addresses to remain unchanged
6152 modulo the page size. That's something we cannot represent
6153 inside BFD, and we don't want to force the section alignment to
6154 be the page size. */
6155 if (htab->fix_cortex_a8)
6156 (*htab->layout_sections_again) ();
6157
906e58ca
NC		 6158 while (1)
6159 {
6160 bfd *input_bfd;
6161 unsigned int bfd_indx;
6162 asection *stub_sec;
d7c5bd02 6163 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6164 bfd_boolean stub_changed = FALSE;
6165 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6166
48229727 6167 num_a8_fixes = 0;
906e58ca
NC		 6168 for (input_bfd = info->input_bfds, bfd_indx = 0;
6169 input_bfd != NULL;
c72f2fb2 6170 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6171 {
6172 Elf_Internal_Shdr *symtab_hdr;
6173 asection *section;
6174 Elf_Internal_Sym *local_syms = NULL;
6175
99059e56
RM		 6176 if (!is_arm_elf (input_bfd))
6177 continue;
adbcc655 6178
48229727
JB		 6179 num_a8_relocs = 0;
6180
906e58ca
NC		 6181 /* We'll need the symbol table in a second. */
6182 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6183 if (symtab_hdr->sh_info == 0)
6184 continue;
6185
4ba2ef8f
TP		 6186 /* Limit scan of symbols to object file whose profile is
6187 Microcontroller to not hinder performance in the general case. */
6188 if (m_profile && first_veneer_scan)
6189 {
6190 struct elf_link_hash_entry **sym_hashes;
6191
6192 sym_hashes = elf_sym_hashes (input_bfd);
6193 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6194 &cmse_stub_created))
4ba2ef8f 6195 goto error_ret_free_local;
0955507f
TP		 6196
6197 if (cmse_stub_created != 0)
6198 stub_changed = TRUE;
4ba2ef8f
TP		 6199 }
6200
906e58ca
NC		 6201 /* Walk over each section attached to the input bfd. */
6202 for (section = input_bfd->sections;
6203 section != NULL;
6204 section = section->next)
6205 {
6206 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6207
6208 /* If there aren't any relocs, then there's nothing more
6209 to do. */
6210 if ((section->flags & SEC_RELOC) == 0
6211 || section->reloc_count == 0
6212 || (section->flags & SEC_CODE) == 0)
6213 continue;
6214
6215 /* If this section is a link-once section that will be
6216 discarded, then don't create any stubs. */
6217 if (section->output_section == NULL
6218 || section->output_section->owner != output_bfd)
6219 continue;
6220
6221 /* Get the relocs. */
6222 internal_relocs
6223 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6224 NULL, info->keep_memory);
6225 if (internal_relocs == NULL)
6226 goto error_ret_free_local;
6227
6228 /* Now examine each relocation. */
6229 irela = internal_relocs;
6230 irelaend = irela + section->reloc_count;
6231 for (; irela < irelaend; irela++)
6232 {
6233 unsigned int r_type, r_indx;
906e58ca
NC		 6234 asection *sym_sec;
6235 bfd_vma sym_value;
6236 bfd_vma destination;
6237 struct elf32_arm_link_hash_entry *hash;
7413f23f 6238 const char *sym_name;
34e77a92 6239 unsigned char st_type;
35fc36a8 6240 enum arm_st_branch_type branch_type;
48229727 6241 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6242
6243 r_type = ELF32_R_TYPE (irela->r_info);
6244 r_indx = ELF32_R_SYM (irela->r_info);
6245
6246 if (r_type >= (unsigned int) R_ARM_max)
6247 {
6248 bfd_set_error (bfd_error_bad_value);
6249 error_ret_free_internal:
6250 if (elf_section_data (section)->relocs == NULL)
6251 free (internal_relocs);
15dd01b1
TP		 6252 /* Fall through. */
6253 error_ret_free_local:
6254 if (local_syms != NULL
6255 && (symtab_hdr->contents
6256 != (unsigned char *) local_syms))
6257 free (local_syms);
6258 return FALSE;
906e58ca 6259 }
b38cadfb 6260
0855e32b
NS		 6261 hash = NULL;
6262 if (r_indx >= symtab_hdr->sh_info)
6263 hash = elf32_arm_hash_entry
6264 (elf_sym_hashes (input_bfd)
6265 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6266
0855e32b
NS		 6267 /* Only look for stubs on branch instructions, or
6268 non-relaxed TLSCALL */
906e58ca 6269 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6270 && (r_type != (unsigned int) R_ARM_THM_CALL)
6271 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6272 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6273 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6274 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6275 && (r_type != (unsigned int) R_ARM_PLT32)
6276 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6277 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6278 && r_type == elf32_arm_tls_transition
6279 (info, r_type, &hash->root)
6280 && ((hash ? hash->tls_type
6281 : (elf32_arm_local_got_tls_type
6282 (input_bfd)[r_indx]))
6283 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6284 continue;
6285
6286 /* Now determine the call target, its name, value,
6287 section. */
6288 sym_sec = NULL;
6289 sym_value = 0;
6290 destination = 0;
7413f23f 6291 sym_name = NULL;
b38cadfb 6292
0855e32b
NS		 6293 if (r_type == (unsigned int) R_ARM_TLS_CALL
6294 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6295 {
6296 /* A non-relaxed TLS call. The target is the
6297 plt-resident trampoline and nothing to do
6298 with the symbol. */
6299 BFD_ASSERT (htab->tls_trampoline > 0);
6300 sym_sec = htab->root.splt;
6301 sym_value = htab->tls_trampoline;
6302 hash = 0;
34e77a92 6303 st_type = STT_FUNC;
35fc36a8 6304 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6305 }
6306 else if (!hash)
906e58ca
NC		 6307 {
6308 /* It's a local symbol. */
6309 Elf_Internal_Sym *sym;
906e58ca
NC		 6310
6311 if (local_syms == NULL)
6312 {
6313 local_syms
6314 = (Elf_Internal_Sym *) symtab_hdr->contents;
6315 if (local_syms == NULL)
6316 local_syms
6317 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6318 symtab_hdr->sh_info, 0,
6319 NULL, NULL, NULL);
6320 if (local_syms == NULL)
6321 goto error_ret_free_internal;
6322 }
6323
6324 sym = local_syms + r_indx;
f6d250ce
TS		 6325 if (sym->st_shndx == SHN_UNDEF)
6326 sym_sec = bfd_und_section_ptr;
6327 else if (sym->st_shndx == SHN_ABS)
6328 sym_sec = bfd_abs_section_ptr;
6329 else if (sym->st_shndx == SHN_COMMON)
6330 sym_sec = bfd_com_section_ptr;
6331 else
6332 sym_sec =
6333 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6334
ffcb4889
NS		 6335 if (!sym_sec)
6336 /* This is an undefined symbol. It can never
6a631e86 6337 be resolved. */
ffcb4889 6338 continue;
fe33d2fa 6339
906e58ca
NC		 6340 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6341 sym_value = sym->st_value;
6342 destination = (sym_value + irela->r_addend
6343 + sym_sec->output_offset
6344 + sym_sec->output_section->vma);
34e77a92 6345 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6346 branch_type =
6347 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6348 sym_name
6349 = bfd_elf_string_from_elf_section (input_bfd,
6350 symtab_hdr->sh_link,
6351 sym->st_name);
906e58ca
NC		 6352 }
6353 else
6354 {
6355 /* It's an external symbol. */
906e58ca
NC		 6356 while (hash->root.root.type == bfd_link_hash_indirect
6357 || hash->root.root.type == bfd_link_hash_warning)
6358 hash = ((struct elf32_arm_link_hash_entry *)
6359 hash->root.root.u.i.link);
6360
6361 if (hash->root.root.type == bfd_link_hash_defined
6362 || hash->root.root.type == bfd_link_hash_defweak)
6363 {
6364 sym_sec = hash->root.root.u.def.section;
6365 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6366
6367 struct elf32_arm_link_hash_table *globals =
6368 elf32_arm_hash_table (info);
6369
6370 /* For a destination in a shared library,
6371 use the PLT stub as target address to
6372 decide whether a branch stub is
6373 needed. */
4dfe6ac6 6374 if (globals != NULL
362d30a1 6375 && globals->root.splt != NULL
4dfe6ac6 6376 && hash != NULL
022f8312
CL		 6377 && hash->root.plt.offset != (bfd_vma) -1)
6378 {
362d30a1 6379 sym_sec = globals->root.splt;
022f8312
CL		 6380 sym_value = hash->root.plt.offset;
6381 if (sym_sec->output_section != NULL)
6382 destination = (sym_value
6383 + sym_sec->output_offset
6384 + sym_sec->output_section->vma);
6385 }
6386 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6387 destination = (sym_value + irela->r_addend
6388 + sym_sec->output_offset
6389 + sym_sec->output_section->vma);
6390 }
69c5861e
CL		 6391 else if ((hash->root.root.type == bfd_link_hash_undefined)
6392 || (hash->root.root.type == bfd_link_hash_undefweak))
6393 {
6394 /* For a shared library, use the PLT stub as
6395 target address to decide whether a long
6396 branch stub is needed.
6397 For absolute code, they cannot be handled. */
6398 struct elf32_arm_link_hash_table *globals =
6399 elf32_arm_hash_table (info);
6400
4dfe6ac6 6401 if (globals != NULL
362d30a1 6402 && globals->root.splt != NULL
4dfe6ac6 6403 && hash != NULL
69c5861e
CL		 6404 && hash->root.plt.offset != (bfd_vma) -1)
6405 {
362d30a1 6406 sym_sec = globals->root.splt;
69c5861e
CL		 6407 sym_value = hash->root.plt.offset;
6408 if (sym_sec->output_section != NULL)
6409 destination = (sym_value
6410 + sym_sec->output_offset
6411 + sym_sec->output_section->vma);
6412 }
6413 else
6414 continue;
6415 }
906e58ca
NC		 6416 else
6417 {
6418 bfd_set_error (bfd_error_bad_value);
6419 goto error_ret_free_internal;
6420 }
34e77a92 6421 st_type = hash->root.type;
39d911fc
TP		 6422 branch_type =
6423 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6424 sym_name = hash->root.root.root.string;
906e58ca
NC		 6425 }
6426
48229727 6427 do
7413f23f 6428 {
b715f643 6429 bfd_boolean new_stub;
0955507f 6430 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6431
48229727
JB		 6432 /* Determine what (if any) linker stub is needed. */
6433 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6434 st_type, &branch_type,
6435 hash, destination, sym_sec,
48229727
JB		 6436 input_bfd, sym_name);
6437 if (stub_type == arm_stub_none)
6438 break;
6439
48229727
JB		 6440 /* We've either created a stub for this reloc already,
6441 or we are about to. */
0955507f 6442 stub_entry =
b715f643
TP		 6443 elf32_arm_create_stub (htab, stub_type, section, irela,
6444 sym_sec, hash,
6445 (char *) sym_name, sym_value,
6446 branch_type, &new_stub);
7413f23f 6447
0955507f 6448 created_stub = stub_entry != NULL;
b715f643
TP		 6449 if (!created_stub)
6450 goto error_ret_free_internal;
6451 else if (!new_stub)
6452 break;
99059e56 6453 else
b715f643 6454 stub_changed = TRUE;
99059e56
RM		 6455 }
6456 while (0);
6457
6458 /* Look for relocations which might trigger Cortex-A8
6459 erratum. */
6460 if (htab->fix_cortex_a8
6461 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6462 || r_type == (unsigned int) R_ARM_THM_JUMP19
6463 || r_type == (unsigned int) R_ARM_THM_CALL
6464 || r_type == (unsigned int) R_ARM_THM_XPC22))
6465 {
6466 bfd_vma from = section->output_section->vma
6467 + section->output_offset
6468 + irela->r_offset;
6469
6470 if ((from & 0xfff) == 0xffe)
6471 {
6472 /* Found a candidate. Note we haven't checked the
6473 destination is within 4K here: if we do so (and
6474 don't create an entry in a8_relocs) we can't tell
6475 that a branch should have been relocated when
6476 scanning later. */
6477 if (num_a8_relocs == a8_reloc_table_size)
6478 {
6479 a8_reloc_table_size *= 2;
6480 a8_relocs = (struct a8_erratum_reloc *)
6481 bfd_realloc (a8_relocs,
6482 sizeof (struct a8_erratum_reloc)
6483 * a8_reloc_table_size);
6484 }
6485
6486 a8_relocs[num_a8_relocs].from = from;
6487 a8_relocs[num_a8_relocs].destination = destination;
6488 a8_relocs[num_a8_relocs].r_type = r_type;
6489 a8_relocs[num_a8_relocs].branch_type = branch_type;
6490 a8_relocs[num_a8_relocs].sym_name = sym_name;
6491 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6492 a8_relocs[num_a8_relocs].hash = hash;
6493
6494 num_a8_relocs++;
6495 }
6496 }
906e58ca
NC		 6497 }
6498
99059e56
RM		 6499 /* We're done with the internal relocs, free them. */
6500 if (elf_section_data (section)->relocs == NULL)
6501 free (internal_relocs);
6502 }
48229727 6503
99059e56 6504 if (htab->fix_cortex_a8)
48229727 6505 {
99059e56
RM		 6506 /* Sort relocs which might apply to Cortex-A8 erratum. */
6507 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6508 sizeof (struct a8_erratum_reloc),
99059e56 6509 &a8_reloc_compare);
48229727 6510
99059e56
RM		 6511 /* Scan for branches which might trigger Cortex-A8 erratum. */
6512 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6513 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6514 a8_relocs, num_a8_relocs,
6515 prev_num_a8_fixes, &stub_changed)
6516 != 0)
48229727 6517 goto error_ret_free_local;
5e681ec4 6518 }
7f991970
AM		 6519
6520 if (local_syms != NULL
6521 && symtab_hdr->contents != (unsigned char *) local_syms)
6522 {
6523 if (!info->keep_memory)
6524 free (local_syms);
6525 else
6526 symtab_hdr->contents = (unsigned char *) local_syms;
6527 }
5e681ec4
PB		 6528 }
6529
0955507f
TP		 6530 if (first_veneer_scan
6531 && !set_cmse_veneer_addr_from_implib (info, htab,
6532 &cmse_stub_created))
6533 ret = FALSE;
6534
eb7c4339 6535 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6536 stub_changed = TRUE;
48229727 6537
906e58ca
NC		 6538 if (!stub_changed)
6539 break;
5e681ec4 6540
906e58ca
NC		 6541 /* OK, we've added some stubs. Find out the new size of the
6542 stub sections. */
6543 for (stub_sec = htab->stub_bfd->sections;
6544 stub_sec != NULL;
6545 stub_sec = stub_sec->next)
3e6b1042
DJ		 6546 {
6547 /* Ignore non-stub sections. */
6548 if (!strstr (stub_sec->name, STUB_SUFFIX))
6549 continue;
6550
6551 stub_sec->size = 0;
6552 }
b34b2d70 6553
0955507f
TP		 6554 /* Add new SG veneers after those already in the input import
6555 library. */
6556 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6557 stub_type++)
6558 {
6559 bfd_vma *start_offset_p;
6560 asection **stub_sec_p;
6561
6562 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6563 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6564 if (start_offset_p == NULL)
6565 continue;
6566
6567 BFD_ASSERT (stub_sec_p != NULL);
6568 if (*stub_sec_p != NULL)
6569 (*stub_sec_p)->size = *start_offset_p;
6570 }
6571
d7c5bd02 6572 /* Compute stub section size, considering padding. */
906e58ca 6573 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6574 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6575 stub_type++)
6576 {
6577 int size, padding;
6578 asection **stub_sec_p;
6579
6580 padding = arm_dedicated_stub_section_padding (stub_type);
6581 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6582 /* Skip if no stub input section or no stub section padding
6583 required. */
6584 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6585 continue;
6586 /* Stub section padding required but no dedicated section. */
6587 BFD_ASSERT (stub_sec_p);
6588
6589 size = (*stub_sec_p)->size;
6590 size = (size + padding - 1) & ~(padding - 1);
6591 (*stub_sec_p)->size = size;
6592 }
906e58ca 6593
48229727
JB		 6594 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6595 if (htab->fix_cortex_a8)
99059e56
RM		 6596 for (i = 0; i < num_a8_fixes; i++)
6597 {
48229727 6598 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6599 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6600
6601 if (stub_sec == NULL)
7f991970 6602 return FALSE;
48229727 6603
99059e56
RM		 6604 stub_sec->size
6605 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6606 NULL);
6607 }
48229727
JB		 6608
6609
906e58ca
NC		 6610 /* Ask the linker to do its stuff. */
6611 (*htab->layout_sections_again) ();
4ba2ef8f 6612 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6613 }
6614
48229727
JB		 6615 /* Add stubs for Cortex-A8 erratum fixes now. */
6616 if (htab->fix_cortex_a8)
6617 {
6618 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6619 {
6620 struct elf32_arm_stub_hash_entry *stub_entry;
6621 char *stub_name = a8_fixes[i].stub_name;
6622 asection *section = a8_fixes[i].section;
6623 unsigned int section_id = a8_fixes[i].section->id;
6624 asection *link_sec = htab->stub_group[section_id].link_sec;
6625 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6626 const insn_sequence *template_sequence;
6627 int template_size, size = 0;
6628
6629 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6630 TRUE, FALSE);
6631 if (stub_entry == NULL)
6632 {
dae82561 6633 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 6634 section->owner, stub_name);
99059e56
RM		 6635 return FALSE;
6636 }
6637
6638 stub_entry->stub_sec = stub_sec;
0955507f 6639 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6640 stub_entry->id_sec = link_sec;
6641 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6642 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6643 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6644 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6645 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6646 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6647
99059e56
RM		 6648 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6649 &template_sequence,
6650 &template_size);
48229727 6651
99059e56
RM		 6652 stub_entry->stub_size = size;
6653 stub_entry->stub_template = template_sequence;
6654 stub_entry->stub_template_size = template_size;
6655 }
48229727
JB		 6656
6657 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6658 elf32_arm_write_section(). */
48229727
JB		 6659 htab->a8_erratum_fixes = a8_fixes;
6660 htab->num_a8_erratum_fixes = num_a8_fixes;
6661 }
6662 else
6663 {
6664 htab->a8_erratum_fixes = NULL;
6665 htab->num_a8_erratum_fixes = 0;
6666 }
0955507f 6667 return ret;
5e681ec4
PB		 6668}
6669
906e58ca
NC		 6670/* Build all the stubs associated with the current output file. The
6671 stubs are kept in a hash table attached to the main linker hash
6672 table. We also set up the .plt entries for statically linked PIC
6673 functions here. This function is called via arm_elf_finish in the
6674 linker. */
252b5132 6675
906e58ca
NC		 6676bfd_boolean
6677elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6678{
906e58ca
NC		 6679 asection *stub_sec;
6680 struct bfd_hash_table *table;
0955507f 6681 enum elf32_arm_stub_type stub_type;
906e58ca 6682 struct elf32_arm_link_hash_table *htab;
252b5132 6683
906e58ca 6684 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6685 if (htab == NULL)
6686 return FALSE;
252b5132 6687
906e58ca
NC		 6688 for (stub_sec = htab->stub_bfd->sections;
6689 stub_sec != NULL;
6690 stub_sec = stub_sec->next)
252b5132 6691 {
906e58ca
NC		 6692 bfd_size_type size;
6693
8029a119 6694 /* Ignore non-stub sections. */
906e58ca
NC		 6695 if (!strstr (stub_sec->name, STUB_SUFFIX))
6696 continue;
6697
d7c5bd02 6698 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6699 must at least be done for stub section requiring padding and for SG
6700 veneers to ensure that a non secure code branching to a removed SG
6701 veneer causes an error. */
906e58ca 6702 size = stub_sec->size;
21d799b5 6703 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6704 if (stub_sec->contents == NULL && size != 0)
6705 return FALSE;
0955507f 6706
906e58ca 6707 stub_sec->size = 0;
252b5132
RH		 6708 }
6709
0955507f
TP		 6710 /* Add new SG veneers after those already in the input import library. */
6711 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6712 {
6713 bfd_vma *start_offset_p;
6714 asection **stub_sec_p;
6715
6716 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6717 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6718 if (start_offset_p == NULL)
6719 continue;
6720
6721 BFD_ASSERT (stub_sec_p != NULL);
6722 if (*stub_sec_p != NULL)
6723 (*stub_sec_p)->size = *start_offset_p;
6724 }
6725
906e58ca
NC		 6726 /* Build the stubs as directed by the stub hash table. */
6727 table = &htab->stub_hash_table;
6728 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6729 if (htab->fix_cortex_a8)
6730 {
6731 /* Place the cortex a8 stubs last. */
6732 htab->fix_cortex_a8 = -1;
6733 bfd_hash_traverse (table, arm_build_one_stub, info);
6734 }
252b5132 6735
906e58ca 6736 return TRUE;
252b5132
RH		 6737}
6738
9b485d32
NC		 6739/* Locate the Thumb encoded calling stub for NAME. */
6740
252b5132 6741static struct elf_link_hash_entry *
57e8b36a
NC		 6742find_thumb_glue (struct bfd_link_info *link_info,
6743 const char *name,
f2a9dd69 6744 char **error_message)
252b5132
RH		 6745{
6746 char *tmp_name;
6747 struct elf_link_hash_entry *hash;
6748 struct elf32_arm_link_hash_table *hash_table;
6749
6750 /* We need a pointer to the armelf specific hash table. */
6751 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6752 if (hash_table == NULL)
6753 return NULL;
252b5132 6754
21d799b5 6755 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6756 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6757
6758 BFD_ASSERT (tmp_name);
6759
6760 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6761
6762 hash = elf_link_hash_lookup
b34976b6 6763 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6764
b1657152
AM		 6765 if (hash == NULL
6766 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6767 tmp_name, name) == -1)
6768 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6769
6770 free (tmp_name);
6771
6772 return hash;
6773}
6774
9b485d32
NC		 6775/* Locate the ARM encoded calling stub for NAME. */
6776
252b5132 6777static struct elf_link_hash_entry *
57e8b36a
NC		 6778find_arm_glue (struct bfd_link_info *link_info,
6779 const char *name,
f2a9dd69 6780 char **error_message)
252b5132
RH		 6781{
6782 char *tmp_name;
6783 struct elf_link_hash_entry *myh;
6784 struct elf32_arm_link_hash_table *hash_table;
6785
6786 /* We need a pointer to the elfarm specific hash table. */
6787 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6788 if (hash_table == NULL)
6789 return NULL;
252b5132 6790
21d799b5 6791 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6792 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6793
6794 BFD_ASSERT (tmp_name);
6795
6796 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6797
6798 myh = elf_link_hash_lookup
b34976b6 6799 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6800
b1657152
AM		 6801 if (myh == NULL
6802 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6803 tmp_name, name) == -1)
6804 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6805
6806 free (tmp_name);
6807
6808 return myh;
6809}
6810
8f6277f5 6811/* ARM->Thumb glue (static images):
252b5132
RH		 6812
6813 .arm
6814 __func_from_arm:
6815 ldr r12, __func_addr
6816 bx r12
6817 __func_addr:
906e58ca 6818 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6819
26079076
PB		 6820 (v5t static images)
6821 .arm
6822 __func_from_arm:
6823 ldr pc, __func_addr
6824 __func_addr:
906e58ca 6825 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6826
8f6277f5
PB		 6827 (relocatable images)
6828 .arm
6829 __func_from_arm:
6830 ldr r12, __func_offset
6831 add r12, r12, pc
6832 bx r12
6833 __func_offset:
8029a119 6834 .word func - . */
8f6277f5
PB		 6835
6836#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6837static const insn32 a2t1_ldr_insn = 0xe59fc000;
6838static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6839static const insn32 a2t3_func_addr_insn = 0x00000001;
6840
26079076
PB		 6841#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6842static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6843static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6844
8f6277f5
PB		 6845#define ARM2THUMB_PIC_GLUE_SIZE 16
6846static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6847static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6848static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6849
9b485d32 6850/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6851
8029a119
NC		 6852 .thumb .thumb
6853 .align 2 .align 2
6854 __func_from_thumb: __func_from_thumb:
6855 bx pc push {r6, lr}
6856 nop ldr r6, __func_addr
6857 .arm mov lr, pc
6858 b func bx r6
99059e56
RM		 6859 .arm
6860 ;; back_to_thumb
6861 ldmia r13! {r6, lr}
6862 bx lr
6863 __func_addr:
6864 .word func */
252b5132
RH		 6865
6866#define THUMB2ARM_GLUE_SIZE 8
6867static const insn16 t2a1_bx_pc_insn = 0x4778;
6868static const insn16 t2a2_noop_insn = 0x46c0;
6869static const insn32 t2a3_b_insn = 0xea000000;
6870
c7b8f16e 6871#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6872#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6873#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6874
845b51d6
PB		 6875#define ARM_BX_VENEER_SIZE 12
6876static const insn32 armbx1_tst_insn = 0xe3100001;
6877static const insn32 armbx2_moveq_insn = 0x01a0f000;
6878static const insn32 armbx3_bx_insn = 0xe12fff10;
6879
7e392df6 6880#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6881static void
6882arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6883{
6884 asection * s;
8029a119 6885 bfd_byte * contents;
252b5132 6886
8029a119 6887 if (size == 0)
3e6b1042
DJ		 6888 {
6889 /* Do not include empty glue sections in the output. */
6890 if (abfd != NULL)
6891 {
3d4d4302 6892 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6893 if (s != NULL)
6894 s->flags |= SEC_EXCLUDE;
6895 }
6896 return;
6897 }
252b5132 6898
8029a119 6899 BFD_ASSERT (abfd != NULL);
252b5132 6900
3d4d4302 6901 s = bfd_get_linker_section (abfd, name);
8029a119 6902 BFD_ASSERT (s != NULL);
252b5132 6903
21d799b5 6904 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6905
8029a119
NC		 6906 BFD_ASSERT (s->size == size);
6907 s->contents = contents;
6908}
906e58ca 6909
8029a119
NC		 6910bfd_boolean
6911bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6912{
6913 struct elf32_arm_link_hash_table * globals;
906e58ca 6914
8029a119
NC		 6915 globals = elf32_arm_hash_table (info);
6916 BFD_ASSERT (globals != NULL);
906e58ca 6917
8029a119
NC		 6918 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6919 globals->arm_glue_size,
6920 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6921
8029a119
NC		 6922 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6923 globals->thumb_glue_size,
6924 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6925
8029a119
NC		 6926 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6927 globals->vfp11_erratum_glue_size,
6928 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6929
a504d23a
LA		 6930 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6931 globals->stm32l4xx_erratum_glue_size,
6932 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6933
8029a119
NC		 6934 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6935 globals->bx_glue_size,
845b51d6
PB		 6936 ARM_BX_GLUE_SECTION_NAME);
6937
b34976b6 6938 return TRUE;
252b5132
RH		 6939}
6940
a4fd1a8e 6941/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6942 returns the symbol identifying the stub. */
6943
a4fd1a8e 6944static struct elf_link_hash_entry *
57e8b36a
NC		 6945record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6946 struct elf_link_hash_entry * h)
252b5132
RH		 6947{
6948 const char * name = h->root.root.string;
63b0f745 6949 asection * s;
252b5132
RH		 6950 char * tmp_name;
6951 struct elf_link_hash_entry * myh;
14a793b2 6952 struct bfd_link_hash_entry * bh;
252b5132 6953 struct elf32_arm_link_hash_table * globals;
dc810e39 6954 bfd_vma val;
2f475487 6955 bfd_size_type size;
252b5132
RH		 6956
6957 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6958 BFD_ASSERT (globals != NULL);
6959 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6960
3d4d4302 6961 s = bfd_get_linker_section
252b5132
RH		 6962 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6963
252b5132
RH		 6964 BFD_ASSERT (s != NULL);
6965
21d799b5 6966 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6967 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6968
6969 BFD_ASSERT (tmp_name);
6970
6971 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6972
6973 myh = elf_link_hash_lookup
b34976b6 6974 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6975
6976 if (myh != NULL)
6977 {
9b485d32 6978 /* We've already seen this guy. */
252b5132 6979 free (tmp_name);
a4fd1a8e 6980 return myh;
252b5132
RH		 6981 }
6982
57e8b36a
NC		 6983 /* The only trick here is using hash_table->arm_glue_size as the value.
6984 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6985 putting it. The +1 on the value marks that the stub has not been
6986 output yet - not that it is a Thumb function. */
14a793b2 6987 bh = NULL;
dc810e39
AM		 6988 val = globals->arm_glue_size + 1;
6989 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6990 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6991 NULL, TRUE, FALSE, &bh);
252b5132 6992
b7693d02
DJ		 6993 myh = (struct elf_link_hash_entry *) bh;
6994 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6995 myh->forced_local = 1;
6996
252b5132
RH		 6997 free (tmp_name);
6998
0e1862bb
L		 6999 if (bfd_link_pic (link_info)
7000 || globals->root.is_relocatable_executable
27e55c4d 7001 || globals->pic_veneer)
2f475487 7002 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7003 else if (globals->use_blx)
7004 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7005 else
2f475487
AM		 7006 size = ARM2THUMB_STATIC_GLUE_SIZE;
7007
7008 s->size += size;
7009 globals->arm_glue_size += size;
252b5132 7010
a4fd1a8e 7011 return myh;
252b5132
RH		 7012}
7013
845b51d6
PB		 7014/* Allocate space for ARMv4 BX veneers. */
7015
7016static void
7017record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7018{
7019 asection * s;
7020 struct elf32_arm_link_hash_table *globals;
7021 char *tmp_name;
7022 struct elf_link_hash_entry *myh;
7023 struct bfd_link_hash_entry *bh;
7024 bfd_vma val;
7025
7026 /* BX PC does not need a veneer. */
7027 if (reg == 15)
7028 return;
7029
7030 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7031 BFD_ASSERT (globals != NULL);
7032 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7033
7034 /* Check if this veneer has already been allocated. */
7035 if (globals->bx_glue_offset[reg])
7036 return;
7037
3d4d4302 7038 s = bfd_get_linker_section
845b51d6
PB		 7039 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7040
7041 BFD_ASSERT (s != NULL);
7042
7043 /* Add symbol for veneer. */
21d799b5
NC		 7044 tmp_name = (char *)
7045 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7046
845b51d6 7047 BFD_ASSERT (tmp_name);
906e58ca 7048
845b51d6 7049 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7050
845b51d6
PB		 7051 myh = elf_link_hash_lookup
7052 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7053
845b51d6 7054 BFD_ASSERT (myh == NULL);
906e58ca 7055
845b51d6
PB		 7056 bh = NULL;
7057 val = globals->bx_glue_size;
7058 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7059 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7060 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7061
7062 myh = (struct elf_link_hash_entry *) bh;
7063 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7064 myh->forced_local = 1;
7065
7066 s->size += ARM_BX_VENEER_SIZE;
7067 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7068 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7069}
7070
7071
c7b8f16e
JB		 7072/* Add an entry to the code/data map for section SEC. */
7073
7074static void
7075elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7076{
7077 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7078 unsigned int newidx;
906e58ca 7079
c7b8f16e
JB		 7080 if (sec_data->map == NULL)
7081 {
21d799b5 7082 sec_data->map = (elf32_arm_section_map *)
99059e56 7083 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7084 sec_data->mapcount = 0;
7085 sec_data->mapsize = 1;
7086 }
906e58ca 7087
c7b8f16e 7088 newidx = sec_data->mapcount++;
906e58ca 7089
c7b8f16e
JB		 7090 if (sec_data->mapcount > sec_data->mapsize)
7091 {
7092 sec_data->mapsize *= 2;
21d799b5 7093 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7094 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7095 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7096 }
7097
7098 if (sec_data->map)
7099 {
7100 sec_data->map[newidx].vma = vma;
7101 sec_data->map[newidx].type = type;
c7b8f16e 7102 }
c7b8f16e
JB		 7103}
7104
7105
7106/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7107 veneers are handled for now. */
7108
7109static bfd_vma
7110record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7111 elf32_vfp11_erratum_list *branch,
7112 bfd *branch_bfd,
7113 asection *branch_sec,
7114 unsigned int offset)
c7b8f16e
JB		 7115{
7116 asection *s;
7117 struct elf32_arm_link_hash_table *hash_table;
7118 char *tmp_name;
7119 struct elf_link_hash_entry *myh;
7120 struct bfd_link_hash_entry *bh;
7121 bfd_vma val;
7122 struct _arm_elf_section_data *sec_data;
c7b8f16e 7123 elf32_vfp11_erratum_list *newerr;
906e58ca 7124
c7b8f16e 7125 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7126 BFD_ASSERT (hash_table != NULL);
7127 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7128
3d4d4302 7129 s = bfd_get_linker_section
c7b8f16e 7130 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7131
c7b8f16e 7132 sec_data = elf32_arm_section_data (s);
906e58ca 7133
c7b8f16e 7134 BFD_ASSERT (s != NULL);
906e58ca 7135
21d799b5 7136 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7137 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7138
c7b8f16e 7139 BFD_ASSERT (tmp_name);
906e58ca 7140
c7b8f16e
JB		 7141 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7142 hash_table->num_vfp11_fixes);
906e58ca 7143
c7b8f16e
JB		 7144 myh = elf_link_hash_lookup
7145 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7146
c7b8f16e 7147 BFD_ASSERT (myh == NULL);
906e58ca 7148
c7b8f16e
JB		 7149 bh = NULL;
7150 val = hash_table->vfp11_erratum_glue_size;
7151 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7152 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7153 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7154
7155 myh = (struct elf_link_hash_entry *) bh;
7156 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7157 myh->forced_local = 1;
7158
7159 /* Link veneer back to calling location. */
c7e2358a 7160 sec_data->erratumcount += 1;
21d799b5
NC		 7161 newerr = (elf32_vfp11_erratum_list *)
7162 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7163
c7b8f16e
JB		 7164 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7165 newerr->vma = -1;
7166 newerr->u.v.branch = branch;
7167 newerr->u.v.id = hash_table->num_vfp11_fixes;
7168 branch->u.b.veneer = newerr;
7169
7170 newerr->next = sec_data->erratumlist;
7171 sec_data->erratumlist = newerr;
7172
7173 /* A symbol for the return from the veneer. */
7174 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7175 hash_table->num_vfp11_fixes);
7176
7177 myh = elf_link_hash_lookup
7178 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7179
c7b8f16e
JB		 7180 if (myh != NULL)
7181 abort ();
7182
7183 bh = NULL;
7184 val = offset + 4;
7185 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7186 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7187
c7b8f16e
JB		 7188 myh = (struct elf_link_hash_entry *) bh;
7189 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7190 myh->forced_local = 1;
7191
7192 free (tmp_name);
906e58ca 7193
c7b8f16e
JB		 7194 /* Generate a mapping symbol for the veneer section, and explicitly add an
7195 entry for that symbol to the code/data map for the section. */
7196 if (hash_table->vfp11_erratum_glue_size == 0)
7197 {
7198 bh = NULL;
7199 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7200 ever requires this erratum fix. */
c7b8f16e
JB		 7201 _bfd_generic_link_add_one_symbol (link_info,
7202 hash_table->bfd_of_glue_owner, "$a",
7203 BSF_LOCAL, s, 0, NULL,
99059e56 7204 TRUE, FALSE, &bh);
c7b8f16e
JB		 7205
7206 myh = (struct elf_link_hash_entry *) bh;
7207 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7208 myh->forced_local = 1;
906e58ca 7209
c7b8f16e 7210 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7211 BFDs. We must make a note of this generated mapping symbol
7212 ourselves so that code byteswapping works properly in
7213 elf32_arm_write_section. */
c7b8f16e
JB		 7214 elf32_arm_section_map_add (s, 'a', 0);
7215 }
906e58ca 7216
c7b8f16e
JB		 7217 s->size += VFP11_ERRATUM_VENEER_SIZE;
7218 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7219 hash_table->num_vfp11_fixes++;
906e58ca 7220
c7b8f16e
JB		 7221 /* The offset of the veneer. */
7222 return val;
7223}
7224
a504d23a
LA		 7225/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7226 veneers need to be handled because used only in Cortex-M. */
7227
7228static bfd_vma
7229record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7230 elf32_stm32l4xx_erratum_list *branch,
7231 bfd *branch_bfd,
7232 asection *branch_sec,
7233 unsigned int offset,
7234 bfd_size_type veneer_size)
7235{
7236 asection *s;
7237 struct elf32_arm_link_hash_table *hash_table;
7238 char *tmp_name;
7239 struct elf_link_hash_entry *myh;
7240 struct bfd_link_hash_entry *bh;
7241 bfd_vma val;
7242 struct _arm_elf_section_data *sec_data;
7243 elf32_stm32l4xx_erratum_list *newerr;
7244
7245 hash_table = elf32_arm_hash_table (link_info);
7246 BFD_ASSERT (hash_table != NULL);
7247 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7248
7249 s = bfd_get_linker_section
7250 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7251
7252 BFD_ASSERT (s != NULL);
7253
7254 sec_data = elf32_arm_section_data (s);
7255
7256 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7257 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7258
7259 BFD_ASSERT (tmp_name);
7260
7261 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7262 hash_table->num_stm32l4xx_fixes);
7263
7264 myh = elf_link_hash_lookup
7265 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7266
7267 BFD_ASSERT (myh == NULL);
7268
7269 bh = NULL;
7270 val = hash_table->stm32l4xx_erratum_glue_size;
7271 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7272 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7273 NULL, TRUE, FALSE, &bh);
7274
7275 myh = (struct elf_link_hash_entry *) bh;
7276 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7277 myh->forced_local = 1;
7278
7279 /* Link veneer back to calling location. */
7280 sec_data->stm32l4xx_erratumcount += 1;
7281 newerr = (elf32_stm32l4xx_erratum_list *)
7282 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7283
7284 newerr->type = STM32L4XX_ERRATUM_VENEER;
7285 newerr->vma = -1;
7286 newerr->u.v.branch = branch;
7287 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7288 branch->u.b.veneer = newerr;
7289
7290 newerr->next = sec_data->stm32l4xx_erratumlist;
7291 sec_data->stm32l4xx_erratumlist = newerr;
7292
7293 /* A symbol for the return from the veneer. */
7294 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7295 hash_table->num_stm32l4xx_fixes);
7296
7297 myh = elf_link_hash_lookup
7298 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7299
7300 if (myh != NULL)
7301 abort ();
7302
7303 bh = NULL;
7304 val = offset + 4;
7305 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7306 branch_sec, val, NULL, TRUE, FALSE, &bh);
7307
7308 myh = (struct elf_link_hash_entry *) bh;
7309 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7310 myh->forced_local = 1;
7311
7312 free (tmp_name);
7313
7314 /* Generate a mapping symbol for the veneer section, and explicitly add an
7315 entry for that symbol to the code/data map for the section. */
7316 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7317 {
7318 bh = NULL;
7319 /* Creates a THUMB symbol since there is no other choice. */
7320 _bfd_generic_link_add_one_symbol (link_info,
7321 hash_table->bfd_of_glue_owner, "$t",
7322 BSF_LOCAL, s, 0, NULL,
7323 TRUE, FALSE, &bh);
7324
7325 myh = (struct elf_link_hash_entry *) bh;
7326 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7327 myh->forced_local = 1;
7328
7329 /* The elf32_arm_init_maps function only cares about symbols from input
7330 BFDs. We must make a note of this generated mapping symbol
7331 ourselves so that code byteswapping works properly in
7332 elf32_arm_write_section. */
7333 elf32_arm_section_map_add (s, 't', 0);
7334 }
7335
7336 s->size += veneer_size;
7337 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7338 hash_table->num_stm32l4xx_fixes++;
7339
7340 /* The offset of the veneer. */
7341 return val;
7342}
7343
8029a119 7344#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7345 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7346 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7347
7348/* Create a fake section for use by the ARM backend of the linker. */
7349
7350static bfd_boolean
7351arm_make_glue_section (bfd * abfd, const char * name)
7352{
7353 asection * sec;
7354
3d4d4302 7355 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7356 if (sec != NULL)
7357 /* Already made. */
7358 return TRUE;
7359
3d4d4302 7360 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7361
7362 if (sec == NULL
7363 || !bfd_set_section_alignment (abfd, sec, 2))
7364 return FALSE;
7365
7366 /* Set the gc mark to prevent the section from being removed by garbage
7367 collection, despite the fact that no relocs refer to this section. */
7368 sec->gc_mark = 1;
7369
7370 return TRUE;
7371}
7372
1db37fe6
YG		 7373/* Set size of .plt entries. This function is called from the
7374 linker scripts in ld/emultempl/{armelf}.em. */
7375
7376void
7377bfd_elf32_arm_use_long_plt (void)
7378{
7379 elf32_arm_use_long_plt_entry = TRUE;
7380}
7381
8afb0e02
NC		 7382/* Add the glue sections to ABFD. This function is called from the
7383 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7384
b34976b6 7385bfd_boolean
57e8b36a
NC		 7386bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7387 struct bfd_link_info *info)
252b5132 7388{
a504d23a
LA		 7389 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7390 bfd_boolean dostm32l4xx = globals
7391 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7392 bfd_boolean addglue;
7393
8afb0e02
NC		 7394 /* If we are only performing a partial
7395 link do not bother adding the glue. */
0e1862bb 7396 if (bfd_link_relocatable (info))
b34976b6 7397 return TRUE;
252b5132 7398
a504d23a 7399 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7400 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7401 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7402 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7403
7404 if (!dostm32l4xx)
7405 return addglue;
7406
7407 return addglue
7408 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7409}
7410
daa4adae
TP		 7411/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7412 ensures they are not marked for deletion by
7413 strip_excluded_output_sections () when veneers are going to be created
7414 later. Not doing so would trigger assert on empty section size in
7415 lang_size_sections_1 (). */
7416
7417void
7418bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7419{
7420 enum elf32_arm_stub_type stub_type;
7421
7422 /* If we are only performing a partial
7423 link do not bother adding the glue. */
7424 if (bfd_link_relocatable (info))
7425 return;
7426
7427 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7428 {
7429 asection *out_sec;
7430 const char *out_sec_name;
7431
7432 if (!arm_dedicated_stub_output_section_required (stub_type))
7433 continue;
7434
7435 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7436 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7437 if (out_sec != NULL)
7438 out_sec->flags |= SEC_KEEP;
7439 }
7440}
7441
8afb0e02
NC		 7442/* Select a BFD to be used to hold the sections used by the glue code.
7443 This function is called from the linker scripts in ld/emultempl/
8029a119 7444 {armelf/pe}.em. */
8afb0e02 7445
b34976b6 7446bfd_boolean
57e8b36a 7447bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7448{
7449 struct elf32_arm_link_hash_table *globals;
7450
7451 /* If we are only performing a partial link
7452 do not bother getting a bfd to hold the glue. */
0e1862bb 7453 if (bfd_link_relocatable (info))
b34976b6 7454 return TRUE;
8afb0e02 7455
b7693d02
DJ		 7456 /* Make sure we don't attach the glue sections to a dynamic object. */
7457 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7458
8afb0e02 7459 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7460 BFD_ASSERT (globals != NULL);
7461
7462 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7463 return TRUE;
8afb0e02 7464
252b5132
RH		 7465 /* Save the bfd for later use. */
7466 globals->bfd_of_glue_owner = abfd;
cedb70c5 7467
b34976b6 7468 return TRUE;
252b5132
RH		 7469}
7470
906e58ca
NC		 7471static void
7472check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7473{
2de70689
MGD		 7474 int cpu_arch;
7475
b38cadfb 7476 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7477 Tag_CPU_arch);
7478
7479 if (globals->fix_arm1176)
7480 {
7481 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7482 globals->use_blx = 1;
7483 }
7484 else
7485 {
7486 if (cpu_arch > TAG_CPU_ARCH_V4T)
7487 globals->use_blx = 1;
7488 }
39b41c9c
PB		 7489}
7490
b34976b6 7491bfd_boolean
57e8b36a 7492bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7493 struct bfd_link_info *link_info)
252b5132
RH		 7494{
7495 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7496 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7497 Elf_Internal_Rela *irel, *irelend;
7498 bfd_byte *contents = NULL;
252b5132
RH		 7499
7500 asection *sec;
7501 struct elf32_arm_link_hash_table *globals;
7502
7503 /* If we are only performing a partial link do not bother
7504 to construct any glue. */
0e1862bb 7505 if (bfd_link_relocatable (link_info))
b34976b6 7506 return TRUE;
252b5132 7507
39ce1a6a
NC		 7508 /* Here we have a bfd that is to be included on the link. We have a
7509 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7510 globals = elf32_arm_hash_table (link_info);
252b5132 7511 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7512
7513 check_use_blx (globals);
252b5132 7514
d504ffc8 7515 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7516 {
d003868e
AM		 7517 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7518 abfd);
e489d0ae
PB		 7519 return FALSE;
7520 }
f21f3fe0 7521
39ce1a6a
NC		 7522 /* PR 5398: If we have not decided to include any loadable sections in
7523 the output then we will not have a glue owner bfd. This is OK, it
7524 just means that there is nothing else for us to do here. */
7525 if (globals->bfd_of_glue_owner == NULL)
7526 return TRUE;
7527
252b5132
RH		 7528 /* Rummage around all the relocs and map the glue vectors. */
7529 sec = abfd->sections;
7530
7531 if (sec == NULL)
b34976b6 7532 return TRUE;
252b5132
RH		 7533
7534 for (; sec != NULL; sec = sec->next)
7535 {
7536 if (sec->reloc_count == 0)
7537 continue;
7538
2f475487
AM		 7539 if ((sec->flags & SEC_EXCLUDE) != 0)
7540 continue;
7541
0ffa91dd 7542 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7543
9b485d32 7544 /* Load the relocs. */
6cdc0ccc 7545 internal_relocs
906e58ca 7546 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7547
6cdc0ccc
AM		 7548 if (internal_relocs == NULL)
7549 goto error_return;
252b5132 7550
6cdc0ccc
AM		 7551 irelend = internal_relocs + sec->reloc_count;
7552 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7553 {
7554 long r_type;
7555 unsigned long r_index;
252b5132
RH		 7556
7557 struct elf_link_hash_entry *h;
7558
7559 r_type = ELF32_R_TYPE (irel->r_info);
7560 r_index = ELF32_R_SYM (irel->r_info);
7561
9b485d32 7562 /* These are the only relocation types we care about. */
ba96a88f 7563 if ( r_type != R_ARM_PC24
845b51d6 7564 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7565 continue;
7566
7567 /* Get the section contents if we haven't done so already. */
7568 if (contents == NULL)
7569 {
7570 /* Get cached copy if it exists. */
7571 if (elf_section_data (sec)->this_hdr.contents != NULL)
7572 contents = elf_section_data (sec)->this_hdr.contents;
7573 else
7574 {
7575 /* Go get them off disk. */
57e8b36a 7576 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7577 goto error_return;
7578 }
7579 }
7580
845b51d6
PB		 7581 if (r_type == R_ARM_V4BX)
7582 {
7583 int reg;
7584
7585 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7586 record_arm_bx_glue (link_info, reg);
7587 continue;
7588 }
7589
a7c10850 7590 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7591 h = NULL;
7592
9b485d32 7593 /* We don't care about local symbols. */
252b5132
RH		 7594 if (r_index < symtab_hdr->sh_info)
7595 continue;
7596
9b485d32 7597 /* This is an external symbol. */
252b5132
RH		 7598 r_index -= symtab_hdr->sh_info;
7599 h = (struct elf_link_hash_entry *)
7600 elf_sym_hashes (abfd)[r_index];
7601
7602 /* If the relocation is against a static symbol it must be within
7603 the current section and so cannot be a cross ARM/Thumb relocation. */
7604 if (h == NULL)
7605 continue;
7606
d504ffc8
DJ		 7607 /* If the call will go through a PLT entry then we do not need
7608 glue. */
362d30a1 7609 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7610 continue;
7611
252b5132
RH		 7612 switch (r_type)
7613 {
7614 case R_ARM_PC24:
7615 /* This one is a call from arm code. We need to look up
99059e56
RM		 7616 the target of the call. If it is a thumb target, we
7617 insert glue. */
39d911fc
TP		 7618 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7619 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7620 record_arm_to_thumb_glue (link_info, h);
7621 break;
7622
252b5132 7623 default:
c6596c5e 7624 abort ();
252b5132
RH		 7625 }
7626 }
6cdc0ccc
AM		 7627
7628 if (contents != NULL
7629 && elf_section_data (sec)->this_hdr.contents != contents)
7630 free (contents);
7631 contents = NULL;
7632
7633 if (internal_relocs != NULL
7634 && elf_section_data (sec)->relocs != internal_relocs)
7635 free (internal_relocs);
7636 internal_relocs = NULL;
252b5132
RH		 7637 }
7638
b34976b6 7639 return TRUE;
9a5aca8c 7640
252b5132 7641error_return:
6cdc0ccc
AM		 7642 if (contents != NULL
7643 && elf_section_data (sec)->this_hdr.contents != contents)
7644 free (contents);
7645 if (internal_relocs != NULL
7646 && elf_section_data (sec)->relocs != internal_relocs)
7647 free (internal_relocs);
9a5aca8c 7648
b34976b6 7649 return FALSE;
252b5132 7650}
7e392df6 7651#endif
252b5132 7652
eb043451 7653
c7b8f16e
JB		 7654/* Initialise maps of ARM/Thumb/data for input BFDs. */
7655
7656void
7657bfd_elf32_arm_init_maps (bfd *abfd)
7658{
7659 Elf_Internal_Sym *isymbuf;
7660 Elf_Internal_Shdr *hdr;
7661 unsigned int i, localsyms;
7662
af1f4419
NC		 7663 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7664 if (! is_arm_elf (abfd))
7665 return;
7666
c7b8f16e
JB		 7667 if ((abfd->flags & DYNAMIC) != 0)
7668 return;
7669
0ffa91dd 7670 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7671 localsyms = hdr->sh_info;
7672
7673 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7674 should contain the number of local symbols, which should come before any
7675 global symbols. Mapping symbols are always local. */
7676 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7677 NULL);
7678
7679 /* No internal symbols read? Skip this BFD. */
7680 if (isymbuf == NULL)
7681 return;
7682
7683 for (i = 0; i < localsyms; i++)
7684 {
7685 Elf_Internal_Sym *isym = &isymbuf[i];
7686 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7687 const char *name;
906e58ca 7688
c7b8f16e 7689 if (sec != NULL
99059e56
RM		 7690 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7691 {
7692 name = bfd_elf_string_from_elf_section (abfd,
7693 hdr->sh_link, isym->st_name);
906e58ca 7694
99059e56 7695 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7696 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7697 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7698 }
c7b8f16e
JB		 7699 }
7700}
7701
7702
48229727
JB		 7703/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7704 say what they wanted. */
7705
7706void
7707bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7708{
7709 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7710 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7711
4dfe6ac6
NC		 7712 if (globals == NULL)
7713 return;
7714
48229727
JB		 7715 if (globals->fix_cortex_a8 == -1)
7716 {
7717 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7718 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7719 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7720 || out_attr[Tag_CPU_arch_profile].i == 0))
7721 globals->fix_cortex_a8 = 1;
7722 else
7723 globals->fix_cortex_a8 = 0;
7724 }
7725}
7726
7727
c7b8f16e
JB		 7728void
7729bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7730{
7731 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7732 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7733
4dfe6ac6
NC		 7734 if (globals == NULL)
7735 return;
c7b8f16e
JB		 7736 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7737 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7738 {
7739 switch (globals->vfp11_fix)
99059e56
RM		 7740 {
7741 case BFD_ARM_VFP11_FIX_DEFAULT:
7742 case BFD_ARM_VFP11_FIX_NONE:
7743 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7744 break;
7745
7746 default:
7747 /* Give a warning, but do as the user requests anyway. */
4eca0228 7748 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7749 "workaround is not necessary for target architecture"), obfd);
7750 }
c7b8f16e
JB		 7751 }
7752 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7753 /* For earlier architectures, we might need the workaround, but do not
7754 enable it by default. If users is running with broken hardware, they
7755 must enable the erratum fix explicitly. */
7756 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7757}
7758
a504d23a
LA		 7759void
7760bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7761{
7762 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7763 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7764
7765 if (globals == NULL)
7766 return;
7767
7768 /* We assume only Cortex-M4 may require the fix. */
7769 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7770 || out_attr[Tag_CPU_arch_profile].i != 'M')
7771 {
7772 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7773 /* Give a warning, but do as the user requests anyway. */
4eca0228 7774 _bfd_error_handler
a504d23a
LA		 7775 (_("%B: warning: selected STM32L4XX erratum "
7776 "workaround is not necessary for target architecture"), obfd);
7777 }
7778}
c7b8f16e 7779
906e58ca
NC		 7780enum bfd_arm_vfp11_pipe
7781{
c7b8f16e
JB		 7782 VFP11_FMAC,
7783 VFP11_LS,
7784 VFP11_DS,
7785 VFP11_BAD
7786};
7787
7788/* Return a VFP register number. This is encoded as RX:X for single-precision
7789 registers, or X:RX for double-precision registers, where RX is the group of
7790 four bits in the instruction encoding and X is the single extension bit.
7791 RX and X fields are specified using their lowest (starting) bit. The return
7792 value is:
7793
7794 0...31: single-precision registers s0...s31
7795 32...63: double-precision registers d0...d31.
906e58ca 7796
c7b8f16e
JB		 7797 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7798 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7799
c7b8f16e
JB		 7800static unsigned int
7801bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7802 unsigned int x)
c7b8f16e
JB		 7803{
7804 if (is_double)
7805 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7806 else
7807 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7808}
7809
7810/* Set bits in *WMASK according to a register number REG as encoded by
7811 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7812
7813static void
7814bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7815{
7816 if (reg < 32)
7817 *wmask |= 1 << reg;
7818 else if (reg < 48)
7819 *wmask |= 3 << ((reg - 32) * 2);
7820}
7821
7822/* Return TRUE if WMASK overwrites anything in REGS. */
7823
7824static bfd_boolean
7825bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7826{
7827 int i;
906e58ca 7828
c7b8f16e
JB		 7829 for (i = 0; i < numregs; i++)
7830 {
7831 unsigned int reg = regs[i];
7832
7833 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7834 return TRUE;
906e58ca 7835
c7b8f16e
JB		 7836 reg -= 32;
7837
7838 if (reg >= 16)
99059e56 7839 continue;
906e58ca 7840
c7b8f16e 7841 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7842 return TRUE;
c7b8f16e 7843 }
906e58ca 7844
c7b8f16e
JB		 7845 return FALSE;
7846}
7847
7848/* In this function, we're interested in two things: finding input registers
7849 for VFP data-processing instructions, and finding the set of registers which
7850 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7851 hold the written set, so FLDM etc. are easy to deal with (we're only
7852 interested in 32 SP registers or 16 dp registers, due to the VFP version
7853 implemented by the chip in question). DP registers are marked by setting
7854 both SP registers in the write mask). */
7855
7856static enum bfd_arm_vfp11_pipe
7857bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7858 int *numregs)
c7b8f16e 7859{
91d6fa6a 7860 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7861 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7862
7863 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7864 {
7865 unsigned int pqrs;
7866 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7867 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7868
7869 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7870 | ((insn & 0x00300000) >> 19)
7871 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7872
7873 switch (pqrs)
99059e56
RM		 7874 {
7875 case 0: /* fmac[sd]. */
7876 case 1: /* fnmac[sd]. */
7877 case 2: /* fmsc[sd]. */
7878 case 3: /* fnmsc[sd]. */
7879 vpipe = VFP11_FMAC;
7880 bfd_arm_vfp11_write_mask (destmask, fd);
7881 regs[0] = fd;
7882 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7883 regs[2] = fm;
7884 *numregs = 3;
7885 break;
7886
7887 case 4: /* fmul[sd]. */
7888 case 5: /* fnmul[sd]. */
7889 case 6: /* fadd[sd]. */
7890 case 7: /* fsub[sd]. */
7891 vpipe = VFP11_FMAC;
7892 goto vfp_binop;
7893
7894 case 8: /* fdiv[sd]. */
7895 vpipe = VFP11_DS;
7896 vfp_binop:
7897 bfd_arm_vfp11_write_mask (destmask, fd);
7898 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7899 regs[1] = fm;
7900 *numregs = 2;
7901 break;
7902
7903 case 15: /* extended opcode. */
7904 {
7905 unsigned int extn = ((insn >> 15) & 0x1e)
7906 | ((insn >> 7) & 1);
7907
7908 switch (extn)
7909 {
7910 case 0: /* fcpy[sd]. */
7911 case 1: /* fabs[sd]. */
7912 case 2: /* fneg[sd]. */
7913 case 8: /* fcmp[sd]. */
7914 case 9: /* fcmpe[sd]. */
7915 case 10: /* fcmpz[sd]. */
7916 case 11: /* fcmpez[sd]. */
7917 case 16: /* fuito[sd]. */
7918 case 17: /* fsito[sd]. */
7919 case 24: /* ftoui[sd]. */
7920 case 25: /* ftouiz[sd]. */
7921 case 26: /* ftosi[sd]. */
7922 case 27: /* ftosiz[sd]. */
7923 /* These instructions will not bounce due to underflow. */
7924 *numregs = 0;
7925 vpipe = VFP11_FMAC;
7926 break;
7927
7928 case 3: /* fsqrt[sd]. */
7929 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7930 registers to cause the erratum in previous instructions. */
7931 bfd_arm_vfp11_write_mask (destmask, fd);
7932 vpipe = VFP11_DS;
7933 break;
7934
7935 case 15: /* fcvt{ds,sd}. */
7936 {
7937 int rnum = 0;
7938
7939 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7940
7941 /* Only FCVTSD can underflow. */
99059e56
RM		 7942 if ((insn & 0x100) != 0)
7943 regs[rnum++] = fm;
c7b8f16e 7944
99059e56 7945 *numregs = rnum;
c7b8f16e 7946
99059e56
RM		 7947 vpipe = VFP11_FMAC;
7948 }
7949 break;
c7b8f16e 7950
99059e56
RM		 7951 default:
7952 return VFP11_BAD;
7953 }
7954 }
7955 break;
c7b8f16e 7956
99059e56
RM		 7957 default:
7958 return VFP11_BAD;
7959 }
c7b8f16e
JB		 7960 }
7961 /* Two-register transfer. */
7962 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7963 {
7964 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7965
c7b8f16e
JB		 7966 if ((insn & 0x100000) == 0)
7967 {
99059e56
RM		 7968 if (is_double)
7969 bfd_arm_vfp11_write_mask (destmask, fm);
7970 else
7971 {
7972 bfd_arm_vfp11_write_mask (destmask, fm);
7973 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7974 }
c7b8f16e
JB		 7975 }
7976
91d6fa6a 7977 vpipe = VFP11_LS;
c7b8f16e
JB		 7978 }
7979 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7980 {
7981 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7982 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7983
c7b8f16e 7984 switch (puw)
99059e56
RM		 7985 {
7986 case 0: /* Two-reg transfer. We should catch these above. */
7987 abort ();
906e58ca 7988
99059e56
RM		 7989 case 2: /* fldm[sdx]. */
7990 case 3:
7991 case 5:
7992 {
7993 unsigned int i, offset = insn & 0xff;
c7b8f16e 7994
99059e56
RM		 7995 if (is_double)
7996 offset >>= 1;
c7b8f16e 7997
99059e56
RM		 7998 for (i = fd; i < fd + offset; i++)
7999 bfd_arm_vfp11_write_mask (destmask, i);
8000 }
8001 break;
906e58ca 8002
99059e56
RM		 8003 case 4: /* fld[sd]. */
8004 case 6:
8005 bfd_arm_vfp11_write_mask (destmask, fd);
8006 break;
906e58ca 8007
99059e56
RM		 8008 default:
8009 return VFP11_BAD;
8010 }
c7b8f16e 8011
91d6fa6a 8012 vpipe = VFP11_LS;
c7b8f16e
JB		 8013 }
8014 /* Single-register transfer. Note L==0. */
8015 else if ((insn & 0x0f100e10) == 0x0e000a10)
8016 {
8017 unsigned int opcode = (insn >> 21) & 7;
8018 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8019
8020 switch (opcode)
99059e56
RM		 8021 {
8022 case 0: /* fmsr/fmdlr. */
8023 case 1: /* fmdhr. */
8024 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8025 destination register. I don't know if this is exactly right,
8026 but it is the conservative choice. */
8027 bfd_arm_vfp11_write_mask (destmask, fn);
8028 break;
8029
8030 case 7: /* fmxr. */
8031 break;
8032 }
c7b8f16e 8033
91d6fa6a 8034 vpipe = VFP11_LS;
c7b8f16e
JB		 8035 }
8036
91d6fa6a 8037 return vpipe;
c7b8f16e
JB		 8038}
8039
8040
8041static int elf32_arm_compare_mapping (const void * a, const void * b);
8042
8043
8044/* Look for potentially-troublesome code sequences which might trigger the
8045 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8046 (available from ARM) for details of the erratum. A short version is
8047 described in ld.texinfo. */
8048
8049bfd_boolean
8050bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8051{
8052 asection *sec;
8053 bfd_byte *contents = NULL;
8054 int state = 0;
8055 int regs[3], numregs = 0;
8056 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8057 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8058
4dfe6ac6
NC		 8059 if (globals == NULL)
8060 return FALSE;
8061
c7b8f16e
JB		 8062 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8063 The states transition as follows:
906e58ca 8064
c7b8f16e 8065 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8066 A VFP FMAC-pipeline instruction has been seen. Fill
8067 regs[0]..regs[numregs-1] with its input operands. Remember this
8068 instruction in 'first_fmac'.
c7b8f16e
JB		 8069
8070 1 -> 2
99059e56
RM		 8071 Any instruction, except for a VFP instruction which overwrites
8072 regs[*].
906e58ca 8073
c7b8f16e
JB		 8074 1 -> 3 [ -> 0 ] or
8075 2 -> 3 [ -> 0 ]
99059e56
RM		 8076 A VFP instruction has been seen which overwrites any of regs[*].
8077 We must make a veneer! Reset state to 0 before examining next
8078 instruction.
906e58ca 8079
c7b8f16e 8080 2 -> 0
99059e56
RM		 8081 If we fail to match anything in state 2, reset to state 0 and reset
8082 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8083
8084 If the VFP11 vector mode is in use, there must be at least two unrelated
8085 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8086 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8087
8088 /* If we are only performing a partial link do not bother
8089 to construct any glue. */
0e1862bb 8090 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8091 return TRUE;
8092
0ffa91dd
NC		 8093 /* Skip if this bfd does not correspond to an ELF image. */
8094 if (! is_arm_elf (abfd))
8095 return TRUE;
906e58ca 8096
c7b8f16e
JB		 8097 /* We should have chosen a fix type by the time we get here. */
8098 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8099
8100 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8101 return TRUE;
2e6030b9 8102
33a7ffc2
JM		 8103 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8104 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8105 return TRUE;
8106
c7b8f16e
JB		 8107 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8108 {
8109 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8110 struct _arm_elf_section_data *sec_data;
8111
8112 /* If we don't have executable progbits, we're not interested in this
99059e56 8113 section. Also skip if section is to be excluded. */
c7b8f16e 8114 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8115 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8116 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8117 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8118 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8119 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8120 continue;
c7b8f16e
JB		 8121
8122 sec_data = elf32_arm_section_data (sec);
906e58ca 8123
c7b8f16e 8124 if (sec_data->mapcount == 0)
99059e56 8125 continue;
906e58ca 8126
c7b8f16e
JB		 8127 if (elf_section_data (sec)->this_hdr.contents != NULL)
8128 contents = elf_section_data (sec)->this_hdr.contents;
8129 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8130 goto error_return;
8131
8132 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8133 elf32_arm_compare_mapping);
8134
8135 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8136 {
8137 unsigned int span_start = sec_data->map[span].vma;
8138 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8139 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8140 char span_type = sec_data->map[span].type;
8141
8142 /* FIXME: Only ARM mode is supported at present. We may need to
8143 support Thumb-2 mode also at some point. */
8144 if (span_type != 'a')
8145 continue;
8146
8147 for (i = span_start; i < span_end;)
8148 {
8149 unsigned int next_i = i + 4;
8150 unsigned int insn = bfd_big_endian (abfd)
8151 ? (contents[i] << 24)
8152 | (contents[i + 1] << 16)
8153 | (contents[i + 2] << 8)
8154 | contents[i + 3]
8155 : (contents[i + 3] << 24)
8156 | (contents[i + 2] << 16)
8157 | (contents[i + 1] << 8)
8158 | contents[i];
8159 unsigned int writemask = 0;
8160 enum bfd_arm_vfp11_pipe vpipe;
8161
8162 switch (state)
8163 {
8164 case 0:
8165 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8166 &numregs);
8167 /* I'm assuming the VFP11 erratum can trigger with denorm
8168 operands on either the FMAC or the DS pipeline. This might
8169 lead to slightly overenthusiastic veneer insertion. */
8170 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8171 {
8172 state = use_vector ? 1 : 2;
8173 first_fmac = i;
8174 veneer_of_insn = insn;
8175 }
8176 break;
8177
8178 case 1:
8179 {
8180 int other_regs[3], other_numregs;
8181 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8182 other_regs,
99059e56
RM		 8183 &other_numregs);
8184 if (vpipe != VFP11_BAD
8185 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8186 numregs))
99059e56
RM		 8187 state = 3;
8188 else
8189 state = 2;
8190 }
8191 break;
8192
8193 case 2:
8194 {
8195 int other_regs[3], other_numregs;
8196 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8197 other_regs,
99059e56
RM		 8198 &other_numregs);
8199 if (vpipe != VFP11_BAD
8200 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8201 numregs))
99059e56
RM		 8202 state = 3;
8203 else
8204 {
8205 state = 0;
8206 next_i = first_fmac + 4;
8207 }
8208 }
8209 break;
8210
8211 case 3:
8212 abort (); /* Should be unreachable. */
8213 }
8214
8215 if (state == 3)
8216 {
8217 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8218 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8219
8220 elf32_arm_section_data (sec)->erratumcount += 1;
8221
8222 newerr->u.b.vfp_insn = veneer_of_insn;
8223
8224 switch (span_type)
8225 {
8226 case 'a':
8227 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8228 break;
8229
8230 default:
8231 abort ();
8232 }
8233
8234 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8235 first_fmac);
8236
99059e56 8237 newerr->vma = -1;
c7b8f16e 8238
99059e56
RM		 8239 newerr->next = sec_data->erratumlist;
8240 sec_data->erratumlist = newerr;
c7b8f16e 8241
99059e56
RM		 8242 state = 0;
8243 }
c7b8f16e 8244
99059e56
RM		 8245 i = next_i;
8246 }
8247 }
906e58ca 8248
c7b8f16e 8249 if (contents != NULL
99059e56
RM		 8250 && elf_section_data (sec)->this_hdr.contents != contents)
8251 free (contents);
c7b8f16e
JB		 8252 contents = NULL;
8253 }
8254
8255 return TRUE;
8256
8257error_return:
8258 if (contents != NULL
8259 && elf_section_data (sec)->this_hdr.contents != contents)
8260 free (contents);
906e58ca 8261
c7b8f16e
JB		 8262 return FALSE;
8263}
8264
8265/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8266 after sections have been laid out, using specially-named symbols. */
8267
8268void
8269bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8270 struct bfd_link_info *link_info)
8271{
8272 asection *sec;
8273 struct elf32_arm_link_hash_table *globals;
8274 char *tmp_name;
906e58ca 8275
0e1862bb 8276 if (bfd_link_relocatable (link_info))
c7b8f16e 8277 return;
2e6030b9
MS		 8278
8279 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8280 if (! is_arm_elf (abfd))
2e6030b9
MS		 8281 return;
8282
c7b8f16e 8283 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8284 if (globals == NULL)
8285 return;
906e58ca 8286
21d799b5 8287 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8288 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8289
8290 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8291 {
8292 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8293 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8294
c7b8f16e 8295 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8296 {
8297 struct elf_link_hash_entry *myh;
8298 bfd_vma vma;
8299
8300 switch (errnode->type)
8301 {
8302 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8303 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8304 /* Find veneer symbol. */
8305 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8306 errnode->u.b.veneer->u.v.id);
8307
99059e56
RM		 8308 myh = elf_link_hash_lookup
8309 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8310
a504d23a 8311 if (myh == NULL)
4eca0228
AM		 8312 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8313 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8314
8315 vma = myh->root.u.def.section->output_section->vma
8316 + myh->root.u.def.section->output_offset
8317 + myh->root.u.def.value;
8318
8319 errnode->u.b.veneer->vma = vma;
8320 break;
8321
8322 case VFP11_ERRATUM_ARM_VENEER:
8323 case VFP11_ERRATUM_THUMB_VENEER:
8324 /* Find return location. */
8325 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8326 errnode->u.v.id);
8327
8328 myh = elf_link_hash_lookup
8329 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8330
8331 if (myh == NULL)
4eca0228
AM		 8332 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8333 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8334
8335 vma = myh->root.u.def.section->output_section->vma
8336 + myh->root.u.def.section->output_offset
8337 + myh->root.u.def.value;
8338
8339 errnode->u.v.branch->vma = vma;
8340 break;
8341
8342 default:
8343 abort ();
8344 }
8345 }
8346 }
8347
8348 free (tmp_name);
8349}
8350
8351/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8352 return locations after sections have been laid out, using
8353 specially-named symbols. */
8354
8355void
8356bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8357 struct bfd_link_info *link_info)
8358{
8359 asection *sec;
8360 struct elf32_arm_link_hash_table *globals;
8361 char *tmp_name;
8362
8363 if (bfd_link_relocatable (link_info))
8364 return;
8365
8366 /* Skip if this bfd does not correspond to an ELF image. */
8367 if (! is_arm_elf (abfd))
8368 return;
8369
8370 globals = elf32_arm_hash_table (link_info);
8371 if (globals == NULL)
8372 return;
8373
8374 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8375 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8376
8377 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8378 {
8379 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8380 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8381
8382 for (; errnode != NULL; errnode = errnode->next)
8383 {
8384 struct elf_link_hash_entry *myh;
8385 bfd_vma vma;
8386
8387 switch (errnode->type)
8388 {
8389 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8390 /* Find veneer symbol. */
8391 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8392 errnode->u.b.veneer->u.v.id);
8393
8394 myh = elf_link_hash_lookup
8395 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8396
8397 if (myh == NULL)
4eca0228
AM		 8398 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8399 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8400
8401 vma = myh->root.u.def.section->output_section->vma
8402 + myh->root.u.def.section->output_offset
8403 + myh->root.u.def.value;
8404
8405 errnode->u.b.veneer->vma = vma;
8406 break;
8407
8408 case STM32L4XX_ERRATUM_VENEER:
8409 /* Find return location. */
8410 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8411 errnode->u.v.id);
8412
8413 myh = elf_link_hash_lookup
8414 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8415
8416 if (myh == NULL)
4eca0228
AM		 8417 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8418 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8419
8420 vma = myh->root.u.def.section->output_section->vma
8421 + myh->root.u.def.section->output_offset
8422 + myh->root.u.def.value;
8423
8424 errnode->u.v.branch->vma = vma;
8425 break;
8426
8427 default:
8428 abort ();
8429 }
8430 }
8431 }
8432
8433 free (tmp_name);
8434}
8435
8436static inline bfd_boolean
8437is_thumb2_ldmia (const insn32 insn)
8438{
8439 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8440 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8441 return (insn & 0xffd02000) == 0xe8900000;
8442}
8443
8444static inline bfd_boolean
8445is_thumb2_ldmdb (const insn32 insn)
8446{
8447 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8448 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8449 return (insn & 0xffd02000) == 0xe9100000;
8450}
8451
8452static inline bfd_boolean
8453is_thumb2_vldm (const insn32 insn)
8454{
8455 /* A6.5 Extension register load or store instruction
8456 A7.7.229
9239bbd3
CM		 8457 We look for SP 32-bit and DP 64-bit registers.
8458 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8459 <list> is consecutive 64-bit registers
8460 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8461 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8462 <list> is consecutive 32-bit registers
8463 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8464 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8465 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8466 return
9239bbd3
CM		 8467 (((insn & 0xfe100f00) == 0xec100b00) ||
8468 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8469 && /* (IA without !). */
8470 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8471 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8472 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8473 /* (DB with !). */
8474 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8475}
8476
8477/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8478 VLDM opcode and:
8479 - computes the number and the mode of memory accesses
8480 - decides if the replacement should be done:
8481 . replaces only if > 8-word accesses
8482 . or (testing purposes only) replaces all accesses. */
8483
8484static bfd_boolean
8485stm32l4xx_need_create_replacing_stub (const insn32 insn,
8486 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8487{
9239bbd3 8488 int nb_words = 0;
a504d23a
LA		 8489
8490 /* The field encoding the register list is the same for both LDMIA
8491 and LDMDB encodings. */
8492 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8493 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8494 else if (is_thumb2_vldm (insn))
9239bbd3 8495 nb_words = (insn & 0xff);
a504d23a
LA		 8496
8497 /* DEFAULT mode accounts for the real bug condition situation,
8498 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8499 return
9239bbd3 8500 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8501 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8502}
8503
8504/* Look for potentially-troublesome code sequences which might trigger
8505 the STM STM32L4XX erratum. */
8506
8507bfd_boolean
8508bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8509 struct bfd_link_info *link_info)
8510{
8511 asection *sec;
8512 bfd_byte *contents = NULL;
8513 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8514
8515 if (globals == NULL)
8516 return FALSE;
8517
8518 /* If we are only performing a partial link do not bother
8519 to construct any glue. */
8520 if (bfd_link_relocatable (link_info))
8521 return TRUE;
8522
8523 /* Skip if this bfd does not correspond to an ELF image. */
8524 if (! is_arm_elf (abfd))
8525 return TRUE;
8526
8527 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8528 return TRUE;
8529
8530 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8531 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8532 return TRUE;
8533
8534 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8535 {
8536 unsigned int i, span;
8537 struct _arm_elf_section_data *sec_data;
8538
8539 /* If we don't have executable progbits, we're not interested in this
8540 section. Also skip if section is to be excluded. */
8541 if (elf_section_type (sec) != SHT_PROGBITS
8542 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8543 || (sec->flags & SEC_EXCLUDE) != 0
8544 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8545 || sec->output_section == bfd_abs_section_ptr
8546 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8547 continue;
8548
8549 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8550
a504d23a
LA		 8551 if (sec_data->mapcount == 0)
8552 continue;
c7b8f16e 8553
a504d23a
LA		 8554 if (elf_section_data (sec)->this_hdr.contents != NULL)
8555 contents = elf_section_data (sec)->this_hdr.contents;
8556 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8557 goto error_return;
c7b8f16e 8558
a504d23a
LA		 8559 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8560 elf32_arm_compare_mapping);
c7b8f16e 8561
a504d23a
LA		 8562 for (span = 0; span < sec_data->mapcount; span++)
8563 {
8564 unsigned int span_start = sec_data->map[span].vma;
8565 unsigned int span_end = (span == sec_data->mapcount - 1)
8566 ? sec->size : sec_data->map[span + 1].vma;
8567 char span_type = sec_data->map[span].type;
8568 int itblock_current_pos = 0;
c7b8f16e 8569
a504d23a
LA		 8570 /* Only Thumb2 mode need be supported with this CM4 specific
8571 code, we should not encounter any arm mode eg span_type
8572 != 'a'. */
8573 if (span_type != 't')
8574 continue;
c7b8f16e 8575
a504d23a
LA		 8576 for (i = span_start; i < span_end;)
8577 {
8578 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8579 bfd_boolean insn_32bit = FALSE;
8580 bfd_boolean is_ldm = FALSE;
8581 bfd_boolean is_vldm = FALSE;
8582 bfd_boolean is_not_last_in_it_block = FALSE;
8583
8584 /* The first 16-bits of all 32-bit thumb2 instructions start
8585 with opcode[15..13]=0b111 and the encoded op1 can be anything
8586 except opcode[12..11]!=0b00.
8587 See 32-bit Thumb instruction encoding. */
8588 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8589 insn_32bit = TRUE;
c7b8f16e 8590
a504d23a
LA		 8591 /* Compute the predicate that tells if the instruction
8592 is concerned by the IT block
8593 - Creates an error if there is a ldm that is not
8594 last in the IT block thus cannot be replaced
8595 - Otherwise we can create a branch at the end of the
8596 IT block, it will be controlled naturally by IT
8597 with the proper pseudo-predicate
8598 - So the only interesting predicate is the one that
8599 tells that we are not on the last item of an IT
8600 block. */
8601 if (itblock_current_pos != 0)
8602 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8603
a504d23a
LA		 8604 if (insn_32bit)
8605 {
8606 /* Load the rest of the insn (in manual-friendly order). */
8607 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8608 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8609 is_vldm = is_thumb2_vldm (insn);
8610
8611 /* Veneers are created for (v)ldm depending on
8612 option flags and memory accesses conditions; but
8613 if the instruction is not the last instruction of
8614 an IT block, we cannot create a jump there, so we
8615 bail out. */
5025eb7c
AO		 8616 if ((is_ldm || is_vldm)
8617 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8618 (insn, globals->stm32l4xx_fix))
8619 {
8620 if (is_not_last_in_it_block)
8621 {
4eca0228 8622 _bfd_error_handler
a504d23a 8623 /* Note - overlong line used here to allow for translation. */
695344c0 8624 /* xgettext:c-format */
a504d23a
LA		 8625 (_("\
8626%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8627 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
695344c0 8628 abfd, sec, (long) i);
a504d23a
LA		 8629 }
8630 else
8631 {
8632 elf32_stm32l4xx_erratum_list *newerr =
8633 (elf32_stm32l4xx_erratum_list *)
8634 bfd_zmalloc
8635 (sizeof (elf32_stm32l4xx_erratum_list));
8636
8637 elf32_arm_section_data (sec)
8638 ->stm32l4xx_erratumcount += 1;
8639 newerr->u.b.insn = insn;
8640 /* We create only thumb branches. */
8641 newerr->type =
8642 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8643 record_stm32l4xx_erratum_veneer
8644 (link_info, newerr, abfd, sec,
8645 i,
8646 is_ldm ?
8647 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8648 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8649 newerr->vma = -1;
8650 newerr->next = sec_data->stm32l4xx_erratumlist;
8651 sec_data->stm32l4xx_erratumlist = newerr;
8652 }
8653 }
8654 }
8655 else
8656 {
8657 /* A7.7.37 IT p208
8658 IT blocks are only encoded in T1
8659 Encoding T1: IT{x{y{z}}} <firstcond>
8660 1 0 1 1 - 1 1 1 1 - firstcond - mask
8661 if mask = '0000' then see 'related encodings'
8662 We don't deal with UNPREDICTABLE, just ignore these.
8663 There can be no nested IT blocks so an IT block
8664 is naturally a new one for which it is worth
8665 computing its size. */
5025eb7c
AO		 8666 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8667 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8668 /* If we have a new IT block we compute its size. */
8669 if (is_newitblock)
8670 {
8671 /* Compute the number of instructions controlled
8672 by the IT block, it will be used to decide
8673 whether we are inside an IT block or not. */
8674 unsigned int mask = insn & 0x000f;
8675 itblock_current_pos = 4 - ctz (mask);
8676 }
8677 }
8678
8679 i += insn_32bit ? 4 : 2;
99059e56
RM		 8680 }
8681 }
a504d23a
LA		 8682
8683 if (contents != NULL
8684 && elf_section_data (sec)->this_hdr.contents != contents)
8685 free (contents);
8686 contents = NULL;
c7b8f16e 8687 }
906e58ca 8688
a504d23a
LA		 8689 return TRUE;
8690
8691error_return:
8692 if (contents != NULL
8693 && elf_section_data (sec)->this_hdr.contents != contents)
8694 free (contents);
c7b8f16e 8695
a504d23a
LA		 8696 return FALSE;
8697}
c7b8f16e 8698
eb043451
PB		 8699/* Set target relocation values needed during linking. */
8700
8701void
68c39892 8702bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8703 struct bfd_link_info *link_info,
68c39892 8704 struct elf32_arm_params *params)
eb043451
PB		 8705{
8706 struct elf32_arm_link_hash_table *globals;
8707
8708 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8709 if (globals == NULL)
8710 return;
eb043451 8711
68c39892
TP		 8712 globals->target1_is_rel = params->target1_is_rel;
8713 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8714 globals->target2_reloc = R_ARM_REL32;
68c39892 8715 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8716 globals->target2_reloc = R_ARM_ABS32;
68c39892 8717 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8718 globals->target2_reloc = R_ARM_GOT_PREL;
8719 else
8720 {
8721 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8722 params->target2_type);
eb043451 8723 }
68c39892
TP		 8724 globals->fix_v4bx = params->fix_v4bx;
8725 globals->use_blx |= params->use_blx;
8726 globals->vfp11_fix = params->vfp11_denorm_fix;
8727 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8728 globals->pic_veneer = params->pic_veneer;
8729 globals->fix_cortex_a8 = params->fix_cortex_a8;
8730 globals->fix_arm1176 = params->fix_arm1176;
8731 globals->cmse_implib = params->cmse_implib;
8732 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8733
0ffa91dd 8734 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8735 elf_arm_tdata (output_bfd)->no_enum_size_warning
8736 = params->no_enum_size_warning;
8737 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8738 = params->no_wchar_size_warning;
eb043451 8739}
eb043451 8740
12a0a0fd 8741/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8742
12a0a0fd
PB		 8743static void
8744insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8745{
8746 bfd_vma upper;
8747 bfd_vma lower;
8748 int reloc_sign;
8749
8750 BFD_ASSERT ((offset & 1) == 0);
8751
8752 upper = bfd_get_16 (abfd, insn);
8753 lower = bfd_get_16 (abfd, insn + 2);
8754 reloc_sign = (offset < 0) ? 1 : 0;
8755 upper = (upper & ~(bfd_vma) 0x7ff)
8756 | ((offset >> 12) & 0x3ff)
8757 | (reloc_sign << 10);
906e58ca 8758 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8759 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8760 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8761 | ((offset >> 1) & 0x7ff);
8762 bfd_put_16 (abfd, upper, insn);
8763 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8764}
8765
9b485d32
NC		 8766/* Thumb code calling an ARM function. */
8767
252b5132 8768static int
57e8b36a
NC		 8769elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8770 const char * name,
8771 bfd * input_bfd,
8772 bfd * output_bfd,
8773 asection * input_section,
8774 bfd_byte * hit_data,
8775 asection * sym_sec,
8776 bfd_vma offset,
8777 bfd_signed_vma addend,
f2a9dd69
DJ		 8778 bfd_vma val,
8779 char **error_message)
252b5132 8780{
bcbdc74c 8781 asection * s = 0;
dc810e39 8782 bfd_vma my_offset;
252b5132 8783 long int ret_offset;
bcbdc74c
NC		 8784 struct elf_link_hash_entry * myh;
8785 struct elf32_arm_link_hash_table * globals;
252b5132 8786
f2a9dd69 8787 myh = find_thumb_glue (info, name, error_message);
252b5132 8788 if (myh == NULL)
b34976b6 8789 return FALSE;
252b5132
RH		 8790
8791 globals = elf32_arm_hash_table (info);
252b5132
RH		 8792 BFD_ASSERT (globals != NULL);
8793 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8794
8795 my_offset = myh->root.u.def.value;
8796
3d4d4302
AM		 8797 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8798 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8799
8800 BFD_ASSERT (s != NULL);
8801 BFD_ASSERT (s->contents != NULL);
8802 BFD_ASSERT (s->output_section != NULL);
8803
8804 if ((my_offset & 0x01) == 0x01)
8805 {
8806 if (sym_sec != NULL
8807 && sym_sec->owner != NULL
8808 && !INTERWORK_FLAG (sym_sec->owner))
8809 {
4eca0228 8810 _bfd_error_handler
d003868e 8811 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8812 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 8813 sym_sec->owner, name, input_bfd);
252b5132 8814
b34976b6 8815 return FALSE;
252b5132
RH		 8816 }
8817
8818 --my_offset;
8819 myh->root.u.def.value = my_offset;
8820
52ab56c2
PB		 8821 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8822 s->contents + my_offset);
252b5132 8823
52ab56c2
PB		 8824 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8825 s->contents + my_offset + 2);
252b5132
RH		 8826
8827 ret_offset =
9b485d32
NC		 8828 /* Address of destination of the stub. */
8829 ((bfd_signed_vma) val)
252b5132 8830 - ((bfd_signed_vma)
57e8b36a
NC		 8831 /* Offset from the start of the current section
8832 to the start of the stubs. */
9b485d32
NC		 8833 (s->output_offset
8834 /* Offset of the start of this stub from the start of the stubs. */
8835 + my_offset
8836 /* Address of the start of the current section. */
8837 + s->output_section->vma)
8838 /* The branch instruction is 4 bytes into the stub. */
8839 + 4
8840 /* ARM branches work from the pc of the instruction + 8. */
8841 + 8);
252b5132 8842
52ab56c2
PB		 8843 put_arm_insn (globals, output_bfd,
8844 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8845 s->contents + my_offset + 4);
252b5132
RH		 8846 }
8847
8848 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8849
427bfd90
NC		 8850 /* Now go back and fix up the original BL insn to point to here. */
8851 ret_offset =
8852 /* Address of where the stub is located. */
8853 (s->output_section->vma + s->output_offset + my_offset)
8854 /* Address of where the BL is located. */
57e8b36a
NC		 8855 - (input_section->output_section->vma + input_section->output_offset
8856 + offset)
427bfd90
NC		 8857 /* Addend in the relocation. */
8858 - addend
8859 /* Biassing for PC-relative addressing. */
8860 - 8;
252b5132 8861
12a0a0fd 8862 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8863
b34976b6 8864 return TRUE;
252b5132
RH		 8865}
8866
a4fd1a8e 8867/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8868
a4fd1a8e
PB		 8869static struct elf_link_hash_entry *
8870elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8871 const char * name,
8872 bfd * input_bfd,
8873 bfd * output_bfd,
8874 asection * sym_sec,
8875 bfd_vma val,
8029a119
NC		 8876 asection * s,
8877 char ** error_message)
252b5132 8878{
dc810e39 8879 bfd_vma my_offset;
252b5132 8880 long int ret_offset;
bcbdc74c
NC		 8881 struct elf_link_hash_entry * myh;
8882 struct elf32_arm_link_hash_table * globals;
252b5132 8883
f2a9dd69 8884 myh = find_arm_glue (info, name, error_message);
252b5132 8885 if (myh == NULL)
a4fd1a8e 8886 return NULL;
252b5132
RH		 8887
8888 globals = elf32_arm_hash_table (info);
252b5132
RH		 8889 BFD_ASSERT (globals != NULL);
8890 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8891
8892 my_offset = myh->root.u.def.value;
252b5132
RH		 8893
8894 if ((my_offset & 0x01) == 0x01)
8895 {
8896 if (sym_sec != NULL
8897 && sym_sec->owner != NULL
8898 && !INTERWORK_FLAG (sym_sec->owner))
8899 {
4eca0228 8900 _bfd_error_handler
d003868e
AM		 8901 (_("%B(%s): warning: interworking not enabled.\n"
8902 " first occurrence: %B: arm call to thumb"),
c08bb8dd 8903 sym_sec->owner, name, input_bfd);
252b5132 8904 }
9b485d32 8905
252b5132
RH		 8906 --my_offset;
8907 myh->root.u.def.value = my_offset;
8908
0e1862bb
L		 8909 if (bfd_link_pic (info)
8910 || globals->root.is_relocatable_executable
27e55c4d 8911 || globals->pic_veneer)
8f6277f5
PB		 8912 {
8913 /* For relocatable objects we can't use absolute addresses,
8914 so construct the address from a relative offset. */
8915 /* TODO: If the offset is small it's probably worth
8916 constructing the address with adds. */
52ab56c2
PB		 8917 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8918 s->contents + my_offset);
8919 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8920 s->contents + my_offset + 4);
8921 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8922 s->contents + my_offset + 8);
8f6277f5
PB		 8923 /* Adjust the offset by 4 for the position of the add,
8924 and 8 for the pipeline offset. */
8925 ret_offset = (val - (s->output_offset
8926 + s->output_section->vma
8927 + my_offset + 12))
8928 | 1;
8929 bfd_put_32 (output_bfd, ret_offset,
8930 s->contents + my_offset + 12);
8931 }
26079076
PB		 8932 else if (globals->use_blx)
8933 {
8934 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8935 s->contents + my_offset);
8936
8937 /* It's a thumb address. Add the low order bit. */
8938 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8939 s->contents + my_offset + 4);
8940 }
8f6277f5
PB		 8941 else
8942 {
52ab56c2
PB		 8943 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8944 s->contents + my_offset);
252b5132 8945
52ab56c2
PB		 8946 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8947 s->contents + my_offset + 4);
252b5132 8948
8f6277f5
PB		 8949 /* It's a thumb address. Add the low order bit. */
8950 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8951 s->contents + my_offset + 8);
8029a119
NC		 8952
8953 my_offset += 12;
8f6277f5 8954 }
252b5132
RH		 8955 }
8956
8957 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8958
a4fd1a8e
PB		 8959 return myh;
8960}
8961
8962/* Arm code calling a Thumb function. */
8963
8964static int
8965elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8966 const char * name,
8967 bfd * input_bfd,
8968 bfd * output_bfd,
8969 asection * input_section,
8970 bfd_byte * hit_data,
8971 asection * sym_sec,
8972 bfd_vma offset,
8973 bfd_signed_vma addend,
f2a9dd69
DJ		 8974 bfd_vma val,
8975 char **error_message)
a4fd1a8e
PB		 8976{
8977 unsigned long int tmp;
8978 bfd_vma my_offset;
8979 asection * s;
8980 long int ret_offset;
8981 struct elf_link_hash_entry * myh;
8982 struct elf32_arm_link_hash_table * globals;
8983
8984 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8985 BFD_ASSERT (globals != NULL);
8986 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8987
3d4d4302
AM		 8988 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8989 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8990 BFD_ASSERT (s != NULL);
8991 BFD_ASSERT (s->contents != NULL);
8992 BFD_ASSERT (s->output_section != NULL);
8993
8994 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8995 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8996 if (!myh)
8997 return FALSE;
8998
8999 my_offset = myh->root.u.def.value;
252b5132
RH		 9000 tmp = bfd_get_32 (input_bfd, hit_data);
9001 tmp = tmp & 0xFF000000;
9002
9b485d32 9003 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9004 ret_offset = (s->output_offset
9005 + my_offset
9006 + s->output_section->vma
9007 - (input_section->output_offset
9008 + input_section->output_section->vma
9009 + offset + addend)
9010 - 8);
9a5aca8c 9011
252b5132
RH		 9012 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9013
dc810e39 9014 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9015
b34976b6 9016 return TRUE;
252b5132
RH		 9017}
9018
a4fd1a8e
PB		 9019/* Populate Arm stub for an exported Thumb function. */
9020
9021static bfd_boolean
9022elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9023{
9024 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9025 asection * s;
9026 struct elf_link_hash_entry * myh;
9027 struct elf32_arm_link_hash_entry *eh;
9028 struct elf32_arm_link_hash_table * globals;
9029 asection *sec;
9030 bfd_vma val;
f2a9dd69 9031 char *error_message;
a4fd1a8e 9032
906e58ca 9033 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9034 /* Allocate stubs for exported Thumb functions on v4t. */
9035 if (eh->export_glue == NULL)
9036 return TRUE;
9037
9038 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9039 BFD_ASSERT (globals != NULL);
9040 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9041
3d4d4302
AM		 9042 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9043 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9044 BFD_ASSERT (s != NULL);
9045 BFD_ASSERT (s->contents != NULL);
9046 BFD_ASSERT (s->output_section != NULL);
9047
9048 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9049
9050 BFD_ASSERT (sec->output_section != NULL);
9051
a4fd1a8e
PB		 9052 val = eh->export_glue->root.u.def.value + sec->output_offset
9053 + sec->output_section->vma;
8029a119 9054
a4fd1a8e
PB		 9055 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9056 h->root.u.def.section->owner,
f2a9dd69
DJ		 9057 globals->obfd, sec, val, s,
9058 &error_message);
a4fd1a8e
PB		 9059 BFD_ASSERT (myh);
9060 return TRUE;
9061}
9062
845b51d6
PB		 9063/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9064
9065static bfd_vma
9066elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9067{
9068 bfd_byte *p;
9069 bfd_vma glue_addr;
9070 asection *s;
9071 struct elf32_arm_link_hash_table *globals;
9072
9073 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9074 BFD_ASSERT (globals != NULL);
9075 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9076
3d4d4302
AM		 9077 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9078 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9079 BFD_ASSERT (s != NULL);
9080 BFD_ASSERT (s->contents != NULL);
9081 BFD_ASSERT (s->output_section != NULL);
9082
9083 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9084
9085 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9086
9087 if ((globals->bx_glue_offset[reg] & 1) == 0)
9088 {
9089 p = s->contents + glue_addr;
9090 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9091 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9092 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9093 globals->bx_glue_offset[reg] |= 1;
9094 }
9095
9096 return glue_addr + s->output_section->vma + s->output_offset;
9097}
9098
a4fd1a8e
PB		 9099/* Generate Arm stubs for exported Thumb symbols. */
9100static void
906e58ca 9101elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9102 struct bfd_link_info *link_info)
9103{
9104 struct elf32_arm_link_hash_table * globals;
9105
8029a119
NC		 9106 if (link_info == NULL)
9107 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9108 return;
9109
9110 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9111 if (globals == NULL)
9112 return;
9113
84c08195
PB		 9114 /* If blx is available then exported Thumb symbols are OK and there is
9115 nothing to do. */
a4fd1a8e
PB		 9116 if (globals->use_blx)
9117 return;
9118
9119 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9120 link_info);
9121}
9122
47beaa6a
RS		 9123/* Reserve space for COUNT dynamic relocations in relocation selection
9124 SRELOC. */
9125
9126static void
9127elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9128 bfd_size_type count)
9129{
9130 struct elf32_arm_link_hash_table *htab;
9131
9132 htab = elf32_arm_hash_table (info);
9133 BFD_ASSERT (htab->root.dynamic_sections_created);
9134 if (sreloc == NULL)
9135 abort ();
9136 sreloc->size += RELOC_SIZE (htab) * count;
9137}
9138
34e77a92
RS		 9139/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9140 dynamic, the relocations should go in SRELOC, otherwise they should
9141 go in the special .rel.iplt section. */
9142
9143static void
9144elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9145 bfd_size_type count)
9146{
9147 struct elf32_arm_link_hash_table *htab;
9148
9149 htab = elf32_arm_hash_table (info);
9150 if (!htab->root.dynamic_sections_created)
9151 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9152 else
9153 {
9154 BFD_ASSERT (sreloc != NULL);
9155 sreloc->size += RELOC_SIZE (htab) * count;
9156 }
9157}
9158
47beaa6a
RS		 9159/* Add relocation REL to the end of relocation section SRELOC. */
9160
9161static void
9162elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9163 asection *sreloc, Elf_Internal_Rela *rel)
9164{
9165 bfd_byte *loc;
9166 struct elf32_arm_link_hash_table *htab;
9167
9168 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9169 if (!htab->root.dynamic_sections_created
9170 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9171 sreloc = htab->root.irelplt;
47beaa6a
RS		 9172 if (sreloc == NULL)
9173 abort ();
9174 loc = sreloc->contents;
9175 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9176 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9177 abort ();
9178 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9179}
9180
34e77a92
RS		 9181/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9182 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9183 to .plt. */
9184
9185static void
9186elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9187 bfd_boolean is_iplt_entry,
9188 union gotplt_union *root_plt,
9189 struct arm_plt_info *arm_plt)
9190{
9191 struct elf32_arm_link_hash_table *htab;
9192 asection *splt;
9193 asection *sgotplt;
9194
9195 htab = elf32_arm_hash_table (info);
9196
9197 if (is_iplt_entry)
9198 {
9199 splt = htab->root.iplt;
9200 sgotplt = htab->root.igotplt;
9201
99059e56
RM		 9202 /* NaCl uses a special first entry in .iplt too. */
9203 if (htab->nacl_p && splt->size == 0)
9204 splt->size += htab->plt_header_size;
9205
34e77a92
RS		 9206 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9207 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9208 }
9209 else
9210 {
9211 splt = htab->root.splt;
9212 sgotplt = htab->root.sgotplt;
9213
9214 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9215 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9216
9217 /* If this is the first .plt entry, make room for the special
9218 first entry. */
9219 if (splt->size == 0)
9220 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9221
9222 htab->next_tls_desc_index++;
34e77a92
RS		 9223 }
9224
9225 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9226 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9227 splt->size += PLT_THUMB_STUB_SIZE;
9228 root_plt->offset = splt->size;
9229 splt->size += htab->plt_entry_size;
9230
9231 if (!htab->symbian_p)
9232 {
9233 /* We also need to make an entry in the .got.plt section, which
9234 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9235 if (is_iplt_entry)
9236 arm_plt->got_offset = sgotplt->size;
9237 else
9238 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9239 sgotplt->size += 4;
9240 }
9241}
9242
b38cadfb
NC		 9243static bfd_vma
9244arm_movw_immediate (bfd_vma value)
9245{
9246 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9247}
9248
9249static bfd_vma
9250arm_movt_immediate (bfd_vma value)
9251{
9252 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9253}
9254
34e77a92
RS		 9255/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9256 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9257 Otherwise, DYNINDX is the index of the symbol in the dynamic
9258 symbol table and SYM_VALUE is undefined.
9259
9260 ROOT_PLT points to the offset of the PLT entry from the start of its
9261 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9262 bookkeeping information.
34e77a92 9263
57460bcf
NC		 9264 Returns FALSE if there was a problem. */
9265
9266static bfd_boolean
34e77a92
RS		 9267elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9268 union gotplt_union *root_plt,
9269 struct arm_plt_info *arm_plt,
9270 int dynindx, bfd_vma sym_value)
9271{
9272 struct elf32_arm_link_hash_table *htab;
9273 asection *sgot;
9274 asection *splt;
9275 asection *srel;
9276 bfd_byte *loc;
9277 bfd_vma plt_index;
9278 Elf_Internal_Rela rel;
9279 bfd_vma plt_header_size;
9280 bfd_vma got_header_size;
9281
9282 htab = elf32_arm_hash_table (info);
9283
9284 /* Pick the appropriate sections and sizes. */
9285 if (dynindx == -1)
9286 {
9287 splt = htab->root.iplt;
9288 sgot = htab->root.igotplt;
9289 srel = htab->root.irelplt;
9290
9291 /* There are no reserved entries in .igot.plt, and no special
9292 first entry in .iplt. */
9293 got_header_size = 0;
9294 plt_header_size = 0;
9295 }
9296 else
9297 {
9298 splt = htab->root.splt;
9299 sgot = htab->root.sgotplt;
9300 srel = htab->root.srelplt;
9301
9302 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9303 plt_header_size = htab->plt_header_size;
9304 }
9305 BFD_ASSERT (splt != NULL && srel != NULL);
9306
9307 /* Fill in the entry in the procedure linkage table. */
9308 if (htab->symbian_p)
9309 {
9310 BFD_ASSERT (dynindx >= 0);
9311 put_arm_insn (htab, output_bfd,
9312 elf32_arm_symbian_plt_entry[0],
9313 splt->contents + root_plt->offset);
9314 bfd_put_32 (output_bfd,
9315 elf32_arm_symbian_plt_entry[1],
9316 splt->contents + root_plt->offset + 4);
9317
9318 /* Fill in the entry in the .rel.plt section. */
9319 rel.r_offset = (splt->output_section->vma
9320 + splt->output_offset
9321 + root_plt->offset + 4);
9322 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9323
9324 /* Get the index in the procedure linkage table which
9325 corresponds to this symbol. This is the index of this symbol
9326 in all the symbols for which we are making plt entries. The
9327 first entry in the procedure linkage table is reserved. */
9328 plt_index = ((root_plt->offset - plt_header_size)
9329 / htab->plt_entry_size);
9330 }
9331 else
9332 {
9333 bfd_vma got_offset, got_address, plt_address;
9334 bfd_vma got_displacement, initial_got_entry;
9335 bfd_byte * ptr;
9336
9337 BFD_ASSERT (sgot != NULL);
9338
9339 /* Get the offset into the .(i)got.plt table of the entry that
9340 corresponds to this function. */
9341 got_offset = (arm_plt->got_offset & -2);
9342
9343 /* Get the index in the procedure linkage table which
9344 corresponds to this symbol. This is the index of this symbol
9345 in all the symbols for which we are making plt entries.
9346 After the reserved .got.plt entries, all symbols appear in
9347 the same order as in .plt. */
9348 plt_index = (got_offset - got_header_size) / 4;
9349
9350 /* Calculate the address of the GOT entry. */
9351 got_address = (sgot->output_section->vma
9352 + sgot->output_offset
9353 + got_offset);
9354
9355 /* ...and the address of the PLT entry. */
9356 plt_address = (splt->output_section->vma
9357 + splt->output_offset
9358 + root_plt->offset);
9359
9360 ptr = splt->contents + root_plt->offset;
0e1862bb 9361 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9362 {
9363 unsigned int i;
9364 bfd_vma val;
9365
9366 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9367 {
9368 val = elf32_arm_vxworks_shared_plt_entry[i];
9369 if (i == 2)
9370 val |= got_address - sgot->output_section->vma;
9371 if (i == 5)
9372 val |= plt_index * RELOC_SIZE (htab);
9373 if (i == 2 || i == 5)
9374 bfd_put_32 (output_bfd, val, ptr);
9375 else
9376 put_arm_insn (htab, output_bfd, val, ptr);
9377 }
9378 }
9379 else if (htab->vxworks_p)
9380 {
9381 unsigned int i;
9382 bfd_vma val;
9383
9384 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9385 {
9386 val = elf32_arm_vxworks_exec_plt_entry[i];
9387 if (i == 2)
9388 val |= got_address;
9389 if (i == 4)
9390 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9391 if (i == 5)
9392 val |= plt_index * RELOC_SIZE (htab);
9393 if (i == 2 || i == 5)
9394 bfd_put_32 (output_bfd, val, ptr);
9395 else
9396 put_arm_insn (htab, output_bfd, val, ptr);
9397 }
9398
9399 loc = (htab->srelplt2->contents
9400 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9401
9402 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9403 referencing the GOT for this PLT entry. */
9404 rel.r_offset = plt_address + 8;
9405 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9406 rel.r_addend = got_offset;
9407 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9408 loc += RELOC_SIZE (htab);
9409
9410 /* Create the R_ARM_ABS32 relocation referencing the
9411 beginning of the PLT for this GOT entry. */
9412 rel.r_offset = got_address;
9413 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9414 rel.r_addend = 0;
9415 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9416 }
b38cadfb
NC		 9417 else if (htab->nacl_p)
9418 {
9419 /* Calculate the displacement between the PLT slot and the
9420 common tail that's part of the special initial PLT slot. */
6034aab8 9421 int32_t tail_displacement
b38cadfb
NC		 9422 = ((splt->output_section->vma + splt->output_offset
9423 + ARM_NACL_PLT_TAIL_OFFSET)
9424 - (plt_address + htab->plt_entry_size + 4));
9425 BFD_ASSERT ((tail_displacement & 3) == 0);
9426 tail_displacement >>= 2;
9427
9428 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9429 || (-tail_displacement & 0xff000000) == 0);
9430
9431 /* Calculate the displacement between the PLT slot and the entry
9432 in the GOT. The offset accounts for the value produced by
9433 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9434 got_displacement = (got_address
99059e56 9435 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9436
9437 /* NaCl does not support interworking at all. */
9438 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9439
9440 put_arm_insn (htab, output_bfd,
9441 elf32_arm_nacl_plt_entry[0]
9442 | arm_movw_immediate (got_displacement),
9443 ptr + 0);
9444 put_arm_insn (htab, output_bfd,
9445 elf32_arm_nacl_plt_entry[1]
9446 | arm_movt_immediate (got_displacement),
9447 ptr + 4);
9448 put_arm_insn (htab, output_bfd,
9449 elf32_arm_nacl_plt_entry[2],
9450 ptr + 8);
9451 put_arm_insn (htab, output_bfd,
9452 elf32_arm_nacl_plt_entry[3]
9453 | (tail_displacement & 0x00ffffff),
9454 ptr + 12);
9455 }
57460bcf
NC		 9456 else if (using_thumb_only (htab))
9457 {
eed94f8f 9458 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9459 if (!using_thumb2 (htab))
eed94f8f
NC		 9460 {
9461 /* FIXME: We ought to be able to generate thumb-1 PLT
9462 instructions... */
9463 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9464 output_bfd);
9465 return FALSE;
9466 }
57460bcf 9467
eed94f8f
NC		 9468 /* Calculate the displacement between the PLT slot and the entry in
9469 the GOT. The 12-byte offset accounts for the value produced by
9470 adding to pc in the 3rd instruction of the PLT stub. */
9471 got_displacement = got_address - (plt_address + 12);
9472
9473 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9474 instead of 'put_thumb_insn'. */
9475 put_arm_insn (htab, output_bfd,
9476 elf32_thumb2_plt_entry[0]
9477 | ((got_displacement & 0x000000ff) << 16)
9478 | ((got_displacement & 0x00000700) << 20)
9479 | ((got_displacement & 0x00000800) >> 1)
9480 | ((got_displacement & 0x0000f000) >> 12),
9481 ptr + 0);
9482 put_arm_insn (htab, output_bfd,
9483 elf32_thumb2_plt_entry[1]
9484 | ((got_displacement & 0x00ff0000) )
9485 | ((got_displacement & 0x07000000) << 4)
9486 | ((got_displacement & 0x08000000) >> 17)
9487 | ((got_displacement & 0xf0000000) >> 28),
9488 ptr + 4);
9489 put_arm_insn (htab, output_bfd,
9490 elf32_thumb2_plt_entry[2],
9491 ptr + 8);
9492 put_arm_insn (htab, output_bfd,
9493 elf32_thumb2_plt_entry[3],
9494 ptr + 12);
57460bcf 9495 }
34e77a92
RS		 9496 else
9497 {
9498 /* Calculate the displacement between the PLT slot and the
9499 entry in the GOT. The eight-byte offset accounts for the
9500 value produced by adding to pc in the first instruction
9501 of the PLT stub. */
9502 got_displacement = got_address - (plt_address + 8);
9503
34e77a92
RS		 9504 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9505 {
9506 put_thumb_insn (htab, output_bfd,
9507 elf32_arm_plt_thumb_stub[0], ptr - 4);
9508 put_thumb_insn (htab, output_bfd,
9509 elf32_arm_plt_thumb_stub[1], ptr - 2);
9510 }
9511
1db37fe6
YG		 9512 if (!elf32_arm_use_long_plt_entry)
9513 {
9514 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9515
9516 put_arm_insn (htab, output_bfd,
9517 elf32_arm_plt_entry_short[0]
9518 | ((got_displacement & 0x0ff00000) >> 20),
9519 ptr + 0);
9520 put_arm_insn (htab, output_bfd,
9521 elf32_arm_plt_entry_short[1]
9522 | ((got_displacement & 0x000ff000) >> 12),
9523 ptr+ 4);
9524 put_arm_insn (htab, output_bfd,
9525 elf32_arm_plt_entry_short[2]
9526 | (got_displacement & 0x00000fff),
9527 ptr + 8);
34e77a92 9528#ifdef FOUR_WORD_PLT
1db37fe6 9529 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9530#endif
1db37fe6
YG		 9531 }
9532 else
9533 {
9534 put_arm_insn (htab, output_bfd,
9535 elf32_arm_plt_entry_long[0]
9536 | ((got_displacement & 0xf0000000) >> 28),
9537 ptr + 0);
9538 put_arm_insn (htab, output_bfd,
9539 elf32_arm_plt_entry_long[1]
9540 | ((got_displacement & 0x0ff00000) >> 20),
9541 ptr + 4);
9542 put_arm_insn (htab, output_bfd,
9543 elf32_arm_plt_entry_long[2]
9544 | ((got_displacement & 0x000ff000) >> 12),
9545 ptr+ 8);
9546 put_arm_insn (htab, output_bfd,
9547 elf32_arm_plt_entry_long[3]
9548 | (got_displacement & 0x00000fff),
9549 ptr + 12);
9550 }
34e77a92
RS		 9551 }
9552
9553 /* Fill in the entry in the .rel(a).(i)plt section. */
9554 rel.r_offset = got_address;
9555 rel.r_addend = 0;
9556 if (dynindx == -1)
9557 {
9558 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9559 The dynamic linker or static executable then calls SYM_VALUE
9560 to determine the correct run-time value of the .igot.plt entry. */
9561 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9562 initial_got_entry = sym_value;
9563 }
9564 else
9565 {
9566 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9567 initial_got_entry = (splt->output_section->vma
9568 + splt->output_offset);
9569 }
9570
9571 /* Fill in the entry in the global offset table. */
9572 bfd_put_32 (output_bfd, initial_got_entry,
9573 sgot->contents + got_offset);
9574 }
9575
aba8c3de
WN		 9576 if (dynindx == -1)
9577 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9578 else
9579 {
9580 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9581 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9582 }
57460bcf
NC		 9583
9584 return TRUE;
34e77a92
RS		 9585}
9586
eb043451
PB		 9587/* Some relocations map to different relocations depending on the
9588 target. Return the real relocation. */
8029a119 9589
eb043451
PB		 9590static int
9591arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9592 int r_type)
9593{
9594 switch (r_type)
9595 {
9596 case R_ARM_TARGET1:
9597 if (globals->target1_is_rel)
9598 return R_ARM_REL32;
9599 else
9600 return R_ARM_ABS32;
9601
9602 case R_ARM_TARGET2:
9603 return globals->target2_reloc;
9604
9605 default:
9606 return r_type;
9607 }
9608}
eb043451 9609
ba93b8ac
DJ		 9610/* Return the base VMA address which should be subtracted from real addresses
9611 when resolving @dtpoff relocation.
9612 This is PT_TLS segment p_vaddr. */
9613
9614static bfd_vma
9615dtpoff_base (struct bfd_link_info *info)
9616{
9617 /* If tls_sec is NULL, we should have signalled an error already. */
9618 if (elf_hash_table (info)->tls_sec == NULL)
9619 return 0;
9620 return elf_hash_table (info)->tls_sec->vma;
9621}
9622
9623/* Return the relocation value for @tpoff relocation
9624 if STT_TLS virtual address is ADDRESS. */
9625
9626static bfd_vma
9627tpoff (struct bfd_link_info *info, bfd_vma address)
9628{
9629 struct elf_link_hash_table *htab = elf_hash_table (info);
9630 bfd_vma base;
9631
9632 /* If tls_sec is NULL, we should have signalled an error already. */
9633 if (htab->tls_sec == NULL)
9634 return 0;
9635 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9636 return address - htab->tls_sec->vma + base;
9637}
9638
00a97672
RS		 9639/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9640 VALUE is the relocation value. */
9641
9642static bfd_reloc_status_type
9643elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9644{
9645 if (value > 0xfff)
9646 return bfd_reloc_overflow;
9647
9648 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9649 bfd_put_32 (abfd, value, data);
9650 return bfd_reloc_ok;
9651}
9652
0855e32b
NS		 9653/* Handle TLS relaxations. Relaxing is possible for symbols that use
9654 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9655 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9656
9657 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9658 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9659 case of error.
9660
9661 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9662 the pre-relaxed code. It would be nice if the relocs were updated
9663 to match the optimization. */
0855e32b 9664
b38cadfb 9665static bfd_reloc_status_type
0855e32b 9666elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9667 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9668 Elf_Internal_Rela *rel, unsigned long is_local)
9669{
9670 unsigned long insn;
b38cadfb 9671
0855e32b
NS		 9672 switch (ELF32_R_TYPE (rel->r_info))
9673 {
9674 default:
9675 return bfd_reloc_notsupported;
b38cadfb 9676
0855e32b
NS		 9677 case R_ARM_TLS_GOTDESC:
9678 if (is_local)
9679 insn = 0;
9680 else
9681 {
9682 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9683 if (insn & 1)
9684 insn -= 5; /* THUMB */
9685 else
9686 insn -= 8; /* ARM */
9687 }
9688 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9689 return bfd_reloc_continue;
9690
9691 case R_ARM_THM_TLS_DESCSEQ:
9692 /* Thumb insn. */
9693 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9694 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9695 {
9696 if (is_local)
9697 /* nop */
9698 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9699 }
9700 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9701 {
9702 if (is_local)
9703 /* nop */
9704 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9705 else
9706 /* ldr rx,[ry] */
9707 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9708 }
9709 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9710 {
9711 if (is_local)
9712 /* nop */
9713 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9714 else
9715 /* mov r0, rx */
9716 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9717 contents + rel->r_offset);
9718 }
9719 else
9720 {
9721 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9722 /* It's a 32 bit instruction, fetch the rest of it for
9723 error generation. */
9724 insn = (insn << 16)
9725 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9726 _bfd_error_handler
695344c0
NC		 9727 /* xgettext:c-format */
9728 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9729 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9730 return bfd_reloc_notsupported;
9731 }
9732 break;
b38cadfb 9733
0855e32b
NS		 9734 case R_ARM_TLS_DESCSEQ:
9735 /* arm insn. */
9736 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9737 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9738 {
9739 if (is_local)
9740 /* mov rx, ry */
9741 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9742 contents + rel->r_offset);
9743 }
9744 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9745 {
9746 if (is_local)
9747 /* nop */
9748 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9749 else
9750 /* ldr rx,[ry] */
9751 bfd_put_32 (input_bfd, insn & 0xfffff000,
9752 contents + rel->r_offset);
9753 }
9754 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9755 {
9756 if (is_local)
9757 /* nop */
9758 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9759 else
9760 /* mov r0, rx */
9761 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9762 contents + rel->r_offset);
9763 }
9764 else
9765 {
4eca0228 9766 _bfd_error_handler
695344c0
NC		 9767 /* xgettext:c-format */
9768 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9769 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9770 return bfd_reloc_notsupported;
9771 }
9772 break;
9773
9774 case R_ARM_TLS_CALL:
9775 /* GD->IE relaxation, turn the instruction into 'nop' or
9776 'ldr r0, [pc,r0]' */
9777 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9778 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9779 break;
b38cadfb 9780
0855e32b 9781 case R_ARM_THM_TLS_CALL:
6a631e86 9782 /* GD->IE relaxation. */
0855e32b
NS		 9783 if (!is_local)
9784 /* add r0,pc; ldr r0, [r0] */
9785 insn = 0x44786800;
60a019a0 9786 else if (using_thumb2 (globals))
0855e32b
NS		 9787 /* nop.w */
9788 insn = 0xf3af8000;
9789 else
9790 /* nop; nop */
9791 insn = 0xbf00bf00;
b38cadfb 9792
0855e32b
NS		 9793 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9794 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9795 break;
9796 }
9797 return bfd_reloc_ok;
9798}
9799
4962c51a
MS		 9800/* For a given value of n, calculate the value of G_n as required to
9801 deal with group relocations. We return it in the form of an
9802 encoded constant-and-rotation, together with the final residual. If n is
9803 specified as less than zero, then final_residual is filled with the
9804 input value and no further action is performed. */
9805
9806static bfd_vma
9807calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9808{
9809 int current_n;
9810 bfd_vma g_n;
9811 bfd_vma encoded_g_n = 0;
9812 bfd_vma residual = value; /* Also known as Y_n. */
9813
9814 for (current_n = 0; current_n <= n; current_n++)
9815 {
9816 int shift;
9817
9818 /* Calculate which part of the value to mask. */
9819 if (residual == 0)
99059e56 9820 shift = 0;
4962c51a 9821 else
99059e56
RM		 9822 {
9823 int msb;
9824
9825 /* Determine the most significant bit in the residual and
9826 align the resulting value to a 2-bit boundary. */
9827 for (msb = 30; msb >= 0; msb -= 2)
9828 if (residual & (3 << msb))
9829 break;
9830
9831 /* The desired shift is now (msb - 6), or zero, whichever
9832 is the greater. */
9833 shift = msb - 6;
9834 if (shift < 0)
9835 shift = 0;
9836 }
4962c51a
MS		 9837
9838 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9839 g_n = residual & (0xff << shift);
9840 encoded_g_n = (g_n >> shift)
99059e56 9841 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9842
9843 /* Calculate the residual for the next time around. */
9844 residual &= ~g_n;
9845 }
9846
9847 *final_residual = residual;
9848
9849 return encoded_g_n;
9850}
9851
9852/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9853 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9854
4962c51a 9855static int
906e58ca 9856identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9857{
9858 int opcode = insn & 0x1e00000;
9859
9860 if (opcode == 1 << 23) /* ADD */
9861 return 1;
9862
9863 if (opcode == 1 << 22) /* SUB */
9864 return -1;
9865
9866 return 0;
9867}
9868
252b5132 9869/* Perform a relocation as part of a final link. */
9b485d32 9870
252b5132 9871static bfd_reloc_status_type
57e8b36a
NC		 9872elf32_arm_final_link_relocate (reloc_howto_type * howto,
9873 bfd * input_bfd,
9874 bfd * output_bfd,
9875 asection * input_section,
9876 bfd_byte * contents,
9877 Elf_Internal_Rela * rel,
9878 bfd_vma value,
9879 struct bfd_link_info * info,
9880 asection * sym_sec,
9881 const char * sym_name,
34e77a92
RS		 9882 unsigned char st_type,
9883 enum arm_st_branch_type branch_type,
0945cdfd 9884 struct elf_link_hash_entry * h,
f2a9dd69 9885 bfd_boolean * unresolved_reloc_p,
8029a119 9886 char ** error_message)
252b5132
RH		 9887{
9888 unsigned long r_type = howto->type;
9889 unsigned long r_symndx;
9890 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9891 bfd_vma * local_got_offsets;
0855e32b 9892 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9893 asection * sgot;
9894 asection * splt;
252b5132 9895 asection * sreloc = NULL;
362d30a1 9896 asection * srelgot;
252b5132 9897 bfd_vma addend;
ba96a88f 9898 bfd_signed_vma signed_addend;
34e77a92
RS		 9899 unsigned char dynreloc_st_type;
9900 bfd_vma dynreloc_value;
ba96a88f 9901 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9902 struct elf32_arm_link_hash_entry *eh;
9903 union gotplt_union *root_plt;
9904 struct arm_plt_info *arm_plt;
9905 bfd_vma plt_offset;
9906 bfd_vma gotplt_offset;
9907 bfd_boolean has_iplt_entry;
f21f3fe0 9908
9c504268 9909 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9910 if (globals == NULL)
9911 return bfd_reloc_notsupported;
9c504268 9912
0ffa91dd
NC		 9913 BFD_ASSERT (is_arm_elf (input_bfd));
9914
9915 /* Some relocation types map to different relocations depending on the
9c504268 9916 target. We pick the right one here. */
eb043451 9917 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9918
9919 /* It is possible to have linker relaxations on some TLS access
9920 models. Update our information here. */
9921 r_type = elf32_arm_tls_transition (info, r_type, h);
9922
eb043451
PB		 9923 if (r_type != howto->type)
9924 howto = elf32_arm_howto_from_type (r_type);
9c504268 9925
34e77a92 9926 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9927 sgot = globals->root.sgot;
252b5132 9928 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9929 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9930
34e77a92
RS		 9931 if (globals->root.dynamic_sections_created)
9932 srelgot = globals->root.srelgot;
9933 else
9934 srelgot = NULL;
9935
252b5132
RH		 9936 r_symndx = ELF32_R_SYM (rel->r_info);
9937
4e7fd91e 9938 if (globals->use_rel)
ba96a88f 9939 {
4e7fd91e
PB		 9940 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9941
9942 if (addend & ((howto->src_mask + 1) >> 1))
9943 {
9944 signed_addend = -1;
9945 signed_addend &= ~ howto->src_mask;
9946 signed_addend |= addend;
9947 }
9948 else
9949 signed_addend = addend;
ba96a88f
NC		 9950 }
9951 else
4e7fd91e 9952 addend = signed_addend = rel->r_addend;
f21f3fe0 9953
39f21624
NC		 9954 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9955 are resolving a function call relocation. */
9956 if (using_thumb_only (globals)
9957 && (r_type == R_ARM_THM_CALL
9958 || r_type == R_ARM_THM_JUMP24)
9959 && branch_type == ST_BRANCH_TO_ARM)
9960 branch_type = ST_BRANCH_TO_THUMB;
9961
34e77a92
RS		 9962 /* Record the symbol information that should be used in dynamic
9963 relocations. */
9964 dynreloc_st_type = st_type;
9965 dynreloc_value = value;
9966 if (branch_type == ST_BRANCH_TO_THUMB)
9967 dynreloc_value |= 1;
9968
9969 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9970 VALUE appropriately for relocations that we resolve at link time. */
9971 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9972 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9973 &arm_plt)
34e77a92
RS		 9974 && root_plt->offset != (bfd_vma) -1)
9975 {
9976 plt_offset = root_plt->offset;
9977 gotplt_offset = arm_plt->got_offset;
9978
9979 if (h == NULL || eh->is_iplt)
9980 {
9981 has_iplt_entry = TRUE;
9982 splt = globals->root.iplt;
9983
9984 /* Populate .iplt entries here, because not all of them will
9985 be seen by finish_dynamic_symbol. The lower bit is set if
9986 we have already populated the entry. */
9987 if (plt_offset & 1)
9988 plt_offset--;
9989 else
9990 {
57460bcf
NC		 9991 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9992 -1, dynreloc_value))
9993 root_plt->offset |= 1;
9994 else
9995 return bfd_reloc_notsupported;
34e77a92
RS		 9996 }
9997
9998 /* Static relocations always resolve to the .iplt entry. */
9999 st_type = STT_FUNC;
10000 value = (splt->output_section->vma
10001 + splt->output_offset
10002 + plt_offset);
10003 branch_type = ST_BRANCH_TO_ARM;
10004
10005 /* If there are non-call relocations that resolve to the .iplt
10006 entry, then all dynamic ones must too. */
10007 if (arm_plt->noncall_refcount != 0)
10008 {
10009 dynreloc_st_type = st_type;
10010 dynreloc_value = value;
10011 }
10012 }
10013 else
10014 /* We populate the .plt entry in finish_dynamic_symbol. */
10015 splt = globals->root.splt;
10016 }
10017 else
10018 {
10019 splt = NULL;
10020 plt_offset = (bfd_vma) -1;
10021 gotplt_offset = (bfd_vma) -1;
10022 }
10023
252b5132
RH		 10024 switch (r_type)
10025 {
10026 case R_ARM_NONE:
28a094c2
DJ		 10027 /* We don't need to find a value for this symbol. It's just a
10028 marker. */
10029 *unresolved_reloc_p = FALSE;
252b5132
RH		 10030 return bfd_reloc_ok;
10031
00a97672
RS		 10032 case R_ARM_ABS12:
10033 if (!globals->vxworks_p)
10034 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10035 /* Fall through. */
00a97672 10036
252b5132
RH		 10037 case R_ARM_PC24:
10038 case R_ARM_ABS32:
bb224fc3 10039 case R_ARM_ABS32_NOI:
252b5132 10040 case R_ARM_REL32:
bb224fc3 10041 case R_ARM_REL32_NOI:
5b5bb741
PB		 10042 case R_ARM_CALL:
10043 case R_ARM_JUMP24:
dfc5f959 10044 case R_ARM_XPC25:
eb043451 10045 case R_ARM_PREL31:
7359ea65 10046 case R_ARM_PLT32:
7359ea65
DJ		 10047 /* Handle relocations which should use the PLT entry. ABS32/REL32
10048 will use the symbol's value, which may point to a PLT entry, but we
10049 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10050 branches in this object should go to it, except if the PLT is too
10051 far away, in which case a long branch stub should be inserted. */
bb224fc3 10052 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10053 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10054 && r_type != R_ARM_CALL
10055 && r_type != R_ARM_JUMP24
10056 && r_type != R_ARM_PLT32)
34e77a92 10057 && plt_offset != (bfd_vma) -1)
7359ea65 10058 {
34e77a92
RS		 10059 /* If we've created a .plt section, and assigned a PLT entry
10060 to this function, it must either be a STT_GNU_IFUNC reference
10061 or not be known to bind locally. In other cases, we should
10062 have cleared the PLT entry by now. */
10063 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10064
10065 value = (splt->output_section->vma
10066 + splt->output_offset
34e77a92 10067 + plt_offset);
0945cdfd 10068 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10069 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10070 contents, rel->r_offset, value,
00a97672 10071 rel->r_addend);
7359ea65
DJ		 10072 }
10073
67687978
PB		 10074 /* When generating a shared object or relocatable executable, these
10075 relocations are copied into the output file to be resolved at
10076 run time. */
0e1862bb
L		 10077 if ((bfd_link_pic (info)
10078 || globals->root.is_relocatable_executable)
7359ea65 10079 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10080 && !(globals->vxworks_p
3348747a
NS		 10081 && strcmp (input_section->output_section->name,
10082 ".tls_vars") == 0)
bb224fc3 10083 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10084 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10085 && !(input_bfd == globals->stub_bfd
10086 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10087 && (h == NULL
10088 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10089 || h->root.type != bfd_link_hash_undefweak)
10090 && r_type != R_ARM_PC24
5b5bb741
PB		 10091 && r_type != R_ARM_CALL
10092 && r_type != R_ARM_JUMP24
ee06dc07 10093 && r_type != R_ARM_PREL31
7359ea65 10094 && r_type != R_ARM_PLT32)
252b5132 10095 {
947216bf 10096 Elf_Internal_Rela outrel;
b34976b6 10097 bfd_boolean skip, relocate;
f21f3fe0 10098
52db4ec2
JW		 10099 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10100 && !h->def_regular)
10101 {
10102 char *v = _("shared object");
10103
0e1862bb 10104 if (bfd_link_executable (info))
52db4ec2
JW		 10105 v = _("PIE executable");
10106
4eca0228 10107 _bfd_error_handler
52db4ec2
JW		 10108 (_("%B: relocation %s against external or undefined symbol `%s'"
10109 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10110 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10111 return bfd_reloc_notsupported;
10112 }
10113
0945cdfd
DJ		 10114 *unresolved_reloc_p = FALSE;
10115
34e77a92 10116 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10117 {
83bac4b0
NC		 10118 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10119 ! globals->use_rel);
f21f3fe0 10120
83bac4b0 10121 if (sreloc == NULL)
252b5132 10122 return bfd_reloc_notsupported;
252b5132 10123 }
f21f3fe0 10124
b34976b6
AM		 10125 skip = FALSE;
10126 relocate = FALSE;
f21f3fe0 10127
00a97672 10128 outrel.r_addend = addend;
c629eae0
JJ		 10129 outrel.r_offset =
10130 _bfd_elf_section_offset (output_bfd, info, input_section,
10131 rel->r_offset);
10132 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10133 skip = TRUE;
0bb2d96a 10134 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10135 skip = TRUE, relocate = TRUE;
252b5132
RH		 10136 outrel.r_offset += (input_section->output_section->vma
10137 + input_section->output_offset);
f21f3fe0 10138
252b5132 10139 if (skip)
0bb2d96a 10140 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10141 else if (h != NULL
10142 && h->dynindx != -1
0e1862bb 10143 && (!bfd_link_pic (info)
1dcb9720
JW		 10144 || !(bfd_link_pie (info)
10145 || SYMBOLIC_BIND (info, h))
f5385ebf 10146 || !h->def_regular))
5e681ec4 10147 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10148 else
10149 {
a16385dc
MM		 10150 int symbol;
10151
5e681ec4 10152 /* This symbol is local, or marked to become local. */
34e77a92 10153 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10154 if (globals->symbian_p)
6366ff1e 10155 {
74541ad4
AM		 10156 asection *osec;
10157
6366ff1e
MM		 10158 /* On Symbian OS, the data segment and text segement
10159 can be relocated independently. Therefore, we
10160 must indicate the segment to which this
10161 relocation is relative. The BPABI allows us to
10162 use any symbol in the right segment; we just use
10163 the section symbol as it is convenient. (We
10164 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10165 will not appear in the dynamic symbol table.)
10166
10167 Note that the dynamic linker ignores the section
10168 symbol value, so we don't subtract osec->vma
10169 from the emitted reloc addend. */
10dbd1f3 10170 if (sym_sec)
74541ad4 10171 osec = sym_sec->output_section;
10dbd1f3 10172 else
74541ad4
AM		 10173 osec = input_section->output_section;
10174 symbol = elf_section_data (osec)->dynindx;
10175 if (symbol == 0)
10176 {
10177 struct elf_link_hash_table *htab = elf_hash_table (info);
10178
10179 if ((osec->flags & SEC_READONLY) == 0
10180 && htab->data_index_section != NULL)
10181 osec = htab->data_index_section;
10182 else
10183 osec = htab->text_index_section;
10184 symbol = elf_section_data (osec)->dynindx;
10185 }
6366ff1e
MM		 10186 BFD_ASSERT (symbol != 0);
10187 }
a16385dc
MM		 10188 else
10189 /* On SVR4-ish systems, the dynamic loader cannot
10190 relocate the text and data segments independently,
10191 so the symbol does not matter. */
10192 symbol = 0;
34e77a92
RS		 10193 if (dynreloc_st_type == STT_GNU_IFUNC)
10194 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10195 to the .iplt entry. Instead, every non-call reference
10196 must use an R_ARM_IRELATIVE relocation to obtain the
10197 correct run-time address. */
10198 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10199 else
10200 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10201 if (globals->use_rel)
10202 relocate = TRUE;
10203 else
34e77a92 10204 outrel.r_addend += dynreloc_value;
252b5132 10205 }
f21f3fe0 10206
47beaa6a 10207 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10208
f21f3fe0 10209 /* If this reloc is against an external symbol, we do not want to
252b5132 10210 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10211 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10212 if (! relocate)
10213 return bfd_reloc_ok;
9a5aca8c 10214
f21f3fe0 10215 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10216 contents, rel->r_offset,
10217 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10218 }
10219 else switch (r_type)
10220 {
00a97672
RS		 10221 case R_ARM_ABS12:
10222 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10223
dfc5f959 10224 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10225 case R_ARM_CALL:
10226 case R_ARM_JUMP24:
8029a119 10227 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10228 case R_ARM_PLT32:
906e58ca 10229 {
906e58ca
NC		 10230 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10231
dfc5f959 10232 if (r_type == R_ARM_XPC25)
252b5132 10233 {
dfc5f959
NC		 10234 /* Check for Arm calling Arm function. */
10235 /* FIXME: Should we translate the instruction into a BL
10236 instruction instead ? */
35fc36a8 10237 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10238 _bfd_error_handler
d003868e
AM		 10239 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10240 input_bfd,
10241 h ? h->root.root.string : "(local)");
dfc5f959 10242 }
155d87d7 10243 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10244 {
10245 /* Check for Arm calling Thumb function. */
35fc36a8 10246 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10247 {
f2a9dd69
DJ		 10248 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10249 output_bfd, input_section,
10250 hit_data, sym_sec, rel->r_offset,
10251 signed_addend, value,
10252 error_message))
10253 return bfd_reloc_ok;
10254 else
10255 return bfd_reloc_dangerous;
dfc5f959 10256 }
252b5132 10257 }
ba96a88f 10258
906e58ca 10259 /* Check if a stub has to be inserted because the
8029a119 10260 destination is too far or we are changing mode. */
155d87d7
CL		 10261 if ( r_type == R_ARM_CALL
10262 || r_type == R_ARM_JUMP24
10263 || r_type == R_ARM_PLT32)
906e58ca 10264 {
fe33d2fa
CL		 10265 enum elf32_arm_stub_type stub_type = arm_stub_none;
10266 struct elf32_arm_link_hash_entry *hash;
10267
10268 hash = (struct elf32_arm_link_hash_entry *) h;
10269 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10270 st_type, &branch_type,
10271 hash, value, sym_sec,
fe33d2fa 10272 input_bfd, sym_name);
5fa9e92f 10273
fe33d2fa 10274 if (stub_type != arm_stub_none)
906e58ca
NC		 10275 {
10276 /* The target is out of reach, so redirect the
10277 branch to the local stub for this function. */
906e58ca
NC		 10278 stub_entry = elf32_arm_get_stub_entry (input_section,
10279 sym_sec, h,
fe33d2fa
CL		 10280 rel, globals,
10281 stub_type);
9cd3e4e5
NC		 10282 {
10283 if (stub_entry != NULL)
10284 value = (stub_entry->stub_offset
10285 + stub_entry->stub_sec->output_offset
10286 + stub_entry->stub_sec->output_section->vma);
10287
10288 if (plt_offset != (bfd_vma) -1)
10289 *unresolved_reloc_p = FALSE;
10290 }
906e58ca 10291 }
fe33d2fa
CL		 10292 else
10293 {
10294 /* If the call goes through a PLT entry, make sure to
10295 check distance to the right destination address. */
34e77a92 10296 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10297 {
10298 value = (splt->output_section->vma
10299 + splt->output_offset
34e77a92 10300 + plt_offset);
fe33d2fa
CL		 10301 *unresolved_reloc_p = FALSE;
10302 /* The PLT entry is in ARM mode, regardless of the
10303 target function. */
35fc36a8 10304 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10305 }
10306 }
906e58ca
NC		 10307 }
10308
dea514f5
PB		 10309 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10310 where:
10311 S is the address of the symbol in the relocation.
10312 P is address of the instruction being relocated.
10313 A is the addend (extracted from the instruction) in bytes.
10314
10315 S is held in 'value'.
10316 P is the base address of the section containing the
10317 instruction plus the offset of the reloc into that
10318 section, ie:
10319 (input_section->output_section->vma +
10320 input_section->output_offset +
10321 rel->r_offset).
10322 A is the addend, converted into bytes, ie:
10323 (signed_addend * 4)
10324
10325 Note: None of these operations have knowledge of the pipeline
10326 size of the processor, thus it is up to the assembler to
10327 encode this information into the addend. */
10328 value -= (input_section->output_section->vma
10329 + input_section->output_offset);
10330 value -= rel->r_offset;
4e7fd91e
PB		 10331 if (globals->use_rel)
10332 value += (signed_addend << howto->size);
10333 else
10334 /* RELA addends do not have to be adjusted by howto->size. */
10335 value += signed_addend;
23080146 10336
dcb5e6e6
NC		 10337 signed_addend = value;
10338 signed_addend >>= howto->rightshift;
9a5aca8c 10339
5ab79981 10340 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10341 the next instruction unless a PLT entry will be created.
77b4f08f 10342 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10343 The jump to the next instruction is optimized as a NOP depending
10344 on the architecture. */
ffcb4889 10345 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10346 && plt_offset == (bfd_vma) -1)
77b4f08f 10347 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10348 {
cd1dac3d
DG		 10349 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10350
10351 if (arch_has_arm_nop (globals))
10352 value |= 0x0320f000;
10353 else
10354 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10355 }
10356 else
59f2c4e7 10357 {
9b485d32 10358 /* Perform a signed range check. */
dcb5e6e6 10359 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10360 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10361 return bfd_reloc_overflow;
9a5aca8c 10362
5ab79981 10363 addend = (value & 2);
39b41c9c 10364
5ab79981
PB		 10365 value = (signed_addend & howto->dst_mask)
10366 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10367
5ab79981
PB		 10368 if (r_type == R_ARM_CALL)
10369 {
155d87d7 10370 /* Set the H bit in the BLX instruction. */
35fc36a8 10371 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10372 {
10373 if (addend)
10374 value |= (1 << 24);
10375 else
10376 value &= ~(bfd_vma)(1 << 24);
10377 }
10378
5ab79981 10379 /* Select the correct instruction (BL or BLX). */
906e58ca 10380 /* Only if we are not handling a BL to a stub. In this
8029a119 10381 case, mode switching is performed by the stub. */
35fc36a8 10382 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10383 value |= (1 << 28);
63e1a0fc 10384 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10385 {
10386 value &= ~(bfd_vma)(1 << 28);
10387 value |= (1 << 24);
10388 }
39b41c9c
PB		 10389 }
10390 }
906e58ca 10391 }
252b5132 10392 break;
f21f3fe0 10393
252b5132
RH		 10394 case R_ARM_ABS32:
10395 value += addend;
35fc36a8 10396 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10397 value |= 1;
10398 break;
f21f3fe0 10399
bb224fc3
MS		 10400 case R_ARM_ABS32_NOI:
10401 value += addend;
10402 break;
10403
252b5132 10404 case R_ARM_REL32:
a8bc6c78 10405 value += addend;
35fc36a8 10406 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10407 value |= 1;
252b5132 10408 value -= (input_section->output_section->vma
62efb346 10409 + input_section->output_offset + rel->r_offset);
252b5132 10410 break;
eb043451 10411
bb224fc3
MS		 10412 case R_ARM_REL32_NOI:
10413 value += addend;
10414 value -= (input_section->output_section->vma
10415 + input_section->output_offset + rel->r_offset);
10416 break;
10417
eb043451
PB		 10418 case R_ARM_PREL31:
10419 value -= (input_section->output_section->vma
10420 + input_section->output_offset + rel->r_offset);
10421 value += signed_addend;
10422 if (! h || h->root.type != bfd_link_hash_undefweak)
10423 {
8029a119 10424 /* Check for overflow. */
eb043451
PB		 10425 if ((value ^ (value >> 1)) & (1 << 30))
10426 return bfd_reloc_overflow;
10427 }
10428 value &= 0x7fffffff;
10429 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10430 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10431 value |= 1;
10432 break;
252b5132 10433 }
f21f3fe0 10434
252b5132
RH		 10435 bfd_put_32 (input_bfd, value, hit_data);
10436 return bfd_reloc_ok;
10437
10438 case R_ARM_ABS8:
fd0fd00c
MJ		 10439 /* PR 16202: Refectch the addend using the correct size. */
10440 if (globals->use_rel)
10441 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10442 value += addend;
4e67d4ca
DG		 10443
10444 /* There is no way to tell whether the user intended to use a signed or
10445 unsigned addend. When checking for overflow we accept either,
10446 as specified by the AAELF. */
10447 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10448 return bfd_reloc_overflow;
10449
10450 bfd_put_8 (input_bfd, value, hit_data);
10451 return bfd_reloc_ok;
10452
10453 case R_ARM_ABS16:
fd0fd00c
MJ		 10454 /* PR 16202: Refectch the addend using the correct size. */
10455 if (globals->use_rel)
10456 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10457 value += addend;
10458
4e67d4ca
DG		 10459 /* See comment for R_ARM_ABS8. */
10460 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10461 return bfd_reloc_overflow;
10462
10463 bfd_put_16 (input_bfd, value, hit_data);
10464 return bfd_reloc_ok;
10465
252b5132 10466 case R_ARM_THM_ABS5:
9b485d32 10467 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10468 if (globals->use_rel)
10469 {
10470 /* Need to refetch addend. */
10471 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10472 /* ??? Need to determine shift amount from operand size. */
10473 addend >>= howto->rightshift;
10474 }
252b5132
RH		 10475 value += addend;
10476
10477 /* ??? Isn't value unsigned? */
10478 if ((long) value > 0x1f || (long) value < -0x10)
10479 return bfd_reloc_overflow;
10480
10481 /* ??? Value needs to be properly shifted into place first. */
10482 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10483 bfd_put_16 (input_bfd, value, hit_data);
10484 return bfd_reloc_ok;
10485
2cab6cc3
MS		 10486 case R_ARM_THM_ALU_PREL_11_0:
10487 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10488 {
10489 bfd_vma insn;
10490 bfd_signed_vma relocation;
10491
10492 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10493 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10494
99059e56
RM		 10495 if (globals->use_rel)
10496 {
10497 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10498 | ((insn & (1 << 26)) >> 15);
10499 if (insn & 0xf00000)
10500 signed_addend = -signed_addend;
10501 }
2cab6cc3
MS		 10502
10503 relocation = value + signed_addend;
79f08007 10504 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10505 + input_section->output_offset
10506 + rel->r_offset);
2cab6cc3 10507
b6518b38 10508 value = relocation;
2cab6cc3 10509
99059e56
RM		 10510 if (value >= 0x1000)
10511 return bfd_reloc_overflow;
2cab6cc3
MS		 10512
10513 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10514 | ((value & 0x700) << 4)
10515 | ((value & 0x800) << 15);
10516 if (relocation < 0)
10517 insn |= 0xa00000;
2cab6cc3
MS		 10518
10519 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10520 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10521
99059e56 10522 return bfd_reloc_ok;
2cab6cc3
MS		 10523 }
10524
e1ec24c6
NC		 10525 case R_ARM_THM_PC8:
10526 /* PR 10073: This reloc is not generated by the GNU toolchain,
10527 but it is supported for compatibility with third party libraries
10528 generated by other compilers, specifically the ARM/IAR. */
10529 {
10530 bfd_vma insn;
10531 bfd_signed_vma relocation;
10532
10533 insn = bfd_get_16 (input_bfd, hit_data);
10534
99059e56 10535 if (globals->use_rel)
79f08007 10536 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10537
10538 relocation = value + addend;
79f08007 10539 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10540 + input_section->output_offset
10541 + rel->r_offset);
e1ec24c6 10542
b6518b38 10543 value = relocation;
e1ec24c6
NC		 10544
10545 /* We do not check for overflow of this reloc. Although strictly
10546 speaking this is incorrect, it appears to be necessary in order
10547 to work with IAR generated relocs. Since GCC and GAS do not
10548 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10549 a problem for them. */
10550 value &= 0x3fc;
10551
10552 insn = (insn & 0xff00) | (value >> 2);
10553
10554 bfd_put_16 (input_bfd, insn, hit_data);
10555
99059e56 10556 return bfd_reloc_ok;
e1ec24c6
NC		 10557 }
10558
2cab6cc3
MS		 10559 case R_ARM_THM_PC12:
10560 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10561 {
10562 bfd_vma insn;
10563 bfd_signed_vma relocation;
10564
10565 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10566 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10567
99059e56
RM		 10568 if (globals->use_rel)
10569 {
10570 signed_addend = insn & 0xfff;
10571 if (!(insn & (1 << 23)))
10572 signed_addend = -signed_addend;
10573 }
2cab6cc3
MS		 10574
10575 relocation = value + signed_addend;
79f08007 10576 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10577 + input_section->output_offset
10578 + rel->r_offset);
2cab6cc3 10579
b6518b38 10580 value = relocation;
2cab6cc3 10581
99059e56
RM		 10582 if (value >= 0x1000)
10583 return bfd_reloc_overflow;
2cab6cc3
MS		 10584
10585 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10586 if (relocation >= 0)
10587 insn |= (1 << 23);
2cab6cc3
MS		 10588
10589 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10590 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10591
99059e56 10592 return bfd_reloc_ok;
2cab6cc3
MS		 10593 }
10594
dfc5f959 10595 case R_ARM_THM_XPC22:
c19d1205 10596 case R_ARM_THM_CALL:
bd97cb95 10597 case R_ARM_THM_JUMP24:
dfc5f959 10598 /* Thumb BL (branch long instruction). */
252b5132 10599 {
b34976b6 10600 bfd_vma relocation;
99059e56 10601 bfd_vma reloc_sign;
b34976b6
AM		 10602 bfd_boolean overflow = FALSE;
10603 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10604 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10605 bfd_signed_vma reloc_signed_max;
10606 bfd_signed_vma reloc_signed_min;
b34976b6 10607 bfd_vma check;
252b5132 10608 bfd_signed_vma signed_check;
e95de063 10609 int bitsize;
cd1dac3d 10610 const int thumb2 = using_thumb2 (globals);
5e866f5a 10611 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10612
5ab79981 10613 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10614 the next instruction unless a PLT entry will be created.
10615 The jump to the next instruction is optimized as a NOP.W for
10616 Thumb-2 enabled architectures. */
19540007 10617 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10618 && plt_offset == (bfd_vma) -1)
5ab79981 10619 {
60a019a0 10620 if (thumb2)
cd1dac3d
DG		 10621 {
10622 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10623 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10624 }
10625 else
10626 {
10627 bfd_put_16 (input_bfd, 0xe000, hit_data);
10628 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10629 }
5ab79981
PB		 10630 return bfd_reloc_ok;
10631 }
10632
e95de063 10633 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10634 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10635 if (globals->use_rel)
10636 {
99059e56
RM		 10637 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10638 bfd_vma upper = upper_insn & 0x3ff;
10639 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10640 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10641 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10642 bfd_vma i1 = j1 ^ s ? 0 : 1;
10643 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10644
99059e56
RM		 10645 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10646 /* Sign extend. */
10647 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10648
4e7fd91e
PB		 10649 signed_addend = addend;
10650 }
cb1afa5c 10651
dfc5f959
NC		 10652 if (r_type == R_ARM_THM_XPC22)
10653 {
10654 /* Check for Thumb to Thumb call. */
10655 /* FIXME: Should we translate the instruction into a BL
10656 instruction instead ? */
35fc36a8 10657 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10658 _bfd_error_handler
d003868e
AM		 10659 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10660 input_bfd,
10661 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10662 }
10663 else
252b5132 10664 {
dfc5f959
NC		 10665 /* If it is not a call to Thumb, assume call to Arm.
10666 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10667 function call at all, but rather a long jump. Calls through
10668 the PLT do not require stubs. */
34e77a92 10669 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10670 {
bd97cb95 10671 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10672 {
10673 /* Convert BL to BLX. */
10674 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10675 }
155d87d7
CL		 10676 else if (( r_type != R_ARM_THM_CALL)
10677 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10678 {
10679 if (elf32_thumb_to_arm_stub
10680 (info, sym_name, input_bfd, output_bfd, input_section,
10681 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10682 error_message))
10683 return bfd_reloc_ok;
10684 else
10685 return bfd_reloc_dangerous;
10686 }
da5938a2 10687 }
35fc36a8
RS		 10688 else if (branch_type == ST_BRANCH_TO_THUMB
10689 && globals->use_blx
bd97cb95 10690 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10691 {
10692 /* Make sure this is a BL. */
10693 lower_insn |= 0x1800;
10694 }
252b5132 10695 }
f21f3fe0 10696
fe33d2fa 10697 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10698 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10699 {
10700 /* Check if a stub has to be inserted because the destination
8029a119 10701 is too far. */
fe33d2fa
CL		 10702 struct elf32_arm_stub_hash_entry *stub_entry;
10703 struct elf32_arm_link_hash_entry *hash;
10704
10705 hash = (struct elf32_arm_link_hash_entry *) h;
10706
10707 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10708 st_type, &branch_type,
10709 hash, value, sym_sec,
fe33d2fa
CL		 10710 input_bfd, sym_name);
10711
10712 if (stub_type != arm_stub_none)
906e58ca
NC		 10713 {
10714 /* The target is out of reach or we are changing modes, so
10715 redirect the branch to the local stub for this
10716 function. */
10717 stub_entry = elf32_arm_get_stub_entry (input_section,
10718 sym_sec, h,
fe33d2fa
CL		 10719 rel, globals,
10720 stub_type);
906e58ca 10721 if (stub_entry != NULL)
9cd3e4e5
NC		 10722 {
10723 value = (stub_entry->stub_offset
10724 + stub_entry->stub_sec->output_offset
10725 + stub_entry->stub_sec->output_section->vma);
10726
10727 if (plt_offset != (bfd_vma) -1)
10728 *unresolved_reloc_p = FALSE;
10729 }
906e58ca 10730
f4ac8484 10731 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10732 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10733 {
10734 if ((stub_entry
10735 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10736 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10737 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10738 }
906e58ca
NC		 10739 }
10740 }
10741
fe33d2fa 10742 /* Handle calls via the PLT. */
34e77a92 10743 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10744 {
10745 value = (splt->output_section->vma
10746 + splt->output_offset
34e77a92 10747 + plt_offset);
fe33d2fa 10748
eed94f8f
NC		 10749 if (globals->use_blx
10750 && r_type == R_ARM_THM_CALL
10751 && ! using_thumb_only (globals))
fe33d2fa
CL		 10752 {
10753 /* If the Thumb BLX instruction is available, convert
10754 the BL to a BLX instruction to call the ARM-mode
10755 PLT entry. */
10756 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10757 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10758 }
10759 else
10760 {
eed94f8f
NC		 10761 if (! using_thumb_only (globals))
10762 /* Target the Thumb stub before the ARM PLT entry. */
10763 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10764 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10765 }
10766 *unresolved_reloc_p = FALSE;
10767 }
10768
ba96a88f 10769 relocation = value + signed_addend;
f21f3fe0 10770
252b5132 10771 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10772 + input_section->output_offset
10773 + rel->r_offset);
9a5aca8c 10774
252b5132
RH		 10775 check = relocation >> howto->rightshift;
10776
10777 /* If this is a signed value, the rightshift just dropped
10778 leading 1 bits (assuming twos complement). */
10779 if ((bfd_signed_vma) relocation >= 0)
10780 signed_check = check;
10781 else
10782 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10783
e95de063
MS		 10784 /* Calculate the permissable maximum and minimum values for
10785 this relocation according to whether we're relocating for
10786 Thumb-2 or not. */
10787 bitsize = howto->bitsize;
5e866f5a 10788 if (!thumb2_bl)
e95de063 10789 bitsize -= 2;
f6ebfac0 10790 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10791 reloc_signed_min = ~reloc_signed_max;
10792
252b5132 10793 /* Assumes two's complement. */
ba96a88f 10794 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10795 overflow = TRUE;
252b5132 10796
bd97cb95 10797 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10798 /* For a BLX instruction, make sure that the relocation is rounded up
10799 to a word boundary. This follows the semantics of the instruction
10800 which specifies that bit 1 of the target address will come from bit
10801 1 of the base address. */
10802 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10803
e95de063
MS		 10804 /* Put RELOCATION back into the insn. Assumes two's complement.
10805 We use the Thumb-2 encoding, which is safe even if dealing with
10806 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10807 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10808 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10809 | ((relocation >> 12) & 0x3ff)
10810 | (reloc_sign << 10);
906e58ca 10811 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10812 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10813 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10814 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10815
252b5132
RH		 10816 /* Put the relocated value back in the object file: */
10817 bfd_put_16 (input_bfd, upper_insn, hit_data);
10818 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10819
10820 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10821 }
10822 break;
10823
c19d1205
ZW		 10824 case R_ARM_THM_JUMP19:
10825 /* Thumb32 conditional branch instruction. */
10826 {
10827 bfd_vma relocation;
10828 bfd_boolean overflow = FALSE;
10829 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10830 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10831 bfd_signed_vma reloc_signed_max = 0xffffe;
10832 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10833 bfd_signed_vma signed_check;
c5423981
TG		 10834 enum elf32_arm_stub_type stub_type = arm_stub_none;
10835 struct elf32_arm_stub_hash_entry *stub_entry;
10836 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10837
10838 /* Need to refetch the addend, reconstruct the top three bits,
10839 and squish the two 11 bit pieces together. */
10840 if (globals->use_rel)
10841 {
10842 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10843 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10844 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10845 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10846 bfd_vma lower = (lower_insn & 0x07ff);
10847
a00a1f35
MS		 10848 upper |= J1 << 6;
10849 upper |= J2 << 7;
10850 upper |= (!S) << 8;
c19d1205
ZW		 10851 upper -= 0x0100; /* Sign extend. */
10852
10853 addend = (upper << 12) | (lower << 1);
10854 signed_addend = addend;
10855 }
10856
bd97cb95 10857 /* Handle calls via the PLT. */
34e77a92 10858 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10859 {
10860 value = (splt->output_section->vma
10861 + splt->output_offset
34e77a92 10862 + plt_offset);
bd97cb95
DJ		 10863 /* Target the Thumb stub before the ARM PLT entry. */
10864 value -= PLT_THUMB_STUB_SIZE;
10865 *unresolved_reloc_p = FALSE;
10866 }
10867
c5423981
TG		 10868 hash = (struct elf32_arm_link_hash_entry *)h;
10869
10870 stub_type = arm_type_of_stub (info, input_section, rel,
10871 st_type, &branch_type,
10872 hash, value, sym_sec,
10873 input_bfd, sym_name);
10874 if (stub_type != arm_stub_none)
10875 {
10876 stub_entry = elf32_arm_get_stub_entry (input_section,
10877 sym_sec, h,
10878 rel, globals,
10879 stub_type);
10880 if (stub_entry != NULL)
10881 {
10882 value = (stub_entry->stub_offset
10883 + stub_entry->stub_sec->output_offset
10884 + stub_entry->stub_sec->output_section->vma);
10885 }
10886 }
c19d1205 10887
99059e56 10888 relocation = value + signed_addend;
c19d1205
ZW		 10889 relocation -= (input_section->output_section->vma
10890 + input_section->output_offset
10891 + rel->r_offset);
a00a1f35 10892 signed_check = (bfd_signed_vma) relocation;
c19d1205 10893
c19d1205
ZW		 10894 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10895 overflow = TRUE;
10896
10897 /* Put RELOCATION back into the insn. */
10898 {
10899 bfd_vma S = (relocation & 0x00100000) >> 20;
10900 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10901 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10902 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10903 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10904
a00a1f35 10905 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10906 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10907 }
10908
10909 /* Put the relocated value back in the object file: */
10910 bfd_put_16 (input_bfd, upper_insn, hit_data);
10911 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10912
10913 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10914 }
10915
10916 case R_ARM_THM_JUMP11:
10917 case R_ARM_THM_JUMP8:
10918 case R_ARM_THM_JUMP6:
51c5503b
NC		 10919 /* Thumb B (branch) instruction). */
10920 {
6cf9e9fe 10921 bfd_signed_vma relocation;
51c5503b
NC		 10922 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10923 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10924 bfd_signed_vma signed_check;
10925
c19d1205
ZW		 10926 /* CZB cannot jump backward. */
10927 if (r_type == R_ARM_THM_JUMP6)
10928 reloc_signed_min = 0;
10929
4e7fd91e 10930 if (globals->use_rel)
6cf9e9fe 10931 {
4e7fd91e
PB		 10932 /* Need to refetch addend. */
10933 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10934 if (addend & ((howto->src_mask + 1) >> 1))
10935 {
10936 signed_addend = -1;
10937 signed_addend &= ~ howto->src_mask;
10938 signed_addend |= addend;
10939 }
10940 else
10941 signed_addend = addend;
10942 /* The value in the insn has been right shifted. We need to
10943 undo this, so that we can perform the address calculation
10944 in terms of bytes. */
10945 signed_addend <<= howto->rightshift;
6cf9e9fe 10946 }
6cf9e9fe 10947 relocation = value + signed_addend;
51c5503b
NC		 10948
10949 relocation -= (input_section->output_section->vma
10950 + input_section->output_offset
10951 + rel->r_offset);
10952
6cf9e9fe
NC		 10953 relocation >>= howto->rightshift;
10954 signed_check = relocation;
c19d1205
ZW		 10955
10956 if (r_type == R_ARM_THM_JUMP6)
10957 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10958 else
10959 relocation &= howto->dst_mask;
51c5503b 10960 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10961
51c5503b
NC		 10962 bfd_put_16 (input_bfd, relocation, hit_data);
10963
10964 /* Assumes two's complement. */
10965 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10966 return bfd_reloc_overflow;
10967
10968 return bfd_reloc_ok;
10969 }
cedb70c5 10970
8375c36b
PB		 10971 case R_ARM_ALU_PCREL7_0:
10972 case R_ARM_ALU_PCREL15_8:
10973 case R_ARM_ALU_PCREL23_15:
10974 {
10975 bfd_vma insn;
10976 bfd_vma relocation;
10977
10978 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10979 if (globals->use_rel)
10980 {
10981 /* Extract the addend. */
10982 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10983 signed_addend = addend;
10984 }
8375c36b
PB		 10985 relocation = value + signed_addend;
10986
10987 relocation -= (input_section->output_section->vma
10988 + input_section->output_offset
10989 + rel->r_offset);
10990 insn = (insn & ~0xfff)
10991 | ((howto->bitpos << 7) & 0xf00)
10992 | ((relocation >> howto->bitpos) & 0xff);
10993 bfd_put_32 (input_bfd, value, hit_data);
10994 }
10995 return bfd_reloc_ok;
10996
252b5132
RH		 10997 case R_ARM_GNU_VTINHERIT:
10998 case R_ARM_GNU_VTENTRY:
10999 return bfd_reloc_ok;
11000
c19d1205 11001 case R_ARM_GOTOFF32:
252b5132 11002 /* Relocation is relative to the start of the
99059e56 11003 global offset table. */
252b5132
RH		 11004
11005 BFD_ASSERT (sgot != NULL);
11006 if (sgot == NULL)
99059e56 11007 return bfd_reloc_notsupported;
9a5aca8c 11008
cedb70c5 11009 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11010 address by one, so that attempts to call the function pointer will
11011 correctly interpret it as Thumb code. */
35fc36a8 11012 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11013 value += 1;
11014
252b5132 11015 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11016 calculation. We always want the start of .got. If we
11017 define _GLOBAL_OFFSET_TABLE in a different way, as is
11018 permitted by the ABI, we might have to change this
11019 calculation. */
252b5132 11020 value -= sgot->output_section->vma;
f21f3fe0 11021 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11022 contents, rel->r_offset, value,
00a97672 11023 rel->r_addend);
252b5132
RH		 11024
11025 case R_ARM_GOTPC:
a7c10850 11026 /* Use global offset table as symbol value. */
252b5132 11027 BFD_ASSERT (sgot != NULL);
f21f3fe0 11028
252b5132 11029 if (sgot == NULL)
99059e56 11030 return bfd_reloc_notsupported;
252b5132 11031
0945cdfd 11032 *unresolved_reloc_p = FALSE;
252b5132 11033 value = sgot->output_section->vma;
f21f3fe0 11034 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11035 contents, rel->r_offset, value,
00a97672 11036 rel->r_addend);
f21f3fe0 11037
252b5132 11038 case R_ARM_GOT32:
eb043451 11039 case R_ARM_GOT_PREL:
252b5132 11040 /* Relocation is to the entry for this symbol in the
99059e56 11041 global offset table. */
252b5132
RH		 11042 if (sgot == NULL)
11043 return bfd_reloc_notsupported;
f21f3fe0 11044
34e77a92
RS		 11045 if (dynreloc_st_type == STT_GNU_IFUNC
11046 && plt_offset != (bfd_vma) -1
11047 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11048 {
11049 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11050 symbol, and the relocation resolves directly to the runtime
11051 target rather than to the .iplt entry. This means that any
11052 .got entry would be the same value as the .igot.plt entry,
11053 so there's no point creating both. */
11054 sgot = globals->root.igotplt;
11055 value = sgot->output_offset + gotplt_offset;
11056 }
11057 else if (h != NULL)
252b5132
RH		 11058 {
11059 bfd_vma off;
f21f3fe0 11060
252b5132
RH		 11061 off = h->got.offset;
11062 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11063 if ((off & 1) != 0)
252b5132 11064 {
b436d854
RS		 11065 /* We have already processsed one GOT relocation against
11066 this symbol. */
11067 off &= ~1;
11068 if (globals->root.dynamic_sections_created
11069 && !SYMBOL_REFERENCES_LOCAL (info, h))
11070 *unresolved_reloc_p = FALSE;
11071 }
11072 else
11073 {
11074 Elf_Internal_Rela outrel;
11075
6f820c85 11076 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11077 {
11078 /* If the symbol doesn't resolve locally in a static
11079 object, we have an undefined reference. If the
11080 symbol doesn't resolve locally in a dynamic object,
11081 it should be resolved by the dynamic linker. */
11082 if (globals->root.dynamic_sections_created)
11083 {
11084 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11085 *unresolved_reloc_p = FALSE;
11086 }
11087 else
11088 outrel.r_info = 0;
11089 outrel.r_addend = 0;
11090 }
252b5132
RH		 11091 else
11092 {
34e77a92 11093 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11094 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11095 else if (bfd_link_pic (info)
11096 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11097 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11098 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11099 else
11100 outrel.r_info = 0;
34e77a92 11101 outrel.r_addend = dynreloc_value;
b436d854 11102 }
ee29b9fb 11103
b436d854
RS		 11104 /* The GOT entry is initialized to zero by default.
11105 See if we should install a different value. */
11106 if (outrel.r_addend != 0
11107 && (outrel.r_info == 0 || globals->use_rel))
11108 {
11109 bfd_put_32 (output_bfd, outrel.r_addend,
11110 sgot->contents + off);
11111 outrel.r_addend = 0;
252b5132 11112 }
f21f3fe0 11113
b436d854
RS		 11114 if (outrel.r_info != 0)
11115 {
11116 outrel.r_offset = (sgot->output_section->vma
11117 + sgot->output_offset
11118 + off);
11119 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11120 }
11121 h->got.offset |= 1;
11122 }
252b5132
RH		 11123 value = sgot->output_offset + off;
11124 }
11125 else
11126 {
11127 bfd_vma off;
f21f3fe0 11128
5025eb7c
AO		 11129 BFD_ASSERT (local_got_offsets != NULL
11130 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11131
252b5132 11132 off = local_got_offsets[r_symndx];
f21f3fe0 11133
252b5132
RH		 11134 /* The offset must always be a multiple of 4. We use the
11135 least significant bit to record whether we have already
9b485d32 11136 generated the necessary reloc. */
252b5132
RH		 11137 if ((off & 1) != 0)
11138 off &= ~1;
11139 else
11140 {
00a97672 11141 if (globals->use_rel)
34e77a92 11142 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11143
0e1862bb 11144 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11145 {
947216bf 11146 Elf_Internal_Rela outrel;
f21f3fe0 11147
34e77a92 11148 outrel.r_addend = addend + dynreloc_value;
252b5132 11149 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11150 + sgot->output_offset
252b5132 11151 + off);
34e77a92 11152 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11153 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11154 else
11155 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11156 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11157 }
f21f3fe0 11158
252b5132
RH		 11159 local_got_offsets[r_symndx] |= 1;
11160 }
f21f3fe0 11161
252b5132
RH		 11162 value = sgot->output_offset + off;
11163 }
eb043451
PB		 11164 if (r_type != R_ARM_GOT32)
11165 value += sgot->output_section->vma;
9a5aca8c 11166
f21f3fe0 11167 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11168 contents, rel->r_offset, value,
00a97672 11169 rel->r_addend);
f21f3fe0 11170
ba93b8ac
DJ		 11171 case R_ARM_TLS_LDO32:
11172 value = value - dtpoff_base (info);
11173
11174 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11175 contents, rel->r_offset, value,
11176 rel->r_addend);
ba93b8ac
DJ		 11177
11178 case R_ARM_TLS_LDM32:
11179 {
11180 bfd_vma off;
11181
362d30a1 11182 if (sgot == NULL)
ba93b8ac
DJ		 11183 abort ();
11184
11185 off = globals->tls_ldm_got.offset;
11186
11187 if ((off & 1) != 0)
11188 off &= ~1;
11189 else
11190 {
11191 /* If we don't know the module number, create a relocation
11192 for it. */
0e1862bb 11193 if (bfd_link_pic (info))
ba93b8ac
DJ		 11194 {
11195 Elf_Internal_Rela outrel;
ba93b8ac 11196
362d30a1 11197 if (srelgot == NULL)
ba93b8ac
DJ		 11198 abort ();
11199
00a97672 11200 outrel.r_addend = 0;
362d30a1
RS		 11201 outrel.r_offset = (sgot->output_section->vma
11202 + sgot->output_offset + off);
ba93b8ac
DJ		 11203 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11204
00a97672
RS		 11205 if (globals->use_rel)
11206 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11207 sgot->contents + off);
ba93b8ac 11208
47beaa6a 11209 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11210 }
11211 else
362d30a1 11212 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11213
11214 globals->tls_ldm_got.offset |= 1;
11215 }
11216
362d30a1 11217 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11218 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11219
11220 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11221 contents, rel->r_offset, value,
00a97672 11222 rel->r_addend);
ba93b8ac
DJ		 11223 }
11224
0855e32b
NS		 11225 case R_ARM_TLS_CALL:
11226 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11227 case R_ARM_TLS_GD32:
11228 case R_ARM_TLS_IE32:
0855e32b
NS		 11229 case R_ARM_TLS_GOTDESC:
11230 case R_ARM_TLS_DESCSEQ:
11231 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11232 {
0855e32b
NS		 11233 bfd_vma off, offplt;
11234 int indx = 0;
ba93b8ac
DJ		 11235 char tls_type;
11236
0855e32b 11237 BFD_ASSERT (sgot != NULL);
ba93b8ac 11238
ba93b8ac
DJ		 11239 if (h != NULL)
11240 {
11241 bfd_boolean dyn;
11242 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11243 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11244 bfd_link_pic (info),
11245 h)
11246 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11247 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11248 {
11249 *unresolved_reloc_p = FALSE;
11250 indx = h->dynindx;
11251 }
11252 off = h->got.offset;
0855e32b 11253 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11254 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11255 }
11256 else
11257 {
0855e32b 11258 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11259 off = local_got_offsets[r_symndx];
0855e32b 11260 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11261 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11262 }
11263
0855e32b 11264 /* Linker relaxations happens from one of the
b38cadfb 11265 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11266 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11267 tls_type = GOT_TLS_IE;
0855e32b
NS		 11268
11269 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11270
11271 if ((off & 1) != 0)
11272 off &= ~1;
11273 else
11274 {
11275 bfd_boolean need_relocs = FALSE;
11276 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11277 int cur_off = off;
11278
11279 /* The GOT entries have not been initialized yet. Do it
11280 now, and emit any relocations. If both an IE GOT and a
11281 GD GOT are necessary, we emit the GD first. */
11282
0e1862bb 11283 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11284 && (h == NULL
11285 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11286 || h->root.type != bfd_link_hash_undefweak))
11287 {
11288 need_relocs = TRUE;
0855e32b 11289 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11290 }
11291
0855e32b
NS		 11292 if (tls_type & GOT_TLS_GDESC)
11293 {
47beaa6a
RS		 11294 bfd_byte *loc;
11295
0855e32b
NS		 11296 /* We should have relaxed, unless this is an undefined
11297 weak symbol. */
11298 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11299 || bfd_link_pic (info));
0855e32b 11300 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11301 <= globals->root.sgotplt->size);
0855e32b
NS		 11302
11303 outrel.r_addend = 0;
11304 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11305 + globals->root.sgotplt->output_offset
11306 + offplt
11307 + globals->sgotplt_jump_table_size);
b38cadfb 11308
0855e32b
NS		 11309 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11310 sreloc = globals->root.srelplt;
11311 loc = sreloc->contents;
11312 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11313 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11314 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11315
11316 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11317
11318 /* For globals, the first word in the relocation gets
11319 the relocation index and the top bit set, or zero,
11320 if we're binding now. For locals, it gets the
11321 symbol's offset in the tls section. */
99059e56 11322 bfd_put_32 (output_bfd,
0855e32b
NS		 11323 !h ? value - elf_hash_table (info)->tls_sec->vma
11324 : info->flags & DF_BIND_NOW ? 0
11325 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11326 globals->root.sgotplt->contents + offplt
11327 + globals->sgotplt_jump_table_size);
11328
0855e32b 11329 /* Second word in the relocation is always zero. */
99059e56 11330 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11331 globals->root.sgotplt->contents + offplt
11332 + globals->sgotplt_jump_table_size + 4);
0855e32b 11333 }
ba93b8ac
DJ		 11334 if (tls_type & GOT_TLS_GD)
11335 {
11336 if (need_relocs)
11337 {
00a97672 11338 outrel.r_addend = 0;
362d30a1
RS		 11339 outrel.r_offset = (sgot->output_section->vma
11340 + sgot->output_offset
00a97672 11341 + cur_off);
ba93b8ac 11342 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11343
00a97672
RS		 11344 if (globals->use_rel)
11345 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11346 sgot->contents + cur_off);
00a97672 11347
47beaa6a 11348 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11349
11350 if (indx == 0)
11351 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11352 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11353 else
11354 {
00a97672 11355 outrel.r_addend = 0;
ba93b8ac
DJ		 11356 outrel.r_info = ELF32_R_INFO (indx,
11357 R_ARM_TLS_DTPOFF32);
11358 outrel.r_offset += 4;
00a97672
RS		 11359
11360 if (globals->use_rel)
11361 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11362 sgot->contents + cur_off + 4);
00a97672 11363
47beaa6a
RS		 11364 elf32_arm_add_dynreloc (output_bfd, info,
11365 srelgot, &outrel);
ba93b8ac
DJ		 11366 }
11367 }
11368 else
11369 {
11370 /* If we are not emitting relocations for a
11371 general dynamic reference, then we must be in a
11372 static link or an executable link with the
11373 symbol binding locally. Mark it as belonging
11374 to module 1, the executable. */
11375 bfd_put_32 (output_bfd, 1,
362d30a1 11376 sgot->contents + cur_off);
ba93b8ac 11377 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11378 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11379 }
11380
11381 cur_off += 8;
11382 }
11383
11384 if (tls_type & GOT_TLS_IE)
11385 {
11386 if (need_relocs)
11387 {
00a97672
RS		 11388 if (indx == 0)
11389 outrel.r_addend = value - dtpoff_base (info);
11390 else
11391 outrel.r_addend = 0;
362d30a1
RS		 11392 outrel.r_offset = (sgot->output_section->vma
11393 + sgot->output_offset
ba93b8ac
DJ		 11394 + cur_off);
11395 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11396
00a97672
RS		 11397 if (globals->use_rel)
11398 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11399 sgot->contents + cur_off);
ba93b8ac 11400
47beaa6a 11401 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11402 }
11403 else
11404 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11405 sgot->contents + cur_off);
ba93b8ac
DJ		 11406 cur_off += 4;
11407 }
11408
11409 if (h != NULL)
11410 h->got.offset |= 1;
11411 else
11412 local_got_offsets[r_symndx] |= 1;
11413 }
11414
11415 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11416 off += 8;
0855e32b
NS		 11417 else if (tls_type & GOT_TLS_GDESC)
11418 off = offplt;
11419
11420 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11421 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11422 {
11423 bfd_signed_vma offset;
12352d3f
PB		 11424 /* TLS stubs are arm mode. The original symbol is a
11425 data object, so branch_type is bogus. */
11426 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11427 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11428 = arm_type_of_stub (info, input_section, rel,
11429 st_type, &branch_type,
0855e32b
NS		 11430 (struct elf32_arm_link_hash_entry *)h,
11431 globals->tls_trampoline, globals->root.splt,
11432 input_bfd, sym_name);
11433
11434 if (stub_type != arm_stub_none)
11435 {
11436 struct elf32_arm_stub_hash_entry *stub_entry
11437 = elf32_arm_get_stub_entry
11438 (input_section, globals->root.splt, 0, rel,
11439 globals, stub_type);
11440 offset = (stub_entry->stub_offset
11441 + stub_entry->stub_sec->output_offset
11442 + stub_entry->stub_sec->output_section->vma);
11443 }
11444 else
11445 offset = (globals->root.splt->output_section->vma
11446 + globals->root.splt->output_offset
11447 + globals->tls_trampoline);
11448
11449 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11450 {
11451 unsigned long inst;
b38cadfb
NC		 11452
11453 offset -= (input_section->output_section->vma
11454 + input_section->output_offset
11455 + rel->r_offset + 8);
0855e32b
NS		 11456
11457 inst = offset >> 2;
11458 inst &= 0x00ffffff;
11459 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11460 }
11461 else
11462 {
11463 /* Thumb blx encodes the offset in a complicated
11464 fashion. */
11465 unsigned upper_insn, lower_insn;
11466 unsigned neg;
11467
b38cadfb
NC		 11468 offset -= (input_section->output_section->vma
11469 + input_section->output_offset
0855e32b 11470 + rel->r_offset + 4);
b38cadfb 11471
12352d3f
PB		 11472 if (stub_type != arm_stub_none
11473 && arm_stub_is_thumb (stub_type))
11474 {
11475 lower_insn = 0xd000;
11476 }
11477 else
11478 {
11479 lower_insn = 0xc000;
6a631e86 11480 /* Round up the offset to a word boundary. */
12352d3f
PB		 11481 offset = (offset + 2) & ~2;
11482 }
11483
0855e32b
NS		 11484 neg = offset < 0;
11485 upper_insn = (0xf000
11486 | ((offset >> 12) & 0x3ff)
11487 | (neg << 10));
12352d3f 11488 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11489 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11490 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11491 bfd_put_16 (input_bfd, upper_insn, hit_data);
11492 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11493 return bfd_reloc_ok;
11494 }
11495 }
11496 /* These relocations needs special care, as besides the fact
11497 they point somewhere in .gotplt, the addend must be
11498 adjusted accordingly depending on the type of instruction
6a631e86 11499 we refer to. */
0855e32b
NS		 11500 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11501 {
11502 unsigned long data, insn;
11503 unsigned thumb;
b38cadfb 11504
0855e32b
NS		 11505 data = bfd_get_32 (input_bfd, hit_data);
11506 thumb = data & 1;
11507 data &= ~1u;
b38cadfb 11508
0855e32b
NS		 11509 if (thumb)
11510 {
11511 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11512 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11513 insn = (insn << 16)
11514 | bfd_get_16 (input_bfd,
11515 contents + rel->r_offset - data + 2);
11516 if ((insn & 0xf800c000) == 0xf000c000)
11517 /* bl/blx */
11518 value = -6;
11519 else if ((insn & 0xffffff00) == 0x4400)
11520 /* add */
11521 value = -5;
11522 else
11523 {
4eca0228 11524 _bfd_error_handler
695344c0
NC		 11525 /* xgettext:c-format */
11526 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11527 input_bfd, input_section,
11528 (unsigned long)rel->r_offset, insn);
11529 return bfd_reloc_notsupported;
11530 }
11531 }
11532 else
11533 {
11534 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11535
11536 switch (insn >> 24)
11537 {
11538 case 0xeb: /* bl */
11539 case 0xfa: /* blx */
11540 value = -4;
11541 break;
11542
11543 case 0xe0: /* add */
11544 value = -8;
11545 break;
b38cadfb 11546
0855e32b 11547 default:
4eca0228 11548 _bfd_error_handler
695344c0
NC		 11549 /* xgettext:c-format */
11550 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11551 input_bfd, input_section,
11552 (unsigned long)rel->r_offset, insn);
11553 return bfd_reloc_notsupported;
11554 }
11555 }
b38cadfb 11556
0855e32b
NS		 11557 value += ((globals->root.sgotplt->output_section->vma
11558 + globals->root.sgotplt->output_offset + off)
11559 - (input_section->output_section->vma
11560 + input_section->output_offset
11561 + rel->r_offset)
11562 + globals->sgotplt_jump_table_size);
11563 }
11564 else
11565 value = ((globals->root.sgot->output_section->vma
11566 + globals->root.sgot->output_offset + off)
11567 - (input_section->output_section->vma
11568 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11569
11570 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11571 contents, rel->r_offset, value,
00a97672 11572 rel->r_addend);
ba93b8ac
DJ		 11573 }
11574
11575 case R_ARM_TLS_LE32:
3cbc1e5e 11576 if (bfd_link_dll (info))
ba93b8ac 11577 {
4eca0228 11578 _bfd_error_handler
695344c0 11579 /* xgettext:c-format */
ba93b8ac
DJ		 11580 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11581 input_bfd, input_section,
11582 (long) rel->r_offset, howto->name);
46691134 11583 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11584 }
11585 else
11586 value = tpoff (info, value);
906e58ca 11587
ba93b8ac 11588 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11589 contents, rel->r_offset, value,
11590 rel->r_addend);
ba93b8ac 11591
319850b4
JB		 11592 case R_ARM_V4BX:
11593 if (globals->fix_v4bx)
845b51d6
PB		 11594 {
11595 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11596
845b51d6
PB		 11597 /* Ensure that we have a BX instruction. */
11598 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11599
845b51d6
PB		 11600 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11601 {
11602 /* Branch to veneer. */
11603 bfd_vma glue_addr;
11604 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11605 glue_addr -= input_section->output_section->vma
11606 + input_section->output_offset
11607 + rel->r_offset + 8;
11608 insn = (insn & 0xf0000000) | 0x0a000000
11609 | ((glue_addr >> 2) & 0x00ffffff);
11610 }
11611 else
11612 {
11613 /* Preserve Rm (lowest four bits) and the condition code
11614 (highest four bits). Other bits encode MOV PC,Rm. */
11615 insn = (insn & 0xf000000f) | 0x01a0f000;
11616 }
319850b4 11617
845b51d6
PB		 11618 bfd_put_32 (input_bfd, insn, hit_data);
11619 }
319850b4
JB		 11620 return bfd_reloc_ok;
11621
b6895b4f
PB		 11622 case R_ARM_MOVW_ABS_NC:
11623 case R_ARM_MOVT_ABS:
11624 case R_ARM_MOVW_PREL_NC:
11625 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11626 /* Until we properly support segment-base-relative addressing then
11627 we assume the segment base to be zero, as for the group relocations.
11628 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11629 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11630 case R_ARM_MOVW_BREL_NC:
11631 case R_ARM_MOVW_BREL:
11632 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11633 {
11634 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11635
11636 if (globals->use_rel)
11637 {
11638 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11639 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11640 }
92f5d02b 11641
b6895b4f 11642 value += signed_addend;
b6895b4f
PB		 11643
11644 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11645 value -= (input_section->output_section->vma
11646 + input_section->output_offset + rel->r_offset);
11647
92f5d02b 11648 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11649 return bfd_reloc_overflow;
92f5d02b 11650
35fc36a8 11651 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11652 value |= 1;
11653
11654 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11655 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11656 value >>= 16;
11657
11658 insn &= 0xfff0f000;
11659 insn |= value & 0xfff;
11660 insn |= (value & 0xf000) << 4;
11661 bfd_put_32 (input_bfd, insn, hit_data);
11662 }
11663 return bfd_reloc_ok;
11664
11665 case R_ARM_THM_MOVW_ABS_NC:
11666 case R_ARM_THM_MOVT_ABS:
11667 case R_ARM_THM_MOVW_PREL_NC:
11668 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11669 /* Until we properly support segment-base-relative addressing then
11670 we assume the segment base to be zero, as for the above relocations.
11671 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11672 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11673 as R_ARM_THM_MOVT_ABS. */
11674 case R_ARM_THM_MOVW_BREL_NC:
11675 case R_ARM_THM_MOVW_BREL:
11676 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11677 {
11678 bfd_vma insn;
906e58ca 11679
b6895b4f
PB		 11680 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11681 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11682
11683 if (globals->use_rel)
11684 {
11685 addend = ((insn >> 4) & 0xf000)
11686 | ((insn >> 15) & 0x0800)
11687 | ((insn >> 4) & 0x0700)
11688 | (insn & 0x00ff);
39623e12 11689 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11690 }
92f5d02b 11691
b6895b4f 11692 value += signed_addend;
b6895b4f
PB		 11693
11694 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11695 value -= (input_section->output_section->vma
11696 + input_section->output_offset + rel->r_offset);
11697
92f5d02b 11698 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11699 return bfd_reloc_overflow;
92f5d02b 11700
35fc36a8 11701 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11702 value |= 1;
11703
11704 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11705 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11706 value >>= 16;
11707
11708 insn &= 0xfbf08f00;
11709 insn |= (value & 0xf000) << 4;
11710 insn |= (value & 0x0800) << 15;
11711 insn |= (value & 0x0700) << 4;
11712 insn |= (value & 0x00ff);
11713
11714 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11715 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11716 }
11717 return bfd_reloc_ok;
11718
4962c51a
MS		 11719 case R_ARM_ALU_PC_G0_NC:
11720 case R_ARM_ALU_PC_G1_NC:
11721 case R_ARM_ALU_PC_G0:
11722 case R_ARM_ALU_PC_G1:
11723 case R_ARM_ALU_PC_G2:
11724 case R_ARM_ALU_SB_G0_NC:
11725 case R_ARM_ALU_SB_G1_NC:
11726 case R_ARM_ALU_SB_G0:
11727 case R_ARM_ALU_SB_G1:
11728 case R_ARM_ALU_SB_G2:
11729 {
11730 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11731 bfd_vma pc = input_section->output_section->vma
4962c51a 11732 + input_section->output_offset + rel->r_offset;
31a91d61 11733 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11734 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11735 bfd_vma residual;
11736 bfd_vma g_n;
4962c51a 11737 bfd_signed_vma signed_value;
99059e56
RM		 11738 int group = 0;
11739
11740 /* Determine which group of bits to select. */
11741 switch (r_type)
11742 {
11743 case R_ARM_ALU_PC_G0_NC:
11744 case R_ARM_ALU_PC_G0:
11745 case R_ARM_ALU_SB_G0_NC:
11746 case R_ARM_ALU_SB_G0:
11747 group = 0;
11748 break;
11749
11750 case R_ARM_ALU_PC_G1_NC:
11751 case R_ARM_ALU_PC_G1:
11752 case R_ARM_ALU_SB_G1_NC:
11753 case R_ARM_ALU_SB_G1:
11754 group = 1;
11755 break;
11756
11757 case R_ARM_ALU_PC_G2:
11758 case R_ARM_ALU_SB_G2:
11759 group = 2;
11760 break;
11761
11762 default:
11763 abort ();
11764 }
11765
11766 /* If REL, extract the addend from the insn. If RELA, it will
11767 have already been fetched for us. */
4962c51a 11768 if (globals->use_rel)
99059e56
RM		 11769 {
11770 int negative;
11771 bfd_vma constant = insn & 0xff;
11772 bfd_vma rotation = (insn & 0xf00) >> 8;
11773
11774 if (rotation == 0)
11775 signed_addend = constant;
11776 else
11777 {
11778 /* Compensate for the fact that in the instruction, the
11779 rotation is stored in multiples of 2 bits. */
11780 rotation *= 2;
11781
11782 /* Rotate "constant" right by "rotation" bits. */
11783 signed_addend = (constant >> rotation) |
11784 (constant << (8 * sizeof (bfd_vma) - rotation));
11785 }
11786
11787 /* Determine if the instruction is an ADD or a SUB.
11788 (For REL, this determines the sign of the addend.) */
11789 negative = identify_add_or_sub (insn);
11790 if (negative == 0)
11791 {
4eca0228 11792 _bfd_error_handler
695344c0 11793 /* xgettext:c-format */
99059e56
RM		 11794 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11795 input_bfd, input_section,
11796 (long) rel->r_offset, howto->name);
11797 return bfd_reloc_overflow;
11798 }
11799
11800 signed_addend *= negative;
11801 }
4962c51a
MS		 11802
11803 /* Compute the value (X) to go in the place. */
99059e56
RM		 11804 if (r_type == R_ARM_ALU_PC_G0_NC
11805 || r_type == R_ARM_ALU_PC_G1_NC
11806 || r_type == R_ARM_ALU_PC_G0
11807 || r_type == R_ARM_ALU_PC_G1
11808 || r_type == R_ARM_ALU_PC_G2)
11809 /* PC relative. */
11810 signed_value = value - pc + signed_addend;
11811 else
11812 /* Section base relative. */
11813 signed_value = value - sb + signed_addend;
11814
11815 /* If the target symbol is a Thumb function, then set the
11816 Thumb bit in the address. */
35fc36a8 11817 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11818 signed_value |= 1;
11819
99059e56
RM		 11820 /* Calculate the value of the relevant G_n, in encoded
11821 constant-with-rotation format. */
b6518b38
NC		 11822 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11823 group, &residual);
99059e56
RM		 11824
11825 /* Check for overflow if required. */
11826 if ((r_type == R_ARM_ALU_PC_G0
11827 || r_type == R_ARM_ALU_PC_G1
11828 || r_type == R_ARM_ALU_PC_G2
11829 || r_type == R_ARM_ALU_SB_G0
11830 || r_type == R_ARM_ALU_SB_G1
11831 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11832 {
4eca0228 11833 _bfd_error_handler
695344c0 11834 /* xgettext:c-format */
99059e56
RM		 11835 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11836 input_bfd, input_section,
b6518b38
NC		 11837 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11838 howto->name);
99059e56
RM		 11839 return bfd_reloc_overflow;
11840 }
11841
11842 /* Mask out the value and the ADD/SUB part of the opcode; take care
11843 not to destroy the S bit. */
11844 insn &= 0xff1ff000;
11845
11846 /* Set the opcode according to whether the value to go in the
11847 place is negative. */
11848 if (signed_value < 0)
11849 insn |= 1 << 22;
11850 else
11851 insn |= 1 << 23;
11852
11853 /* Encode the offset. */
11854 insn |= g_n;
4962c51a
MS		 11855
11856 bfd_put_32 (input_bfd, insn, hit_data);
11857 }
11858 return bfd_reloc_ok;
11859
11860 case R_ARM_LDR_PC_G0:
11861 case R_ARM_LDR_PC_G1:
11862 case R_ARM_LDR_PC_G2:
11863 case R_ARM_LDR_SB_G0:
11864 case R_ARM_LDR_SB_G1:
11865 case R_ARM_LDR_SB_G2:
11866 {
11867 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11868 bfd_vma pc = input_section->output_section->vma
4962c51a 11869 + input_section->output_offset + rel->r_offset;
31a91d61 11870 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11871 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11872 bfd_vma residual;
4962c51a 11873 bfd_signed_vma signed_value;
99059e56
RM		 11874 int group = 0;
11875
11876 /* Determine which groups of bits to calculate. */
11877 switch (r_type)
11878 {
11879 case R_ARM_LDR_PC_G0:
11880 case R_ARM_LDR_SB_G0:
11881 group = 0;
11882 break;
11883
11884 case R_ARM_LDR_PC_G1:
11885 case R_ARM_LDR_SB_G1:
11886 group = 1;
11887 break;
11888
11889 case R_ARM_LDR_PC_G2:
11890 case R_ARM_LDR_SB_G2:
11891 group = 2;
11892 break;
11893
11894 default:
11895 abort ();
11896 }
11897
11898 /* If REL, extract the addend from the insn. If RELA, it will
11899 have already been fetched for us. */
4962c51a 11900 if (globals->use_rel)
99059e56
RM		 11901 {
11902 int negative = (insn & (1 << 23)) ? 1 : -1;
11903 signed_addend = negative * (insn & 0xfff);
11904 }
4962c51a
MS		 11905
11906 /* Compute the value (X) to go in the place. */
99059e56
RM		 11907 if (r_type == R_ARM_LDR_PC_G0
11908 || r_type == R_ARM_LDR_PC_G1
11909 || r_type == R_ARM_LDR_PC_G2)
11910 /* PC relative. */
11911 signed_value = value - pc + signed_addend;
11912 else
11913 /* Section base relative. */
11914 signed_value = value - sb + signed_addend;
11915
11916 /* Calculate the value of the relevant G_{n-1} to obtain
11917 the residual at that stage. */
b6518b38
NC		 11918 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11919 group - 1, &residual);
99059e56
RM		 11920
11921 /* Check for overflow. */
11922 if (residual >= 0x1000)
11923 {
4eca0228 11924 _bfd_error_handler
695344c0 11925 /* xgettext:c-format */
99059e56 11926 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11927 input_bfd, input_section,
11928 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11929 return bfd_reloc_overflow;
11930 }
11931
11932 /* Mask out the value and U bit. */
11933 insn &= 0xff7ff000;
11934
11935 /* Set the U bit if the value to go in the place is non-negative. */
11936 if (signed_value >= 0)
11937 insn |= 1 << 23;
11938
11939 /* Encode the offset. */
11940 insn |= residual;
4962c51a
MS		 11941
11942 bfd_put_32 (input_bfd, insn, hit_data);
11943 }
11944 return bfd_reloc_ok;
11945
11946 case R_ARM_LDRS_PC_G0:
11947 case R_ARM_LDRS_PC_G1:
11948 case R_ARM_LDRS_PC_G2:
11949 case R_ARM_LDRS_SB_G0:
11950 case R_ARM_LDRS_SB_G1:
11951 case R_ARM_LDRS_SB_G2:
11952 {
11953 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11954 bfd_vma pc = input_section->output_section->vma
4962c51a 11955 + input_section->output_offset + rel->r_offset;
31a91d61 11956 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11957 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11958 bfd_vma residual;
4962c51a 11959 bfd_signed_vma signed_value;
99059e56
RM		 11960 int group = 0;
11961
11962 /* Determine which groups of bits to calculate. */
11963 switch (r_type)
11964 {
11965 case R_ARM_LDRS_PC_G0:
11966 case R_ARM_LDRS_SB_G0:
11967 group = 0;
11968 break;
11969
11970 case R_ARM_LDRS_PC_G1:
11971 case R_ARM_LDRS_SB_G1:
11972 group = 1;
11973 break;
11974
11975 case R_ARM_LDRS_PC_G2:
11976 case R_ARM_LDRS_SB_G2:
11977 group = 2;
11978 break;
11979
11980 default:
11981 abort ();
11982 }
11983
11984 /* If REL, extract the addend from the insn. If RELA, it will
11985 have already been fetched for us. */
4962c51a 11986 if (globals->use_rel)
99059e56
RM		 11987 {
11988 int negative = (insn & (1 << 23)) ? 1 : -1;
11989 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11990 }
4962c51a
MS		 11991
11992 /* Compute the value (X) to go in the place. */
99059e56
RM		 11993 if (r_type == R_ARM_LDRS_PC_G0
11994 || r_type == R_ARM_LDRS_PC_G1
11995 || r_type == R_ARM_LDRS_PC_G2)
11996 /* PC relative. */
11997 signed_value = value - pc + signed_addend;
11998 else
11999 /* Section base relative. */
12000 signed_value = value - sb + signed_addend;
12001
12002 /* Calculate the value of the relevant G_{n-1} to obtain
12003 the residual at that stage. */
b6518b38
NC		 12004 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12005 group - 1, &residual);
99059e56
RM		 12006
12007 /* Check for overflow. */
12008 if (residual >= 0x100)
12009 {
4eca0228 12010 _bfd_error_handler
695344c0 12011 /* xgettext:c-format */
99059e56 12012 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12013 input_bfd, input_section,
12014 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12015 return bfd_reloc_overflow;
12016 }
12017
12018 /* Mask out the value and U bit. */
12019 insn &= 0xff7ff0f0;
12020
12021 /* Set the U bit if the value to go in the place is non-negative. */
12022 if (signed_value >= 0)
12023 insn |= 1 << 23;
12024
12025 /* Encode the offset. */
12026 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12027
12028 bfd_put_32 (input_bfd, insn, hit_data);
12029 }
12030 return bfd_reloc_ok;
12031
12032 case R_ARM_LDC_PC_G0:
12033 case R_ARM_LDC_PC_G1:
12034 case R_ARM_LDC_PC_G2:
12035 case R_ARM_LDC_SB_G0:
12036 case R_ARM_LDC_SB_G1:
12037 case R_ARM_LDC_SB_G2:
12038 {
12039 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12040 bfd_vma pc = input_section->output_section->vma
4962c51a 12041 + input_section->output_offset + rel->r_offset;
31a91d61 12042 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12043 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12044 bfd_vma residual;
4962c51a 12045 bfd_signed_vma signed_value;
99059e56
RM		 12046 int group = 0;
12047
12048 /* Determine which groups of bits to calculate. */
12049 switch (r_type)
12050 {
12051 case R_ARM_LDC_PC_G0:
12052 case R_ARM_LDC_SB_G0:
12053 group = 0;
12054 break;
12055
12056 case R_ARM_LDC_PC_G1:
12057 case R_ARM_LDC_SB_G1:
12058 group = 1;
12059 break;
12060
12061 case R_ARM_LDC_PC_G2:
12062 case R_ARM_LDC_SB_G2:
12063 group = 2;
12064 break;
12065
12066 default:
12067 abort ();
12068 }
12069
12070 /* If REL, extract the addend from the insn. If RELA, it will
12071 have already been fetched for us. */
4962c51a 12072 if (globals->use_rel)
99059e56
RM		 12073 {
12074 int negative = (insn & (1 << 23)) ? 1 : -1;
12075 signed_addend = negative * ((insn & 0xff) << 2);
12076 }
4962c51a
MS		 12077
12078 /* Compute the value (X) to go in the place. */
99059e56
RM		 12079 if (r_type == R_ARM_LDC_PC_G0
12080 || r_type == R_ARM_LDC_PC_G1
12081 || r_type == R_ARM_LDC_PC_G2)
12082 /* PC relative. */
12083 signed_value = value - pc + signed_addend;
12084 else
12085 /* Section base relative. */
12086 signed_value = value - sb + signed_addend;
12087
12088 /* Calculate the value of the relevant G_{n-1} to obtain
12089 the residual at that stage. */
b6518b38
NC		 12090 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12091 group - 1, &residual);
99059e56
RM		 12092
12093 /* Check for overflow. (The absolute value to go in the place must be
12094 divisible by four and, after having been divided by four, must
12095 fit in eight bits.) */
12096 if ((residual & 0x3) != 0 || residual >= 0x400)
12097 {
4eca0228 12098 _bfd_error_handler
695344c0 12099 /* xgettext:c-format */
99059e56
RM		 12100 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12101 input_bfd, input_section,
b6518b38 12102 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12103 return bfd_reloc_overflow;
12104 }
12105
12106 /* Mask out the value and U bit. */
12107 insn &= 0xff7fff00;
12108
12109 /* Set the U bit if the value to go in the place is non-negative. */
12110 if (signed_value >= 0)
12111 insn |= 1 << 23;
12112
12113 /* Encode the offset. */
12114 insn |= residual >> 2;
4962c51a
MS		 12115
12116 bfd_put_32 (input_bfd, insn, hit_data);
12117 }
12118 return bfd_reloc_ok;
12119
72d98d16
MG		 12120 case R_ARM_THM_ALU_ABS_G0_NC:
12121 case R_ARM_THM_ALU_ABS_G1_NC:
12122 case R_ARM_THM_ALU_ABS_G2_NC:
12123 case R_ARM_THM_ALU_ABS_G3_NC:
12124 {
12125 const int shift_array[4] = {0, 8, 16, 24};
12126 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12127 bfd_vma addr = value;
12128 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12129
12130 /* Compute address. */
12131 if (globals->use_rel)
12132 signed_addend = insn & 0xff;
12133 addr += signed_addend;
12134 if (branch_type == ST_BRANCH_TO_THUMB)
12135 addr |= 1;
12136 /* Clean imm8 insn. */
12137 insn &= 0xff00;
12138 /* And update with correct part of address. */
12139 insn |= (addr >> shift) & 0xff;
12140 /* Update insn. */
12141 bfd_put_16 (input_bfd, insn, hit_data);
12142 }
12143
12144 *unresolved_reloc_p = FALSE;
12145 return bfd_reloc_ok;
12146
252b5132
RH		 12147 default:
12148 return bfd_reloc_notsupported;
12149 }
12150}
12151
98c1d4aa
NC		 12152/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12153static void
57e8b36a
NC		 12154arm_add_to_rel (bfd * abfd,
12155 bfd_byte * address,
12156 reloc_howto_type * howto,
12157 bfd_signed_vma increment)
98c1d4aa 12158{
98c1d4aa
NC		 12159 bfd_signed_vma addend;
12160
bd97cb95
DJ		 12161 if (howto->type == R_ARM_THM_CALL
12162 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12163 {
9a5aca8c
AM		 12164 int upper_insn, lower_insn;
12165 int upper, lower;
98c1d4aa 12166
9a5aca8c
AM		 12167 upper_insn = bfd_get_16 (abfd, address);
12168 lower_insn = bfd_get_16 (abfd, address + 2);
12169 upper = upper_insn & 0x7ff;
12170 lower = lower_insn & 0x7ff;
12171
12172 addend = (upper << 12) | (lower << 1);
ddda4409 12173 addend += increment;
9a5aca8c 12174 addend >>= 1;
98c1d4aa 12175
9a5aca8c
AM		 12176 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12177 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12178
dc810e39
AM		 12179 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12180 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12181 }
12182 else
12183 {
12184 bfd_vma contents;
12185
12186 contents = bfd_get_32 (abfd, address);
12187
12188 /* Get the (signed) value from the instruction. */
12189 addend = contents & howto->src_mask;
12190 if (addend & ((howto->src_mask + 1) >> 1))
12191 {
12192 bfd_signed_vma mask;
12193
12194 mask = -1;
12195 mask &= ~ howto->src_mask;
12196 addend |= mask;
12197 }
12198
12199 /* Add in the increment, (which is a byte value). */
12200 switch (howto->type)
12201 {
12202 default:
12203 addend += increment;
12204 break;
12205
12206 case R_ARM_PC24:
c6596c5e 12207 case R_ARM_PLT32:
5b5bb741
PB		 12208 case R_ARM_CALL:
12209 case R_ARM_JUMP24:
9a5aca8c 12210 addend <<= howto->size;
dc810e39 12211 addend += increment;
9a5aca8c
AM		 12212
12213 /* Should we check for overflow here ? */
12214
12215 /* Drop any undesired bits. */
12216 addend >>= howto->rightshift;
12217 break;
12218 }
12219
12220 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12221
12222 bfd_put_32 (abfd, contents, address);
ddda4409 12223 }
98c1d4aa 12224}
252b5132 12225
ba93b8ac
DJ		 12226#define IS_ARM_TLS_RELOC(R_TYPE) \
12227 ((R_TYPE) == R_ARM_TLS_GD32 \
12228 || (R_TYPE) == R_ARM_TLS_LDO32 \
12229 || (R_TYPE) == R_ARM_TLS_LDM32 \
12230 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12231 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12232 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12233 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12234 || (R_TYPE) == R_ARM_TLS_IE32 \
12235 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12236
12237/* Specific set of relocations for the gnu tls dialect. */
12238#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12239 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12240 || (R_TYPE) == R_ARM_TLS_CALL \
12241 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12242 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12243 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12244
252b5132 12245/* Relocate an ARM ELF section. */
906e58ca 12246
b34976b6 12247static bfd_boolean
57e8b36a
NC		 12248elf32_arm_relocate_section (bfd * output_bfd,
12249 struct bfd_link_info * info,
12250 bfd * input_bfd,
12251 asection * input_section,
12252 bfd_byte * contents,
12253 Elf_Internal_Rela * relocs,
12254 Elf_Internal_Sym * local_syms,
12255 asection ** local_sections)
252b5132 12256{
b34976b6
AM		 12257 Elf_Internal_Shdr *symtab_hdr;
12258 struct elf_link_hash_entry **sym_hashes;
12259 Elf_Internal_Rela *rel;
12260 Elf_Internal_Rela *relend;
12261 const char *name;
b32d3aa2 12262 struct elf32_arm_link_hash_table * globals;
252b5132 12263
4e7fd91e 12264 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12265 if (globals == NULL)
12266 return FALSE;
b491616a 12267
0ffa91dd 12268 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12269 sym_hashes = elf_sym_hashes (input_bfd);
12270
12271 rel = relocs;
12272 relend = relocs + input_section->reloc_count;
12273 for (; rel < relend; rel++)
12274 {
ba96a88f
NC		 12275 int r_type;
12276 reloc_howto_type * howto;
12277 unsigned long r_symndx;
12278 Elf_Internal_Sym * sym;
12279 asection * sec;
252b5132 12280 struct elf_link_hash_entry * h;
ba96a88f
NC		 12281 bfd_vma relocation;
12282 bfd_reloc_status_type r;
12283 arelent bfd_reloc;
ba93b8ac 12284 char sym_type;
0945cdfd 12285 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12286 char *error_message = NULL;
f21f3fe0 12287
252b5132 12288 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12289 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12290 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12291
ba96a88f 12292 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12293 || r_type == R_ARM_GNU_VTINHERIT)
12294 continue;
252b5132 12295
b32d3aa2 12296 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12297 howto = bfd_reloc.howto;
252b5132 12298
252b5132
RH		 12299 h = NULL;
12300 sym = NULL;
12301 sec = NULL;
9b485d32 12302
252b5132
RH		 12303 if (r_symndx < symtab_hdr->sh_info)
12304 {
12305 sym = local_syms + r_symndx;
ba93b8ac 12306 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12307 sec = local_sections[r_symndx];
ffcb4889
NS		 12308
12309 /* An object file might have a reference to a local
12310 undefined symbol. This is a daft object file, but we
12311 should at least do something about it. V4BX & NONE
12312 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12313 allowed to use the undefined symbol, so allow those.
12314 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12315 if (r_type != R_ARM_V4BX
12316 && r_type != R_ARM_NONE
77b4f08f 12317 && r_symndx != STN_UNDEF
ffcb4889
NS		 12318 && bfd_is_und_section (sec)
12319 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12320 (*info->callbacks->undefined_symbol)
12321 (info, bfd_elf_string_from_elf_section
12322 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12323 input_bfd, input_section,
12324 rel->r_offset, TRUE);
b38cadfb 12325
4e7fd91e 12326 if (globals->use_rel)
f8df10f4 12327 {
4e7fd91e
PB		 12328 relocation = (sec->output_section->vma
12329 + sec->output_offset
12330 + sym->st_value);
0e1862bb 12331 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12332 && (sec->flags & SEC_MERGE)
12333 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12334 {
4e7fd91e
PB		 12335 asection *msec;
12336 bfd_vma addend, value;
12337
39623e12 12338 switch (r_type)
4e7fd91e 12339 {
39623e12
PB		 12340 case R_ARM_MOVW_ABS_NC:
12341 case R_ARM_MOVT_ABS:
12342 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12343 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12344 addend = (addend ^ 0x8000) - 0x8000;
12345 break;
f8df10f4 12346
39623e12
PB		 12347 case R_ARM_THM_MOVW_ABS_NC:
12348 case R_ARM_THM_MOVT_ABS:
12349 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12350 << 16;
12351 value |= bfd_get_16 (input_bfd,
12352 contents + rel->r_offset + 2);
12353 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12354 | ((value & 0x04000000) >> 15);
12355 addend = (addend ^ 0x8000) - 0x8000;
12356 break;
f8df10f4 12357
39623e12
PB		 12358 default:
12359 if (howto->rightshift
12360 || (howto->src_mask & (howto->src_mask + 1)))
12361 {
4eca0228 12362 _bfd_error_handler
695344c0 12363 /* xgettext:c-format */
39623e12
PB		 12364 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12365 input_bfd, input_section,
12366 (long) rel->r_offset, howto->name);
12367 return FALSE;
12368 }
12369
12370 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12371
12372 /* Get the (signed) value from the instruction. */
12373 addend = value & howto->src_mask;
12374 if (addend & ((howto->src_mask + 1) >> 1))
12375 {
12376 bfd_signed_vma mask;
12377
12378 mask = -1;
12379 mask &= ~ howto->src_mask;
12380 addend |= mask;
12381 }
12382 break;
4e7fd91e 12383 }
39623e12 12384
4e7fd91e
PB		 12385 msec = sec;
12386 addend =
12387 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12388 - relocation;
12389 addend += msec->output_section->vma + msec->output_offset;
39623e12 12390
cc643b88 12391 /* Cases here must match those in the preceding
39623e12
PB		 12392 switch statement. */
12393 switch (r_type)
12394 {
12395 case R_ARM_MOVW_ABS_NC:
12396 case R_ARM_MOVT_ABS:
12397 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12398 | (addend & 0xfff);
12399 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12400 break;
12401
12402 case R_ARM_THM_MOVW_ABS_NC:
12403 case R_ARM_THM_MOVT_ABS:
12404 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12405 | (addend & 0xff) | ((addend & 0x0800) << 15);
12406 bfd_put_16 (input_bfd, value >> 16,
12407 contents + rel->r_offset);
12408 bfd_put_16 (input_bfd, value,
12409 contents + rel->r_offset + 2);
12410 break;
12411
12412 default:
12413 value = (value & ~ howto->dst_mask)
12414 | (addend & howto->dst_mask);
12415 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12416 break;
12417 }
f8df10f4 12418 }
f8df10f4 12419 }
4e7fd91e
PB		 12420 else
12421 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12422 }
12423 else
12424 {
62d887d4 12425 bfd_boolean warned, ignored;
560e09e9 12426
b2a8e766
AM		 12427 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12428 r_symndx, symtab_hdr, sym_hashes,
12429 h, sec, relocation,
62d887d4 12430 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12431
12432 sym_type = h->type;
252b5132
RH		 12433 }
12434
dbaa2011 12435 if (sec != NULL && discarded_section (sec))
e4067dbb 12436 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12437 rel, 1, relend, howto, 0, contents);
ab96bf03 12438
0e1862bb 12439 if (bfd_link_relocatable (info))
ab96bf03
AM		 12440 {
12441 /* This is a relocatable link. We don't have to change
12442 anything, unless the reloc is against a section symbol,
12443 in which case we have to adjust according to where the
12444 section symbol winds up in the output section. */
12445 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12446 {
12447 if (globals->use_rel)
12448 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12449 howto, (bfd_signed_vma) sec->output_offset);
12450 else
12451 rel->r_addend += sec->output_offset;
12452 }
12453 continue;
12454 }
12455
252b5132
RH		 12456 if (h != NULL)
12457 name = h->root.root.string;
12458 else
12459 {
12460 name = (bfd_elf_string_from_elf_section
12461 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12462 if (name == NULL || *name == '\0')
12463 name = bfd_section_name (input_bfd, sec);
12464 }
f21f3fe0 12465
cf35638d 12466 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12467 && r_type != R_ARM_NONE
12468 && (h == NULL
12469 || h->root.type == bfd_link_hash_defined
12470 || h->root.type == bfd_link_hash_defweak)
12471 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12472 {
4eca0228 12473 _bfd_error_handler
ba93b8ac 12474 ((sym_type == STT_TLS
695344c0 12475 /* xgettext:c-format */
ba93b8ac 12476 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
695344c0 12477 /* xgettext:c-format */
ba93b8ac
DJ		 12478 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12479 input_bfd,
12480 input_section,
12481 (long) rel->r_offset,
12482 howto->name,
12483 name);
12484 }
12485
0855e32b 12486 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12487 done, i.e., the relaxation produced the final output we want,
12488 and we won't let anybody mess with it. Also, we have to do
12489 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12490 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12491 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12492 || (IS_ARM_TLS_GNU_RELOC (r_type)
12493 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12494 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12495 & GOT_TLS_GDESC)))
12496 {
12497 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12498 contents, rel, h == NULL);
12499 /* This may have been marked unresolved because it came from
12500 a shared library. But we've just dealt with that. */
12501 unresolved_reloc = 0;
12502 }
12503 else
12504 r = bfd_reloc_continue;
b38cadfb 12505
39d911fc
TP		 12506 if (r == bfd_reloc_continue)
12507 {
12508 unsigned char branch_type =
12509 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12510 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12511
12512 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12513 input_section, contents, rel,
12514 relocation, info, sec, name,
12515 sym_type, branch_type, h,
12516 &unresolved_reloc,
12517 &error_message);
12518 }
0945cdfd
DJ		 12519
12520 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12521 because such sections are not SEC_ALLOC and thus ld.so will
12522 not process them. */
12523 if (unresolved_reloc
99059e56
RM		 12524 && !((input_section->flags & SEC_DEBUGGING) != 0
12525 && h->def_dynamic)
1d5316ab
AM		 12526 && _bfd_elf_section_offset (output_bfd, info, input_section,
12527 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12528 {
4eca0228 12529 _bfd_error_handler
695344c0 12530 /* xgettext:c-format */
843fe662
L		 12531 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12532 input_bfd,
12533 input_section,
12534 (long) rel->r_offset,
12535 howto->name,
12536 h->root.root.string);
0945cdfd
DJ		 12537 return FALSE;
12538 }
252b5132
RH		 12539
12540 if (r != bfd_reloc_ok)
12541 {
252b5132
RH		 12542 switch (r)
12543 {
12544 case bfd_reloc_overflow:
cf919dfd
PB		 12545 /* If the overflowing reloc was to an undefined symbol,
12546 we have already printed one error message and there
12547 is no point complaining again. */
1a72702b
AM		 12548 if (!h || h->root.type != bfd_link_hash_undefined)
12549 (*info->callbacks->reloc_overflow)
12550 (info, (h ? &h->root : NULL), name, howto->name,
12551 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12552 break;
12553
12554 case bfd_reloc_undefined:
1a72702b
AM		 12555 (*info->callbacks->undefined_symbol)
12556 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12557 break;
12558
12559 case bfd_reloc_outofrange:
f2a9dd69 12560 error_message = _("out of range");
252b5132
RH		 12561 goto common_error;
12562
12563 case bfd_reloc_notsupported:
f2a9dd69 12564 error_message = _("unsupported relocation");
252b5132
RH		 12565 goto common_error;
12566
12567 case bfd_reloc_dangerous:
f2a9dd69 12568 /* error_message should already be set. */
252b5132
RH		 12569 goto common_error;
12570
12571 default:
f2a9dd69 12572 error_message = _("unknown error");
8029a119 12573 /* Fall through. */
252b5132
RH		 12574
12575 common_error:
f2a9dd69 12576 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12577 (*info->callbacks->reloc_dangerous)
12578 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12579 break;
12580 }
12581 }
12582 }
12583
b34976b6 12584 return TRUE;
252b5132
RH		 12585}
12586
91d6fa6a 12587/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12588 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12589 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12590 maintaining that condition). */
12591
12592static void
12593add_unwind_table_edit (arm_unwind_table_edit **head,
12594 arm_unwind_table_edit **tail,
12595 arm_unwind_edit_type type,
12596 asection *linked_section,
91d6fa6a 12597 unsigned int tindex)
2468f9c9 12598{
21d799b5
NC		 12599 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12600 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12601
2468f9c9
PB		 12602 new_edit->type = type;
12603 new_edit->linked_section = linked_section;
91d6fa6a 12604 new_edit->index = tindex;
b38cadfb 12605
91d6fa6a 12606 if (tindex > 0)
2468f9c9
PB		 12607 {
12608 new_edit->next = NULL;
12609
12610 if (*tail)
12611 (*tail)->next = new_edit;
12612
12613 (*tail) = new_edit;
12614
12615 if (!*head)
12616 (*head) = new_edit;
12617 }
12618 else
12619 {
12620 new_edit->next = *head;
12621
12622 if (!*tail)
12623 *tail = new_edit;
12624
12625 *head = new_edit;
12626 }
12627}
12628
12629static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12630
12631/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12632static void
12633adjust_exidx_size(asection *exidx_sec, int adjust)
12634{
12635 asection *out_sec;
12636
12637 if (!exidx_sec->rawsize)
12638 exidx_sec->rawsize = exidx_sec->size;
12639
12640 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12641 out_sec = exidx_sec->output_section;
12642 /* Adjust size of output section. */
12643 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12644}
12645
12646/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12647static void
12648insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12649{
12650 struct _arm_elf_section_data *exidx_arm_data;
12651
12652 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12653 add_unwind_table_edit (
12654 &exidx_arm_data->u.exidx.unwind_edit_list,
12655 &exidx_arm_data->u.exidx.unwind_edit_tail,
12656 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12657
491d01d3
YU		 12658 exidx_arm_data->additional_reloc_count++;
12659
2468f9c9
PB		 12660 adjust_exidx_size(exidx_sec, 8);
12661}
12662
12663/* Scan .ARM.exidx tables, and create a list describing edits which should be
12664 made to those tables, such that:
b38cadfb 12665
2468f9c9
PB		 12666 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12667 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12668 codes which have been inlined into the index).
2468f9c9 12669
85fdf906
AH		 12670 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12671
2468f9c9 12672 The edits are applied when the tables are written
b38cadfb 12673 (in elf32_arm_write_section). */
2468f9c9
PB		 12674
12675bfd_boolean
12676elf32_arm_fix_exidx_coverage (asection **text_section_order,
12677 unsigned int num_text_sections,
85fdf906
AH		 12678 struct bfd_link_info *info,
12679 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12680{
12681 bfd *inp;
12682 unsigned int last_second_word = 0, i;
12683 asection *last_exidx_sec = NULL;
12684 asection *last_text_sec = NULL;
12685 int last_unwind_type = -1;
12686
12687 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12688 text sections. */
c72f2fb2 12689 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12690 {
12691 asection *sec;
b38cadfb 12692
2468f9c9 12693 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12694 {
2468f9c9
PB		 12695 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12696 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12697
dec9d5df 12698 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12699 continue;
b38cadfb 12700
2468f9c9
PB		 12701 if (elf_sec->linked_to)
12702 {
12703 Elf_Internal_Shdr *linked_hdr
99059e56 12704 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12705 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12706 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12707
12708 if (linked_sec_arm_data == NULL)
99059e56 12709 continue;
2468f9c9
PB		 12710
12711 /* Link this .ARM.exidx section back from the text section it
99059e56 12712 describes. */
2468f9c9
PB		 12713 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12714 }
12715 }
12716 }
12717
12718 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12719 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12720 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12721
12722 for (i = 0; i < num_text_sections; i++)
12723 {
12724 asection *sec = text_section_order[i];
12725 asection *exidx_sec;
12726 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12727 struct _arm_elf_section_data *exidx_arm_data;
12728 bfd_byte *contents = NULL;
12729 int deleted_exidx_bytes = 0;
12730 bfd_vma j;
12731 arm_unwind_table_edit *unwind_edit_head = NULL;
12732 arm_unwind_table_edit *unwind_edit_tail = NULL;
12733 Elf_Internal_Shdr *hdr;
12734 bfd *ibfd;
12735
12736 if (arm_data == NULL)
99059e56 12737 continue;
2468f9c9
PB		 12738
12739 exidx_sec = arm_data->u.text.arm_exidx_sec;
12740 if (exidx_sec == NULL)
12741 {
12742 /* Section has no unwind data. */
12743 if (last_unwind_type == 0 || !last_exidx_sec)
12744 continue;
12745
12746 /* Ignore zero sized sections. */
12747 if (sec->size == 0)
12748 continue;
12749
12750 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12751 last_unwind_type = 0;
12752 continue;
12753 }
12754
22a8f80e
PB		 12755 /* Skip /DISCARD/ sections. */
12756 if (bfd_is_abs_section (exidx_sec->output_section))
12757 continue;
12758
2468f9c9
PB		 12759 hdr = &elf_section_data (exidx_sec)->this_hdr;
12760 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12761 continue;
b38cadfb 12762
2468f9c9
PB		 12763 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12764 if (exidx_arm_data == NULL)
99059e56 12765 continue;
b38cadfb 12766
2468f9c9 12767 ibfd = exidx_sec->owner;
b38cadfb 12768
2468f9c9
PB		 12769 if (hdr->contents != NULL)
12770 contents = hdr->contents;
12771 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12772 /* An error? */
12773 continue;
12774
ac06903d
YU		 12775 if (last_unwind_type > 0)
12776 {
12777 unsigned int first_word = bfd_get_32 (ibfd, contents);
12778 /* Add cantunwind if first unwind item does not match section
12779 start. */
12780 if (first_word != sec->vma)
12781 {
12782 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12783 last_unwind_type = 0;
12784 }
12785 }
12786
2468f9c9
PB		 12787 for (j = 0; j < hdr->sh_size; j += 8)
12788 {
12789 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12790 int unwind_type;
12791 int elide = 0;
12792
12793 /* An EXIDX_CANTUNWIND entry. */
12794 if (second_word == 1)
12795 {
12796 if (last_unwind_type == 0)
12797 elide = 1;
12798 unwind_type = 0;
12799 }
12800 /* Inlined unwinding data. Merge if equal to previous. */
12801 else if ((second_word & 0x80000000) != 0)
12802 {
85fdf906
AH		 12803 if (merge_exidx_entries
12804 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12805 elide = 1;
12806 unwind_type = 1;
12807 last_second_word = second_word;
12808 }
12809 /* Normal table entry. In theory we could merge these too,
12810 but duplicate entries are likely to be much less common. */
12811 else
12812 unwind_type = 2;
12813
491d01d3 12814 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12815 {
12816 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12817 DELETE_EXIDX_ENTRY, NULL, j / 8);
12818
12819 deleted_exidx_bytes += 8;
12820 }
12821
12822 last_unwind_type = unwind_type;
12823 }
12824
12825 /* Free contents if we allocated it ourselves. */
12826 if (contents != hdr->contents)
99059e56 12827 free (contents);
2468f9c9
PB		 12828
12829 /* Record edits to be applied later (in elf32_arm_write_section). */
12830 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12831 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12832
2468f9c9
PB		 12833 if (deleted_exidx_bytes > 0)
12834 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12835
12836 last_exidx_sec = exidx_sec;
12837 last_text_sec = sec;
12838 }
12839
12840 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12841 if (!bfd_link_relocatable (info) && last_exidx_sec
12842 && last_unwind_type != 0)
2468f9c9
PB		 12843 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12844
12845 return TRUE;
12846}
12847
3e6b1042
DJ		 12848static bfd_boolean
12849elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12850 bfd *ibfd, const char *name)
12851{
12852 asection *sec, *osec;
12853
3d4d4302 12854 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12855 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12856 return TRUE;
12857
12858 osec = sec->output_section;
12859 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12860 return TRUE;
12861
12862 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12863 sec->output_offset, sec->size))
12864 return FALSE;
12865
12866 return TRUE;
12867}
12868
12869static bfd_boolean
12870elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12871{
12872 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12873 asection *sec, *osec;
3e6b1042 12874
4dfe6ac6
NC		 12875 if (globals == NULL)
12876 return FALSE;
12877
3e6b1042
DJ		 12878 /* Invoke the regular ELF backend linker to do all the work. */
12879 if (!bfd_elf_final_link (abfd, info))
12880 return FALSE;
12881
fe33d2fa
CL		 12882 /* Process stub sections (eg BE8 encoding, ...). */
12883 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12884 unsigned int i;
cdb21a0a
NS		 12885 for (i=0; i<htab->top_id; i++)
12886 {
12887 sec = htab->stub_group[i].stub_sec;
12888 /* Only process it once, in its link_sec slot. */
12889 if (sec && i == htab->stub_group[i].link_sec->id)
12890 {
12891 osec = sec->output_section;
12892 elf32_arm_write_section (abfd, info, sec, sec->contents);
12893 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12894 sec->output_offset, sec->size))
12895 return FALSE;
12896 }
fe33d2fa 12897 }
fe33d2fa 12898
3e6b1042
DJ		 12899 /* Write out any glue sections now that we have created all the
12900 stubs. */
12901 if (globals->bfd_of_glue_owner != NULL)
12902 {
12903 if (! elf32_arm_output_glue_section (info, abfd,
12904 globals->bfd_of_glue_owner,
12905 ARM2THUMB_GLUE_SECTION_NAME))
12906 return FALSE;
12907
12908 if (! elf32_arm_output_glue_section (info, abfd,
12909 globals->bfd_of_glue_owner,
12910 THUMB2ARM_GLUE_SECTION_NAME))
12911 return FALSE;
12912
12913 if (! elf32_arm_output_glue_section (info, abfd,
12914 globals->bfd_of_glue_owner,
12915 VFP11_ERRATUM_VENEER_SECTION_NAME))
12916 return FALSE;
12917
a504d23a
LA		 12918 if (! elf32_arm_output_glue_section (info, abfd,
12919 globals->bfd_of_glue_owner,
12920 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12921 return FALSE;
12922
3e6b1042
DJ		 12923 if (! elf32_arm_output_glue_section (info, abfd,
12924 globals->bfd_of_glue_owner,
12925 ARM_BX_GLUE_SECTION_NAME))
12926 return FALSE;
12927 }
12928
12929 return TRUE;
12930}
12931
5968a7b8
NC		 12932/* Return a best guess for the machine number based on the attributes. */
12933
12934static unsigned int
12935bfd_arm_get_mach_from_attributes (bfd * abfd)
12936{
12937 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12938
12939 switch (arch)
12940 {
12941 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12942 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12943 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12944
12945 case TAG_CPU_ARCH_V5TE:
12946 {
12947 char * name;
12948
12949 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12950 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12951
12952 if (name)
12953 {
12954 if (strcmp (name, "IWMMXT2") == 0)
12955 return bfd_mach_arm_iWMMXt2;
12956
12957 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12958 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12959
12960 if (strcmp (name, "XSCALE") == 0)
12961 {
12962 int wmmx;
12963
12964 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12965 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12966 switch (wmmx)
12967 {
12968 case 1: return bfd_mach_arm_iWMMXt;
12969 case 2: return bfd_mach_arm_iWMMXt2;
12970 default: return bfd_mach_arm_XScale;
12971 }
12972 }
5968a7b8
NC		 12973 }
12974
12975 return bfd_mach_arm_5TE;
12976 }
12977
12978 default:
12979 return bfd_mach_arm_unknown;
12980 }
12981}
12982
c178919b
NC		 12983/* Set the right machine number. */
12984
12985static bfd_boolean
57e8b36a 12986elf32_arm_object_p (bfd *abfd)
c178919b 12987{
5a6c6817 12988 unsigned int mach;
57e8b36a 12989
5a6c6817 12990 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12991
5968a7b8
NC		 12992 if (mach == bfd_mach_arm_unknown)
12993 {
12994 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12995 mach = bfd_mach_arm_ep9312;
12996 else
12997 mach = bfd_arm_get_mach_from_attributes (abfd);
12998 }
c178919b 12999
5968a7b8 13000 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13001 return TRUE;
13002}
13003
fc830a83 13004/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13005
b34976b6 13006static bfd_boolean
57e8b36a 13007elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13008{
13009 if (elf_flags_init (abfd)
13010 && elf_elfheader (abfd)->e_flags != flags)
13011 {
fc830a83
NC		 13012 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13013 {
fd2ec330 13014 if (flags & EF_ARM_INTERWORK)
4eca0228 13015 _bfd_error_handler
d003868e
AM		 13016 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13017 abfd);
fc830a83 13018 else
d003868e
AM		 13019 _bfd_error_handler
13020 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13021 abfd);
fc830a83 13022 }
252b5132
RH		 13023 }
13024 else
13025 {
13026 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13027 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13028 }
13029
b34976b6 13030 return TRUE;
252b5132
RH		 13031}
13032
fc830a83 13033/* Copy backend specific data from one object module to another. */
9b485d32 13034
b34976b6 13035static bfd_boolean
57e8b36a 13036elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13037{
13038 flagword in_flags;
13039 flagword out_flags;
13040
0ffa91dd 13041 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13042 return TRUE;
252b5132 13043
fc830a83 13044 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13045 out_flags = elf_elfheader (obfd)->e_flags;
13046
fc830a83
NC		 13047 if (elf_flags_init (obfd)
13048 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13049 && in_flags != out_flags)
252b5132 13050 {
252b5132 13051 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13052 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13053 return FALSE;
252b5132
RH		 13054
13055 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13056 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13057 return FALSE;
252b5132
RH		 13058
13059 /* If the src and dest have different interworking flags
99059e56 13060 then turn off the interworking bit. */
fd2ec330 13061 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13062 {
fd2ec330 13063 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13064 _bfd_error_handler
13065 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13066 obfd, ibfd);
252b5132 13067
fd2ec330 13068 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13069 }
1006ba19
PB		 13070
13071 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13072 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13073 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13074 }
13075
13076 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13077 elf_flags_init (obfd) = TRUE;
252b5132 13078
e2349352 13079 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13080}
13081
13082/* Values for Tag_ABI_PCS_R9_use. */
13083enum
13084{
13085 AEABI_R9_V6,
13086 AEABI_R9_SB,
13087 AEABI_R9_TLS,
13088 AEABI_R9_unused
13089};
13090
13091/* Values for Tag_ABI_PCS_RW_data. */
13092enum
13093{
13094 AEABI_PCS_RW_data_absolute,
13095 AEABI_PCS_RW_data_PCrel,
13096 AEABI_PCS_RW_data_SBrel,
13097 AEABI_PCS_RW_data_unused
13098};
13099
13100/* Values for Tag_ABI_enum_size. */
13101enum
13102{
13103 AEABI_enum_unused,
13104 AEABI_enum_short,
13105 AEABI_enum_wide,
13106 AEABI_enum_forced_wide
13107};
13108
104d59d1
JM		 13109/* Determine whether an object attribute tag takes an integer, a
13110 string or both. */
906e58ca 13111
104d59d1
JM		 13112static int
13113elf32_arm_obj_attrs_arg_type (int tag)
13114{
13115 if (tag == Tag_compatibility)
3483fe2e 13116 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13117 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13118 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13119 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13120 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13121 else if (tag < 32)
3483fe2e 13122 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13123 else
3483fe2e 13124 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13125}
13126
5aa6ff7c
AS		 13127/* The ABI defines that Tag_conformance should be emitted first, and that
13128 Tag_nodefaults should be second (if either is defined). This sets those
13129 two positions, and bumps up the position of all the remaining tags to
13130 compensate. */
13131static int
13132elf32_arm_obj_attrs_order (int num)
13133{
3de4a297 13134 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13135 return Tag_conformance;
3de4a297 13136 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13137 return Tag_nodefaults;
13138 if ((num - 2) < Tag_nodefaults)
13139 return num - 2;
13140 if ((num - 1) < Tag_conformance)
13141 return num - 1;
13142 return num;
13143}
13144
e8b36cd1
JM		 13145/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13146static bfd_boolean
13147elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13148{
13149 if ((tag & 127) < 64)
13150 {
13151 _bfd_error_handler
13152 (_("%B: Unknown mandatory EABI object attribute %d"),
13153 abfd, tag);
13154 bfd_set_error (bfd_error_bad_value);
13155 return FALSE;
13156 }
13157 else
13158 {
13159 _bfd_error_handler
13160 (_("Warning: %B: Unknown EABI object attribute %d"),
13161 abfd, tag);
13162 return TRUE;
13163 }
13164}
13165
91e22acd
AS		 13166/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13167 Returns -1 if no architecture could be read. */
13168
13169static int
13170get_secondary_compatible_arch (bfd *abfd)
13171{
13172 obj_attribute *attr =
13173 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13174
13175 /* Note: the tag and its argument below are uleb128 values, though
13176 currently-defined values fit in one byte for each. */
13177 if (attr->s
13178 && attr->s[0] == Tag_CPU_arch
13179 && (attr->s[1] & 128) != 128
13180 && attr->s[2] == 0)
13181 return attr->s[1];
13182
13183 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13184 return -1;
13185}
13186
13187/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13188 The tag is removed if ARCH is -1. */
13189
8e79c3df 13190static void
91e22acd 13191set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13192{
91e22acd
AS		 13193 obj_attribute *attr =
13194 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13195
91e22acd
AS		 13196 if (arch == -1)
13197 {
13198 attr->s = NULL;
13199 return;
8e79c3df 13200 }
91e22acd
AS		 13201
13202 /* Note: the tag and its argument below are uleb128 values, though
13203 currently-defined values fit in one byte for each. */
13204 if (!attr->s)
21d799b5 13205 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13206 attr->s[0] = Tag_CPU_arch;
13207 attr->s[1] = arch;
13208 attr->s[2] = '\0';
8e79c3df
CM		 13209}
13210
91e22acd
AS		 13211/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13212 into account. */
13213
13214static int
13215tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13216 int newtag, int secondary_compat)
8e79c3df 13217{
91e22acd
AS		 13218#define T(X) TAG_CPU_ARCH_##X
13219 int tagl, tagh, result;
13220 const int v6t2[] =
13221 {
13222 T(V6T2), /* PRE_V4. */
13223 T(V6T2), /* V4. */
13224 T(V6T2), /* V4T. */
13225 T(V6T2), /* V5T. */
13226 T(V6T2), /* V5TE. */
13227 T(V6T2), /* V5TEJ. */
13228 T(V6T2), /* V6. */
13229 T(V7), /* V6KZ. */
13230 T(V6T2) /* V6T2. */
13231 };
13232 const int v6k[] =
13233 {
13234 T(V6K), /* PRE_V4. */
13235 T(V6K), /* V4. */
13236 T(V6K), /* V4T. */
13237 T(V6K), /* V5T. */
13238 T(V6K), /* V5TE. */
13239 T(V6K), /* V5TEJ. */
13240 T(V6K), /* V6. */
13241 T(V6KZ), /* V6KZ. */
13242 T(V7), /* V6T2. */
13243 T(V6K) /* V6K. */
13244 };
13245 const int v7[] =
13246 {
13247 T(V7), /* PRE_V4. */
13248 T(V7), /* V4. */
13249 T(V7), /* V4T. */
13250 T(V7), /* V5T. */
13251 T(V7), /* V5TE. */
13252 T(V7), /* V5TEJ. */
13253 T(V7), /* V6. */
13254 T(V7), /* V6KZ. */
13255 T(V7), /* V6T2. */
13256 T(V7), /* V6K. */
13257 T(V7) /* V7. */
13258 };
13259 const int v6_m[] =
13260 {
13261 -1, /* PRE_V4. */
13262 -1, /* V4. */
13263 T(V6K), /* V4T. */
13264 T(V6K), /* V5T. */
13265 T(V6K), /* V5TE. */
13266 T(V6K), /* V5TEJ. */
13267 T(V6K), /* V6. */
13268 T(V6KZ), /* V6KZ. */
13269 T(V7), /* V6T2. */
13270 T(V6K), /* V6K. */
13271 T(V7), /* V7. */
13272 T(V6_M) /* V6_M. */
13273 };
13274 const int v6s_m[] =
13275 {
13276 -1, /* PRE_V4. */
13277 -1, /* V4. */
13278 T(V6K), /* V4T. */
13279 T(V6K), /* V5T. */
13280 T(V6K), /* V5TE. */
13281 T(V6K), /* V5TEJ. */
13282 T(V6K), /* V6. */
13283 T(V6KZ), /* V6KZ. */
13284 T(V7), /* V6T2. */
13285 T(V6K), /* V6K. */
13286 T(V7), /* V7. */
13287 T(V6S_M), /* V6_M. */
13288 T(V6S_M) /* V6S_M. */
13289 };
9e3c6df6
PB		 13290 const int v7e_m[] =
13291 {
13292 -1, /* PRE_V4. */
13293 -1, /* V4. */
13294 T(V7E_M), /* V4T. */
13295 T(V7E_M), /* V5T. */
13296 T(V7E_M), /* V5TE. */
13297 T(V7E_M), /* V5TEJ. */
13298 T(V7E_M), /* V6. */
13299 T(V7E_M), /* V6KZ. */
13300 T(V7E_M), /* V6T2. */
13301 T(V7E_M), /* V6K. */
13302 T(V7E_M), /* V7. */
13303 T(V7E_M), /* V6_M. */
13304 T(V7E_M), /* V6S_M. */
13305 T(V7E_M) /* V7E_M. */
13306 };
bca38921
MGD		 13307 const int v8[] =
13308 {
13309 T(V8), /* PRE_V4. */
13310 T(V8), /* V4. */
13311 T(V8), /* V4T. */
13312 T(V8), /* V5T. */
13313 T(V8), /* V5TE. */
13314 T(V8), /* V5TEJ. */
13315 T(V8), /* V6. */
13316 T(V8), /* V6KZ. */
13317 T(V8), /* V6T2. */
13318 T(V8), /* V6K. */
13319 T(V8), /* V7. */
13320 T(V8), /* V6_M. */
13321 T(V8), /* V6S_M. */
13322 T(V8), /* V7E_M. */
13323 T(V8) /* V8. */
13324 };
2fd158eb
TP		 13325 const int v8m_baseline[] =
13326 {
13327 -1, /* PRE_V4. */
13328 -1, /* V4. */
13329 -1, /* V4T. */
13330 -1, /* V5T. */
13331 -1, /* V5TE. */
13332 -1, /* V5TEJ. */
13333 -1, /* V6. */
13334 -1, /* V6KZ. */
13335 -1, /* V6T2. */
13336 -1, /* V6K. */
13337 -1, /* V7. */
13338 T(V8M_BASE), /* V6_M. */
13339 T(V8M_BASE), /* V6S_M. */
13340 -1, /* V7E_M. */
13341 -1, /* V8. */
13342 -1,
13343 T(V8M_BASE) /* V8-M BASELINE. */
13344 };
13345 const int v8m_mainline[] =
13346 {
13347 -1, /* PRE_V4. */
13348 -1, /* V4. */
13349 -1, /* V4T. */
13350 -1, /* V5T. */
13351 -1, /* V5TE. */
13352 -1, /* V5TEJ. */
13353 -1, /* V6. */
13354 -1, /* V6KZ. */
13355 -1, /* V6T2. */
13356 -1, /* V6K. */
13357 T(V8M_MAIN), /* V7. */
13358 T(V8M_MAIN), /* V6_M. */
13359 T(V8M_MAIN), /* V6S_M. */
13360 T(V8M_MAIN), /* V7E_M. */
13361 -1, /* V8. */
13362 -1,
13363 T(V8M_MAIN), /* V8-M BASELINE. */
13364 T(V8M_MAIN) /* V8-M MAINLINE. */
13365 };
91e22acd
AS		 13366 const int v4t_plus_v6_m[] =
13367 {
13368 -1, /* PRE_V4. */
13369 -1, /* V4. */
13370 T(V4T), /* V4T. */
13371 T(V5T), /* V5T. */
13372 T(V5TE), /* V5TE. */
13373 T(V5TEJ), /* V5TEJ. */
13374 T(V6), /* V6. */
13375 T(V6KZ), /* V6KZ. */
13376 T(V6T2), /* V6T2. */
13377 T(V6K), /* V6K. */
13378 T(V7), /* V7. */
13379 T(V6_M), /* V6_M. */
13380 T(V6S_M), /* V6S_M. */
9e3c6df6 13381 T(V7E_M), /* V7E_M. */
bca38921 13382 T(V8), /* V8. */
4ed7ed8d 13383 -1, /* Unused. */
2fd158eb
TP		 13384 T(V8M_BASE), /* V8-M BASELINE. */
13385 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13386 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13387 };
13388 const int *comb[] =
13389 {
13390 v6t2,
13391 v6k,
13392 v7,
13393 v6_m,
13394 v6s_m,
9e3c6df6 13395 v7e_m,
bca38921 13396 v8,
4ed7ed8d 13397 NULL,
2fd158eb
TP		 13398 v8m_baseline,
13399 v8m_mainline,
91e22acd
AS		 13400 /* Pseudo-architecture. */
13401 v4t_plus_v6_m
13402 };
13403
13404 /* Check we've not got a higher architecture than we know about. */
13405
9e3c6df6 13406 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13407 {
3895f852 13408 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13409 return -1;
13410 }
13411
13412 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13413
13414 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13415 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13416 oldtag = T(V4T_PLUS_V6_M);
13417
13418 /* And override the new tag if we have a Tag_also_compatible_with on the
13419 input. */
13420
13421 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13422 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13423 newtag = T(V4T_PLUS_V6_M);
13424
13425 tagl = (oldtag < newtag) ? oldtag : newtag;
13426 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13427
13428 /* Architectures before V6KZ add features monotonically. */
13429 if (tagh <= TAG_CPU_ARCH_V6KZ)
13430 return result;
13431
4ed7ed8d 13432 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13433
13434 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13435 as the canonical version. */
13436 if (result == T(V4T_PLUS_V6_M))
13437 {
13438 result = T(V4T);
13439 *secondary_compat_out = T(V6_M);
13440 }
13441 else
13442 *secondary_compat_out = -1;
13443
13444 if (result == -1)
13445 {
3895f852 13446 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13447 ibfd, oldtag, newtag);
13448 return -1;
13449 }
13450
13451 return result;
13452#undef T
8e79c3df
CM		 13453}
13454
ac56ee8f
MGD		 13455/* Query attributes object to see if integer divide instructions may be
13456 present in an object. */
13457static bfd_boolean
13458elf32_arm_attributes_accept_div (const obj_attribute *attr)
13459{
13460 int arch = attr[Tag_CPU_arch].i;
13461 int profile = attr[Tag_CPU_arch_profile].i;
13462
13463 switch (attr[Tag_DIV_use].i)
13464 {
13465 case 0:
13466 /* Integer divide allowed if instruction contained in archetecture. */
13467 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13468 return TRUE;
13469 else if (arch >= TAG_CPU_ARCH_V7E_M)
13470 return TRUE;
13471 else
13472 return FALSE;
13473
13474 case 1:
13475 /* Integer divide explicitly prohibited. */
13476 return FALSE;
13477
13478 default:
13479 /* Unrecognised case - treat as allowing divide everywhere. */
13480 case 2:
13481 /* Integer divide allowed in ARM state. */
13482 return TRUE;
13483 }
13484}
13485
13486/* Query attributes object to see if integer divide instructions are
13487 forbidden to be in the object. This is not the inverse of
13488 elf32_arm_attributes_accept_div. */
13489static bfd_boolean
13490elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13491{
13492 return attr[Tag_DIV_use].i == 1;
13493}
13494
ee065d83
PB		 13495/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13496 are conflicting attributes. */
906e58ca 13497
ee065d83 13498static bfd_boolean
50e03d47 13499elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13500{
50e03d47 13501 bfd *obfd = info->output_bfd;
104d59d1
JM		 13502 obj_attribute *in_attr;
13503 obj_attribute *out_attr;
ee065d83
PB		 13504 /* Some tags have 0 = don't care, 1 = strong requirement,
13505 2 = weak requirement. */
91e22acd 13506 static const int order_021[3] = {0, 2, 1};
ee065d83 13507 int i;
91e22acd 13508 bfd_boolean result = TRUE;
9274e9de 13509 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13510
3e6b1042
DJ		 13511 /* Skip the linker stubs file. This preserves previous behavior
13512 of accepting unknown attributes in the first input file - but
13513 is that a bug? */
13514 if (ibfd->flags & BFD_LINKER_CREATED)
13515 return TRUE;
13516
9274e9de
TG		 13517 /* Skip any input that hasn't attribute section.
13518 This enables to link object files without attribute section with
13519 any others. */
13520 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13521 return TRUE;
13522
104d59d1 13523 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13524 {
13525 /* This is the first object. Copy the attributes. */
104d59d1 13526 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13527
cd21e546
MGD		 13528 out_attr = elf_known_obj_attributes_proc (obfd);
13529
004ae526
PB		 13530 /* Use the Tag_null value to indicate the attributes have been
13531 initialized. */
cd21e546 13532 out_attr[0].i = 1;
004ae526 13533
cd21e546
MGD		 13534 /* We do not output objects with Tag_MPextension_use_legacy - we move
13535 the attribute's value to Tag_MPextension_use. */
13536 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13537 {
13538 if (out_attr[Tag_MPextension_use].i != 0
13539 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13540 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13541 {
13542 _bfd_error_handler
13543 (_("Error: %B has both the current and legacy "
13544 "Tag_MPextension_use attributes"), ibfd);
13545 result = FALSE;
13546 }
13547
13548 out_attr[Tag_MPextension_use] =
13549 out_attr[Tag_MPextension_use_legacy];
13550 out_attr[Tag_MPextension_use_legacy].type = 0;
13551 out_attr[Tag_MPextension_use_legacy].i = 0;
13552 }
13553
13554 return result;
ee065d83
PB		 13555 }
13556
104d59d1
JM		 13557 in_attr = elf_known_obj_attributes_proc (ibfd);
13558 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13559 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13560 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13561 {
5c294fee
TG		 13562 /* Ignore mismatches if the object doesn't use floating point or is
13563 floating point ABI independent. */
13564 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13565 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13566 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13567 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13568 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13569 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13570 {
13571 _bfd_error_handler
3895f852 13572 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13573 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13574 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13575 result = FALSE;
ee065d83
PB		 13576 }
13577 }
13578
3de4a297 13579 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13580 {
13581 /* Merge this attribute with existing attributes. */
13582 switch (i)
13583 {
13584 case Tag_CPU_raw_name:
13585 case Tag_CPU_name:
6a631e86 13586 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13587 break;
13588
13589 case Tag_ABI_optimization_goals:
13590 case Tag_ABI_FP_optimization_goals:
13591 /* Use the first value seen. */
13592 break;
13593
13594 case Tag_CPU_arch:
91e22acd
AS		 13595 {
13596 int secondary_compat = -1, secondary_compat_out = -1;
13597 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13598 int arch_attr;
13599 static const char *name_table[] =
13600 {
91e22acd
AS		 13601 /* These aren't real CPU names, but we can't guess
13602 that from the architecture version alone. */
13603 "Pre v4",
13604 "ARM v4",
13605 "ARM v4T",
13606 "ARM v5T",
13607 "ARM v5TE",
13608 "ARM v5TEJ",
13609 "ARM v6",
13610 "ARM v6KZ",
13611 "ARM v6T2",
13612 "ARM v6K",
13613 "ARM v7",
13614 "ARM v6-M",
bca38921 13615 "ARM v6S-M",
2fd158eb
TP		 13616 "ARM v8",
13617 "",
13618 "ARM v8-M.baseline",
13619 "ARM v8-M.mainline",
91e22acd
AS		 13620 };
13621
13622 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13623 secondary_compat = get_secondary_compatible_arch (ibfd);
13624 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13625 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13626 &secondary_compat_out,
13627 in_attr[i].i,
13628 secondary_compat);
13629
13630 /* Return with error if failed to merge. */
13631 if (arch_attr == -1)
13632 return FALSE;
13633
13634 out_attr[i].i = arch_attr;
13635
91e22acd
AS		 13636 set_secondary_compatible_arch (obfd, secondary_compat_out);
13637
13638 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13639 if (out_attr[i].i == saved_out_attr)
13640 ; /* Leave the names alone. */
13641 else if (out_attr[i].i == in_attr[i].i)
13642 {
13643 /* The output architecture has been changed to match the
13644 input architecture. Use the input names. */
13645 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13646 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13647 : NULL;
13648 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13649 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13650 : NULL;
13651 }
13652 else
13653 {
13654 out_attr[Tag_CPU_name].s = NULL;
13655 out_attr[Tag_CPU_raw_name].s = NULL;
13656 }
13657
13658 /* If we still don't have a value for Tag_CPU_name,
13659 make one up now. Tag_CPU_raw_name remains blank. */
13660 if (out_attr[Tag_CPU_name].s == NULL
13661 && out_attr[i].i < ARRAY_SIZE (name_table))
13662 out_attr[Tag_CPU_name].s =
13663 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13664 }
13665 break;
13666
ee065d83
PB		 13667 case Tag_ARM_ISA_use:
13668 case Tag_THUMB_ISA_use:
ee065d83 13669 case Tag_WMMX_arch:
91e22acd
AS		 13670 case Tag_Advanced_SIMD_arch:
13671 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13672 case Tag_ABI_FP_rounding:
ee065d83
PB		 13673 case Tag_ABI_FP_exceptions:
13674 case Tag_ABI_FP_user_exceptions:
13675 case Tag_ABI_FP_number_model:
75375b3e 13676 case Tag_FP_HP_extension:
91e22acd
AS		 13677 case Tag_CPU_unaligned_access:
13678 case Tag_T2EE_use:
91e22acd 13679 case Tag_MPextension_use:
ee065d83
PB		 13680 /* Use the largest value specified. */
13681 if (in_attr[i].i > out_attr[i].i)
13682 out_attr[i].i = in_attr[i].i;
13683 break;
13684
75375b3e 13685 case Tag_ABI_align_preserved:
91e22acd
AS		 13686 case Tag_ABI_PCS_RO_data:
13687 /* Use the smallest value specified. */
13688 if (in_attr[i].i < out_attr[i].i)
13689 out_attr[i].i = in_attr[i].i;
13690 break;
13691
75375b3e 13692 case Tag_ABI_align_needed:
91e22acd 13693 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13694 && (in_attr[Tag_ABI_align_preserved].i == 0
13695 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13696 {
91e22acd
AS		 13697 /* This error message should be enabled once all non-conformant
13698 binaries in the toolchain have had the attributes set
13699 properly.
ee065d83 13700 _bfd_error_handler
3895f852 13701 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13702 obfd, ibfd);
13703 result = FALSE; */
ee065d83 13704 }
91e22acd
AS		 13705 /* Fall through. */
13706 case Tag_ABI_FP_denormal:
13707 case Tag_ABI_PCS_GOT_use:
13708 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13709 value if greater than 2 (for future-proofing). */
13710 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13711 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13712 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13713 out_attr[i].i = in_attr[i].i;
13714 break;
91e22acd 13715
75375b3e
MGD		 13716 case Tag_Virtualization_use:
13717 /* The virtualization tag effectively stores two bits of
13718 information: the intended use of TrustZone (in bit 0), and the
13719 intended use of Virtualization (in bit 1). */
13720 if (out_attr[i].i == 0)
13721 out_attr[i].i = in_attr[i].i;
13722 else if (in_attr[i].i != 0
13723 && in_attr[i].i != out_attr[i].i)
13724 {
13725 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13726 out_attr[i].i = 3;
13727 else
13728 {
13729 _bfd_error_handler
13730 (_("error: %B: unable to merge virtualization attributes "
13731 "with %B"),
13732 obfd, ibfd);
13733 result = FALSE;
13734 }
13735 }
13736 break;
91e22acd
AS		 13737
13738 case Tag_CPU_arch_profile:
13739 if (out_attr[i].i != in_attr[i].i)
13740 {
13741 /* 0 will merge with anything.
13742 'A' and 'S' merge to 'A'.
13743 'R' and 'S' merge to 'R'.
99059e56 13744 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13745 if (out_attr[i].i == 0
13746 || (out_attr[i].i == 'S'
13747 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13748 out_attr[i].i = in_attr[i].i;
13749 else if (in_attr[i].i == 0
13750 || (in_attr[i].i == 'S'
13751 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13752 ; /* Do nothing. */
91e22acd
AS		 13753 else
13754 {
13755 _bfd_error_handler
3895f852 13756 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13757 ibfd,
13758 in_attr[i].i ? in_attr[i].i : '0',
13759 out_attr[i].i ? out_attr[i].i : '0');
13760 result = FALSE;
13761 }
13762 }
13763 break;
15afaa63
TP		 13764
13765 case Tag_DSP_extension:
13766 /* No need to change output value if any of:
13767 - pre (<=) ARMv5T input architecture (do not have DSP)
13768 - M input profile not ARMv7E-M and do not have DSP. */
13769 if (in_attr[Tag_CPU_arch].i <= 3
13770 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13771 && in_attr[Tag_CPU_arch].i != 13
13772 && in_attr[i].i == 0))
13773 ; /* Do nothing. */
13774 /* Output value should be 0 if DSP part of architecture, ie.
13775 - post (>=) ARMv5te architecture output
13776 - A, R or S profile output or ARMv7E-M output architecture. */
13777 else if (out_attr[Tag_CPU_arch].i >= 4
13778 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13779 || out_attr[Tag_CPU_arch_profile].i == 'R'
13780 || out_attr[Tag_CPU_arch_profile].i == 'S'
13781 || out_attr[Tag_CPU_arch].i == 13))
13782 out_attr[i].i = 0;
13783 /* Otherwise, DSP instructions are added and not part of output
13784 architecture. */
13785 else
13786 out_attr[i].i = 1;
13787 break;
13788
75375b3e 13789 case Tag_FP_arch:
62f3b8c8 13790 {
4547cb56
NC		 13791 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13792 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13793 when it's 0. It might mean absence of FP hardware if
99654aaf 13794 Tag_FP_arch is zero. */
4547cb56 13795
a715796b 13796#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13797 static const struct
13798 {
13799 int ver;
13800 int regs;
bca38921 13801 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13802 {
13803 {0, 0},
13804 {1, 16},
13805 {2, 16},
13806 {3, 32},
13807 {3, 16},
13808 {4, 32},
bca38921 13809 {4, 16},
a715796b
TG		 13810 {8, 32},
13811 {8, 16}
62f3b8c8
PB		 13812 };
13813 int ver;
13814 int regs;
13815 int newval;
13816
4547cb56
NC		 13817 /* If the output has no requirement about FP hardware,
13818 follow the requirement of the input. */
13819 if (out_attr[i].i == 0)
13820 {
13821 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13822 out_attr[i].i = in_attr[i].i;
13823 out_attr[Tag_ABI_HardFP_use].i
13824 = in_attr[Tag_ABI_HardFP_use].i;
13825 break;
13826 }
13827 /* If the input has no requirement about FP hardware, do
13828 nothing. */
13829 else if (in_attr[i].i == 0)
13830 {
13831 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13832 break;
13833 }
13834
13835 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13836 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13837
13838 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13839 do nothing. */
13840 if (in_attr[Tag_ABI_HardFP_use].i == 0
13841 && out_attr[Tag_ABI_HardFP_use].i == 0)
13842 ;
13843 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13844 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13845 else if (in_attr[Tag_ABI_HardFP_use].i
13846 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13847 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13848
13849 /* Now we can handle Tag_FP_arch. */
13850
bca38921
MGD		 13851 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13852 pick the biggest. */
13853 if (in_attr[i].i >= VFP_VERSION_COUNT
13854 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13855 {
13856 out_attr[i] = in_attr[i];
13857 break;
13858 }
13859 /* The output uses the superset of input features
13860 (ISA version) and registers. */
13861 ver = vfp_versions[in_attr[i].i].ver;
13862 if (ver < vfp_versions[out_attr[i].i].ver)
13863 ver = vfp_versions[out_attr[i].i].ver;
13864 regs = vfp_versions[in_attr[i].i].regs;
13865 if (regs < vfp_versions[out_attr[i].i].regs)
13866 regs = vfp_versions[out_attr[i].i].regs;
13867 /* This assumes all possible supersets are also a valid
99059e56 13868 options. */
bca38921 13869 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13870 {
13871 if (regs == vfp_versions[newval].regs
13872 && ver == vfp_versions[newval].ver)
13873 break;
13874 }
13875 out_attr[i].i = newval;
13876 }
b1cc4aeb 13877 break;
ee065d83
PB		 13878 case Tag_PCS_config:
13879 if (out_attr[i].i == 0)
13880 out_attr[i].i = in_attr[i].i;
b6009aca 13881 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13882 {
13883 /* It's sometimes ok to mix different configs, so this is only
99059e56 13884 a warning. */
ee065d83
PB		 13885 _bfd_error_handler
13886 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13887 }
13888 break;
13889 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13890 if (in_attr[i].i != out_attr[i].i
13891 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13892 && in_attr[i].i != AEABI_R9_unused)
13893 {
13894 _bfd_error_handler
3895f852 13895 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13896 result = FALSE;
ee065d83
PB		 13897 }
13898 if (out_attr[i].i == AEABI_R9_unused)
13899 out_attr[i].i = in_attr[i].i;
13900 break;
13901 case Tag_ABI_PCS_RW_data:
13902 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13903 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13904 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13905 {
13906 _bfd_error_handler
3895f852 13907 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13908 ibfd);
91e22acd 13909 result = FALSE;
ee065d83
PB		 13910 }
13911 /* Use the smallest value specified. */
13912 if (in_attr[i].i < out_attr[i].i)
13913 out_attr[i].i = in_attr[i].i;
13914 break;
ee065d83 13915 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13916 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13917 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13918 {
13919 _bfd_error_handler
a9dc9481
JM		 13920 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13921 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13922 }
a9dc9481 13923 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13924 out_attr[i].i = in_attr[i].i;
13925 break;
ee065d83
PB		 13926 case Tag_ABI_enum_size:
13927 if (in_attr[i].i != AEABI_enum_unused)
13928 {
13929 if (out_attr[i].i == AEABI_enum_unused
13930 || out_attr[i].i == AEABI_enum_forced_wide)
13931 {
13932 /* The existing object is compatible with anything.
13933 Use whatever requirements the new object has. */
13934 out_attr[i].i = in_attr[i].i;
13935 }
13936 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13937 && out_attr[i].i != in_attr[i].i
0ffa91dd 13938 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13939 {
91e22acd 13940 static const char *aeabi_enum_names[] =
bf21ed78 13941 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13942 const char *in_name =
13943 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13944 ? aeabi_enum_names[in_attr[i].i]
13945 : "<unknown>";
13946 const char *out_name =
13947 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13948 ? aeabi_enum_names[out_attr[i].i]
13949 : "<unknown>";
ee065d83 13950 _bfd_error_handler
bf21ed78 13951 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13952 ibfd, in_name, out_name);
ee065d83
PB		 13953 }
13954 }
13955 break;
13956 case Tag_ABI_VFP_args:
13957 /* Aready done. */
13958 break;
13959 case Tag_ABI_WMMX_args:
13960 if (in_attr[i].i != out_attr[i].i)
13961 {
13962 _bfd_error_handler
3895f852 13963 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13964 ibfd, obfd);
91e22acd 13965 result = FALSE;
ee065d83
PB		 13966 }
13967 break;
7b86a9fa
AS		 13968 case Tag_compatibility:
13969 /* Merged in target-independent code. */
13970 break;
91e22acd 13971 case Tag_ABI_HardFP_use:
4547cb56 13972 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13973 break;
13974 case Tag_ABI_FP_16bit_format:
13975 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13976 {
13977 if (in_attr[i].i != out_attr[i].i)
13978 {
13979 _bfd_error_handler
3895f852 13980 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13981 ibfd, obfd);
13982 result = FALSE;
13983 }
13984 }
13985 if (in_attr[i].i != 0)
13986 out_attr[i].i = in_attr[i].i;
13987 break;
7b86a9fa 13988
cd21e546 13989 case Tag_DIV_use:
ac56ee8f
MGD		 13990 /* A value of zero on input means that the divide instruction may
13991 be used if available in the base architecture as specified via
13992 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13993 the user did not want divide instructions. A value of 2
13994 explicitly means that divide instructions were allowed in ARM
13995 and Thumb state. */
13996 if (in_attr[i].i == out_attr[i].i)
13997 /* Do nothing. */ ;
13998 else if (elf32_arm_attributes_forbid_div (in_attr)
13999 && !elf32_arm_attributes_accept_div (out_attr))
14000 out_attr[i].i = 1;
14001 else if (elf32_arm_attributes_forbid_div (out_attr)
14002 && elf32_arm_attributes_accept_div (in_attr))
14003 out_attr[i].i = in_attr[i].i;
14004 else if (in_attr[i].i == 2)
14005 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14006 break;
14007
14008 case Tag_MPextension_use_legacy:
14009 /* We don't output objects with Tag_MPextension_use_legacy - we
14010 move the value to Tag_MPextension_use. */
14011 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14012 {
14013 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14014 {
14015 _bfd_error_handler
14016 (_("%B has has both the current and legacy "
b38cadfb 14017 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14018 ibfd);
14019 result = FALSE;
14020 }
14021 }
14022
14023 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14024 out_attr[Tag_MPextension_use] = in_attr[i];
14025
14026 break;
14027
91e22acd 14028 case Tag_nodefaults:
2d0bb761
AS		 14029 /* This tag is set if it exists, but the value is unused (and is
14030 typically zero). We don't actually need to do anything here -
14031 the merge happens automatically when the type flags are merged
14032 below. */
91e22acd
AS		 14033 break;
14034 case Tag_also_compatible_with:
14035 /* Already done in Tag_CPU_arch. */
14036 break;
14037 case Tag_conformance:
14038 /* Keep the attribute if it matches. Throw it away otherwise.
14039 No attribute means no claim to conform. */
14040 if (!in_attr[i].s || !out_attr[i].s
14041 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14042 out_attr[i].s = NULL;
14043 break;
3cfad14c 14044
91e22acd 14045 default:
e8b36cd1
JM		 14046 result
14047 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14048 }
14049
14050 /* If out_attr was copied from in_attr then it won't have a type yet. */
14051 if (in_attr[i].type && !out_attr[i].type)
14052 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14053 }
14054
104d59d1 14055 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14056 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14057 return FALSE;
ee065d83 14058
104d59d1 14059 /* Check for any attributes not known on ARM. */
e8b36cd1 14060 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14061
91e22acd 14062 return result;
252b5132
RH		 14063}
14064
3a4a14e9
PB		 14065
14066/* Return TRUE if the two EABI versions are incompatible. */
14067
14068static bfd_boolean
14069elf32_arm_versions_compatible (unsigned iver, unsigned over)
14070{
14071 /* v4 and v5 are the same spec before and after it was released,
14072 so allow mixing them. */
14073 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14074 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14075 return TRUE;
14076
14077 return (iver == over);
14078}
14079
252b5132
RH		 14080/* Merge backend specific data from an object file to the output
14081 object file when linking. */
9b485d32 14082
b34976b6 14083static bfd_boolean
50e03d47 14084elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14085
9b485d32
NC		 14086/* Display the flags field. */
14087
b34976b6 14088static bfd_boolean
57e8b36a 14089elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14090{
fc830a83
NC		 14091 FILE * file = (FILE *) ptr;
14092 unsigned long flags;
252b5132
RH		 14093
14094 BFD_ASSERT (abfd != NULL && ptr != NULL);
14095
14096 /* Print normal ELF private data. */
14097 _bfd_elf_print_private_bfd_data (abfd, ptr);
14098
fc830a83 14099 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14100 /* Ignore init flag - it may not be set, despite the flags field
14101 containing valid data. */
252b5132 14102
9b485d32 14103 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14104
fc830a83
NC		 14105 switch (EF_ARM_EABI_VERSION (flags))
14106 {
14107 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14108 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14109 official ARM ELF extended ABI. Hence they are only decoded if
14110 the EABI version is not set. */
fd2ec330 14111 if (flags & EF_ARM_INTERWORK)
9b485d32 14112 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14113
fd2ec330 14114 if (flags & EF_ARM_APCS_26)
6c571f00 14115 fprintf (file, " [APCS-26]");
fc830a83 14116 else
6c571f00 14117 fprintf (file, " [APCS-32]");
9a5aca8c 14118
96a846ea
RE		 14119 if (flags & EF_ARM_VFP_FLOAT)
14120 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14121 else if (flags & EF_ARM_MAVERICK_FLOAT)
14122 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14123 else
14124 fprintf (file, _(" [FPA float format]"));
14125
fd2ec330 14126 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14127 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14128
fd2ec330 14129 if (flags & EF_ARM_PIC)
9b485d32 14130 fprintf (file, _(" [position independent]"));
fc830a83 14131
fd2ec330 14132 if (flags & EF_ARM_NEW_ABI)
9b485d32 14133 fprintf (file, _(" [new ABI]"));
9a5aca8c 14134
fd2ec330 14135 if (flags & EF_ARM_OLD_ABI)
9b485d32 14136 fprintf (file, _(" [old ABI]"));
9a5aca8c 14137
fd2ec330 14138 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14139 fprintf (file, _(" [software FP]"));
9a5aca8c 14140
96a846ea
RE		 14141 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14142 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14143 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14144 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14145 break;
9a5aca8c 14146
fc830a83 14147 case EF_ARM_EABI_VER1:
9b485d32 14148 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14149
fc830a83 14150 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14151 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14152 else
9b485d32 14153 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14154
fc830a83
NC		 14155 flags &= ~ EF_ARM_SYMSARESORTED;
14156 break;
9a5aca8c 14157
fd2ec330
PB		 14158 case EF_ARM_EABI_VER2:
14159 fprintf (file, _(" [Version2 EABI]"));
14160
14161 if (flags & EF_ARM_SYMSARESORTED)
14162 fprintf (file, _(" [sorted symbol table]"));
14163 else
14164 fprintf (file, _(" [unsorted symbol table]"));
14165
14166 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14167 fprintf (file, _(" [dynamic symbols use segment index]"));
14168
14169 if (flags & EF_ARM_MAPSYMSFIRST)
14170 fprintf (file, _(" [mapping symbols precede others]"));
14171
99e4ae17 14172 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14173 | EF_ARM_MAPSYMSFIRST);
14174 break;
14175
d507cf36
PB		 14176 case EF_ARM_EABI_VER3:
14177 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14178 break;
14179
14180 case EF_ARM_EABI_VER4:
14181 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14182 goto eabi;
d507cf36 14183
3a4a14e9
PB		 14184 case EF_ARM_EABI_VER5:
14185 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14186
14187 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14188 fprintf (file, _(" [soft-float ABI]"));
14189
14190 if (flags & EF_ARM_ABI_FLOAT_HARD)
14191 fprintf (file, _(" [hard-float ABI]"));
14192
14193 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14194
3a4a14e9 14195 eabi:
d507cf36
PB		 14196 if (flags & EF_ARM_BE8)
14197 fprintf (file, _(" [BE8]"));
14198
14199 if (flags & EF_ARM_LE8)
14200 fprintf (file, _(" [LE8]"));
14201
14202 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14203 break;
14204
fc830a83 14205 default:
9b485d32 14206 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14207 break;
14208 }
252b5132 14209
fc830a83 14210 flags &= ~ EF_ARM_EABIMASK;
252b5132 14211
fc830a83 14212 if (flags & EF_ARM_RELEXEC)
9b485d32 14213 fprintf (file, _(" [relocatable executable]"));
252b5132 14214
a5721edd 14215 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14216
14217 if (flags)
9b485d32 14218 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14219
252b5132
RH		 14220 fputc ('\n', file);
14221
b34976b6 14222 return TRUE;
252b5132
RH		 14223}
14224
14225static int
57e8b36a 14226elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14227{
2f0ca46a
NC		 14228 switch (ELF_ST_TYPE (elf_sym->st_info))
14229 {
14230 case STT_ARM_TFUNC:
14231 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14232
2f0ca46a
NC		 14233 case STT_ARM_16BIT:
14234 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14235 This allows us to distinguish between data used by Thumb instructions
14236 and non-data (which is probably code) inside Thumb regions of an
14237 executable. */
1a0eb693 14238 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14239 return ELF_ST_TYPE (elf_sym->st_info);
14240 break;
9a5aca8c 14241
ce855c42
NC		 14242 default:
14243 break;
2f0ca46a
NC		 14244 }
14245
14246 return type;
252b5132 14247}
f21f3fe0 14248
252b5132 14249static asection *
07adf181
AM		 14250elf32_arm_gc_mark_hook (asection *sec,
14251 struct bfd_link_info *info,
14252 Elf_Internal_Rela *rel,
14253 struct elf_link_hash_entry *h,
14254 Elf_Internal_Sym *sym)
252b5132
RH		 14255{
14256 if (h != NULL)
07adf181 14257 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14258 {
14259 case R_ARM_GNU_VTINHERIT:
14260 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14261 return NULL;
14262 }
9ad5cbcf 14263
07adf181 14264 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14265}
14266
780a67af
NC		 14267/* Update the got entry reference counts for the section being removed. */
14268
b34976b6 14269static bfd_boolean
ba93b8ac
DJ		 14270elf32_arm_gc_sweep_hook (bfd * abfd,
14271 struct bfd_link_info * info,
14272 asection * sec,
14273 const Elf_Internal_Rela * relocs)
252b5132 14274{
5e681ec4
PB		 14275 Elf_Internal_Shdr *symtab_hdr;
14276 struct elf_link_hash_entry **sym_hashes;
14277 bfd_signed_vma *local_got_refcounts;
14278 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14279 struct elf32_arm_link_hash_table * globals;
14280
0e1862bb 14281 if (bfd_link_relocatable (info))
7dda2462
TG		 14282 return TRUE;
14283
eb043451 14284 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14285 if (globals == NULL)
14286 return FALSE;
5e681ec4
PB		 14287
14288 elf_section_data (sec)->local_dynrel = NULL;
14289
0ffa91dd 14290 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14291 sym_hashes = elf_sym_hashes (abfd);
14292 local_got_refcounts = elf_local_got_refcounts (abfd);
14293
906e58ca 14294 check_use_blx (globals);
bd97cb95 14295
5e681ec4
PB		 14296 relend = relocs + sec->reloc_count;
14297 for (rel = relocs; rel < relend; rel++)
eb043451 14298 {
3eb128b2
AM		 14299 unsigned long r_symndx;
14300 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14301 struct elf32_arm_link_hash_entry *eh;
eb043451 14302 int r_type;
34e77a92 14303 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14304 bfd_boolean may_become_dynamic_p;
14305 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14306 union gotplt_union *root_plt;
14307 struct arm_plt_info *arm_plt;
5e681ec4 14308
3eb128b2
AM		 14309 r_symndx = ELF32_R_SYM (rel->r_info);
14310 if (r_symndx >= symtab_hdr->sh_info)
14311 {
14312 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14313 while (h->root.type == bfd_link_hash_indirect
14314 || h->root.type == bfd_link_hash_warning)
14315 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14316 }
f6e32f6d
RS		 14317 eh = (struct elf32_arm_link_hash_entry *) h;
14318
34e77a92 14319 call_reloc_p = FALSE;
f6e32f6d
RS		 14320 may_become_dynamic_p = FALSE;
14321 may_need_local_target_p = FALSE;
3eb128b2 14322
eb043451 14323 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14324 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14325 switch (r_type)
14326 {
14327 case R_ARM_GOT32:
eb043451 14328 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14329 case R_ARM_TLS_GD32:
14330 case R_ARM_TLS_IE32:
3eb128b2 14331 if (h != NULL)
eb043451 14332 {
eb043451
PB		 14333 if (h->got.refcount > 0)
14334 h->got.refcount -= 1;
14335 }
14336 else if (local_got_refcounts != NULL)
14337 {
14338 if (local_got_refcounts[r_symndx] > 0)
14339 local_got_refcounts[r_symndx] -= 1;
14340 }
14341 break;
14342
ba93b8ac 14343 case R_ARM_TLS_LDM32:
4dfe6ac6 14344 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14345 break;
14346
eb043451
PB		 14347 case R_ARM_PC24:
14348 case R_ARM_PLT32:
5b5bb741
PB		 14349 case R_ARM_CALL:
14350 case R_ARM_JUMP24:
eb043451 14351 case R_ARM_PREL31:
c19d1205 14352 case R_ARM_THM_CALL:
bd97cb95
DJ		 14353 case R_ARM_THM_JUMP24:
14354 case R_ARM_THM_JUMP19:
34e77a92 14355 call_reloc_p = TRUE;
f6e32f6d
RS		 14356 may_need_local_target_p = TRUE;
14357 break;
14358
14359 case R_ARM_ABS12:
14360 if (!globals->vxworks_p)
14361 {
14362 may_need_local_target_p = TRUE;
14363 break;
14364 }
14365 /* Fall through. */
14366 case R_ARM_ABS32:
14367 case R_ARM_ABS32_NOI:
14368 case R_ARM_REL32:
14369 case R_ARM_REL32_NOI:
b6895b4f
PB		 14370 case R_ARM_MOVW_ABS_NC:
14371 case R_ARM_MOVT_ABS:
14372 case R_ARM_MOVW_PREL_NC:
14373 case R_ARM_MOVT_PREL:
14374 case R_ARM_THM_MOVW_ABS_NC:
14375 case R_ARM_THM_MOVT_ABS:
14376 case R_ARM_THM_MOVW_PREL_NC:
14377 case R_ARM_THM_MOVT_PREL:
b7693d02 14378 /* Should the interworking branches be here also? */
0e1862bb 14379 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14380 && (sec->flags & SEC_ALLOC) != 0)
14381 {
14382 if (h == NULL
469a3493 14383 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14384 {
14385 call_reloc_p = TRUE;
14386 may_need_local_target_p = TRUE;
14387 }
14388 else
14389 may_become_dynamic_p = TRUE;
14390 }
f6e32f6d
RS		 14391 else
14392 may_need_local_target_p = TRUE;
14393 break;
b7693d02 14394
f6e32f6d
RS		 14395 default:
14396 break;
14397 }
5e681ec4 14398
34e77a92 14399 if (may_need_local_target_p
4ba2ef8f
TP		 14400 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14401 &arm_plt))
f6e32f6d 14402 {
27586251
HPN		 14403 /* If PLT refcount book-keeping is wrong and too low, we'll
14404 see a zero value (going to -1) for the root PLT reference
14405 count. */
14406 if (root_plt->refcount >= 0)
14407 {
14408 BFD_ASSERT (root_plt->refcount != 0);
14409 root_plt->refcount -= 1;
14410 }
14411 else
14412 /* A value of -1 means the symbol has become local, forced
14413 or seeing a hidden definition. Any other negative value
14414 is an error. */
14415 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14416
14417 if (!call_reloc_p)
14418 arm_plt->noncall_refcount--;
5e681ec4 14419
f6e32f6d 14420 if (r_type == R_ARM_THM_CALL)
34e77a92 14421 arm_plt->maybe_thumb_refcount--;
bd97cb95 14422
f6e32f6d
RS		 14423 if (r_type == R_ARM_THM_JUMP24
14424 || r_type == R_ARM_THM_JUMP19)
34e77a92 14425 arm_plt->thumb_refcount--;
f6e32f6d 14426 }
5e681ec4 14427
34e77a92 14428 if (may_become_dynamic_p)
f6e32f6d
RS		 14429 {
14430 struct elf_dyn_relocs **pp;
14431 struct elf_dyn_relocs *p;
5e681ec4 14432
34e77a92 14433 if (h != NULL)
9c489990 14434 pp = &(eh->dyn_relocs);
34e77a92
RS		 14435 else
14436 {
14437 Elf_Internal_Sym *isym;
14438
14439 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14440 abfd, r_symndx);
14441 if (isym == NULL)
14442 return FALSE;
14443 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14444 if (pp == NULL)
14445 return FALSE;
14446 }
9c489990 14447 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14448 if (p->sec == sec)
14449 {
14450 /* Everything must go for SEC. */
14451 *pp = p->next;
14452 break;
14453 }
eb043451
PB		 14454 }
14455 }
5e681ec4 14456
b34976b6 14457 return TRUE;
252b5132
RH		 14458}
14459
780a67af
NC		 14460/* Look through the relocs for a section during the first phase. */
14461
b34976b6 14462static bfd_boolean
57e8b36a
NC		 14463elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14464 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14465{
b34976b6
AM		 14466 Elf_Internal_Shdr *symtab_hdr;
14467 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14468 const Elf_Internal_Rela *rel;
14469 const Elf_Internal_Rela *rel_end;
14470 bfd *dynobj;
5e681ec4 14471 asection *sreloc;
5e681ec4 14472 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14473 bfd_boolean call_reloc_p;
14474 bfd_boolean may_become_dynamic_p;
14475 bfd_boolean may_need_local_target_p;
ce98a316 14476 unsigned long nsyms;
9a5aca8c 14477
0e1862bb 14478 if (bfd_link_relocatable (info))
b34976b6 14479 return TRUE;
9a5aca8c 14480
0ffa91dd
NC		 14481 BFD_ASSERT (is_arm_elf (abfd));
14482
5e681ec4 14483 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14484 if (htab == NULL)
14485 return FALSE;
14486
5e681ec4 14487 sreloc = NULL;
9a5aca8c 14488
67687978
PB		 14489 /* Create dynamic sections for relocatable executables so that we can
14490 copy relocations. */
14491 if (htab->root.is_relocatable_executable
14492 && ! htab->root.dynamic_sections_created)
14493 {
14494 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14495 return FALSE;
14496 }
14497
cbc704f3
RS		 14498 if (htab->root.dynobj == NULL)
14499 htab->root.dynobj = abfd;
34e77a92
RS		 14500 if (!create_ifunc_sections (info))
14501 return FALSE;
cbc704f3
RS		 14502
14503 dynobj = htab->root.dynobj;
14504
0ffa91dd 14505 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14506 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14507 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14508
252b5132
RH		 14509 rel_end = relocs + sec->reloc_count;
14510 for (rel = relocs; rel < rel_end; rel++)
14511 {
34e77a92 14512 Elf_Internal_Sym *isym;
252b5132 14513 struct elf_link_hash_entry *h;
b7693d02 14514 struct elf32_arm_link_hash_entry *eh;
252b5132 14515 unsigned long r_symndx;
eb043451 14516 int r_type;
9a5aca8c 14517
252b5132 14518 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14519 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14520 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14521
ce98a316
NC		 14522 if (r_symndx >= nsyms
14523 /* PR 9934: It is possible to have relocations that do not
14524 refer to symbols, thus it is also possible to have an
14525 object file containing relocations but no symbol table. */
cf35638d 14526 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14527 {
4eca0228
AM		 14528 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14529 r_symndx);
ba93b8ac
DJ		 14530 return FALSE;
14531 }
14532
34e77a92
RS		 14533 h = NULL;
14534 isym = NULL;
14535 if (nsyms > 0)
973a3492 14536 {
34e77a92
RS		 14537 if (r_symndx < symtab_hdr->sh_info)
14538 {
14539 /* A local symbol. */
14540 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14541 abfd, r_symndx);
14542 if (isym == NULL)
14543 return FALSE;
14544 }
14545 else
14546 {
14547 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14548 while (h->root.type == bfd_link_hash_indirect
14549 || h->root.type == bfd_link_hash_warning)
14550 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14551
14552 /* PR15323, ref flags aren't set for references in the
14553 same object. */
14554 h->root.non_ir_ref = 1;
34e77a92 14555 }
973a3492 14556 }
9a5aca8c 14557
b7693d02
DJ		 14558 eh = (struct elf32_arm_link_hash_entry *) h;
14559
f6e32f6d
RS		 14560 call_reloc_p = FALSE;
14561 may_become_dynamic_p = FALSE;
14562 may_need_local_target_p = FALSE;
14563
0855e32b
NS		 14564 /* Could be done earlier, if h were already available. */
14565 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14566 switch (r_type)
99059e56 14567 {
5e681ec4 14568 case R_ARM_GOT32:
eb043451 14569 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14570 case R_ARM_TLS_GD32:
14571 case R_ARM_TLS_IE32:
0855e32b
NS		 14572 case R_ARM_TLS_GOTDESC:
14573 case R_ARM_TLS_DESCSEQ:
14574 case R_ARM_THM_TLS_DESCSEQ:
14575 case R_ARM_TLS_CALL:
14576 case R_ARM_THM_TLS_CALL:
5e681ec4 14577 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14578 {
14579 int tls_type, old_tls_type;
5e681ec4 14580
ba93b8ac
DJ		 14581 switch (r_type)
14582 {
14583 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14584
ba93b8ac 14585 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14586
0855e32b
NS		 14587 case R_ARM_TLS_GOTDESC:
14588 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14589 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14590 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14591
ba93b8ac
DJ		 14592 default: tls_type = GOT_NORMAL; break;
14593 }
252b5132 14594
0e1862bb 14595 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14596 info->flags |= DF_STATIC_TLS;
14597
ba93b8ac
DJ		 14598 if (h != NULL)
14599 {
14600 h->got.refcount++;
14601 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14602 }
14603 else
14604 {
ba93b8ac 14605 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14606 if (!elf32_arm_allocate_local_sym_info (abfd))
14607 return FALSE;
14608 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14609 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14610 }
14611
0855e32b 14612 /* If a variable is accessed with both tls methods, two
99059e56 14613 slots may be created. */
0855e32b
NS		 14614 if (GOT_TLS_GD_ANY_P (old_tls_type)
14615 && GOT_TLS_GD_ANY_P (tls_type))
14616 tls_type |= old_tls_type;
14617
14618 /* We will already have issued an error message if there
14619 is a TLS/non-TLS mismatch, based on the symbol
14620 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14621 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14622 && tls_type != GOT_NORMAL)
14623 tls_type |= old_tls_type;
14624
0855e32b 14625 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14626 method, we're able to relax. Turn off the GDESC flag,
14627 without messing up with any other kind of tls types
6a631e86 14628 that may be involved. */
0855e32b
NS		 14629 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14630 tls_type &= ~GOT_TLS_GDESC;
14631
ba93b8ac
DJ		 14632 if (old_tls_type != tls_type)
14633 {
14634 if (h != NULL)
14635 elf32_arm_hash_entry (h)->tls_type = tls_type;
14636 else
14637 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14638 }
14639 }
8029a119 14640 /* Fall through. */
ba93b8ac
DJ		 14641
14642 case R_ARM_TLS_LDM32:
14643 if (r_type == R_ARM_TLS_LDM32)
14644 htab->tls_ldm_got.refcount++;
8029a119 14645 /* Fall through. */
252b5132 14646
c19d1205 14647 case R_ARM_GOTOFF32:
5e681ec4 14648 case R_ARM_GOTPC:
cbc704f3
RS		 14649 if (htab->root.sgot == NULL
14650 && !create_got_section (htab->root.dynobj, info))
14651 return FALSE;
252b5132
RH		 14652 break;
14653
252b5132 14654 case R_ARM_PC24:
7359ea65 14655 case R_ARM_PLT32:
5b5bb741
PB		 14656 case R_ARM_CALL:
14657 case R_ARM_JUMP24:
eb043451 14658 case R_ARM_PREL31:
c19d1205 14659 case R_ARM_THM_CALL:
bd97cb95
DJ		 14660 case R_ARM_THM_JUMP24:
14661 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14662 call_reloc_p = TRUE;
14663 may_need_local_target_p = TRUE;
14664 break;
14665
14666 case R_ARM_ABS12:
14667 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14668 ldr __GOTT_INDEX__ offsets. */
14669 if (!htab->vxworks_p)
14670 {
14671 may_need_local_target_p = TRUE;
14672 break;
14673 }
aebf9be7 14674 else goto jump_over;
9eaff861 14675
f6e32f6d 14676 /* Fall through. */
39623e12 14677
96c23d59
JM		 14678 case R_ARM_MOVW_ABS_NC:
14679 case R_ARM_MOVT_ABS:
14680 case R_ARM_THM_MOVW_ABS_NC:
14681 case R_ARM_THM_MOVT_ABS:
0e1862bb 14682 if (bfd_link_pic (info))
96c23d59 14683 {
4eca0228 14684 _bfd_error_handler
96c23d59
JM		 14685 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14686 abfd, elf32_arm_howto_table_1[r_type].name,
14687 (h) ? h->root.root.string : "a local symbol");
14688 bfd_set_error (bfd_error_bad_value);
14689 return FALSE;
14690 }
14691
14692 /* Fall through. */
39623e12
PB		 14693 case R_ARM_ABS32:
14694 case R_ARM_ABS32_NOI:
aebf9be7 14695 jump_over:
0e1862bb 14696 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14697 {
14698 h->pointer_equality_needed = 1;
14699 }
14700 /* Fall through. */
39623e12
PB		 14701 case R_ARM_REL32:
14702 case R_ARM_REL32_NOI:
b6895b4f
PB		 14703 case R_ARM_MOVW_PREL_NC:
14704 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14705 case R_ARM_THM_MOVW_PREL_NC:
14706 case R_ARM_THM_MOVT_PREL:
39623e12 14707
b7693d02 14708 /* Should the interworking branches be listed here? */
0e1862bb 14709 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14710 && (sec->flags & SEC_ALLOC) != 0)
14711 {
14712 if (h == NULL
469a3493 14713 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14714 {
14715 /* In shared libraries and relocatable executables,
14716 we treat local relative references as calls;
14717 see the related SYMBOL_CALLS_LOCAL code in
14718 allocate_dynrelocs. */
14719 call_reloc_p = TRUE;
14720 may_need_local_target_p = TRUE;
14721 }
14722 else
14723 /* We are creating a shared library or relocatable
14724 executable, and this is a reloc against a global symbol,
14725 or a non-PC-relative reloc against a local symbol.
14726 We may need to copy the reloc into the output. */
14727 may_become_dynamic_p = TRUE;
14728 }
f6e32f6d
RS		 14729 else
14730 may_need_local_target_p = TRUE;
252b5132
RH		 14731 break;
14732
99059e56
RM		 14733 /* This relocation describes the C++ object vtable hierarchy.
14734 Reconstruct it for later use during GC. */
14735 case R_ARM_GNU_VTINHERIT:
14736 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14737 return FALSE;
14738 break;
14739
14740 /* This relocation describes which C++ vtable entries are actually
14741 used. Record for later use during GC. */
14742 case R_ARM_GNU_VTENTRY:
14743 BFD_ASSERT (h != NULL);
14744 if (h != NULL
14745 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14746 return FALSE;
14747 break;
14748 }
f6e32f6d
RS		 14749
14750 if (h != NULL)
14751 {
14752 if (call_reloc_p)
14753 /* We may need a .plt entry if the function this reloc
14754 refers to is in a different object, regardless of the
14755 symbol's type. We can't tell for sure yet, because
14756 something later might force the symbol local. */
14757 h->needs_plt = 1;
14758 else if (may_need_local_target_p)
14759 /* If this reloc is in a read-only section, we might
14760 need a copy reloc. We can't check reliably at this
14761 stage whether the section is read-only, as input
14762 sections have not yet been mapped to output sections.
14763 Tentatively set the flag for now, and correct in
14764 adjust_dynamic_symbol. */
14765 h->non_got_ref = 1;
14766 }
14767
34e77a92
RS		 14768 if (may_need_local_target_p
14769 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14770 {
34e77a92
RS		 14771 union gotplt_union *root_plt;
14772 struct arm_plt_info *arm_plt;
14773 struct arm_local_iplt_info *local_iplt;
14774
14775 if (h != NULL)
14776 {
14777 root_plt = &h->plt;
14778 arm_plt = &eh->plt;
14779 }
14780 else
14781 {
14782 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14783 if (local_iplt == NULL)
14784 return FALSE;
14785 root_plt = &local_iplt->root;
14786 arm_plt = &local_iplt->arm;
14787 }
14788
f6e32f6d
RS		 14789 /* If the symbol is a function that doesn't bind locally,
14790 this relocation will need a PLT entry. */
a8c887dd
NC		 14791 if (root_plt->refcount != -1)
14792 root_plt->refcount += 1;
34e77a92
RS		 14793
14794 if (!call_reloc_p)
14795 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14796
14797 /* It's too early to use htab->use_blx here, so we have to
14798 record possible blx references separately from
14799 relocs that definitely need a thumb stub. */
14800
14801 if (r_type == R_ARM_THM_CALL)
34e77a92 14802 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14803
14804 if (r_type == R_ARM_THM_JUMP24
14805 || r_type == R_ARM_THM_JUMP19)
34e77a92 14806 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14807 }
14808
14809 if (may_become_dynamic_p)
14810 {
14811 struct elf_dyn_relocs *p, **head;
14812
14813 /* Create a reloc section in dynobj. */
14814 if (sreloc == NULL)
14815 {
14816 sreloc = _bfd_elf_make_dynamic_reloc_section
14817 (sec, dynobj, 2, abfd, ! htab->use_rel);
14818
14819 if (sreloc == NULL)
14820 return FALSE;
14821
14822 /* BPABI objects never have dynamic relocations mapped. */
14823 if (htab->symbian_p)
14824 {
14825 flagword flags;
14826
14827 flags = bfd_get_section_flags (dynobj, sreloc);
14828 flags &= ~(SEC_LOAD | SEC_ALLOC);
14829 bfd_set_section_flags (dynobj, sreloc, flags);
14830 }
14831 }
14832
14833 /* If this is a global symbol, count the number of
14834 relocations we need for this symbol. */
14835 if (h != NULL)
14836 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14837 else
14838 {
34e77a92
RS		 14839 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14840 if (head == NULL)
f6e32f6d 14841 return FALSE;
f6e32f6d
RS		 14842 }
14843
14844 p = *head;
14845 if (p == NULL || p->sec != sec)
14846 {
14847 bfd_size_type amt = sizeof *p;
14848
14849 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14850 if (p == NULL)
14851 return FALSE;
14852 p->next = *head;
14853 *head = p;
14854 p->sec = sec;
14855 p->count = 0;
14856 p->pc_count = 0;
14857 }
14858
469a3493 14859 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14860 p->pc_count += 1;
14861 p->count += 1;
14862 }
252b5132 14863 }
f21f3fe0 14864
b34976b6 14865 return TRUE;
252b5132
RH		 14866}
14867
9eaff861
AO		 14868static void
14869elf32_arm_update_relocs (asection *o,
14870 struct bfd_elf_section_reloc_data *reldata)
14871{
14872 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14873 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14874 const struct elf_backend_data *bed;
14875 _arm_elf_section_data *eado;
14876 struct bfd_link_order *p;
14877 bfd_byte *erela_head, *erela;
14878 Elf_Internal_Rela *irela_head, *irela;
14879 Elf_Internal_Shdr *rel_hdr;
14880 bfd *abfd;
14881 unsigned int count;
14882
14883 eado = get_arm_elf_section_data (o);
14884
14885 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14886 return;
14887
14888 abfd = o->owner;
14889 bed = get_elf_backend_data (abfd);
14890 rel_hdr = reldata->hdr;
14891
14892 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14893 {
14894 swap_in = bed->s->swap_reloc_in;
14895 swap_out = bed->s->swap_reloc_out;
14896 }
14897 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14898 {
14899 swap_in = bed->s->swap_reloca_in;
14900 swap_out = bed->s->swap_reloca_out;
14901 }
14902 else
14903 abort ();
14904
14905 erela_head = rel_hdr->contents;
14906 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14907 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14908
14909 erela = erela_head;
14910 irela = irela_head;
14911 count = 0;
14912
14913 for (p = o->map_head.link_order; p; p = p->next)
14914 {
14915 if (p->type == bfd_section_reloc_link_order
14916 || p->type == bfd_symbol_reloc_link_order)
14917 {
14918 (*swap_in) (abfd, erela, irela);
14919 erela += rel_hdr->sh_entsize;
14920 irela++;
14921 count++;
14922 }
14923 else if (p->type == bfd_indirect_link_order)
14924 {
14925 struct bfd_elf_section_reloc_data *input_reldata;
14926 arm_unwind_table_edit *edit_list, *edit_tail;
14927 _arm_elf_section_data *eadi;
14928 bfd_size_type j;
14929 bfd_vma offset;
14930 asection *i;
14931
14932 i = p->u.indirect.section;
14933
14934 eadi = get_arm_elf_section_data (i);
14935 edit_list = eadi->u.exidx.unwind_edit_list;
14936 edit_tail = eadi->u.exidx.unwind_edit_tail;
14937 offset = o->vma + i->output_offset;
14938
14939 if (eadi->elf.rel.hdr &&
14940 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14941 input_reldata = &eadi->elf.rel;
14942 else if (eadi->elf.rela.hdr &&
14943 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14944 input_reldata = &eadi->elf.rela;
14945 else
14946 abort ();
14947
14948 if (edit_list)
14949 {
14950 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14951 {
14952 arm_unwind_table_edit *edit_node, *edit_next;
14953 bfd_vma bias;
c48182bf 14954 bfd_vma reloc_index;
9eaff861
AO		 14955
14956 (*swap_in) (abfd, erela, irela);
c48182bf 14957 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14958
14959 bias = 0;
14960 edit_node = edit_list;
14961 for (edit_next = edit_list;
c48182bf 14962 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14963 edit_next = edit_node->next)
14964 {
14965 bias++;
14966 edit_node = edit_next;
14967 }
14968
14969 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14970 || edit_node->index != reloc_index)
9eaff861
AO		 14971 {
14972 irela->r_offset -= bias * 8;
14973 irela++;
14974 count++;
14975 }
14976
14977 erela += rel_hdr->sh_entsize;
14978 }
14979
14980 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14981 {
14982 /* New relocation entity. */
14983 asection *text_sec = edit_tail->linked_section;
14984 asection *text_out = text_sec->output_section;
14985 bfd_vma exidx_offset = offset + i->size - 8;
14986
14987 irela->r_addend = 0;
14988 irela->r_offset = exidx_offset;
14989 irela->r_info = ELF32_R_INFO
14990 (text_out->target_index, R_ARM_PREL31);
14991 irela++;
14992 count++;
14993 }
14994 }
14995 else
14996 {
14997 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14998 {
14999 (*swap_in) (abfd, erela, irela);
15000 erela += rel_hdr->sh_entsize;
15001 irela++;
15002 }
15003
15004 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15005 }
15006 }
15007 }
15008
15009 reldata->count = count;
15010 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15011
15012 erela = erela_head;
15013 irela = irela_head;
15014 while (count > 0)
15015 {
15016 (*swap_out) (abfd, irela, erela);
15017 erela += rel_hdr->sh_entsize;
15018 irela++;
15019 count--;
15020 }
15021
15022 free (irela_head);
15023
15024 /* Hashes are no longer valid. */
15025 free (reldata->hashes);
15026 reldata->hashes = NULL;
15027}
15028
6a5bb875 15029/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15030 required if the corresponding code section is marked. Similarly, ARMv8-M
15031 secure entry functions can only be referenced by SG veneers which are
15032 created after the GC process. They need to be marked in case they reside in
15033 their own section (as would be the case if code was compiled with
15034 -ffunction-sections). */
6a5bb875
PB		 15035
15036static bfd_boolean
906e58ca
NC		 15037elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15038 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15039{
15040 bfd *sub;
15041 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15042 asection *cmse_sec;
15043 obj_attribute *out_attr;
15044 Elf_Internal_Shdr *symtab_hdr;
15045 unsigned i, sym_count, ext_start;
15046 const struct elf_backend_data *bed;
15047 struct elf_link_hash_entry **sym_hashes;
15048 struct elf32_arm_link_hash_entry *cmse_hash;
15049 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15050
7f6ab9f8
AM		 15051 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15052
4ba2ef8f
TP		 15053 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15054 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15055 && out_attr[Tag_CPU_arch_profile].i == 'M';
15056
6a5bb875
PB		 15057 /* Marking EH data may cause additional code sections to be marked,
15058 requiring multiple passes. */
15059 again = TRUE;
15060 while (again)
15061 {
15062 again = FALSE;
c72f2fb2 15063 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15064 {
15065 asection *o;
15066
0ffa91dd 15067 if (! is_arm_elf (sub))
6a5bb875
PB		 15068 continue;
15069
15070 elf_shdrp = elf_elfsections (sub);
15071 for (o = sub->sections; o != NULL; o = o->next)
15072 {
15073 Elf_Internal_Shdr *hdr;
0ffa91dd 15074
6a5bb875 15075 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15076 if (hdr->sh_type == SHT_ARM_EXIDX
15077 && hdr->sh_link
15078 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15079 && !o->gc_mark
15080 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15081 {
15082 again = TRUE;
15083 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15084 return FALSE;
15085 }
15086 }
4ba2ef8f
TP		 15087
15088 /* Mark section holding ARMv8-M secure entry functions. We mark all
15089 of them so no need for a second browsing. */
15090 if (is_v8m && first_bfd_browse)
15091 {
15092 sym_hashes = elf_sym_hashes (sub);
15093 bed = get_elf_backend_data (sub);
15094 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15095 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15096 ext_start = symtab_hdr->sh_info;
15097
15098 /* Scan symbols. */
15099 for (i = ext_start; i < sym_count; i++)
15100 {
15101 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15102
15103 /* Assume it is a special symbol. If not, cmse_scan will
15104 warn about it and user can do something about it. */
15105 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15106 {
15107 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15108 if (!cmse_sec->gc_mark
15109 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15110 return FALSE;
15111 }
15112 }
15113 }
6a5bb875 15114 }
4ba2ef8f 15115 first_bfd_browse = FALSE;
6a5bb875
PB		 15116 }
15117
15118 return TRUE;
15119}
15120
3c9458e9
NC		 15121/* Treat mapping symbols as special target symbols. */
15122
15123static bfd_boolean
15124elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15125{
b0796911
PB		 15126 return bfd_is_arm_special_symbol_name (sym->name,
15127 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15128}
15129
0367ecfb
NC		 15130/* This is a copy of elf_find_function() from elf.c except that
15131 ARM mapping symbols are ignored when looking for function names
15132 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15133
0367ecfb
NC		 15134static bfd_boolean
15135arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15136 asymbol ** symbols,
fb167eb2 15137 asection * section,
0367ecfb
NC		 15138 bfd_vma offset,
15139 const char ** filename_ptr,
15140 const char ** functionname_ptr)
15141{
15142 const char * filename = NULL;
15143 asymbol * func = NULL;
15144 bfd_vma low_func = 0;
15145 asymbol ** p;
252b5132
RH		 15146
15147 for (p = symbols; *p != NULL; p++)
15148 {
15149 elf_symbol_type *q;
15150
15151 q = (elf_symbol_type *) *p;
15152
252b5132
RH		 15153 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15154 {
15155 default:
15156 break;
15157 case STT_FILE:
15158 filename = bfd_asymbol_name (&q->symbol);
15159 break;
252b5132
RH		 15160 case STT_FUNC:
15161 case STT_ARM_TFUNC:
9d2da7ca 15162 case STT_NOTYPE:
b0796911 15163 /* Skip mapping symbols. */
0367ecfb 15164 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15165 && bfd_is_arm_special_symbol_name (q->symbol.name,
15166 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15167 continue;
15168 /* Fall through. */
6b40fcba 15169 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15170 && q->symbol.value >= low_func
15171 && q->symbol.value <= offset)
15172 {
15173 func = (asymbol *) q;
15174 low_func = q->symbol.value;
15175 }
15176 break;
15177 }
15178 }
15179
15180 if (func == NULL)
b34976b6 15181 return FALSE;
252b5132 15182
0367ecfb
NC		 15183 if (filename_ptr)
15184 *filename_ptr = filename;
15185 if (functionname_ptr)
15186 *functionname_ptr = bfd_asymbol_name (func);
15187
15188 return TRUE;
906e58ca 15189}
0367ecfb
NC		 15190
15191
15192/* Find the nearest line to a particular section and offset, for error
15193 reporting. This code is a duplicate of the code in elf.c, except
15194 that it uses arm_elf_find_function. */
15195
15196static bfd_boolean
15197elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15198 asymbol ** symbols,
fb167eb2 15199 asection * section,
0367ecfb
NC		 15200 bfd_vma offset,
15201 const char ** filename_ptr,
15202 const char ** functionname_ptr,
fb167eb2
AM		 15203 unsigned int * line_ptr,
15204 unsigned int * discriminator_ptr)
0367ecfb
NC		 15205{
15206 bfd_boolean found = FALSE;
15207
fb167eb2 15208 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15209 filename_ptr, functionname_ptr,
fb167eb2
AM		 15210 line_ptr, discriminator_ptr,
15211 dwarf_debug_sections, 0,
0367ecfb
NC		 15212 & elf_tdata (abfd)->dwarf2_find_line_info))
15213 {
15214 if (!*functionname_ptr)
fb167eb2 15215 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15216 *filename_ptr ? NULL : filename_ptr,
15217 functionname_ptr);
f21f3fe0 15218
0367ecfb
NC		 15219 return TRUE;
15220 }
15221
fb167eb2
AM		 15222 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15223 uses DWARF1. */
15224
0367ecfb
NC		 15225 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15226 & found, filename_ptr,
15227 functionname_ptr, line_ptr,
15228 & elf_tdata (abfd)->line_info))
15229 return FALSE;
15230
15231 if (found && (*functionname_ptr || *line_ptr))
15232 return TRUE;
15233
15234 if (symbols == NULL)
15235 return FALSE;
15236
fb167eb2 15237 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15238 filename_ptr, functionname_ptr))
15239 return FALSE;
15240
15241 *line_ptr = 0;
b34976b6 15242 return TRUE;
252b5132
RH		 15243}
15244
4ab527b0
FF		 15245static bfd_boolean
15246elf32_arm_find_inliner_info (bfd * abfd,
15247 const char ** filename_ptr,
15248 const char ** functionname_ptr,
15249 unsigned int * line_ptr)
15250{
15251 bfd_boolean found;
15252 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15253 functionname_ptr, line_ptr,
15254 & elf_tdata (abfd)->dwarf2_find_line_info);
15255 return found;
15256}
15257
252b5132
RH		 15258/* Adjust a symbol defined by a dynamic object and referenced by a
15259 regular object. The current definition is in some section of the
15260 dynamic object, but we're not including those sections. We have to
15261 change the definition to something the rest of the link can
15262 understand. */
15263
b34976b6 15264static bfd_boolean
57e8b36a
NC		 15265elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15266 struct elf_link_hash_entry * h)
252b5132
RH		 15267{
15268 bfd * dynobj;
5474d94f 15269 asection *s, *srel;
b7693d02 15270 struct elf32_arm_link_hash_entry * eh;
67687978 15271 struct elf32_arm_link_hash_table *globals;
252b5132 15272
67687978 15273 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15274 if (globals == NULL)
15275 return FALSE;
15276
252b5132
RH		 15277 dynobj = elf_hash_table (info)->dynobj;
15278
15279 /* Make sure we know what is going on here. */
15280 BFD_ASSERT (dynobj != NULL
f5385ebf 15281 && (h->needs_plt
34e77a92 15282 || h->type == STT_GNU_IFUNC
f6e332e6 15283 || h->u.weakdef != NULL
f5385ebf
AM		 15284 || (h->def_dynamic
15285 && h->ref_regular
15286 && !h->def_regular)));
252b5132 15287
b7693d02
DJ		 15288 eh = (struct elf32_arm_link_hash_entry *) h;
15289
252b5132
RH		 15290 /* If this is a function, put it in the procedure linkage table. We
15291 will fill in the contents of the procedure linkage table later,
15292 when we know the address of the .got section. */
34e77a92 15293 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15294 {
34e77a92
RS		 15295 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15296 symbol binds locally. */
5e681ec4 15297 if (h->plt.refcount <= 0
34e77a92
RS		 15298 || (h->type != STT_GNU_IFUNC
15299 && (SYMBOL_CALLS_LOCAL (info, h)
15300 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15301 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15302 {
15303 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15304 file, but the symbol was never referred to by a dynamic
15305 object, or if all references were garbage collected. In
15306 such a case, we don't actually need to build a procedure
15307 linkage table, and we can just do a PC24 reloc instead. */
15308 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15309 eh->plt.thumb_refcount = 0;
15310 eh->plt.maybe_thumb_refcount = 0;
15311 eh->plt.noncall_refcount = 0;
f5385ebf 15312 h->needs_plt = 0;
252b5132
RH		 15313 }
15314
b34976b6 15315 return TRUE;
252b5132 15316 }
5e681ec4 15317 else
b7693d02
DJ		 15318 {
15319 /* It's possible that we incorrectly decided a .plt reloc was
15320 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15321 in check_relocs. We can't decide accurately between function
15322 and non-function syms in check-relocs; Objects loaded later in
15323 the link may change h->type. So fix it now. */
15324 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15325 eh->plt.thumb_refcount = 0;
15326 eh->plt.maybe_thumb_refcount = 0;
15327 eh->plt.noncall_refcount = 0;
b7693d02 15328 }
252b5132
RH		 15329
15330 /* If this is a weak symbol, and there is a real definition, the
15331 processor independent code will have arranged for us to see the
15332 real definition first, and we can just use the same value. */
f6e332e6 15333 if (h->u.weakdef != NULL)
252b5132 15334 {
f6e332e6
AM		 15335 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15336 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15337 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15338 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15339 return TRUE;
252b5132
RH		 15340 }
15341
ba93b8ac
DJ		 15342 /* If there are no non-GOT references, we do not need a copy
15343 relocation. */
15344 if (!h->non_got_ref)
15345 return TRUE;
15346
252b5132
RH		 15347 /* This is a reference to a symbol defined by a dynamic object which
15348 is not a function. */
15349
15350 /* If we are creating a shared library, we must presume that the
15351 only references to the symbol are via the global offset table.
15352 For such cases we need not do anything here; the relocations will
67687978
PB		 15353 be handled correctly by relocate_section. Relocatable executables
15354 can reference data in shared objects directly, so we don't need to
15355 do anything here. */
0e1862bb 15356 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15357 return TRUE;
252b5132
RH		 15358
15359 /* We must allocate the symbol in our .dynbss section, which will
15360 become part of the .bss section of the executable. There will be
15361 an entry for this symbol in the .dynsym section. The dynamic
15362 object will contain position independent code, so all references
15363 from the dynamic object to this symbol will go through the global
15364 offset table. The dynamic linker will use the .dynsym entry to
15365 determine the address it must put in the global offset table, so
15366 both the dynamic object and the regular object will refer to the
15367 same memory location for the variable. */
5522f910
NC		 15368 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15369 linker to copy the initial value out of the dynamic object and into
15370 the runtime process image. We need to remember the offset into the
00a97672 15371 .rel(a).bss section we are going to use. */
5474d94f
AM		 15372 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15373 {
15374 s = globals->root.sdynrelro;
15375 srel = globals->root.sreldynrelro;
15376 }
15377 else
15378 {
15379 s = globals->root.sdynbss;
15380 srel = globals->root.srelbss;
15381 }
5522f910
NC		 15382 if (info->nocopyreloc == 0
15383 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15384 && h->size != 0)
252b5132 15385 {
47beaa6a 15386 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15387 h->needs_copy = 1;
252b5132
RH		 15388 }
15389
6cabe1ea 15390 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15391}
15392
5e681ec4
PB		 15393/* Allocate space in .plt, .got and associated reloc sections for
15394 dynamic relocs. */
15395
15396static bfd_boolean
47beaa6a 15397allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15398{
15399 struct bfd_link_info *info;
15400 struct elf32_arm_link_hash_table *htab;
15401 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15402 struct elf_dyn_relocs *p;
5e681ec4
PB		 15403
15404 if (h->root.type == bfd_link_hash_indirect)
15405 return TRUE;
15406
e6a6bb22
AM		 15407 eh = (struct elf32_arm_link_hash_entry *) h;
15408
5e681ec4
PB		 15409 info = (struct bfd_link_info *) inf;
15410 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15411 if (htab == NULL)
15412 return FALSE;
5e681ec4 15413
34e77a92 15414 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15415 && h->plt.refcount > 0)
15416 {
15417 /* Make sure this symbol is output as a dynamic symbol.
15418 Undefined weak syms won't yet be marked as dynamic. */
15419 if (h->dynindx == -1
f5385ebf 15420 && !h->forced_local)
5e681ec4 15421 {
c152c796 15422 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15423 return FALSE;
15424 }
15425
34e77a92
RS		 15426 /* If the call in the PLT entry binds locally, the associated
15427 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15428 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15429 than the .plt section. */
15430 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15431 {
15432 eh->is_iplt = 1;
15433 if (eh->plt.noncall_refcount == 0
15434 && SYMBOL_REFERENCES_LOCAL (info, h))
15435 /* All non-call references can be resolved directly.
15436 This means that they can (and in some cases, must)
15437 resolve directly to the run-time target, rather than
15438 to the PLT. That in turns means that any .got entry
15439 would be equal to the .igot.plt entry, so there's
15440 no point having both. */
15441 h->got.refcount = 0;
15442 }
15443
0e1862bb 15444 if (bfd_link_pic (info)
34e77a92 15445 || eh->is_iplt
7359ea65 15446 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15447 {
34e77a92 15448 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15449
5e681ec4
PB		 15450 /* If this symbol is not defined in a regular file, and we are
15451 not generating a shared library, then set the symbol to this
15452 location in the .plt. This is required to make function
15453 pointers compare as equal between the normal executable and
15454 the shared library. */
0e1862bb 15455 if (! bfd_link_pic (info)
f5385ebf 15456 && !h->def_regular)
5e681ec4 15457 {
34e77a92 15458 h->root.u.def.section = htab->root.splt;
5e681ec4 15459 h->root.u.def.value = h->plt.offset;
5e681ec4 15460
67d74e43
DJ		 15461 /* Make sure the function is not marked as Thumb, in case
15462 it is the target of an ABS32 relocation, which will
15463 point to the PLT entry. */
39d911fc 15464 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15465 }
022f8312 15466
00a97672
RS		 15467 /* VxWorks executables have a second set of relocations for
15468 each PLT entry. They go in a separate relocation section,
15469 which is processed by the kernel loader. */
0e1862bb 15470 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15471 {
15472 /* There is a relocation for the initial PLT entry:
15473 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15474 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15475 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15476
15477 /* There are two extra relocations for each subsequent
15478 PLT entry: an R_ARM_32 relocation for the GOT entry,
15479 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15480 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15481 }
5e681ec4
PB		 15482 }
15483 else
15484 {
15485 h->plt.offset = (bfd_vma) -1;
f5385ebf 15486 h->needs_plt = 0;
5e681ec4
PB		 15487 }
15488 }
15489 else
15490 {
15491 h->plt.offset = (bfd_vma) -1;
f5385ebf 15492 h->needs_plt = 0;
5e681ec4
PB		 15493 }
15494
0855e32b
NS		 15495 eh = (struct elf32_arm_link_hash_entry *) h;
15496 eh->tlsdesc_got = (bfd_vma) -1;
15497
5e681ec4
PB		 15498 if (h->got.refcount > 0)
15499 {
15500 asection *s;
15501 bfd_boolean dyn;
ba93b8ac
DJ		 15502 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15503 int indx;
5e681ec4
PB		 15504
15505 /* Make sure this symbol is output as a dynamic symbol.
15506 Undefined weak syms won't yet be marked as dynamic. */
15507 if (h->dynindx == -1
f5385ebf 15508 && !h->forced_local)
5e681ec4 15509 {
c152c796 15510 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15511 return FALSE;
15512 }
15513
e5a52504
MM		 15514 if (!htab->symbian_p)
15515 {
362d30a1 15516 s = htab->root.sgot;
e5a52504 15517 h->got.offset = s->size;
ba93b8ac
DJ		 15518
15519 if (tls_type == GOT_UNKNOWN)
15520 abort ();
15521
15522 if (tls_type == GOT_NORMAL)
15523 /* Non-TLS symbols need one GOT slot. */
15524 s->size += 4;
15525 else
15526 {
99059e56
RM		 15527 if (tls_type & GOT_TLS_GDESC)
15528 {
0855e32b 15529 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15530 eh->tlsdesc_got
0855e32b
NS		 15531 = (htab->root.sgotplt->size
15532 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15533 htab->root.sgotplt->size += 8;
15534 h->got.offset = (bfd_vma) -2;
34e77a92 15535 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15536 reloc in the middle of .got.plt. */
99059e56
RM		 15537 htab->num_tls_desc++;
15538 }
0855e32b 15539
ba93b8ac 15540 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15541 {
15542 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15543 the symbol is both GD and GDESC, got.offset may
15544 have been overwritten. */
15545 h->got.offset = s->size;
15546 s->size += 8;
15547 }
15548
ba93b8ac
DJ		 15549 if (tls_type & GOT_TLS_IE)
15550 /* R_ARM_TLS_IE32 needs one GOT slot. */
15551 s->size += 4;
15552 }
15553
e5a52504 15554 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15555
15556 indx = 0;
0e1862bb
L		 15557 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15558 bfd_link_pic (info),
15559 h)
15560 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15561 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15562 indx = h->dynindx;
15563
15564 if (tls_type != GOT_NORMAL
0e1862bb 15565 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15566 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15567 || h->root.type != bfd_link_hash_undefweak))
15568 {
15569 if (tls_type & GOT_TLS_IE)
47beaa6a 15570 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15571
15572 if (tls_type & GOT_TLS_GD)
47beaa6a 15573 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15574
b38cadfb 15575 if (tls_type & GOT_TLS_GDESC)
0855e32b 15576 {
47beaa6a 15577 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15578 /* GDESC needs a trampoline to jump to. */
15579 htab->tls_trampoline = -1;
15580 }
15581
15582 /* Only GD needs it. GDESC just emits one relocation per
15583 2 entries. */
b38cadfb 15584 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15585 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15586 }
6f820c85 15587 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15588 {
15589 if (htab->root.dynamic_sections_created)
15590 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15591 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15592 }
34e77a92
RS		 15593 else if (h->type == STT_GNU_IFUNC
15594 && eh->plt.noncall_refcount == 0)
15595 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15596 they all resolve dynamically instead. Reserve room for the
15597 GOT entry's R_ARM_IRELATIVE relocation. */
15598 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15599 else if (bfd_link_pic (info)
15600 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15601 || h->root.type != bfd_link_hash_undefweak))
b436d854 15602 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15603 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15604 }
5e681ec4
PB		 15605 }
15606 else
15607 h->got.offset = (bfd_vma) -1;
15608
a4fd1a8e
PB		 15609 /* Allocate stubs for exported Thumb functions on v4t. */
15610 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15611 && h->def_regular
39d911fc 15612 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15613 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15614 {
15615 struct elf_link_hash_entry * th;
15616 struct bfd_link_hash_entry * bh;
15617 struct elf_link_hash_entry * myh;
15618 char name[1024];
15619 asection *s;
15620 bh = NULL;
15621 /* Create a new symbol to regist the real location of the function. */
15622 s = h->root.u.def.section;
906e58ca 15623 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15624 _bfd_generic_link_add_one_symbol (info, s->owner,
15625 name, BSF_GLOBAL, s,
15626 h->root.u.def.value,
15627 NULL, TRUE, FALSE, &bh);
15628
15629 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15630 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15631 myh->forced_local = 1;
39d911fc 15632 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15633 eh->export_glue = myh;
15634 th = record_arm_to_thumb_glue (info, h);
15635 /* Point the symbol at the stub. */
15636 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15637 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15638 h->root.u.def.section = th->root.u.def.section;
15639 h->root.u.def.value = th->root.u.def.value & ~1;
15640 }
15641
0bdcacaf 15642 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15643 return TRUE;
15644
15645 /* In the shared -Bsymbolic case, discard space allocated for
15646 dynamic pc-relative relocs against symbols which turn out to be
15647 defined in regular objects. For the normal shared case, discard
15648 space for pc-relative relocs that have become local due to symbol
15649 visibility changes. */
15650
0e1862bb 15651 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15652 {
469a3493
RM		 15653 /* Relocs that use pc_count are PC-relative forms, which will appear
15654 on something like ".long foo - ." or "movw REG, foo - .". We want
15655 calls to protected symbols to resolve directly to the function
15656 rather than going via the plt. If people want function pointer
15657 comparisons to work as expected then they should avoid writing
15658 assembly like ".long foo - .". */
ba93b8ac
DJ		 15659 if (SYMBOL_CALLS_LOCAL (info, h))
15660 {
0bdcacaf 15661 struct elf_dyn_relocs **pp;
ba93b8ac 15662
0bdcacaf 15663 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15664 {
15665 p->count -= p->pc_count;
15666 p->pc_count = 0;
15667 if (p->count == 0)
15668 *pp = p->next;
15669 else
15670 pp = &p->next;
15671 }
15672 }
15673
4dfe6ac6 15674 if (htab->vxworks_p)
3348747a 15675 {
0bdcacaf 15676 struct elf_dyn_relocs **pp;
3348747a 15677
0bdcacaf 15678 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15679 {
0bdcacaf 15680 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15681 *pp = p->next;
15682 else
15683 pp = &p->next;
15684 }
15685 }
15686
ba93b8ac 15687 /* Also discard relocs on undefined weak syms with non-default
99059e56 15688 visibility. */
0bdcacaf 15689 if (eh->dyn_relocs != NULL
5e681ec4 15690 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15691 {
15692 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15693 eh->dyn_relocs = NULL;
22d606e9
AM		 15694
15695 /* Make sure undefined weak symbols are output as a dynamic
15696 symbol in PIEs. */
15697 else if (h->dynindx == -1
15698 && !h->forced_local)
15699 {
15700 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15701 return FALSE;
15702 }
15703 }
15704
67687978
PB		 15705 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15706 && h->root.type == bfd_link_hash_new)
15707 {
15708 /* Output absolute symbols so that we can create relocations
15709 against them. For normal symbols we output a relocation
15710 against the section that contains them. */
15711 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15712 return FALSE;
15713 }
15714
5e681ec4
PB		 15715 }
15716 else
15717 {
15718 /* For the non-shared case, discard space for relocs against
15719 symbols which turn out to need copy relocs or are not
15720 dynamic. */
15721
f5385ebf
AM		 15722 if (!h->non_got_ref
15723 && ((h->def_dynamic
15724 && !h->def_regular)
5e681ec4
PB		 15725 || (htab->root.dynamic_sections_created
15726 && (h->root.type == bfd_link_hash_undefweak
15727 || h->root.type == bfd_link_hash_undefined))))
15728 {
15729 /* Make sure this symbol is output as a dynamic symbol.
15730 Undefined weak syms won't yet be marked as dynamic. */
15731 if (h->dynindx == -1
f5385ebf 15732 && !h->forced_local)
5e681ec4 15733 {
c152c796 15734 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15735 return FALSE;
15736 }
15737
15738 /* If that succeeded, we know we'll be keeping all the
15739 relocs. */
15740 if (h->dynindx != -1)
15741 goto keep;
15742 }
15743
0bdcacaf 15744 eh->dyn_relocs = NULL;
5e681ec4
PB		 15745
15746 keep: ;
15747 }
15748
15749 /* Finally, allocate space. */
0bdcacaf 15750 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15751 {
0bdcacaf 15752 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15753 if (h->type == STT_GNU_IFUNC
15754 && eh->plt.noncall_refcount == 0
15755 && SYMBOL_REFERENCES_LOCAL (info, h))
15756 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15757 else
15758 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15759 }
15760
15761 return TRUE;
15762}
15763
08d1f311
DJ		 15764/* Find any dynamic relocs that apply to read-only sections. */
15765
15766static bfd_boolean
8029a119 15767elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15768{
8029a119 15769 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15770 struct elf_dyn_relocs * p;
08d1f311 15771
08d1f311 15772 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15773 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15774 {
0bdcacaf 15775 asection *s = p->sec;
08d1f311
DJ		 15776
15777 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15778 {
15779 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15780
15781 info->flags |= DF_TEXTREL;
15782
15783 /* Not an error, just cut short the traversal. */
15784 return FALSE;
15785 }
15786 }
15787 return TRUE;
15788}
15789
d504ffc8
DJ		 15790void
15791bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15792 int byteswap_code)
15793{
15794 struct elf32_arm_link_hash_table *globals;
15795
15796 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15797 if (globals == NULL)
15798 return;
15799
d504ffc8
DJ		 15800 globals->byteswap_code = byteswap_code;
15801}
15802
252b5132
RH		 15803/* Set the sizes of the dynamic sections. */
15804
b34976b6 15805static bfd_boolean
57e8b36a
NC		 15806elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15807 struct bfd_link_info * info)
252b5132
RH		 15808{
15809 bfd * dynobj;
15810 asection * s;
b34976b6
AM		 15811 bfd_boolean plt;
15812 bfd_boolean relocs;
5e681ec4
PB		 15813 bfd *ibfd;
15814 struct elf32_arm_link_hash_table *htab;
252b5132 15815
5e681ec4 15816 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15817 if (htab == NULL)
15818 return FALSE;
15819
252b5132
RH		 15820 dynobj = elf_hash_table (info)->dynobj;
15821 BFD_ASSERT (dynobj != NULL);
39b41c9c 15822 check_use_blx (htab);
252b5132
RH		 15823
15824 if (elf_hash_table (info)->dynamic_sections_created)
15825 {
15826 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15827 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15828 {
3d4d4302 15829 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15830 BFD_ASSERT (s != NULL);
eea6121a 15831 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15832 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15833 }
15834 }
5e681ec4
PB		 15835
15836 /* Set up .got offsets for local syms, and space for local dynamic
15837 relocs. */
c72f2fb2 15838 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15839 {
5e681ec4
PB		 15840 bfd_signed_vma *local_got;
15841 bfd_signed_vma *end_local_got;
34e77a92 15842 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15843 char *local_tls_type;
0855e32b 15844 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15845 bfd_size_type locsymcount;
15846 Elf_Internal_Shdr *symtab_hdr;
15847 asection *srel;
4dfe6ac6 15848 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15849 unsigned int symndx;
5e681ec4 15850
0ffa91dd 15851 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15852 continue;
15853
15854 for (s = ibfd->sections; s != NULL; s = s->next)
15855 {
0bdcacaf 15856 struct elf_dyn_relocs *p;
5e681ec4 15857
0bdcacaf 15858 for (p = (struct elf_dyn_relocs *)
99059e56 15859 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15860 {
0bdcacaf
RS		 15861 if (!bfd_is_abs_section (p->sec)
15862 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15863 {
15864 /* Input section has been discarded, either because
15865 it is a copy of a linkonce section or due to
15866 linker script /DISCARD/, so we'll be discarding
15867 the relocs too. */
15868 }
3348747a 15869 else if (is_vxworks
0bdcacaf 15870 && strcmp (p->sec->output_section->name,
3348747a
NS		 15871 ".tls_vars") == 0)
15872 {
15873 /* Relocations in vxworks .tls_vars sections are
15874 handled specially by the loader. */
15875 }
5e681ec4
PB		 15876 else if (p->count != 0)
15877 {
0bdcacaf 15878 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15879 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15880 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15881 info->flags |= DF_TEXTREL;
15882 }
15883 }
15884 }
15885
15886 local_got = elf_local_got_refcounts (ibfd);
15887 if (!local_got)
15888 continue;
15889
0ffa91dd 15890 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15891 locsymcount = symtab_hdr->sh_info;
15892 end_local_got = local_got + locsymcount;
34e77a92 15893 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15894 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15895 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15896 symndx = 0;
362d30a1
RS		 15897 s = htab->root.sgot;
15898 srel = htab->root.srelgot;
0855e32b 15899 for (; local_got < end_local_got;
34e77a92
RS		 15900 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15901 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15902 {
0855e32b 15903 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15904 local_iplt = *local_iplt_ptr;
15905 if (local_iplt != NULL)
15906 {
15907 struct elf_dyn_relocs *p;
15908
15909 if (local_iplt->root.refcount > 0)
15910 {
15911 elf32_arm_allocate_plt_entry (info, TRUE,
15912 &local_iplt->root,
15913 &local_iplt->arm);
15914 if (local_iplt->arm.noncall_refcount == 0)
15915 /* All references to the PLT are calls, so all
15916 non-call references can resolve directly to the
15917 run-time target. This means that the .got entry
15918 would be the same as the .igot.plt entry, so there's
15919 no point creating both. */
15920 *local_got = 0;
15921 }
15922 else
15923 {
15924 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15925 local_iplt->root.offset = (bfd_vma) -1;
15926 }
15927
15928 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15929 {
15930 asection *psrel;
15931
15932 psrel = elf_section_data (p->sec)->sreloc;
15933 if (local_iplt->arm.noncall_refcount == 0)
15934 elf32_arm_allocate_irelocs (info, psrel, p->count);
15935 else
15936 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15937 }
15938 }
5e681ec4
PB		 15939 if (*local_got > 0)
15940 {
34e77a92
RS		 15941 Elf_Internal_Sym *isym;
15942
eea6121a 15943 *local_got = s->size;
ba93b8ac
DJ		 15944 if (*local_tls_type & GOT_TLS_GD)
15945 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15946 s->size += 8;
0855e32b
NS		 15947 if (*local_tls_type & GOT_TLS_GDESC)
15948 {
15949 *local_tlsdesc_gotent = htab->root.sgotplt->size
15950 - elf32_arm_compute_jump_table_size (htab);
15951 htab->root.sgotplt->size += 8;
15952 *local_got = (bfd_vma) -2;
34e77a92 15953 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15954 reloc in the middle of .got.plt. */
99059e56 15955 htab->num_tls_desc++;
0855e32b 15956 }
ba93b8ac
DJ		 15957 if (*local_tls_type & GOT_TLS_IE)
15958 s->size += 4;
ba93b8ac 15959
0855e32b
NS		 15960 if (*local_tls_type & GOT_NORMAL)
15961 {
15962 /* If the symbol is both GD and GDESC, *local_got
15963 may have been overwritten. */
15964 *local_got = s->size;
15965 s->size += 4;
15966 }
15967
34e77a92
RS		 15968 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15969 if (isym == NULL)
15970 return FALSE;
15971
15972 /* If all references to an STT_GNU_IFUNC PLT are calls,
15973 then all non-call references, including this GOT entry,
15974 resolve directly to the run-time target. */
15975 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15976 && (local_iplt == NULL
15977 || local_iplt->arm.noncall_refcount == 0))
15978 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15979 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15980 {
0e1862bb 15981 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15982 || *local_tls_type & GOT_TLS_GD)
15983 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15984
0e1862bb 15985 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15986 {
15987 elf32_arm_allocate_dynrelocs (info,
15988 htab->root.srelplt, 1);
15989 htab->tls_trampoline = -1;
15990 }
0855e32b 15991 }
5e681ec4
PB		 15992 }
15993 else
15994 *local_got = (bfd_vma) -1;
15995 }
252b5132
RH		 15996 }
15997
ba93b8ac
DJ		 15998 if (htab->tls_ldm_got.refcount > 0)
15999 {
16000 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16001 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 16002 htab->tls_ldm_got.offset = htab->root.sgot->size;
16003 htab->root.sgot->size += 8;
0e1862bb 16004 if (bfd_link_pic (info))
47beaa6a 16005 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16006 }
16007 else
16008 htab->tls_ldm_got.offset = -1;
16009
5e681ec4
PB		 16010 /* Allocate global sym .plt and .got entries, and space for global
16011 sym dynamic relocs. */
47beaa6a 16012 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16013
d504ffc8 16014 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16015 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16016 {
0ffa91dd 16017 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16018 continue;
16019
c7b8f16e
JB		 16020 /* Initialise mapping tables for code/data. */
16021 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16022
c7b8f16e 16023 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16024 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16025 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
dae82561 16026 _bfd_error_handler (_("Errors encountered processing file %B"), ibfd);
c7b8f16e 16027 }
d504ffc8 16028
3e6b1042
DJ		 16029 /* Allocate space for the glue sections now that we've sized them. */
16030 bfd_elf32_arm_allocate_interworking_sections (info);
16031
0855e32b
NS		 16032 /* For every jump slot reserved in the sgotplt, reloc_count is
16033 incremented. However, when we reserve space for TLS descriptors,
16034 it's not incremented, so in order to compute the space reserved
16035 for them, it suffices to multiply the reloc count by the jump
16036 slot size. */
16037 if (htab->root.srelplt)
16038 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16039
16040 if (htab->tls_trampoline)
16041 {
16042 if (htab->root.splt->size == 0)
16043 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16044
0855e32b
NS		 16045 htab->tls_trampoline = htab->root.splt->size;
16046 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16047
0855e32b 16048 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16049 PLT and GOT entries they require. */
0855e32b
NS		 16050 if (!(info->flags & DF_BIND_NOW))
16051 {
16052 htab->dt_tlsdesc_got = htab->root.sgot->size;
16053 htab->root.sgot->size += 4;
16054
16055 htab->dt_tlsdesc_plt = htab->root.splt->size;
16056 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16057 }
16058 }
16059
252b5132
RH		 16060 /* The check_relocs and adjust_dynamic_symbol entry points have
16061 determined the sizes of the various dynamic sections. Allocate
16062 memory for them. */
b34976b6
AM		 16063 plt = FALSE;
16064 relocs = FALSE;
252b5132
RH		 16065 for (s = dynobj->sections; s != NULL; s = s->next)
16066 {
16067 const char * name;
252b5132
RH		 16068
16069 if ((s->flags & SEC_LINKER_CREATED) == 0)
16070 continue;
16071
16072 /* It's OK to base decisions on the section name, because none
16073 of the dynobj section names depend upon the input files. */
16074 name = bfd_get_section_name (dynobj, s);
16075
34e77a92 16076 if (s == htab->root.splt)
252b5132 16077 {
c456f082
AM		 16078 /* Remember whether there is a PLT. */
16079 plt = s->size != 0;
252b5132 16080 }
0112cd26 16081 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16082 {
c456f082 16083 if (s->size != 0)
252b5132 16084 {
252b5132 16085 /* Remember whether there are any reloc sections other
00a97672 16086 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16087 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16088 relocs = TRUE;
252b5132
RH		 16089
16090 /* We use the reloc_count field as a counter if we need
16091 to copy relocs into the output file. */
16092 s->reloc_count = 0;
16093 }
16094 }
34e77a92
RS		 16095 else if (s != htab->root.sgot
16096 && s != htab->root.sgotplt
16097 && s != htab->root.iplt
16098 && s != htab->root.igotplt
5474d94f
AM		 16099 && s != htab->root.sdynbss
16100 && s != htab->root.sdynrelro)
252b5132
RH		 16101 {
16102 /* It's not one of our sections, so don't allocate space. */
16103 continue;
16104 }
16105
c456f082 16106 if (s->size == 0)
252b5132 16107 {
c456f082 16108 /* If we don't need this section, strip it from the
00a97672
RS		 16109 output file. This is mostly to handle .rel(a).bss and
16110 .rel(a).plt. We must create both sections in
c456f082
AM		 16111 create_dynamic_sections, because they must be created
16112 before the linker maps input sections to output
16113 sections. The linker does that before
16114 adjust_dynamic_symbol is called, and it is that
16115 function which decides whether anything needs to go
16116 into these sections. */
8423293d 16117 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16118 continue;
16119 }
16120
c456f082
AM		 16121 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16122 continue;
16123
252b5132 16124 /* Allocate memory for the section contents. */
21d799b5 16125 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16126 if (s->contents == NULL)
b34976b6 16127 return FALSE;
252b5132
RH		 16128 }
16129
16130 if (elf_hash_table (info)->dynamic_sections_created)
16131 {
16132 /* Add some entries to the .dynamic section. We fill in the
16133 values later, in elf32_arm_finish_dynamic_sections, but we
16134 must add the entries now so that we get the correct size for
16135 the .dynamic section. The DT_DEBUG entry is filled in by the
16136 dynamic linker and used by the debugger. */
dc810e39 16137#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16138 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16139
0e1862bb 16140 if (bfd_link_executable (info))
252b5132 16141 {
dc810e39 16142 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16143 return FALSE;
252b5132
RH		 16144 }
16145
16146 if (plt)
16147 {
dc810e39
AM		 16148 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16149 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16150 || !add_dynamic_entry (DT_PLTREL,
16151 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16152 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16153 return FALSE;
0855e32b 16154
5025eb7c
AO		 16155 if (htab->dt_tlsdesc_plt
16156 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16157 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16158 return FALSE;
252b5132
RH		 16159 }
16160
16161 if (relocs)
16162 {
00a97672
RS		 16163 if (htab->use_rel)
16164 {
16165 if (!add_dynamic_entry (DT_REL, 0)
16166 || !add_dynamic_entry (DT_RELSZ, 0)
16167 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16168 return FALSE;
16169 }
16170 else
16171 {
16172 if (!add_dynamic_entry (DT_RELA, 0)
16173 || !add_dynamic_entry (DT_RELASZ, 0)
16174 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16175 return FALSE;
16176 }
252b5132
RH		 16177 }
16178
08d1f311
DJ		 16179 /* If any dynamic relocs apply to a read-only section,
16180 then we need a DT_TEXTREL entry. */
16181 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16182 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16183 info);
08d1f311 16184
99e4ae17 16185 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16186 {
dc810e39 16187 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16188 return FALSE;
252b5132 16189 }
7a2b07ff
NS		 16190 if (htab->vxworks_p
16191 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16192 return FALSE;
252b5132 16193 }
8532796c 16194#undef add_dynamic_entry
252b5132 16195
b34976b6 16196 return TRUE;
252b5132
RH		 16197}
16198
0855e32b
NS		 16199/* Size sections even though they're not dynamic. We use it to setup
16200 _TLS_MODULE_BASE_, if needed. */
16201
16202static bfd_boolean
16203elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16204 struct bfd_link_info *info)
0855e32b
NS		 16205{
16206 asection *tls_sec;
16207
0e1862bb 16208 if (bfd_link_relocatable (info))
0855e32b
NS		 16209 return TRUE;
16210
16211 tls_sec = elf_hash_table (info)->tls_sec;
16212
16213 if (tls_sec)
16214 {
16215 struct elf_link_hash_entry *tlsbase;
16216
16217 tlsbase = elf_link_hash_lookup
16218 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16219
16220 if (tlsbase)
99059e56
RM		 16221 {
16222 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16223 const struct elf_backend_data *bed
99059e56 16224 = get_elf_backend_data (output_bfd);
0855e32b 16225
99059e56 16226 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16227 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16228 tls_sec, 0, NULL, FALSE,
16229 bed->collect, &bh)))
16230 return FALSE;
b38cadfb 16231
99059e56
RM		 16232 tlsbase->type = STT_TLS;
16233 tlsbase = (struct elf_link_hash_entry *)bh;
16234 tlsbase->def_regular = 1;
16235 tlsbase->other = STV_HIDDEN;
16236 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16237 }
16238 }
16239 return TRUE;
16240}
16241
252b5132
RH		 16242/* Finish up dynamic symbol handling. We set the contents of various
16243 dynamic sections here. */
16244
b34976b6 16245static bfd_boolean
906e58ca
NC		 16246elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16247 struct bfd_link_info * info,
16248 struct elf_link_hash_entry * h,
16249 Elf_Internal_Sym * sym)
252b5132 16250{
e5a52504 16251 struct elf32_arm_link_hash_table *htab;
b7693d02 16252 struct elf32_arm_link_hash_entry *eh;
252b5132 16253
e5a52504 16254 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16255 if (htab == NULL)
16256 return FALSE;
16257
b7693d02 16258 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16259
16260 if (h->plt.offset != (bfd_vma) -1)
16261 {
34e77a92 16262 if (!eh->is_iplt)
e5a52504 16263 {
34e77a92 16264 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16265 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16266 h->dynindx, 0))
16267 return FALSE;
e5a52504 16268 }
57e8b36a 16269
f5385ebf 16270 if (!h->def_regular)
252b5132
RH		 16271 {
16272 /* Mark the symbol as undefined, rather than as defined in
3a635617 16273 the .plt section. */
252b5132 16274 sym->st_shndx = SHN_UNDEF;
3a635617 16275 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16276 Otherwise, the PLT entry would provide a definition for
16277 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16278 and so the symbol would never be NULL. Leave the value if
16279 there were any relocations where pointer equality matters
16280 (this is a clue for the dynamic linker, to make function
16281 pointer comparisons work between an application and shared
16282 library). */
97323ad1 16283 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16284 sym->st_value = 0;
252b5132 16285 }
34e77a92
RS		 16286 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16287 {
16288 /* At least one non-call relocation references this .iplt entry,
16289 so the .iplt entry is the function's canonical address. */
16290 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16291 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16292 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16293 (output_bfd, htab->root.iplt->output_section));
16294 sym->st_value = (h->plt.offset
16295 + htab->root.iplt->output_section->vma
16296 + htab->root.iplt->output_offset);
16297 }
252b5132
RH		 16298 }
16299
f5385ebf 16300 if (h->needs_copy)
252b5132
RH		 16301 {
16302 asection * s;
947216bf 16303 Elf_Internal_Rela rel;
252b5132
RH		 16304
16305 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16306 BFD_ASSERT (h->dynindx != -1
16307 && (h->root.type == bfd_link_hash_defined
16308 || h->root.type == bfd_link_hash_defweak));
16309
00a97672 16310 rel.r_addend = 0;
252b5132
RH		 16311 rel.r_offset = (h->root.u.def.value
16312 + h->root.u.def.section->output_section->vma
16313 + h->root.u.def.section->output_offset);
16314 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16315 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16316 s = htab->root.sreldynrelro;
16317 else
16318 s = htab->root.srelbss;
47beaa6a 16319 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16320 }
16321
00a97672
RS		 16322 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16323 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16324 to the ".got" section. */
9637f6ef 16325 if (h == htab->root.hdynamic
00a97672 16326 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16327 sym->st_shndx = SHN_ABS;
16328
b34976b6 16329 return TRUE;
252b5132
RH		 16330}
16331
0855e32b
NS		 16332static void
16333arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16334 void *contents,
16335 const unsigned long *template, unsigned count)
16336{
16337 unsigned ix;
b38cadfb 16338
0855e32b
NS		 16339 for (ix = 0; ix != count; ix++)
16340 {
16341 unsigned long insn = template[ix];
16342
16343 /* Emit mov pc,rx if bx is not permitted. */
16344 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16345 insn = (insn & 0xf000000f) | 0x01a0f000;
16346 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16347 }
16348}
16349
99059e56
RM		 16350/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16351 other variants, NaCl needs this entry in a static executable's
16352 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16353 zero. For .iplt really only the last bundle is useful, and .iplt
16354 could have a shorter first entry, with each individual PLT entry's
16355 relative branch calculated differently so it targets the last
16356 bundle instead of the instruction before it (labelled .Lplt_tail
16357 above). But it's simpler to keep the size and layout of PLT0
16358 consistent with the dynamic case, at the cost of some dead code at
16359 the start of .iplt and the one dead store to the stack at the start
16360 of .Lplt_tail. */
16361static void
16362arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16363 asection *plt, bfd_vma got_displacement)
16364{
16365 unsigned int i;
16366
16367 put_arm_insn (htab, output_bfd,
16368 elf32_arm_nacl_plt0_entry[0]
16369 | arm_movw_immediate (got_displacement),
16370 plt->contents + 0);
16371 put_arm_insn (htab, output_bfd,
16372 elf32_arm_nacl_plt0_entry[1]
16373 | arm_movt_immediate (got_displacement),
16374 plt->contents + 4);
16375
16376 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16377 put_arm_insn (htab, output_bfd,
16378 elf32_arm_nacl_plt0_entry[i],
16379 plt->contents + (i * 4));
16380}
16381
252b5132
RH		 16382/* Finish up the dynamic sections. */
16383
b34976b6 16384static bfd_boolean
57e8b36a 16385elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16386{
16387 bfd * dynobj;
16388 asection * sgot;
16389 asection * sdyn;
4dfe6ac6
NC		 16390 struct elf32_arm_link_hash_table *htab;
16391
16392 htab = elf32_arm_hash_table (info);
16393 if (htab == NULL)
16394 return FALSE;
252b5132
RH		 16395
16396 dynobj = elf_hash_table (info)->dynobj;
16397
362d30a1 16398 sgot = htab->root.sgotplt;
894891db
NC		 16399 /* A broken linker script might have discarded the dynamic sections.
16400 Catch this here so that we do not seg-fault later on. */
16401 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16402 return FALSE;
3d4d4302 16403 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16404
16405 if (elf_hash_table (info)->dynamic_sections_created)
16406 {
16407 asection *splt;
16408 Elf32_External_Dyn *dyncon, *dynconend;
16409
362d30a1 16410 splt = htab->root.splt;
24a1ba0f 16411 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16412 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16413
16414 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16415 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16416
252b5132
RH		 16417 for (; dyncon < dynconend; dyncon++)
16418 {
16419 Elf_Internal_Dyn dyn;
16420 const char * name;
16421 asection * s;
16422
16423 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16424
16425 switch (dyn.d_tag)
16426 {
229fcec5
MM		 16427 unsigned int type;
16428
252b5132 16429 default:
7a2b07ff
NS		 16430 if (htab->vxworks_p
16431 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16432 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16433 break;
16434
229fcec5
MM		 16435 case DT_HASH:
16436 name = ".hash";
16437 goto get_vma_if_bpabi;
16438 case DT_STRTAB:
16439 name = ".dynstr";
16440 goto get_vma_if_bpabi;
16441 case DT_SYMTAB:
16442 name = ".dynsym";
16443 goto get_vma_if_bpabi;
c0042f5d
MM		 16444 case DT_VERSYM:
16445 name = ".gnu.version";
16446 goto get_vma_if_bpabi;
16447 case DT_VERDEF:
16448 name = ".gnu.version_d";
16449 goto get_vma_if_bpabi;
16450 case DT_VERNEED:
16451 name = ".gnu.version_r";
16452 goto get_vma_if_bpabi;
16453
252b5132 16454 case DT_PLTGOT:
4ade44b7 16455 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16456 goto get_vma;
16457 case DT_JMPREL:
00a97672 16458 name = RELOC_SECTION (htab, ".plt");
252b5132 16459 get_vma:
4ade44b7 16460 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16461 if (s == NULL)
16462 {
4eca0228 16463 _bfd_error_handler
4ade44b7 16464 (_("could not find section %s"), name);
05456594
NC		 16465 bfd_set_error (bfd_error_invalid_operation);
16466 return FALSE;
16467 }
229fcec5 16468 if (!htab->symbian_p)
4ade44b7 16469 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16470 else
16471 /* In the BPABI, tags in the PT_DYNAMIC section point
16472 at the file offset, not the memory address, for the
16473 convenience of the post linker. */
4ade44b7 16474 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16475 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16476 break;
16477
229fcec5
MM		 16478 get_vma_if_bpabi:
16479 if (htab->symbian_p)
16480 goto get_vma;
16481 break;
16482
252b5132 16483 case DT_PLTRELSZ:
362d30a1 16484 s = htab->root.srelplt;
252b5132 16485 BFD_ASSERT (s != NULL);
eea6121a 16486 dyn.d_un.d_val = s->size;
252b5132
RH		 16487 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16488 break;
906e58ca 16489
252b5132 16490 case DT_RELSZ:
00a97672 16491 case DT_RELASZ:
229fcec5
MM		 16492 case DT_REL:
16493 case DT_RELA:
229fcec5
MM		 16494 /* In the BPABI, the DT_REL tag must point at the file
16495 offset, not the VMA, of the first relocation
16496 section. So, we use code similar to that in
16497 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16498 relocation section, since relocation sections are
16499 never allocated under the BPABI. PLT relocs are also
16500 included. */
229fcec5
MM		 16501 if (htab->symbian_p)
16502 {
16503 unsigned int i;
16504 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16505 ? SHT_REL : SHT_RELA);
16506 dyn.d_un.d_val = 0;
16507 for (i = 1; i < elf_numsections (output_bfd); i++)
16508 {
906e58ca 16509 Elf_Internal_Shdr *hdr
229fcec5
MM		 16510 = elf_elfsections (output_bfd)[i];
16511 if (hdr->sh_type == type)
16512 {
906e58ca 16513 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16514 || dyn.d_tag == DT_RELASZ)
16515 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16516 else if ((ufile_ptr) hdr->sh_offset
16517 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16518 dyn.d_un.d_val = hdr->sh_offset;
16519 }
16520 }
16521 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16522 }
252b5132 16523 break;
88f7bcd5 16524
0855e32b 16525 case DT_TLSDESC_PLT:
99059e56 16526 s = htab->root.splt;
0855e32b
NS		 16527 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16528 + htab->dt_tlsdesc_plt);
16529 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16530 break;
16531
16532 case DT_TLSDESC_GOT:
99059e56 16533 s = htab->root.sgot;
0855e32b 16534 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16535 + htab->dt_tlsdesc_got);
0855e32b
NS		 16536 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16537 break;
16538
88f7bcd5
NC		 16539 /* Set the bottom bit of DT_INIT/FINI if the
16540 corresponding function is Thumb. */
16541 case DT_INIT:
16542 name = info->init_function;
16543 goto get_sym;
16544 case DT_FINI:
16545 name = info->fini_function;
16546 get_sym:
16547 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16548 then there is nothing to adjust. */
88f7bcd5
NC		 16549 if (dyn.d_un.d_val != 0)
16550 {
16551 struct elf_link_hash_entry * eh;
16552
16553 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16554 FALSE, FALSE, TRUE);
39d911fc
TP		 16555 if (eh != NULL
16556 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16557 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16558 {
16559 dyn.d_un.d_val |= 1;
b34976b6 16560 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16561 }
16562 }
16563 break;
252b5132
RH		 16564 }
16565 }
16566
24a1ba0f 16567 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16568 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16569 {
00a97672
RS		 16570 const bfd_vma *plt0_entry;
16571 bfd_vma got_address, plt_address, got_displacement;
16572
16573 /* Calculate the addresses of the GOT and PLT. */
16574 got_address = sgot->output_section->vma + sgot->output_offset;
16575 plt_address = splt->output_section->vma + splt->output_offset;
16576
16577 if (htab->vxworks_p)
16578 {
16579 /* The VxWorks GOT is relocated by the dynamic linker.
16580 Therefore, we must emit relocations rather than simply
16581 computing the values now. */
16582 Elf_Internal_Rela rel;
16583
16584 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16585 put_arm_insn (htab, output_bfd, plt0_entry[0],
16586 splt->contents + 0);
16587 put_arm_insn (htab, output_bfd, plt0_entry[1],
16588 splt->contents + 4);
16589 put_arm_insn (htab, output_bfd, plt0_entry[2],
16590 splt->contents + 8);
00a97672
RS		 16591 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16592
8029a119 16593 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16594 rel.r_offset = plt_address + 12;
16595 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16596 rel.r_addend = 0;
16597 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16598 htab->srelplt2->contents);
16599 }
b38cadfb 16600 else if (htab->nacl_p)
99059e56
RM		 16601 arm_nacl_put_plt0 (htab, output_bfd, splt,
16602 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16603 else if (using_thumb_only (htab))
16604 {
16605 got_displacement = got_address - (plt_address + 12);
16606
16607 plt0_entry = elf32_thumb2_plt0_entry;
16608 put_arm_insn (htab, output_bfd, plt0_entry[0],
16609 splt->contents + 0);
16610 put_arm_insn (htab, output_bfd, plt0_entry[1],
16611 splt->contents + 4);
16612 put_arm_insn (htab, output_bfd, plt0_entry[2],
16613 splt->contents + 8);
16614
16615 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16616 }
00a97672
RS		 16617 else
16618 {
16619 got_displacement = got_address - (plt_address + 16);
16620
16621 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16622 put_arm_insn (htab, output_bfd, plt0_entry[0],
16623 splt->contents + 0);
16624 put_arm_insn (htab, output_bfd, plt0_entry[1],
16625 splt->contents + 4);
16626 put_arm_insn (htab, output_bfd, plt0_entry[2],
16627 splt->contents + 8);
16628 put_arm_insn (htab, output_bfd, plt0_entry[3],
16629 splt->contents + 12);
5e681ec4 16630
5e681ec4 16631#ifdef FOUR_WORD_PLT
00a97672
RS		 16632 /* The displacement value goes in the otherwise-unused
16633 last word of the second entry. */
16634 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16635#else
00a97672 16636 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16637#endif
00a97672 16638 }
f7a74f8c 16639 }
252b5132
RH		 16640
16641 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16642 really seem like the right value. */
74541ad4
AM		 16643 if (splt->output_section->owner == output_bfd)
16644 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16645
0855e32b
NS		 16646 if (htab->dt_tlsdesc_plt)
16647 {
16648 bfd_vma got_address
16649 = sgot->output_section->vma + sgot->output_offset;
16650 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16651 + htab->root.sgot->output_offset);
16652 bfd_vma plt_address
16653 = splt->output_section->vma + splt->output_offset;
16654
b38cadfb 16655 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16656 splt->contents + htab->dt_tlsdesc_plt,
16657 dl_tlsdesc_lazy_trampoline, 6);
16658
16659 bfd_put_32 (output_bfd,
16660 gotplt_address + htab->dt_tlsdesc_got
16661 - (plt_address + htab->dt_tlsdesc_plt)
16662 - dl_tlsdesc_lazy_trampoline[6],
16663 splt->contents + htab->dt_tlsdesc_plt + 24);
16664 bfd_put_32 (output_bfd,
16665 got_address - (plt_address + htab->dt_tlsdesc_plt)
16666 - dl_tlsdesc_lazy_trampoline[7],
16667 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16668 }
16669
16670 if (htab->tls_trampoline)
16671 {
b38cadfb 16672 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16673 splt->contents + htab->tls_trampoline,
16674 tls_trampoline, 3);
16675#ifdef FOUR_WORD_PLT
16676 bfd_put_32 (output_bfd, 0x00000000,
16677 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16678#endif
0855e32b
NS		 16679 }
16680
0e1862bb
L		 16681 if (htab->vxworks_p
16682 && !bfd_link_pic (info)
16683 && htab->root.splt->size > 0)
00a97672
RS		 16684 {
16685 /* Correct the .rel(a).plt.unloaded relocations. They will have
16686 incorrect symbol indexes. */
16687 int num_plts;
eed62c48 16688 unsigned char *p;
00a97672 16689
362d30a1 16690 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16691 / htab->plt_entry_size);
16692 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16693
16694 for (; num_plts; num_plts--)
16695 {
16696 Elf_Internal_Rela rel;
16697
16698 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16699 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16700 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16701 p += RELOC_SIZE (htab);
16702
16703 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16704 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16705 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16706 p += RELOC_SIZE (htab);
16707 }
16708 }
252b5132
RH		 16709 }
16710
99059e56
RM		 16711 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16712 /* NaCl uses a special first entry in .iplt too. */
16713 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16714
252b5132 16715 /* Fill in the first three entries in the global offset table. */
229fcec5 16716 if (sgot)
252b5132 16717 {
229fcec5
MM		 16718 if (sgot->size > 0)
16719 {
16720 if (sdyn == NULL)
16721 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16722 else
16723 bfd_put_32 (output_bfd,
16724 sdyn->output_section->vma + sdyn->output_offset,
16725 sgot->contents);
16726 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16727 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16728 }
252b5132 16729
229fcec5
MM		 16730 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16731 }
252b5132 16732
b34976b6 16733 return TRUE;
252b5132
RH		 16734}
16735
ba96a88f 16736static void
57e8b36a 16737elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16738{
9b485d32 16739 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16740 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16741 struct elf_segment_map *m;
ba96a88f
NC		 16742
16743 i_ehdrp = elf_elfheader (abfd);
16744
94a3258f
PB		 16745 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16746 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16747 else
7394f108 16748 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16749 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16750
93204d3a
PB		 16751 if (link_info)
16752 {
16753 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16754 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16755 i_ehdrp->e_flags |= EF_ARM_BE8;
16756 }
3bfcb652
NC		 16757
16758 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16759 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16760 {
16761 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16762 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16763 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16764 else
16765 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16766 }
ac4c9b04
MG		 16767
16768 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16769 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16770 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16771 {
16772 unsigned int j;
16773
16774 if (m->count == 0)
16775 continue;
16776 for (j = 0; j < m->count; j++)
16777 {
f0728ee3 16778 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16779 break;
16780 }
16781 if (j == m->count)
16782 {
16783 m->p_flags = PF_X;
16784 m->p_flags_valid = 1;
16785 }
16786 }
ba96a88f
NC		 16787}
16788
99e4ae17 16789static enum elf_reloc_type_class
7e612e98
AM		 16790elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16791 const asection *rel_sec ATTRIBUTE_UNUSED,
16792 const Elf_Internal_Rela *rela)
99e4ae17 16793{
f51e552e 16794 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16795 {
16796 case R_ARM_RELATIVE:
16797 return reloc_class_relative;
16798 case R_ARM_JUMP_SLOT:
16799 return reloc_class_plt;
16800 case R_ARM_COPY:
16801 return reloc_class_copy;
109575d7
JW		 16802 case R_ARM_IRELATIVE:
16803 return reloc_class_ifunc;
99e4ae17
AJ		 16804 default:
16805 return reloc_class_normal;
16806 }
16807}
16808
e489d0ae 16809static void
57e8b36a 16810elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16811{
5a6c6817 16812 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16813}
16814
40a18ebd
NC		 16815/* Return TRUE if this is an unwinding table entry. */
16816
16817static bfd_boolean
16818is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16819{
0112cd26
NC		 16820 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16821 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16822}
16823
16824
16825/* Set the type and flags for an ARM section. We do this by
16826 the section name, which is a hack, but ought to work. */
16827
16828static bfd_boolean
16829elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16830{
16831 const char * name;
16832
16833 name = bfd_get_section_name (abfd, sec);
16834
16835 if (is_arm_elf_unwind_section_name (abfd, name))
16836 {
16837 hdr->sh_type = SHT_ARM_EXIDX;
16838 hdr->sh_flags |= SHF_LINK_ORDER;
16839 }
ac4c9b04 16840
f0728ee3
AV		 16841 if (sec->flags & SEC_ELF_PURECODE)
16842 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16843
40a18ebd
NC		 16844 return TRUE;
16845}
16846
6dc132d9
L		 16847/* Handle an ARM specific section when reading an object file. This is
16848 called when bfd_section_from_shdr finds a section with an unknown
16849 type. */
40a18ebd
NC		 16850
16851static bfd_boolean
16852elf32_arm_section_from_shdr (bfd *abfd,
16853 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16854 const char *name,
16855 int shindex)
40a18ebd
NC		 16856{
16857 /* There ought to be a place to keep ELF backend specific flags, but
16858 at the moment there isn't one. We just keep track of the
16859 sections by their name, instead. Fortunately, the ABI gives
16860 names for all the ARM specific sections, so we will probably get
16861 away with this. */
16862 switch (hdr->sh_type)
16863 {
16864 case SHT_ARM_EXIDX:
0951f019
RE		 16865 case SHT_ARM_PREEMPTMAP:
16866 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16867 break;
16868
16869 default:
16870 return FALSE;
16871 }
16872
6dc132d9 16873 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16874 return FALSE;
16875
16876 return TRUE;
16877}
e489d0ae 16878
44444f50
NC		 16879static _arm_elf_section_data *
16880get_arm_elf_section_data (asection * sec)
16881{
47b2e99c
JZ		 16882 if (sec && sec->owner && is_arm_elf (sec->owner))
16883 return elf32_arm_section_data (sec);
44444f50
NC		 16884 else
16885 return NULL;
8e3de13a
NC		 16886}
16887
4e617b1e
PB		 16888typedef struct
16889{
57402f1e 16890 void *flaginfo;
4e617b1e 16891 struct bfd_link_info *info;
91a5743d
PB		 16892 asection *sec;
16893 int sec_shndx;
6e0b88f1
AM		 16894 int (*func) (void *, const char *, Elf_Internal_Sym *,
16895 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16896} output_arch_syminfo;
16897
16898enum map_symbol_type
16899{
16900 ARM_MAP_ARM,
16901 ARM_MAP_THUMB,
16902 ARM_MAP_DATA
16903};
16904
16905
7413f23f 16906/* Output a single mapping symbol. */
4e617b1e
PB		 16907
16908static bfd_boolean
7413f23f
DJ		 16909elf32_arm_output_map_sym (output_arch_syminfo *osi,
16910 enum map_symbol_type type,
16911 bfd_vma offset)
4e617b1e
PB		 16912{
16913 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16914 Elf_Internal_Sym sym;
16915
91a5743d
PB		 16916 sym.st_value = osi->sec->output_section->vma
16917 + osi->sec->output_offset
16918 + offset;
4e617b1e
PB		 16919 sym.st_size = 0;
16920 sym.st_other = 0;
16921 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16922 sym.st_shndx = osi->sec_shndx;
35fc36a8 16923 sym.st_target_internal = 0;
fe33d2fa 16924 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16925 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16926}
16927
34e77a92
RS		 16928/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16929 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16930
16931static bfd_boolean
34e77a92
RS		 16932elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16933 bfd_boolean is_iplt_entry_p,
16934 union gotplt_union *root_plt,
16935 struct arm_plt_info *arm_plt)
4e617b1e 16936{
4e617b1e 16937 struct elf32_arm_link_hash_table *htab;
34e77a92 16938 bfd_vma addr, plt_header_size;
4e617b1e 16939
34e77a92 16940 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16941 return TRUE;
16942
4dfe6ac6
NC		 16943 htab = elf32_arm_hash_table (osi->info);
16944 if (htab == NULL)
16945 return FALSE;
16946
34e77a92
RS		 16947 if (is_iplt_entry_p)
16948 {
16949 osi->sec = htab->root.iplt;
16950 plt_header_size = 0;
16951 }
16952 else
16953 {
16954 osi->sec = htab->root.splt;
16955 plt_header_size = htab->plt_header_size;
16956 }
16957 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16958 (osi->info->output_bfd, osi->sec->output_section));
16959
16960 addr = root_plt->offset & -2;
4e617b1e
PB		 16961 if (htab->symbian_p)
16962 {
7413f23f 16963 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16964 return FALSE;
7413f23f 16965 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16966 return FALSE;
16967 }
16968 else if (htab->vxworks_p)
16969 {
7413f23f 16970 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16971 return FALSE;
7413f23f 16972 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16973 return FALSE;
7413f23f 16974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16975 return FALSE;
7413f23f 16976 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16977 return FALSE;
16978 }
b38cadfb
NC		 16979 else if (htab->nacl_p)
16980 {
16981 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16982 return FALSE;
16983 }
eed94f8f
NC		 16984 else if (using_thumb_only (htab))
16985 {
16986 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16987 return FALSE;
6a631e86 16988 }
4e617b1e
PB		 16989 else
16990 {
34e77a92 16991 bfd_boolean thumb_stub_p;
bd97cb95 16992
34e77a92
RS		 16993 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16994 if (thumb_stub_p)
4e617b1e 16995 {
7413f23f 16996 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16997 return FALSE;
16998 }
16999#ifdef FOUR_WORD_PLT
7413f23f 17000 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17001 return FALSE;
7413f23f 17002 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17003 return FALSE;
17004#else
906e58ca 17005 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17006 so only need to output a mapping symbol for the first PLT entry and
17007 entries with thumb thunks. */
34e77a92 17008 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17009 {
7413f23f 17010 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17011 return FALSE;
17012 }
17013#endif
17014 }
17015
17016 return TRUE;
17017}
17018
34e77a92
RS		 17019/* Output mapping symbols for PLT entries associated with H. */
17020
17021static bfd_boolean
17022elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17023{
17024 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17025 struct elf32_arm_link_hash_entry *eh;
17026
17027 if (h->root.type == bfd_link_hash_indirect)
17028 return TRUE;
17029
17030 if (h->root.type == bfd_link_hash_warning)
17031 /* When warning symbols are created, they **replace** the "real"
17032 entry in the hash table, thus we never get to see the real
17033 symbol in a hash traversal. So look at it now. */
17034 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17035
17036 eh = (struct elf32_arm_link_hash_entry *) h;
17037 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17038 &h->plt, &eh->plt);
17039}
17040
4f4faa4d
TP		 17041/* Bind a veneered symbol to its veneer identified by its hash entry
17042 STUB_ENTRY. The veneered location thus loose its symbol. */
17043
17044static void
17045arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17046{
17047 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17048
17049 BFD_ASSERT (hash);
17050 hash->root.root.u.def.section = stub_entry->stub_sec;
17051 hash->root.root.u.def.value = stub_entry->stub_offset;
17052 hash->root.size = stub_entry->stub_size;
17053}
17054
7413f23f
DJ		 17055/* Output a single local symbol for a generated stub. */
17056
17057static bfd_boolean
17058elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17059 bfd_vma offset, bfd_vma size)
17060{
7413f23f
DJ		 17061 Elf_Internal_Sym sym;
17062
7413f23f
DJ		 17063 sym.st_value = osi->sec->output_section->vma
17064 + osi->sec->output_offset
17065 + offset;
17066 sym.st_size = size;
17067 sym.st_other = 0;
17068 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17069 sym.st_shndx = osi->sec_shndx;
35fc36a8 17070 sym.st_target_internal = 0;
57402f1e 17071 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17072}
4e617b1e 17073
da5938a2 17074static bfd_boolean
8029a119
NC		 17075arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17076 void * in_arg)
da5938a2
NC		 17077{
17078 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17079 asection *stub_sec;
17080 bfd_vma addr;
7413f23f 17081 char *stub_name;
9a008db3 17082 output_arch_syminfo *osi;
d3ce72d0 17083 const insn_sequence *template_sequence;
461a49ca
DJ		 17084 enum stub_insn_type prev_type;
17085 int size;
17086 int i;
17087 enum map_symbol_type sym_type;
da5938a2
NC		 17088
17089 /* Massage our args to the form they really have. */
17090 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17091 osi = (output_arch_syminfo *) in_arg;
da5938a2 17092
da5938a2
NC		 17093 stub_sec = stub_entry->stub_sec;
17094
17095 /* Ensure this stub is attached to the current section being
7413f23f 17096 processed. */
da5938a2
NC		 17097 if (stub_sec != osi->sec)
17098 return TRUE;
17099
7413f23f 17100 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17101 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17102
17103 if (arm_stub_sym_claimed (stub_entry->stub_type))
17104 arm_stub_claim_sym (stub_entry);
17105 else
7413f23f 17106 {
4f4faa4d
TP		 17107 stub_name = stub_entry->output_name;
17108 switch (template_sequence[0].type)
17109 {
17110 case ARM_TYPE:
17111 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17112 stub_entry->stub_size))
17113 return FALSE;
17114 break;
17115 case THUMB16_TYPE:
17116 case THUMB32_TYPE:
17117 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17118 stub_entry->stub_size))
17119 return FALSE;
17120 break;
17121 default:
17122 BFD_FAIL ();
17123 return 0;
17124 }
7413f23f 17125 }
da5938a2 17126
461a49ca
DJ		 17127 prev_type = DATA_TYPE;
17128 size = 0;
17129 for (i = 0; i < stub_entry->stub_template_size; i++)
17130 {
d3ce72d0 17131 switch (template_sequence[i].type)
461a49ca
DJ		 17132 {
17133 case ARM_TYPE:
17134 sym_type = ARM_MAP_ARM;
17135 break;
17136
17137 case THUMB16_TYPE:
48229727 17138 case THUMB32_TYPE:
461a49ca
DJ		 17139 sym_type = ARM_MAP_THUMB;
17140 break;
17141
17142 case DATA_TYPE:
17143 sym_type = ARM_MAP_DATA;
17144 break;
17145
17146 default:
17147 BFD_FAIL ();
4e31c731 17148 return FALSE;
461a49ca
DJ		 17149 }
17150
d3ce72d0 17151 if (template_sequence[i].type != prev_type)
461a49ca 17152 {
d3ce72d0 17153 prev_type = template_sequence[i].type;
461a49ca
DJ		 17154 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17155 return FALSE;
17156 }
17157
d3ce72d0 17158 switch (template_sequence[i].type)
461a49ca
DJ		 17159 {
17160 case ARM_TYPE:
48229727 17161 case THUMB32_TYPE:
461a49ca
DJ		 17162 size += 4;
17163 break;
17164
17165 case THUMB16_TYPE:
17166 size += 2;
17167 break;
17168
17169 case DATA_TYPE:
17170 size += 4;
17171 break;
17172
17173 default:
17174 BFD_FAIL ();
4e31c731 17175 return FALSE;
461a49ca
DJ		 17176 }
17177 }
17178
da5938a2
NC		 17179 return TRUE;
17180}
17181
33811162
DG		 17182/* Output mapping symbols for linker generated sections,
17183 and for those data-only sections that do not have a
17184 $d. */
4e617b1e
PB		 17185
17186static bfd_boolean
17187elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17188 struct bfd_link_info *info,
57402f1e 17189 void *flaginfo,
6e0b88f1
AM		 17190 int (*func) (void *, const char *,
17191 Elf_Internal_Sym *,
17192 asection *,
17193 struct elf_link_hash_entry *))
4e617b1e
PB		 17194{
17195 output_arch_syminfo osi;
17196 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17197 bfd_vma offset;
17198 bfd_size_type size;
33811162 17199 bfd *input_bfd;
4e617b1e
PB		 17200
17201 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17202 if (htab == NULL)
17203 return FALSE;
17204
906e58ca 17205 check_use_blx (htab);
91a5743d 17206
57402f1e 17207 osi.flaginfo = flaginfo;
4e617b1e
PB		 17208 osi.info = info;
17209 osi.func = func;
906e58ca 17210
33811162
DG		 17211 /* Add a $d mapping symbol to data-only sections that
17212 don't have any mapping symbol. This may result in (harmless) redundant
17213 mapping symbols. */
17214 for (input_bfd = info->input_bfds;
17215 input_bfd != NULL;
c72f2fb2 17216 input_bfd = input_bfd->link.next)
33811162
DG		 17217 {
17218 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17219 for (osi.sec = input_bfd->sections;
17220 osi.sec != NULL;
17221 osi.sec = osi.sec->next)
17222 {
17223 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17224 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17225 != 0)
33811162
DG		 17226 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17227 == SEC_HAS_CONTENTS
17228 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17229 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17230 && osi.sec->size > 0
17231 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17232 {
17233 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17234 (output_bfd, osi.sec->output_section);
17235 if (osi.sec_shndx != (int)SHN_BAD)
17236 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17237 }
17238 }
17239 }
17240
91a5743d
PB		 17241 /* ARM->Thumb glue. */
17242 if (htab->arm_glue_size > 0)
17243 {
3d4d4302
AM		 17244 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17245 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17246
17247 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17248 (output_bfd, osi.sec->output_section);
0e1862bb 17249 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17250 || htab->pic_veneer)
17251 size = ARM2THUMB_PIC_GLUE_SIZE;
17252 else if (htab->use_blx)
17253 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17254 else
17255 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17256
91a5743d
PB		 17257 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17258 {
7413f23f
DJ		 17259 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17260 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17261 }
17262 }
17263
17264 /* Thumb->ARM glue. */
17265 if (htab->thumb_glue_size > 0)
17266 {
3d4d4302
AM		 17267 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17268 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17269
17270 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17271 (output_bfd, osi.sec->output_section);
17272 size = THUMB2ARM_GLUE_SIZE;
17273
17274 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17275 {
7413f23f
DJ		 17276 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17277 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17278 }
17279 }
17280
845b51d6
PB		 17281 /* ARMv4 BX veneers. */
17282 if (htab->bx_glue_size > 0)
17283 {
3d4d4302
AM		 17284 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17285 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17286
17287 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17288 (output_bfd, osi.sec->output_section);
17289
7413f23f 17290 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17291 }
17292
8029a119
NC		 17293 /* Long calls stubs. */
17294 if (htab->stub_bfd && htab->stub_bfd->sections)
17295 {
da5938a2 17296 asection* stub_sec;
8029a119 17297
da5938a2
NC		 17298 for (stub_sec = htab->stub_bfd->sections;
17299 stub_sec != NULL;
8029a119
NC		 17300 stub_sec = stub_sec->next)
17301 {
17302 /* Ignore non-stub sections. */
17303 if (!strstr (stub_sec->name, STUB_SUFFIX))
17304 continue;
da5938a2 17305
8029a119 17306 osi.sec = stub_sec;
da5938a2 17307
8029a119
NC		 17308 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17309 (output_bfd, osi.sec->output_section);
da5938a2 17310
8029a119
NC		 17311 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17312 }
17313 }
da5938a2 17314
91a5743d 17315 /* Finally, output mapping symbols for the PLT. */
34e77a92 17316 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17317 {
34e77a92
RS		 17318 osi.sec = htab->root.splt;
17319 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17320 (output_bfd, osi.sec->output_section));
17321
17322 /* Output mapping symbols for the plt header. SymbianOS does not have a
17323 plt header. */
17324 if (htab->vxworks_p)
17325 {
17326 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17327 if (!bfd_link_pic (info))
34e77a92
RS		 17328 {
17329 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17330 return FALSE;
17331 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17332 return FALSE;
17333 }
17334 }
b38cadfb
NC		 17335 else if (htab->nacl_p)
17336 {
17337 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17338 return FALSE;
17339 }
eed94f8f
NC		 17340 else if (using_thumb_only (htab))
17341 {
17342 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17343 return FALSE;
17344 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17345 return FALSE;
17346 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17347 return FALSE;
17348 }
34e77a92 17349 else if (!htab->symbian_p)
4e617b1e 17350 {
7413f23f 17351 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17352 return FALSE;
34e77a92
RS		 17353#ifndef FOUR_WORD_PLT
17354 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17355 return FALSE;
34e77a92 17356#endif
4e617b1e
PB		 17357 }
17358 }
99059e56
RM		 17359 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17360 {
17361 /* NaCl uses a special first entry in .iplt too. */
17362 osi.sec = htab->root.iplt;
17363 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17364 (output_bfd, osi.sec->output_section));
17365 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17366 return FALSE;
17367 }
34e77a92
RS		 17368 if ((htab->root.splt && htab->root.splt->size > 0)
17369 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17370 {
34e77a92
RS		 17371 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17372 for (input_bfd = info->input_bfds;
17373 input_bfd != NULL;
c72f2fb2 17374 input_bfd = input_bfd->link.next)
34e77a92
RS		 17375 {
17376 struct arm_local_iplt_info **local_iplt;
17377 unsigned int i, num_syms;
4e617b1e 17378
34e77a92
RS		 17379 local_iplt = elf32_arm_local_iplt (input_bfd);
17380 if (local_iplt != NULL)
17381 {
17382 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17383 for (i = 0; i < num_syms; i++)
17384 if (local_iplt[i] != NULL
17385 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17386 &local_iplt[i]->root,
17387 &local_iplt[i]->arm))
17388 return FALSE;
17389 }
17390 }
17391 }
0855e32b
NS		 17392 if (htab->dt_tlsdesc_plt != 0)
17393 {
17394 /* Mapping symbols for the lazy tls trampoline. */
17395 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17396 return FALSE;
b38cadfb 17397
0855e32b
NS		 17398 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17399 htab->dt_tlsdesc_plt + 24))
17400 return FALSE;
17401 }
17402 if (htab->tls_trampoline != 0)
17403 {
17404 /* Mapping symbols for the tls trampoline. */
17405 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17406 return FALSE;
17407#ifdef FOUR_WORD_PLT
17408 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17409 htab->tls_trampoline + 12))
17410 return FALSE;
b38cadfb 17411#endif
0855e32b 17412 }
b38cadfb 17413
4e617b1e
PB		 17414 return TRUE;
17415}
17416
54ddd295
TP		 17417/* Filter normal symbols of CMSE entry functions of ABFD to include in
17418 the import library. All SYMCOUNT symbols of ABFD can be examined
17419 from their pointers in SYMS. Pointers of symbols to keep should be
17420 stored continuously at the beginning of that array.
17421
17422 Returns the number of symbols to keep. */
17423
17424static unsigned int
17425elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17426 struct bfd_link_info *info,
17427 asymbol **syms, long symcount)
17428{
17429 size_t maxnamelen;
17430 char *cmse_name;
17431 long src_count, dst_count = 0;
17432 struct elf32_arm_link_hash_table *htab;
17433
17434 htab = elf32_arm_hash_table (info);
17435 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17436 symcount = 0;
17437
17438 maxnamelen = 128;
17439 cmse_name = (char *) bfd_malloc (maxnamelen);
17440 for (src_count = 0; src_count < symcount; src_count++)
17441 {
17442 struct elf32_arm_link_hash_entry *cmse_hash;
17443 asymbol *sym;
17444 flagword flags;
17445 char *name;
17446 size_t namelen;
17447
17448 sym = syms[src_count];
17449 flags = sym->flags;
17450 name = (char *) bfd_asymbol_name (sym);
17451
17452 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17453 continue;
17454 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17455 continue;
17456
17457 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17458 if (namelen > maxnamelen)
17459 {
17460 cmse_name = (char *)
17461 bfd_realloc (cmse_name, namelen);
17462 maxnamelen = namelen;
17463 }
17464 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17465 cmse_hash = (struct elf32_arm_link_hash_entry *)
17466 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17467
17468 if (!cmse_hash
17469 || (cmse_hash->root.root.type != bfd_link_hash_defined
17470 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17471 || cmse_hash->root.type != STT_FUNC)
17472 continue;
17473
17474 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17475 continue;
17476
17477 syms[dst_count++] = sym;
17478 }
17479 free (cmse_name);
17480
17481 syms[dst_count] = NULL;
17482
17483 return dst_count;
17484}
17485
17486/* Filter symbols of ABFD to include in the import library. All
17487 SYMCOUNT symbols of ABFD can be examined from their pointers in
17488 SYMS. Pointers of symbols to keep should be stored continuously at
17489 the beginning of that array.
17490
17491 Returns the number of symbols to keep. */
17492
17493static unsigned int
17494elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17495 struct bfd_link_info *info,
17496 asymbol **syms, long symcount)
17497{
17498 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17499
17500 if (globals->cmse_implib)
17501 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17502 else
17503 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17504}
17505
e489d0ae
PB		 17506/* Allocate target specific section data. */
17507
17508static bfd_boolean
17509elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17510{
f592407e
AM		 17511 if (!sec->used_by_bfd)
17512 {
17513 _arm_elf_section_data *sdata;
17514 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17515
21d799b5 17516 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17517 if (sdata == NULL)
17518 return FALSE;
17519 sec->used_by_bfd = sdata;
17520 }
e489d0ae
PB		 17521
17522 return _bfd_elf_new_section_hook (abfd, sec);
17523}
17524
17525
17526/* Used to order a list of mapping symbols by address. */
17527
17528static int
17529elf32_arm_compare_mapping (const void * a, const void * b)
17530{
7f6a71ff
JM		 17531 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17532 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17533
17534 if (amap->vma > bmap->vma)
17535 return 1;
17536 else if (amap->vma < bmap->vma)
17537 return -1;
17538 else if (amap->type > bmap->type)
17539 /* Ensure results do not depend on the host qsort for objects with
17540 multiple mapping symbols at the same address by sorting on type
17541 after vma. */
17542 return 1;
17543 else if (amap->type < bmap->type)
17544 return -1;
17545 else
17546 return 0;
e489d0ae
PB		 17547}
17548
2468f9c9
PB		 17549/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17550
17551static unsigned long
17552offset_prel31 (unsigned long addr, bfd_vma offset)
17553{
17554 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17555}
17556
17557/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17558 relocations. */
17559
17560static void
17561copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17562{
17563 unsigned long first_word = bfd_get_32 (output_bfd, from);
17564 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17565
2468f9c9
PB		 17566 /* High bit of first word is supposed to be zero. */
17567 if ((first_word & 0x80000000ul) == 0)
17568 first_word = offset_prel31 (first_word, offset);
b38cadfb 17569
2468f9c9
PB		 17570 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17571 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17572 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17573 second_word = offset_prel31 (second_word, offset);
b38cadfb 17574
2468f9c9
PB		 17575 bfd_put_32 (output_bfd, first_word, to);
17576 bfd_put_32 (output_bfd, second_word, to + 4);
17577}
e489d0ae 17578
48229727
JB		 17579/* Data for make_branch_to_a8_stub(). */
17580
b38cadfb
NC		 17581struct a8_branch_to_stub_data
17582{
48229727
JB		 17583 asection *writing_section;
17584 bfd_byte *contents;
17585};
17586
17587
17588/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17589 places for a particular section. */
17590
17591static bfd_boolean
17592make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17593 void *in_arg)
48229727
JB		 17594{
17595 struct elf32_arm_stub_hash_entry *stub_entry;
17596 struct a8_branch_to_stub_data *data;
17597 bfd_byte *contents;
17598 unsigned long branch_insn;
17599 bfd_vma veneered_insn_loc, veneer_entry_loc;
17600 bfd_signed_vma branch_offset;
17601 bfd *abfd;
8d9d9490 17602 unsigned int loc;
48229727
JB		 17603
17604 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17605 data = (struct a8_branch_to_stub_data *) in_arg;
17606
17607 if (stub_entry->target_section != data->writing_section
4563a860 17608 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17609 return TRUE;
17610
17611 contents = data->contents;
17612
8d9d9490
TP		 17613 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17614 generated when both source and target are in the same section. */
48229727
JB		 17615 veneered_insn_loc = stub_entry->target_section->output_section->vma
17616 + stub_entry->target_section->output_offset
8d9d9490 17617 + stub_entry->source_value;
48229727
JB		 17618
17619 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17620 + stub_entry->stub_sec->output_offset
17621 + stub_entry->stub_offset;
17622
17623 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17624 veneered_insn_loc &= ~3u;
17625
17626 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17627
17628 abfd = stub_entry->target_section->owner;
8d9d9490 17629 loc = stub_entry->source_value;
48229727
JB		 17630
17631 /* We attempt to avoid this condition by setting stubs_always_after_branch
17632 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17633 This check is just to be on the safe side... */
17634 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17635 {
4eca0228
AM		 17636 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17637 "allocated in unsafe location"), abfd);
48229727
JB		 17638 return FALSE;
17639 }
17640
17641 switch (stub_entry->stub_type)
17642 {
17643 case arm_stub_a8_veneer_b:
17644 case arm_stub_a8_veneer_b_cond:
17645 branch_insn = 0xf0009000;
17646 goto jump24;
17647
17648 case arm_stub_a8_veneer_blx:
17649 branch_insn = 0xf000e800;
17650 goto jump24;
17651
17652 case arm_stub_a8_veneer_bl:
17653 {
17654 unsigned int i1, j1, i2, j2, s;
17655
17656 branch_insn = 0xf000d000;
17657
17658 jump24:
17659 if (branch_offset < -16777216 || branch_offset > 16777214)
17660 {
17661 /* There's not much we can do apart from complain if this
17662 happens. */
4eca0228
AM		 17663 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17664 "of range (input file too large)"), abfd);
48229727
JB		 17665 return FALSE;
17666 }
17667
17668 /* i1 = not(j1 eor s), so:
17669 not i1 = j1 eor s
17670 j1 = (not i1) eor s. */
17671
17672 branch_insn |= (branch_offset >> 1) & 0x7ff;
17673 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17674 i2 = (branch_offset >> 22) & 1;
17675 i1 = (branch_offset >> 23) & 1;
17676 s = (branch_offset >> 24) & 1;
17677 j1 = (!i1) ^ s;
17678 j2 = (!i2) ^ s;
17679 branch_insn |= j2 << 11;
17680 branch_insn |= j1 << 13;
17681 branch_insn |= s << 26;
17682 }
17683 break;
17684
17685 default:
17686 BFD_FAIL ();
17687 return FALSE;
17688 }
17689
8d9d9490
TP		 17690 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17691 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17692
17693 return TRUE;
17694}
17695
a504d23a
LA		 17696/* Beginning of stm32l4xx work-around. */
17697
17698/* Functions encoding instructions necessary for the emission of the
17699 fix-stm32l4xx-629360.
17700 Encoding is extracted from the
17701 ARM (C) Architecture Reference Manual
17702 ARMv7-A and ARMv7-R edition
17703 ARM DDI 0406C.b (ID072512). */
17704
17705static inline bfd_vma
82188b29 17706create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17707{
17708 /* A8.8.18 B (A8-334)
17709 B target_address (Encoding T4). */
17710 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17711 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17712 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17713
a504d23a
LA		 17714 int s = ((branch_offset & 0x1000000) >> 24);
17715 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17716 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17717
17718 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17719 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17720
17721 bfd_vma patched_inst = 0xf0009000
17722 | s << 26 /* S. */
17723 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17724 | j1 << 13 /* J1. */
17725 | j2 << 11 /* J2. */
17726 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17727
17728 return patched_inst;
17729}
17730
17731static inline bfd_vma
17732create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17733{
17734 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17735 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17736 bfd_vma patched_inst = 0xe8900000
17737 | (/*W=*/wback << 21)
17738 | (base_reg << 16)
17739 | (reg_mask & 0x0000ffff);
17740
17741 return patched_inst;
17742}
17743
17744static inline bfd_vma
17745create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17746{
17747 /* A8.8.60 LDMDB/LDMEA (A8-402)
17748 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17749 bfd_vma patched_inst = 0xe9100000
17750 | (/*W=*/wback << 21)
17751 | (base_reg << 16)
17752 | (reg_mask & 0x0000ffff);
17753
17754 return patched_inst;
17755}
17756
17757static inline bfd_vma
17758create_instruction_mov (int target_reg, int source_reg)
17759{
17760 /* A8.8.103 MOV (register) (A8-486)
17761 MOV Rd, Rm (Encoding T1). */
17762 bfd_vma patched_inst = 0x4600
17763 | (target_reg & 0x7)
17764 | ((target_reg & 0x8) >> 3) << 7
17765 | (source_reg << 3);
17766
17767 return patched_inst;
17768}
17769
17770static inline bfd_vma
17771create_instruction_sub (int target_reg, int source_reg, int value)
17772{
17773 /* A8.8.221 SUB (immediate) (A8-708)
17774 SUB Rd, Rn, #value (Encoding T3). */
17775 bfd_vma patched_inst = 0xf1a00000
17776 | (target_reg << 8)
17777 | (source_reg << 16)
17778 | (/*S=*/0 << 20)
17779 | ((value & 0x800) >> 11) << 26
17780 | ((value & 0x700) >> 8) << 12
17781 | (value & 0x0ff);
17782
17783 return patched_inst;
17784}
17785
17786static inline bfd_vma
9239bbd3 17787create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17788 int first_reg)
17789{
17790 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17791 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17792 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17793 | (/*W=*/wback << 21)
17794 | (base_reg << 16)
9239bbd3
CM		 17795 | (num_words & 0x000000ff)
17796 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17797 | (first_reg & 0x00000001) << 22;
17798
17799 return patched_inst;
17800}
17801
17802static inline bfd_vma
9239bbd3
CM		 17803create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17804 int first_reg)
a504d23a
LA		 17805{
17806 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17807 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17808 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17809 | (base_reg << 16)
9239bbd3
CM		 17810 | (num_words & 0x000000ff)
17811 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17812 | (first_reg & 0x00000001) << 22;
17813
17814 return patched_inst;
17815}
17816
17817static inline bfd_vma
17818create_instruction_udf_w (int value)
17819{
17820 /* A8.8.247 UDF (A8-758)
17821 Undefined (Encoding T2). */
17822 bfd_vma patched_inst = 0xf7f0a000
17823 | (value & 0x00000fff)
17824 | (value & 0x000f0000) << 16;
17825
17826 return patched_inst;
17827}
17828
17829static inline bfd_vma
17830create_instruction_udf (int value)
17831{
17832 /* A8.8.247 UDF (A8-758)
17833 Undefined (Encoding T1). */
17834 bfd_vma patched_inst = 0xde00
17835 | (value & 0xff);
17836
17837 return patched_inst;
17838}
17839
17840/* Functions writing an instruction in memory, returning the next
17841 memory position to write to. */
17842
17843static inline bfd_byte *
17844push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17845 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17846{
17847 put_thumb2_insn (htab, output_bfd, insn, pt);
17848 return pt + 4;
17849}
17850
17851static inline bfd_byte *
17852push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17853 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17854{
17855 put_thumb_insn (htab, output_bfd, insn, pt);
17856 return pt + 2;
17857}
17858
17859/* Function filling up a region in memory with T1 and T2 UDFs taking
17860 care of alignment. */
17861
17862static bfd_byte *
17863stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17864 bfd * output_bfd,
17865 const bfd_byte * const base_stub_contents,
17866 bfd_byte * const from_stub_contents,
17867 const bfd_byte * const end_stub_contents)
17868{
17869 bfd_byte *current_stub_contents = from_stub_contents;
17870
17871 /* Fill the remaining of the stub with deterministic contents : UDF
17872 instructions.
17873 Check if realignment is needed on modulo 4 frontier using T1, to
17874 further use T2. */
17875 if ((current_stub_contents < end_stub_contents)
17876 && !((current_stub_contents - base_stub_contents) % 2)
17877 && ((current_stub_contents - base_stub_contents) % 4))
17878 current_stub_contents =
17879 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17880 create_instruction_udf (0));
17881
17882 for (; current_stub_contents < end_stub_contents;)
17883 current_stub_contents =
17884 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17885 create_instruction_udf_w (0));
17886
17887 return current_stub_contents;
17888}
17889
17890/* Functions writing the stream of instructions equivalent to the
17891 derived sequence for ldmia, ldmdb, vldm respectively. */
17892
17893static void
17894stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17895 bfd * output_bfd,
17896 const insn32 initial_insn,
17897 const bfd_byte *const initial_insn_addr,
17898 bfd_byte *const base_stub_contents)
17899{
17900 int wback = (initial_insn & 0x00200000) >> 21;
17901 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17902 int insn_all_registers = initial_insn & 0x0000ffff;
17903 int insn_low_registers, insn_high_registers;
17904 int usable_register_mask;
b25e998d 17905 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17906 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17907 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17908 bfd_byte *current_stub_contents = base_stub_contents;
17909
17910 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17911
17912 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17913 smaller than 8 registers load sequences that do not cause the
17914 hardware issue. */
17915 if (nb_registers <= 8)
17916 {
17917 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17918 current_stub_contents =
17919 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17920 initial_insn);
17921
17922 /* B initial_insn_addr+4. */
17923 if (!restore_pc)
17924 current_stub_contents =
17925 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17926 create_instruction_branch_absolute
82188b29 17927 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17928
17929 /* Fill the remaining of the stub with deterministic contents. */
17930 current_stub_contents =
17931 stm32l4xx_fill_stub_udf (htab, output_bfd,
17932 base_stub_contents, current_stub_contents,
17933 base_stub_contents +
17934 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17935
17936 return;
17937 }
17938
17939 /* - reg_list[13] == 0. */
17940 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17941
17942 /* - reg_list[14] & reg_list[15] != 1. */
17943 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17944
17945 /* - if (wback==1) reg_list[rn] == 0. */
17946 BFD_ASSERT (!wback || !restore_rn);
17947
17948 /* - nb_registers > 8. */
b25e998d 17949 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17950
17951 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17952
17953 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17954 - One with the 7 lowest registers (register mask 0x007F)
17955 This LDM will finally contain between 2 and 7 registers
17956 - One with the 7 highest registers (register mask 0xDF80)
17957 This ldm will finally contain between 2 and 7 registers. */
17958 insn_low_registers = insn_all_registers & 0x007F;
17959 insn_high_registers = insn_all_registers & 0xDF80;
17960
17961 /* A spare register may be needed during this veneer to temporarily
17962 handle the base register. This register will be restored with the
17963 last LDM operation.
17964 The usable register may be any general purpose register (that
17965 excludes PC, SP, LR : register mask is 0x1FFF). */
17966 usable_register_mask = 0x1FFF;
17967
17968 /* Generate the stub function. */
17969 if (wback)
17970 {
17971 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17972 current_stub_contents =
17973 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17974 create_instruction_ldmia
17975 (rn, /*wback=*/1, insn_low_registers));
17976
17977 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17978 current_stub_contents =
17979 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17980 create_instruction_ldmia
17981 (rn, /*wback=*/1, insn_high_registers));
17982 if (!restore_pc)
17983 {
17984 /* B initial_insn_addr+4. */
17985 current_stub_contents =
17986 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17987 create_instruction_branch_absolute
82188b29 17988 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17989 }
17990 }
17991 else /* if (!wback). */
17992 {
17993 ri = rn;
17994
17995 /* If Rn is not part of the high-register-list, move it there. */
17996 if (!(insn_high_registers & (1 << rn)))
17997 {
17998 /* Choose a Ri in the high-register-list that will be restored. */
17999 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18000
18001 /* MOV Ri, Rn. */
18002 current_stub_contents =
18003 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18004 create_instruction_mov (ri, rn));
18005 }
18006
18007 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18008 current_stub_contents =
18009 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18010 create_instruction_ldmia
18011 (ri, /*wback=*/1, insn_low_registers));
18012
18013 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18014 current_stub_contents =
18015 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18016 create_instruction_ldmia
18017 (ri, /*wback=*/0, insn_high_registers));
18018
18019 if (!restore_pc)
18020 {
18021 /* B initial_insn_addr+4. */
18022 current_stub_contents =
18023 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18024 create_instruction_branch_absolute
82188b29 18025 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18026 }
18027 }
18028
18029 /* Fill the remaining of the stub with deterministic contents. */
18030 current_stub_contents =
18031 stm32l4xx_fill_stub_udf (htab, output_bfd,
18032 base_stub_contents, current_stub_contents,
18033 base_stub_contents +
18034 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18035}
18036
18037static void
18038stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18039 bfd * output_bfd,
18040 const insn32 initial_insn,
18041 const bfd_byte *const initial_insn_addr,
18042 bfd_byte *const base_stub_contents)
18043{
18044 int wback = (initial_insn & 0x00200000) >> 21;
18045 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18046 int insn_all_registers = initial_insn & 0x0000ffff;
18047 int insn_low_registers, insn_high_registers;
18048 int usable_register_mask;
18049 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18050 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18051 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18052 bfd_byte *current_stub_contents = base_stub_contents;
18053
18054 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18055
18056 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18057 smaller than 8 registers load sequences that do not cause the
18058 hardware issue. */
18059 if (nb_registers <= 8)
18060 {
18061 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18062 current_stub_contents =
18063 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18064 initial_insn);
18065
18066 /* B initial_insn_addr+4. */
18067 current_stub_contents =
18068 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18069 create_instruction_branch_absolute
82188b29 18070 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18071
18072 /* Fill the remaining of the stub with deterministic contents. */
18073 current_stub_contents =
18074 stm32l4xx_fill_stub_udf (htab, output_bfd,
18075 base_stub_contents, current_stub_contents,
18076 base_stub_contents +
18077 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18078
18079 return;
18080 }
18081
18082 /* - reg_list[13] == 0. */
18083 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18084
18085 /* - reg_list[14] & reg_list[15] != 1. */
18086 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18087
18088 /* - if (wback==1) reg_list[rn] == 0. */
18089 BFD_ASSERT (!wback || !restore_rn);
18090
18091 /* - nb_registers > 8. */
b25e998d 18092 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18093
18094 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18095
18096 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18097 - One with the 7 lowest registers (register mask 0x007F)
18098 This LDM will finally contain between 2 and 7 registers
18099 - One with the 7 highest registers (register mask 0xDF80)
18100 This ldm will finally contain between 2 and 7 registers. */
18101 insn_low_registers = insn_all_registers & 0x007F;
18102 insn_high_registers = insn_all_registers & 0xDF80;
18103
18104 /* A spare register may be needed during this veneer to temporarily
18105 handle the base register. This register will be restored with
18106 the last LDM operation.
18107 The usable register may be any general purpose register (that excludes
18108 PC, SP, LR : register mask is 0x1FFF). */
18109 usable_register_mask = 0x1FFF;
18110
18111 /* Generate the stub function. */
18112 if (!wback && !restore_pc && !restore_rn)
18113 {
18114 /* Choose a Ri in the low-register-list that will be restored. */
18115 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18116
18117 /* MOV Ri, Rn. */
18118 current_stub_contents =
18119 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18120 create_instruction_mov (ri, rn));
18121
18122 /* LDMDB Ri!, {R-high-register-list}. */
18123 current_stub_contents =
18124 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18125 create_instruction_ldmdb
18126 (ri, /*wback=*/1, insn_high_registers));
18127
18128 /* LDMDB Ri, {R-low-register-list}. */
18129 current_stub_contents =
18130 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18131 create_instruction_ldmdb
18132 (ri, /*wback=*/0, insn_low_registers));
18133
18134 /* B initial_insn_addr+4. */
18135 current_stub_contents =
18136 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18137 create_instruction_branch_absolute
82188b29 18138 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18139 }
18140 else if (wback && !restore_pc && !restore_rn)
18141 {
18142 /* LDMDB Rn!, {R-high-register-list}. */
18143 current_stub_contents =
18144 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18145 create_instruction_ldmdb
18146 (rn, /*wback=*/1, insn_high_registers));
18147
18148 /* LDMDB Rn!, {R-low-register-list}. */
18149 current_stub_contents =
18150 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18151 create_instruction_ldmdb
18152 (rn, /*wback=*/1, insn_low_registers));
18153
18154 /* B initial_insn_addr+4. */
18155 current_stub_contents =
18156 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18157 create_instruction_branch_absolute
82188b29 18158 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18159 }
18160 else if (!wback && restore_pc && !restore_rn)
18161 {
18162 /* Choose a Ri in the high-register-list that will be restored. */
18163 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18164
18165 /* SUB Ri, Rn, #(4*nb_registers). */
18166 current_stub_contents =
18167 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18168 create_instruction_sub (ri, rn, (4 * nb_registers)));
18169
18170 /* LDMIA Ri!, {R-low-register-list}. */
18171 current_stub_contents =
18172 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18173 create_instruction_ldmia
18174 (ri, /*wback=*/1, insn_low_registers));
18175
18176 /* LDMIA Ri, {R-high-register-list}. */
18177 current_stub_contents =
18178 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18179 create_instruction_ldmia
18180 (ri, /*wback=*/0, insn_high_registers));
18181 }
18182 else if (wback && restore_pc && !restore_rn)
18183 {
18184 /* Choose a Ri in the high-register-list that will be restored. */
18185 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18186
18187 /* SUB Rn, Rn, #(4*nb_registers) */
18188 current_stub_contents =
18189 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18190 create_instruction_sub (rn, rn, (4 * nb_registers)));
18191
18192 /* MOV Ri, Rn. */
18193 current_stub_contents =
18194 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18195 create_instruction_mov (ri, rn));
18196
18197 /* LDMIA Ri!, {R-low-register-list}. */
18198 current_stub_contents =
18199 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18200 create_instruction_ldmia
18201 (ri, /*wback=*/1, insn_low_registers));
18202
18203 /* LDMIA Ri, {R-high-register-list}. */
18204 current_stub_contents =
18205 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18206 create_instruction_ldmia
18207 (ri, /*wback=*/0, insn_high_registers));
18208 }
18209 else if (!wback && !restore_pc && restore_rn)
18210 {
18211 ri = rn;
18212 if (!(insn_low_registers & (1 << rn)))
18213 {
18214 /* Choose a Ri in the low-register-list that will be restored. */
18215 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18216
18217 /* MOV Ri, Rn. */
18218 current_stub_contents =
18219 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18220 create_instruction_mov (ri, rn));
18221 }
18222
18223 /* LDMDB Ri!, {R-high-register-list}. */
18224 current_stub_contents =
18225 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18226 create_instruction_ldmdb
18227 (ri, /*wback=*/1, insn_high_registers));
18228
18229 /* LDMDB Ri, {R-low-register-list}. */
18230 current_stub_contents =
18231 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18232 create_instruction_ldmdb
18233 (ri, /*wback=*/0, insn_low_registers));
18234
18235 /* B initial_insn_addr+4. */
18236 current_stub_contents =
18237 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18238 create_instruction_branch_absolute
82188b29 18239 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18240 }
18241 else if (!wback && restore_pc && restore_rn)
18242 {
18243 ri = rn;
18244 if (!(insn_high_registers & (1 << rn)))
18245 {
18246 /* Choose a Ri in the high-register-list that will be restored. */
18247 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18248 }
18249
18250 /* SUB Ri, Rn, #(4*nb_registers). */
18251 current_stub_contents =
18252 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18253 create_instruction_sub (ri, rn, (4 * nb_registers)));
18254
18255 /* LDMIA Ri!, {R-low-register-list}. */
18256 current_stub_contents =
18257 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18258 create_instruction_ldmia
18259 (ri, /*wback=*/1, insn_low_registers));
18260
18261 /* LDMIA Ri, {R-high-register-list}. */
18262 current_stub_contents =
18263 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18264 create_instruction_ldmia
18265 (ri, /*wback=*/0, insn_high_registers));
18266 }
18267 else if (wback && restore_rn)
18268 {
18269 /* The assembler should not have accepted to encode this. */
18270 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18271 "undefined behavior.\n");
18272 }
18273
18274 /* Fill the remaining of the stub with deterministic contents. */
18275 current_stub_contents =
18276 stm32l4xx_fill_stub_udf (htab, output_bfd,
18277 base_stub_contents, current_stub_contents,
18278 base_stub_contents +
18279 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18280
18281}
18282
18283static void
18284stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18285 bfd * output_bfd,
18286 const insn32 initial_insn,
18287 const bfd_byte *const initial_insn_addr,
18288 bfd_byte *const base_stub_contents)
18289{
9239bbd3 18290 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18291 bfd_byte *current_stub_contents = base_stub_contents;
18292
18293 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18294
18295 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18296 smaller than 8 words load sequences that do not cause the
a504d23a 18297 hardware issue. */
9239bbd3 18298 if (num_words <= 8)
a504d23a
LA		 18299 {
18300 /* Untouched instruction. */
18301 current_stub_contents =
18302 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18303 initial_insn);
18304
18305 /* B initial_insn_addr+4. */
18306 current_stub_contents =
18307 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18308 create_instruction_branch_absolute
82188b29 18309 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18310 }
18311 else
18312 {
9eaff861 18313 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18314 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18315 bfd_boolean is_ia_nobang = /* (IA without !). */
18316 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18317 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18318 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18319 bfd_boolean is_db_bang = /* (DB with !). */
18320 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18321 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18322 /* d = UInt (Vd:D);. */
9239bbd3 18323 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18324 | (((unsigned int)initial_insn << 9) >> 31);
18325
9239bbd3
CM		 18326 /* Compute the number of 8-words chunks needed to split. */
18327 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18328 int chunk;
18329
18330 /* The test coverage has been done assuming the following
18331 hypothesis that exactly one of the previous is_ predicates is
18332 true. */
9239bbd3
CM		 18333 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18334 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18335
9239bbd3 18336 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18337 cases, then we emit the adjustments:
18338
18339 vldm rx, {...}
18340 -> vldm rx!, {8_words_or_less} for each needed 8_word
18341 -> sub rx, rx, #size (list)
18342
18343 vldm rx!, {...}
18344 -> vldm rx!, {8_words_or_less} for each needed 8_word
18345 This also handles vpop instruction (when rx is sp)
18346
18347 vldmd rx!, {...}
18348 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18349 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18350 {
9239bbd3
CM		 18351 bfd_vma new_insn = 0;
18352
a504d23a
LA		 18353 if (is_ia_nobang || is_ia_bang)
18354 {
9239bbd3
CM		 18355 new_insn = create_instruction_vldmia
18356 (base_reg,
18357 is_dp,
18358 /*wback= . */1,
18359 chunks - (chunk + 1) ?
18360 8 : num_words - chunk * 8,
18361 first_reg + chunk * 8);
a504d23a
LA		 18362 }
18363 else if (is_db_bang)
18364 {
9239bbd3
CM		 18365 new_insn = create_instruction_vldmdb
18366 (base_reg,
18367 is_dp,
18368 chunks - (chunk + 1) ?
18369 8 : num_words - chunk * 8,
18370 first_reg + chunk * 8);
a504d23a 18371 }
9239bbd3
CM		 18372
18373 if (new_insn)
18374 current_stub_contents =
18375 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18376 new_insn);
a504d23a
LA		 18377 }
18378
18379 /* Only this case requires the base register compensation
18380 subtract. */
18381 if (is_ia_nobang)
18382 {
18383 current_stub_contents =
18384 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18385 create_instruction_sub
9239bbd3 18386 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18387 }
18388
18389 /* B initial_insn_addr+4. */
18390 current_stub_contents =
18391 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18392 create_instruction_branch_absolute
82188b29 18393 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18394 }
18395
18396 /* Fill the remaining of the stub with deterministic contents. */
18397 current_stub_contents =
18398 stm32l4xx_fill_stub_udf (htab, output_bfd,
18399 base_stub_contents, current_stub_contents,
18400 base_stub_contents +
18401 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18402}
18403
18404static void
18405stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18406 bfd * output_bfd,
18407 const insn32 wrong_insn,
18408 const bfd_byte *const wrong_insn_addr,
18409 bfd_byte *const stub_contents)
18410{
18411 if (is_thumb2_ldmia (wrong_insn))
18412 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18413 wrong_insn, wrong_insn_addr,
18414 stub_contents);
18415 else if (is_thumb2_ldmdb (wrong_insn))
18416 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18417 wrong_insn, wrong_insn_addr,
18418 stub_contents);
18419 else if (is_thumb2_vldm (wrong_insn))
18420 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18421 wrong_insn, wrong_insn_addr,
18422 stub_contents);
18423}
18424
18425/* End of stm32l4xx work-around. */
18426
18427
e489d0ae
PB		 18428/* Do code byteswapping. Return FALSE afterwards so that the section is
18429 written out as normal. */
18430
18431static bfd_boolean
c7b8f16e 18432elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18433 struct bfd_link_info *link_info,
18434 asection *sec,
e489d0ae
PB		 18435 bfd_byte *contents)
18436{
48229727 18437 unsigned int mapcount, errcount;
8e3de13a 18438 _arm_elf_section_data *arm_data;
c7b8f16e 18439 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18440 elf32_arm_section_map *map;
c7b8f16e 18441 elf32_vfp11_erratum_list *errnode;
a504d23a 18442 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18443 bfd_vma ptr;
18444 bfd_vma end;
c7b8f16e 18445 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18446 bfd_byte tmp;
48229727 18447 unsigned int i;
57e8b36a 18448
4dfe6ac6
NC		 18449 if (globals == NULL)
18450 return FALSE;
18451
8e3de13a
NC		 18452 /* If this section has not been allocated an _arm_elf_section_data
18453 structure then we cannot record anything. */
18454 arm_data = get_arm_elf_section_data (sec);
18455 if (arm_data == NULL)
18456 return FALSE;
18457
18458 mapcount = arm_data->mapcount;
18459 map = arm_data->map;
c7b8f16e
JB		 18460 errcount = arm_data->erratumcount;
18461
18462 if (errcount != 0)
18463 {
18464 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18465
18466 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18467 errnode = errnode->next)
18468 {
18469 bfd_vma target = errnode->vma - offset;
18470
18471 switch (errnode->type)
18472 {
18473 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18474 {
18475 bfd_vma branch_to_veneer;
18476 /* Original condition code of instruction, plus bit mask for
18477 ARM B instruction. */
18478 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18479 | 0x0a000000;
c7b8f16e
JB		 18480
18481 /* The instruction is before the label. */
91d6fa6a 18482 target -= 4;
c7b8f16e
JB		 18483
18484 /* Above offset included in -4 below. */
18485 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18486 - errnode->vma - 4;
c7b8f16e
JB		 18487
18488 if ((signed) branch_to_veneer < -(1 << 25)
18489 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18490 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18491 "range"), output_bfd);
c7b8f16e 18492
99059e56
RM		 18493 insn |= (branch_to_veneer >> 2) & 0xffffff;
18494 contents[endianflip ^ target] = insn & 0xff;
18495 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18496 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18497 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18498 }
18499 break;
c7b8f16e
JB		 18500
18501 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18502 {
18503 bfd_vma branch_from_veneer;
18504 unsigned int insn;
c7b8f16e 18505
99059e56
RM		 18506 /* Take size of veneer into account. */
18507 branch_from_veneer = errnode->u.v.branch->vma
18508 - errnode->vma - 12;
c7b8f16e
JB		 18509
18510 if ((signed) branch_from_veneer < -(1 << 25)
18511 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18512 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18513 "range"), output_bfd);
c7b8f16e 18514
99059e56
RM		 18515 /* Original instruction. */
18516 insn = errnode->u.v.branch->u.b.vfp_insn;
18517 contents[endianflip ^ target] = insn & 0xff;
18518 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18519 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18520 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18521
18522 /* Branch back to insn after original insn. */
18523 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18524 contents[endianflip ^ (target + 4)] = insn & 0xff;
18525 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18526 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18527 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18528 }
18529 break;
c7b8f16e 18530
99059e56
RM		 18531 default:
18532 abort ();
18533 }
18534 }
c7b8f16e 18535 }
e489d0ae 18536
a504d23a
LA		 18537 if (arm_data->stm32l4xx_erratumcount != 0)
18538 {
18539 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18540 stm32l4xx_errnode != 0;
18541 stm32l4xx_errnode = stm32l4xx_errnode->next)
18542 {
18543 bfd_vma target = stm32l4xx_errnode->vma - offset;
18544
18545 switch (stm32l4xx_errnode->type)
18546 {
18547 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18548 {
18549 unsigned int insn;
18550 bfd_vma branch_to_veneer =
18551 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18552
18553 if ((signed) branch_to_veneer < -(1 << 24)
18554 || (signed) branch_to_veneer >= (1 << 24))
18555 {
18556 bfd_vma out_of_range =
18557 ((signed) branch_to_veneer < -(1 << 24)) ?
18558 - branch_to_veneer - (1 << 24) :
18559 ((signed) branch_to_veneer >= (1 << 24)) ?
18560 branch_to_veneer - (1 << 24) : 0;
18561
4eca0228 18562 _bfd_error_handler
a504d23a 18563 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18564 "Jump out of range by %ld bytes. "
a504d23a
LA		 18565 "Cannot encode branch instruction. "),
18566 output_bfd,
eee926f2 18567 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18568 out_of_range);
18569 continue;
18570 }
18571
18572 insn = create_instruction_branch_absolute
82188b29 18573 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18574
18575 /* The instruction is before the label. */
18576 target -= 4;
18577
18578 put_thumb2_insn (globals, output_bfd,
18579 (bfd_vma) insn, contents + target);
18580 }
18581 break;
18582
18583 case STM32L4XX_ERRATUM_VENEER:
18584 {
82188b29
NC		 18585 bfd_byte * veneer;
18586 bfd_byte * veneer_r;
a504d23a
LA		 18587 unsigned int insn;
18588
82188b29
NC		 18589 veneer = contents + target;
18590 veneer_r = veneer
18591 + stm32l4xx_errnode->u.b.veneer->vma
18592 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18593
18594 if ((signed) (veneer_r - veneer -
18595 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18596 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18597 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18598 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18599 || (signed) (veneer_r - veneer) >= (1 << 24))
18600 {
4eca0228
AM		 18601 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18602 "veneer."), output_bfd);
a504d23a
LA		 18603 continue;
18604 }
18605
18606 /* Original instruction. */
18607 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18608
18609 stm32l4xx_create_replacing_stub
18610 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18611 }
18612 break;
18613
18614 default:
18615 abort ();
18616 }
18617 }
18618 }
18619
2468f9c9
PB		 18620 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18621 {
18622 arm_unwind_table_edit *edit_node
99059e56 18623 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18624 /* Now, sec->size is the size of the section we will write. The original
99059e56 18625 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18626 markers) was sec->rawsize. (This isn't the case if we perform no
18627 edits, then rawsize will be zero and we should use size). */
21d799b5 18628 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18629 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18630 unsigned int in_index, out_index;
18631 bfd_vma add_to_offsets = 0;
18632
18633 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18634 {
2468f9c9
PB		 18635 if (edit_node)
18636 {
18637 unsigned int edit_index = edit_node->index;
b38cadfb 18638
2468f9c9 18639 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18640 {
2468f9c9
PB		 18641 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18642 contents + in_index * 8, add_to_offsets);
18643 out_index++;
18644 in_index++;
18645 }
18646 else if (in_index == edit_index
18647 || (in_index * 8 >= input_size
18648 && edit_index == UINT_MAX))
99059e56 18649 {
2468f9c9
PB		 18650 switch (edit_node->type)
18651 {
18652 case DELETE_EXIDX_ENTRY:
18653 in_index++;
18654 add_to_offsets += 8;
18655 break;
b38cadfb 18656
2468f9c9
PB		 18657 case INSERT_EXIDX_CANTUNWIND_AT_END:
18658 {
99059e56 18659 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18660 bfd_vma text_offset = text_sec->output_section->vma
18661 + text_sec->output_offset
18662 + text_sec->size;
18663 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18664 unsigned long prel31_offset;
2468f9c9
PB		 18665
18666 /* Note: this is meant to be equivalent to an
18667 R_ARM_PREL31 relocation. These synthetic
18668 EXIDX_CANTUNWIND markers are not relocated by the
18669 usual BFD method. */
18670 prel31_offset = (text_offset - exidx_offset)
18671 & 0x7ffffffful;
491d01d3
YU		 18672 if (bfd_link_relocatable (link_info))
18673 {
18674 /* Here relocation for new EXIDX_CANTUNWIND is
18675 created, so there is no need to
18676 adjust offset by hand. */
18677 prel31_offset = text_sec->output_offset
18678 + text_sec->size;
491d01d3 18679 }
2468f9c9
PB		 18680
18681 /* First address we can't unwind. */
18682 bfd_put_32 (output_bfd, prel31_offset,
18683 &edited_contents[out_index * 8]);
18684
18685 /* Code for EXIDX_CANTUNWIND. */
18686 bfd_put_32 (output_bfd, 0x1,
18687 &edited_contents[out_index * 8 + 4]);
18688
18689 out_index++;
18690 add_to_offsets -= 8;
18691 }
18692 break;
18693 }
b38cadfb 18694
2468f9c9
PB		 18695 edit_node = edit_node->next;
18696 }
18697 }
18698 else
18699 {
18700 /* No more edits, copy remaining entries verbatim. */
18701 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18702 contents + in_index * 8, add_to_offsets);
18703 out_index++;
18704 in_index++;
18705 }
18706 }
18707
18708 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18709 bfd_set_section_contents (output_bfd, sec->output_section,
18710 edited_contents,
18711 (file_ptr) sec->output_offset, sec->size);
18712
18713 return TRUE;
18714 }
18715
48229727
JB		 18716 /* Fix code to point to Cortex-A8 erratum stubs. */
18717 if (globals->fix_cortex_a8)
18718 {
18719 struct a8_branch_to_stub_data data;
18720
18721 data.writing_section = sec;
18722 data.contents = contents;
18723
a504d23a
LA		 18724 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18725 & data);
48229727
JB		 18726 }
18727
e489d0ae
PB		 18728 if (mapcount == 0)
18729 return FALSE;
18730
c7b8f16e 18731 if (globals->byteswap_code)
e489d0ae 18732 {
c7b8f16e 18733 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18734
c7b8f16e
JB		 18735 ptr = map[0].vma;
18736 for (i = 0; i < mapcount; i++)
99059e56
RM		 18737 {
18738 if (i == mapcount - 1)
c7b8f16e 18739 end = sec->size;
99059e56
RM		 18740 else
18741 end = map[i + 1].vma;
e489d0ae 18742
99059e56 18743 switch (map[i].type)
e489d0ae 18744 {
c7b8f16e
JB		 18745 case 'a':
18746 /* Byte swap code words. */
18747 while (ptr + 3 < end)
99059e56
RM		 18748 {
18749 tmp = contents[ptr];
18750 contents[ptr] = contents[ptr + 3];
18751 contents[ptr + 3] = tmp;
18752 tmp = contents[ptr + 1];
18753 contents[ptr + 1] = contents[ptr + 2];
18754 contents[ptr + 2] = tmp;
18755 ptr += 4;
18756 }
c7b8f16e 18757 break;
e489d0ae 18758
c7b8f16e
JB		 18759 case 't':
18760 /* Byte swap code halfwords. */
18761 while (ptr + 1 < end)
99059e56
RM		 18762 {
18763 tmp = contents[ptr];
18764 contents[ptr] = contents[ptr + 1];
18765 contents[ptr + 1] = tmp;
18766 ptr += 2;
18767 }
c7b8f16e
JB		 18768 break;
18769
18770 case 'd':
18771 /* Leave data alone. */
18772 break;
18773 }
99059e56
RM		 18774 ptr = end;
18775 }
e489d0ae 18776 }
8e3de13a 18777
93204d3a 18778 free (map);
47b2e99c 18779 arm_data->mapcount = -1;
c7b8f16e 18780 arm_data->mapsize = 0;
8e3de13a 18781 arm_data->map = NULL;
8e3de13a 18782
e489d0ae
PB		 18783 return FALSE;
18784}
18785
0beaef2b
PB		 18786/* Mangle thumb function symbols as we read them in. */
18787
8384fb8f 18788static bfd_boolean
0beaef2b
PB		 18789elf32_arm_swap_symbol_in (bfd * abfd,
18790 const void *psrc,
18791 const void *pshn,
18792 Elf_Internal_Sym *dst)
18793{
4ba2ef8f
TP		 18794 Elf_Internal_Shdr *symtab_hdr;
18795 const char *name = NULL;
18796
8384fb8f
AM		 18797 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18798 return FALSE;
39d911fc 18799 dst->st_target_internal = 0;
0beaef2b
PB		 18800
18801 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18802 the address. */
63e1a0fc
PB		 18803 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18804 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18805 {
63e1a0fc
PB		 18806 if (dst->st_value & 1)
18807 {
18808 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18809 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18810 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18811 }
18812 else
39d911fc 18813 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18814 }
18815 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18816 {
18817 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18818 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18819 }
35fc36a8 18820 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18821 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18822 else
39d911fc 18823 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18824
4ba2ef8f
TP		 18825 /* Mark CMSE special symbols. */
18826 symtab_hdr = & elf_symtab_hdr (abfd);
18827 if (symtab_hdr->sh_size)
18828 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18829 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18830 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18831
8384fb8f 18832 return TRUE;
0beaef2b
PB		 18833}
18834
18835
18836/* Mangle thumb function symbols as we write them out. */
18837
18838static void
18839elf32_arm_swap_symbol_out (bfd *abfd,
18840 const Elf_Internal_Sym *src,
18841 void *cdst,
18842 void *shndx)
18843{
18844 Elf_Internal_Sym newsym;
18845
18846 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18847 of the address set, as per the new EABI. We do this unconditionally
18848 because objcopy does not set the elf header flags until after
18849 it writes out the symbol table. */
39d911fc 18850 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18851 {
18852 newsym = *src;
34e77a92
RS		 18853 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18854 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18855 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18856 {
18857 /* Do this only for defined symbols. At link type, the static
18858 linker will simulate the work of dynamic linker of resolving
18859 symbols and will carry over the thumbness of found symbols to
18860 the output symbol table. It's not clear how it happens, but
18861 the thumbness of undefined symbols can well be different at
18862 runtime, and writing '1' for them will be confusing for users
18863 and possibly for dynamic linker itself.
18864 */
18865 newsym.st_value |= 1;
18866 }
906e58ca 18867
0beaef2b
PB		 18868 src = &newsym;
18869 }
18870 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18871}
18872
b294bdf8
MM		 18873/* Add the PT_ARM_EXIDX program header. */
18874
18875static bfd_boolean
906e58ca 18876elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18877 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18878{
18879 struct elf_segment_map *m;
18880 asection *sec;
18881
18882 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18883 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18884 {
18885 /* If there is already a PT_ARM_EXIDX header, then we do not
18886 want to add another one. This situation arises when running
18887 "strip"; the input binary already has the header. */
12bd6957 18888 m = elf_seg_map (abfd);
b294bdf8
MM		 18889 while (m && m->p_type != PT_ARM_EXIDX)
18890 m = m->next;
18891 if (!m)
18892 {
21d799b5 18893 m = (struct elf_segment_map *)
99059e56 18894 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18895 if (m == NULL)
18896 return FALSE;
18897 m->p_type = PT_ARM_EXIDX;
18898 m->count = 1;
18899 m->sections[0] = sec;
18900
12bd6957
AM		 18901 m->next = elf_seg_map (abfd);
18902 elf_seg_map (abfd) = m;
b294bdf8
MM		 18903 }
18904 }
18905
18906 return TRUE;
18907}
18908
18909/* We may add a PT_ARM_EXIDX program header. */
18910
18911static int
a6b96beb
AM		 18912elf32_arm_additional_program_headers (bfd *abfd,
18913 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18914{
18915 asection *sec;
18916
18917 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18918 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18919 return 1;
18920 else
18921 return 0;
18922}
18923
34e77a92
RS		 18924/* Hook called by the linker routine which adds symbols from an object
18925 file. */
18926
18927static bfd_boolean
18928elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18929 Elf_Internal_Sym *sym, const char **namep,
18930 flagword *flagsp, asection **secp, bfd_vma *valp)
18931{
a43942db 18932 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18933 && (abfd->flags & DYNAMIC) == 0
18934 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18935 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18936
c792917c
NC		 18937 if (elf32_arm_hash_table (info) == NULL)
18938 return FALSE;
18939
34e77a92
RS		 18940 if (elf32_arm_hash_table (info)->vxworks_p
18941 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18942 flagsp, secp, valp))
18943 return FALSE;
18944
18945 return TRUE;
18946}
18947
0beaef2b 18948/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18949const struct elf_size_info elf32_arm_size_info =
18950{
0beaef2b
PB		 18951 sizeof (Elf32_External_Ehdr),
18952 sizeof (Elf32_External_Phdr),
18953 sizeof (Elf32_External_Shdr),
18954 sizeof (Elf32_External_Rel),
18955 sizeof (Elf32_External_Rela),
18956 sizeof (Elf32_External_Sym),
18957 sizeof (Elf32_External_Dyn),
18958 sizeof (Elf_External_Note),
18959 4,
18960 1,
18961 32, 2,
18962 ELFCLASS32, EV_CURRENT,
18963 bfd_elf32_write_out_phdrs,
18964 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18965 bfd_elf32_checksum_contents,
0beaef2b
PB		 18966 bfd_elf32_write_relocs,
18967 elf32_arm_swap_symbol_in,
18968 elf32_arm_swap_symbol_out,
18969 bfd_elf32_slurp_reloc_table,
18970 bfd_elf32_slurp_symbol_table,
18971 bfd_elf32_swap_dyn_in,
18972 bfd_elf32_swap_dyn_out,
18973 bfd_elf32_swap_reloc_in,
18974 bfd_elf32_swap_reloc_out,
18975 bfd_elf32_swap_reloca_in,
18976 bfd_elf32_swap_reloca_out
18977};
18978
685e70ae
VK		 18979static bfd_vma
18980read_code32 (const bfd *abfd, const bfd_byte *addr)
18981{
18982 /* V7 BE8 code is always little endian. */
18983 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18984 return bfd_getl32 (addr);
18985
18986 return bfd_get_32 (abfd, addr);
18987}
18988
18989static bfd_vma
18990read_code16 (const bfd *abfd, const bfd_byte *addr)
18991{
18992 /* V7 BE8 code is always little endian. */
18993 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18994 return bfd_getl16 (addr);
18995
18996 return bfd_get_16 (abfd, addr);
18997}
18998
6a631e86
YG		 18999/* Return size of plt0 entry starting at ADDR
19000 or (bfd_vma) -1 if size can not be determined. */
19001
19002static bfd_vma
19003elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19004{
19005 bfd_vma first_word;
19006 bfd_vma plt0_size;
19007
685e70ae 19008 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19009
19010 if (first_word == elf32_arm_plt0_entry[0])
19011 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19012 else if (first_word == elf32_thumb2_plt0_entry[0])
19013 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19014 else
19015 /* We don't yet handle this PLT format. */
19016 return (bfd_vma) -1;
19017
19018 return plt0_size;
19019}
19020
19021/* Return size of plt entry starting at offset OFFSET
19022 of plt section located at address START
19023 or (bfd_vma) -1 if size can not be determined. */
19024
19025static bfd_vma
19026elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19027{
19028 bfd_vma first_insn;
19029 bfd_vma plt_size = 0;
19030 const bfd_byte *addr = start + offset;
19031
19032 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19033 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19034 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19035
19036 /* Respect Thumb stub if necessary. */
685e70ae 19037 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19038 {
19039 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19040 }
19041
19042 /* Strip immediate from first add. */
685e70ae 19043 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19044
19045#ifdef FOUR_WORD_PLT
19046 if (first_insn == elf32_arm_plt_entry[0])
19047 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19048#else
19049 if (first_insn == elf32_arm_plt_entry_long[0])
19050 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19051 else if (first_insn == elf32_arm_plt_entry_short[0])
19052 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19053#endif
19054 else
19055 /* We don't yet handle this PLT format. */
19056 return (bfd_vma) -1;
19057
19058 return plt_size;
19059}
19060
19061/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19062
19063static long
19064elf32_arm_get_synthetic_symtab (bfd *abfd,
19065 long symcount ATTRIBUTE_UNUSED,
19066 asymbol **syms ATTRIBUTE_UNUSED,
19067 long dynsymcount,
19068 asymbol **dynsyms,
19069 asymbol **ret)
19070{
19071 asection *relplt;
19072 asymbol *s;
19073 arelent *p;
19074 long count, i, n;
19075 size_t size;
19076 Elf_Internal_Shdr *hdr;
19077 char *names;
19078 asection *plt;
19079 bfd_vma offset;
19080 bfd_byte *data;
19081
19082 *ret = NULL;
19083
19084 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19085 return 0;
19086
19087 if (dynsymcount <= 0)
19088 return 0;
19089
19090 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19091 if (relplt == NULL)
19092 return 0;
19093
19094 hdr = &elf_section_data (relplt)->this_hdr;
19095 if (hdr->sh_link != elf_dynsymtab (abfd)
19096 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19097 return 0;
19098
19099 plt = bfd_get_section_by_name (abfd, ".plt");
19100 if (plt == NULL)
19101 return 0;
19102
19103 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19104 return -1;
19105
19106 data = plt->contents;
19107 if (data == NULL)
19108 {
19109 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19110 return -1;
19111 bfd_cache_section_contents((asection *) plt, data);
19112 }
19113
19114 count = relplt->size / hdr->sh_entsize;
19115 size = count * sizeof (asymbol);
19116 p = relplt->relocation;
19117 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19118 {
19119 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19120 if (p->addend != 0)
19121 size += sizeof ("+0x") - 1 + 8;
19122 }
19123
19124 s = *ret = (asymbol *) bfd_malloc (size);
19125 if (s == NULL)
19126 return -1;
19127
19128 offset = elf32_arm_plt0_size (abfd, data);
19129 if (offset == (bfd_vma) -1)
19130 return -1;
19131
19132 names = (char *) (s + count);
19133 p = relplt->relocation;
19134 n = 0;
19135 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19136 {
19137 size_t len;
19138
19139 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19140 if (plt_size == (bfd_vma) -1)
19141 break;
19142
19143 *s = **p->sym_ptr_ptr;
19144 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19145 we are defining a symbol, ensure one of them is set. */
19146 if ((s->flags & BSF_LOCAL) == 0)
19147 s->flags |= BSF_GLOBAL;
19148 s->flags |= BSF_SYNTHETIC;
19149 s->section = plt;
19150 s->value = offset;
19151 s->name = names;
19152 s->udata.p = NULL;
19153 len = strlen ((*p->sym_ptr_ptr)->name);
19154 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19155 names += len;
19156 if (p->addend != 0)
19157 {
19158 char buf[30], *a;
19159
19160 memcpy (names, "+0x", sizeof ("+0x") - 1);
19161 names += sizeof ("+0x") - 1;
19162 bfd_sprintf_vma (abfd, buf, p->addend);
19163 for (a = buf; *a == '0'; ++a)
19164 ;
19165 len = strlen (a);
19166 memcpy (names, a, len);
19167 names += len;
19168 }
19169 memcpy (names, "@plt", sizeof ("@plt"));
19170 names += sizeof ("@plt");
19171 ++s, ++n;
19172 offset += plt_size;
19173 }
19174
19175 return n;
19176}
19177
ac4c9b04
MG		 19178static bfd_boolean
19179elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19180{
f0728ee3
AV		 19181 if (hdr->sh_flags & SHF_ARM_PURECODE)
19182 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19183 return TRUE;
19184}
19185
19186static flagword
19187elf32_arm_lookup_section_flags (char *flag_name)
19188{
f0728ee3
AV		 19189 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19190 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19191
19192 return SEC_NO_FLAGS;
19193}
19194
491d01d3
YU		 19195static unsigned int
19196elf32_arm_count_additional_relocs (asection *sec)
19197{
19198 struct _arm_elf_section_data *arm_data;
19199 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19200
6342be70 19201 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19202}
19203
5522f910 19204/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19205 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19206 FALSE otherwise. ISECTION is the best guess matching section from the
19207 input bfd IBFD, but it might be NULL. */
19208
19209static bfd_boolean
19210elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19211 bfd *obfd ATTRIBUTE_UNUSED,
19212 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19213 Elf_Internal_Shdr *osection)
19214{
19215 switch (osection->sh_type)
19216 {
19217 case SHT_ARM_EXIDX:
19218 {
19219 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19220 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19221 unsigned i = 0;
19222
19223 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19224 osection->sh_info = 0;
19225
19226 /* The sh_link field must be set to the text section associated with
19227 this index section. Unfortunately the ARM EHABI does not specify
19228 exactly how to determine this association. Our caller does try
19229 to match up OSECTION with its corresponding input section however
19230 so that is a good first guess. */
19231 if (isection != NULL
19232 && osection->bfd_section != NULL
19233 && isection->bfd_section != NULL
19234 && isection->bfd_section->output_section != NULL
19235 && isection->bfd_section->output_section == osection->bfd_section
19236 && iheaders != NULL
19237 && isection->sh_link > 0
19238 && isection->sh_link < elf_numsections (ibfd)
19239 && iheaders[isection->sh_link]->bfd_section != NULL
19240 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19241 )
19242 {
19243 for (i = elf_numsections (obfd); i-- > 0;)
19244 if (oheaders[i]->bfd_section
19245 == iheaders[isection->sh_link]->bfd_section->output_section)
19246 break;
19247 }
9eaff861 19248
5522f910
NC		 19249 if (i == 0)
19250 {
19251 /* Failing that we have to find a matching section ourselves. If
19252 we had the output section name available we could compare that
19253 with input section names. Unfortunately we don't. So instead
19254 we use a simple heuristic and look for the nearest executable
19255 section before this one. */
19256 for (i = elf_numsections (obfd); i-- > 0;)
19257 if (oheaders[i] == osection)
19258 break;
19259 if (i == 0)
19260 break;
19261
19262 while (i-- > 0)
19263 if (oheaders[i]->sh_type == SHT_PROGBITS
19264 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19265 == (SHF_ALLOC | SHF_EXECINSTR))
19266 break;
19267 }
19268
19269 if (i)
19270 {
19271 osection->sh_link = i;
19272 /* If the text section was part of a group
19273 then the index section should be too. */
19274 if (oheaders[i]->sh_flags & SHF_GROUP)
19275 osection->sh_flags |= SHF_GROUP;
19276 return TRUE;
19277 }
19278 }
19279 break;
19280
19281 case SHT_ARM_PREEMPTMAP:
19282 osection->sh_flags = SHF_ALLOC;
19283 break;
19284
19285 case SHT_ARM_ATTRIBUTES:
19286 case SHT_ARM_DEBUGOVERLAY:
19287 case SHT_ARM_OVERLAYSECTION:
19288 default:
19289 break;
19290 }
19291
19292 return FALSE;
19293}
19294
d691934d
NC		 19295/* Returns TRUE if NAME is an ARM mapping symbol.
19296 Traditionally the symbols $a, $d and $t have been used.
19297 The ARM ELF standard also defines $x (for A64 code). It also allows a
19298 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19299 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19300 not support them here. $t.x indicates the start of ThumbEE instructions. */
19301
19302static bfd_boolean
19303is_arm_mapping_symbol (const char * name)
19304{
19305 return name != NULL /* Paranoia. */
19306 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19307 the mapping symbols could have acquired a prefix.
19308 We do not support this here, since such symbols no
19309 longer conform to the ARM ELF ABI. */
19310 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19311 && (name[2] == 0 || name[2] == '.');
19312 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19313 any characters that follow the period are legal characters for the body
19314 of a symbol's name. For now we just assume that this is the case. */
19315}
19316
fca2a38f
NC		 19317/* Make sure that mapping symbols in object files are not removed via the
19318 "strip --strip-unneeded" tool. These symbols are needed in order to
19319 correctly generate interworking veneers, and for byte swapping code
19320 regions. Once an object file has been linked, it is safe to remove the
19321 symbols as they will no longer be needed. */
19322
19323static void
19324elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19325{
19326 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19327 && sym->section != bfd_abs_section_ptr
d691934d 19328 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19329 sym->flags |= BSF_KEEP;
19330}
19331
5522f910
NC		 19332#undef elf_backend_copy_special_section_fields
19333#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19334
252b5132 19335#define ELF_ARCH bfd_arch_arm
ae95ffa6 19336#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19337#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19338#ifdef __QNXTARGET__
19339#define ELF_MAXPAGESIZE 0x1000
19340#else
7572ca89 19341#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19342#endif
b1342370 19343#define ELF_MINPAGESIZE 0x1000
24718e3b 19344#define ELF_COMMONPAGESIZE 0x1000
252b5132 19345
ba93b8ac
DJ		 19346#define bfd_elf32_mkobject elf32_arm_mkobject
19347
99e4ae17
AJ		 19348#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19349#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19350#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19351#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19352#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19353#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19354#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19355#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19356#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19357#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19358#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19359#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19360#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19361
19362#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19363#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19364#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19365#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19366#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19367#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19368#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19369#define elf_backend_write_section elf32_arm_write_section
252b5132 19370#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19371#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19372#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19373#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19374#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19375#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19376#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19377#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19378#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19379#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19380#define elf_backend_fake_sections elf32_arm_fake_sections
19381#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19382#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19383#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19384#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19385#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19386#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19387#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19388#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19389#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19390#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19391#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19392#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19393
19394#define elf_backend_can_refcount 1
19395#define elf_backend_can_gc_sections 1
19396#define elf_backend_plt_readonly 1
19397#define elf_backend_want_got_plt 1
19398#define elf_backend_want_plt_sym 0
5474d94f 19399#define elf_backend_want_dynrelro 1
906e58ca
NC		 19400#define elf_backend_may_use_rel_p 1
19401#define elf_backend_may_use_rela_p 0
4e7fd91e 19402#define elf_backend_default_use_rela_p 0
64f52338 19403#define elf_backend_dtrel_excludes_plt 1
252b5132 19404
04f7c78d 19405#define elf_backend_got_header_size 12
b68a20d6 19406#define elf_backend_extern_protected_data 1
04f7c78d 19407
906e58ca
NC		 19408#undef elf_backend_obj_attrs_vendor
19409#define elf_backend_obj_attrs_vendor "aeabi"
19410#undef elf_backend_obj_attrs_section
19411#define elf_backend_obj_attrs_section ".ARM.attributes"
19412#undef elf_backend_obj_attrs_arg_type
19413#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19414#undef elf_backend_obj_attrs_section_type
104d59d1 19415#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19416#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19417#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19418
5025eb7c 19419#undef elf_backend_section_flags
ac4c9b04 19420#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19421#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19422#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19423
252b5132 19424#include "elf32-target.h"
7f266840 19425
b38cadfb
NC		 19426/* Native Client targets. */
19427
19428#undef TARGET_LITTLE_SYM
6d00b590 19429#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19430#undef TARGET_LITTLE_NAME
19431#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19432#undef TARGET_BIG_SYM
6d00b590 19433#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19434#undef TARGET_BIG_NAME
19435#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19436
19437/* Like elf32_arm_link_hash_table_create -- but overrides
19438 appropriately for NaCl. */
19439
19440static struct bfd_link_hash_table *
19441elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19442{
19443 struct bfd_link_hash_table *ret;
19444
19445 ret = elf32_arm_link_hash_table_create (abfd);
19446 if (ret)
19447 {
19448 struct elf32_arm_link_hash_table *htab
19449 = (struct elf32_arm_link_hash_table *) ret;
19450
19451 htab->nacl_p = 1;
19452
19453 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19454 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19455 }
19456 return ret;
19457}
19458
19459/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19460 really need to use elf32_arm_modify_segment_map. But we do it
19461 anyway just to reduce gratuitous differences with the stock ARM backend. */
19462
19463static bfd_boolean
19464elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19465{
19466 return (elf32_arm_modify_segment_map (abfd, info)
19467 && nacl_modify_segment_map (abfd, info));
19468}
19469
887badb3
RM		 19470static void
19471elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19472{
19473 elf32_arm_final_write_processing (abfd, linker);
19474 nacl_final_write_processing (abfd, linker);
19475}
19476
6a631e86
YG		 19477static bfd_vma
19478elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19479 const arelent *rel ATTRIBUTE_UNUSED)
19480{
19481 return plt->vma
19482 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19483 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19484}
887badb3 19485
b38cadfb 19486#undef elf32_bed
6a631e86 19487#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19488#undef bfd_elf32_bfd_link_hash_table_create
19489#define bfd_elf32_bfd_link_hash_table_create \
19490 elf32_arm_nacl_link_hash_table_create
19491#undef elf_backend_plt_alignment
6a631e86 19492#define elf_backend_plt_alignment 4
b38cadfb
NC		 19493#undef elf_backend_modify_segment_map
19494#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19495#undef elf_backend_modify_program_headers
19496#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19497#undef elf_backend_final_write_processing
19498#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19499#undef bfd_elf32_get_synthetic_symtab
19500#undef elf_backend_plt_sym_val
19501#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19502#undef elf_backend_copy_special_section_fields
b38cadfb 19503
887badb3
RM		 19504#undef ELF_MINPAGESIZE
19505#undef ELF_COMMONPAGESIZE
19506
b38cadfb
NC		 19507
19508#include "elf32-target.h"
19509
19510/* Reset to defaults. */
19511#undef elf_backend_plt_alignment
19512#undef elf_backend_modify_segment_map
19513#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19514#undef elf_backend_modify_program_headers
887badb3
RM		 19515#undef elf_backend_final_write_processing
19516#define elf_backend_final_write_processing elf32_arm_final_write_processing
19517#undef ELF_MINPAGESIZE
19518#define ELF_MINPAGESIZE 0x1000
19519#undef ELF_COMMONPAGESIZE
19520#define ELF_COMMONPAGESIZE 0x1000
19521
b38cadfb 19522
906e58ca 19523/* VxWorks Targets. */
4e7fd91e 19524
906e58ca 19525#undef TARGET_LITTLE_SYM
6d00b590 19526#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19527#undef TARGET_LITTLE_NAME
4e7fd91e 19528#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19529#undef TARGET_BIG_SYM
6d00b590 19530#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19531#undef TARGET_BIG_NAME
4e7fd91e
PB		 19532#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19533
19534/* Like elf32_arm_link_hash_table_create -- but overrides
19535 appropriately for VxWorks. */
906e58ca 19536
4e7fd91e
PB		 19537static struct bfd_link_hash_table *
19538elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19539{
19540 struct bfd_link_hash_table *ret;
19541
19542 ret = elf32_arm_link_hash_table_create (abfd);
19543 if (ret)
19544 {
19545 struct elf32_arm_link_hash_table *htab
00a97672 19546 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19547 htab->use_rel = 0;
00a97672 19548 htab->vxworks_p = 1;
4e7fd91e
PB		 19549 }
19550 return ret;
906e58ca 19551}
4e7fd91e 19552
00a97672
RS		 19553static void
19554elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19555{
19556 elf32_arm_final_write_processing (abfd, linker);
19557 elf_vxworks_final_write_processing (abfd, linker);
19558}
19559
906e58ca 19560#undef elf32_bed
4e7fd91e
PB		 19561#define elf32_bed elf32_arm_vxworks_bed
19562
906e58ca
NC		 19563#undef bfd_elf32_bfd_link_hash_table_create
19564#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19565#undef elf_backend_final_write_processing
19566#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19567#undef elf_backend_emit_relocs
9eaff861 19568#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19569
906e58ca 19570#undef elf_backend_may_use_rel_p
00a97672 19571#define elf_backend_may_use_rel_p 0
906e58ca 19572#undef elf_backend_may_use_rela_p
00a97672 19573#define elf_backend_may_use_rela_p 1
906e58ca 19574#undef elf_backend_default_use_rela_p
00a97672 19575#define elf_backend_default_use_rela_p 1
906e58ca 19576#undef elf_backend_want_plt_sym
00a97672 19577#define elf_backend_want_plt_sym 1
906e58ca 19578#undef ELF_MAXPAGESIZE
00a97672 19579#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19580
19581#include "elf32-target.h"
19582
19583
21d799b5
NC		 19584/* Merge backend specific data from an object file to the output
19585 object file when linking. */
19586
19587static bfd_boolean
50e03d47 19588elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19589{
50e03d47 19590 bfd *obfd = info->output_bfd;
21d799b5
NC		 19591 flagword out_flags;
19592 flagword in_flags;
19593 bfd_boolean flags_compatible = TRUE;
19594 asection *sec;
19595
cc643b88 19596 /* Check if we have the same endianness. */
50e03d47 19597 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19598 return FALSE;
19599
19600 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19601 return TRUE;
19602
50e03d47 19603 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19604 return FALSE;
19605
19606 /* The input BFD must have had its flags initialised. */
19607 /* The following seems bogus to me -- The flags are initialized in
19608 the assembler but I don't think an elf_flags_init field is
19609 written into the object. */
19610 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19611
19612 in_flags = elf_elfheader (ibfd)->e_flags;
19613 out_flags = elf_elfheader (obfd)->e_flags;
19614
19615 /* In theory there is no reason why we couldn't handle this. However
19616 in practice it isn't even close to working and there is no real
19617 reason to want it. */
19618 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19619 && !(ibfd->flags & DYNAMIC)
19620 && (in_flags & EF_ARM_BE8))
19621 {
19622 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19623 ibfd);
19624 return FALSE;
19625 }
19626
19627 if (!elf_flags_init (obfd))
19628 {
19629 /* If the input is the default architecture and had the default
19630 flags then do not bother setting the flags for the output
19631 architecture, instead allow future merges to do this. If no
19632 future merges ever set these flags then they will retain their
99059e56
RM		 19633 uninitialised values, which surprise surprise, correspond
19634 to the default values. */
21d799b5
NC		 19635 if (bfd_get_arch_info (ibfd)->the_default
19636 && elf_elfheader (ibfd)->e_flags == 0)
19637 return TRUE;
19638
19639 elf_flags_init (obfd) = TRUE;
19640 elf_elfheader (obfd)->e_flags = in_flags;
19641
19642 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19643 && bfd_get_arch_info (obfd)->the_default)
19644 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19645
19646 return TRUE;
19647 }
19648
19649 /* Determine what should happen if the input ARM architecture
19650 does not match the output ARM architecture. */
19651 if (! bfd_arm_merge_machines (ibfd, obfd))
19652 return FALSE;
19653
19654 /* Identical flags must be compatible. */
19655 if (in_flags == out_flags)
19656 return TRUE;
19657
19658 /* Check to see if the input BFD actually contains any sections. If
19659 not, its flags may not have been initialised either, but it
19660 cannot actually cause any incompatiblity. Do not short-circuit
19661 dynamic objects; their section list may be emptied by
19662 elf_link_add_object_symbols.
19663
19664 Also check to see if there are no code sections in the input.
19665 In this case there is no need to check for code specific flags.
19666 XXX - do we need to worry about floating-point format compatability
19667 in data sections ? */
19668 if (!(ibfd->flags & DYNAMIC))
19669 {
19670 bfd_boolean null_input_bfd = TRUE;
19671 bfd_boolean only_data_sections = TRUE;
19672
19673 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19674 {
19675 /* Ignore synthetic glue sections. */
19676 if (strcmp (sec->name, ".glue_7")
19677 && strcmp (sec->name, ".glue_7t"))
19678 {
19679 if ((bfd_get_section_flags (ibfd, sec)
19680 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19681 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19682 only_data_sections = FALSE;
21d799b5
NC		 19683
19684 null_input_bfd = FALSE;
19685 break;
19686 }
19687 }
19688
19689 if (null_input_bfd || only_data_sections)
19690 return TRUE;
19691 }
19692
19693 /* Complain about various flag mismatches. */
19694 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19695 EF_ARM_EABI_VERSION (out_flags)))
19696 {
19697 _bfd_error_handler
19698 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
c08bb8dd
AM		 19699 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19700 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19701 return FALSE;
19702 }
19703
19704 /* Not sure what needs to be checked for EABI versions >= 1. */
19705 /* VxWorks libraries do not use these flags. */
19706 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19707 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19708 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19709 {
19710 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19711 {
19712 _bfd_error_handler
19713 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
c08bb8dd
AM		 19714 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19715 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19716 flags_compatible = FALSE;
19717 }
19718
19719 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19720 {
19721 if (in_flags & EF_ARM_APCS_FLOAT)
19722 _bfd_error_handler
19723 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19724 ibfd, obfd);
19725 else
19726 _bfd_error_handler
19727 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19728 ibfd, obfd);
19729
19730 flags_compatible = FALSE;
19731 }
19732
19733 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19734 {
19735 if (in_flags & EF_ARM_VFP_FLOAT)
19736 _bfd_error_handler
19737 (_("error: %B uses VFP instructions, whereas %B does not"),
19738 ibfd, obfd);
19739 else
19740 _bfd_error_handler
19741 (_("error: %B uses FPA instructions, whereas %B does not"),
19742 ibfd, obfd);
19743
19744 flags_compatible = FALSE;
19745 }
19746
19747 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19748 {
19749 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19750 _bfd_error_handler
19751 (_("error: %B uses Maverick instructions, whereas %B does not"),
19752 ibfd, obfd);
19753 else
19754 _bfd_error_handler
19755 (_("error: %B does not use Maverick instructions, whereas %B does"),
19756 ibfd, obfd);
19757
19758 flags_compatible = FALSE;
19759 }
19760
19761#ifdef EF_ARM_SOFT_FLOAT
19762 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19763 {
19764 /* We can allow interworking between code that is VFP format
19765 layout, and uses either soft float or integer regs for
19766 passing floating point arguments and results. We already
19767 know that the APCS_FLOAT flags match; similarly for VFP
19768 flags. */
19769 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19770 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19771 {
19772 if (in_flags & EF_ARM_SOFT_FLOAT)
19773 _bfd_error_handler
19774 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19775 ibfd, obfd);
19776 else
19777 _bfd_error_handler
19778 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19779 ibfd, obfd);
19780
19781 flags_compatible = FALSE;
19782 }
19783 }
19784#endif
19785
19786 /* Interworking mismatch is only a warning. */
19787 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19788 {
19789 if (in_flags & EF_ARM_INTERWORK)
19790 {
19791 _bfd_error_handler
19792 (_("Warning: %B supports interworking, whereas %B does not"),
19793 ibfd, obfd);
19794 }
19795 else
19796 {
19797 _bfd_error_handler
19798 (_("Warning: %B does not support interworking, whereas %B does"),
19799 ibfd, obfd);
19800 }
19801 }
19802 }
19803
19804 return flags_compatible;
19805}
19806
19807
906e58ca 19808/* Symbian OS Targets. */
7f266840 19809
906e58ca 19810#undef TARGET_LITTLE_SYM
6d00b590 19811#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19812#undef TARGET_LITTLE_NAME
7f266840 19813#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19814#undef TARGET_BIG_SYM
6d00b590 19815#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19816#undef TARGET_BIG_NAME
7f266840
DJ		 19817#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19818
19819/* Like elf32_arm_link_hash_table_create -- but overrides
19820 appropriately for Symbian OS. */
906e58ca 19821
7f266840
DJ		 19822static struct bfd_link_hash_table *
19823elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19824{
19825 struct bfd_link_hash_table *ret;
19826
19827 ret = elf32_arm_link_hash_table_create (abfd);
19828 if (ret)
19829 {
19830 struct elf32_arm_link_hash_table *htab
19831 = (struct elf32_arm_link_hash_table *)ret;
19832 /* There is no PLT header for Symbian OS. */
19833 htab->plt_header_size = 0;
95720a86
DJ		 19834 /* The PLT entries are each one instruction and one word. */
19835 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19836 htab->symbian_p = 1;
33bfe774
JB		 19837 /* Symbian uses armv5t or above, so use_blx is always true. */
19838 htab->use_blx = 1;
67687978 19839 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19840 }
19841 return ret;
906e58ca 19842}
7f266840 19843
b35d266b 19844static const struct bfd_elf_special_section
551b43fd 19845elf32_arm_symbian_special_sections[] =
7f266840 19846{
5cd3778d
MM		 19847 /* In a BPABI executable, the dynamic linking sections do not go in
19848 the loadable read-only segment. The post-linker may wish to
19849 refer to these sections, but they are not part of the final
19850 program image. */
0112cd26
NC		 19851 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19852 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19853 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19854 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19855 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19856 /* These sections do not need to be writable as the SymbianOS
19857 postlinker will arrange things so that no dynamic relocation is
19858 required. */
0112cd26
NC		 19859 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19860 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19861 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19862 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19863};
19864
c3c76620 19865static void
906e58ca 19866elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19867 struct bfd_link_info *link_info)
c3c76620
MM		 19868{
19869 /* BPABI objects are never loaded directly by an OS kernel; they are
19870 processed by a postlinker first, into an OS-specific format. If
19871 the D_PAGED bit is set on the file, BFD will align segments on
19872 page boundaries, so that an OS can directly map the file. With
19873 BPABI objects, that just results in wasted space. In addition,
19874 because we clear the D_PAGED bit, map_sections_to_segments will
19875 recognize that the program headers should not be mapped into any
19876 loadable segment. */
19877 abfd->flags &= ~D_PAGED;
906e58ca 19878 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19879}
7f266840
DJ		 19880
19881static bfd_boolean
906e58ca 19882elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19883 struct bfd_link_info *info)
7f266840
DJ		 19884{
19885 struct elf_segment_map *m;
19886 asection *dynsec;
19887
7f266840
DJ		 19888 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19889 segment. However, because the .dynamic section is not marked
19890 with SEC_LOAD, the generic ELF code will not create such a
19891 segment. */
19892 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19893 if (dynsec)
19894 {
12bd6957 19895 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19896 if (m->p_type == PT_DYNAMIC)
19897 break;
19898
19899 if (m == NULL)
19900 {
19901 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19902 m->next = elf_seg_map (abfd);
19903 elf_seg_map (abfd) = m;
8ded5a0f 19904 }
7f266840
DJ		 19905 }
19906
b294bdf8
MM		 19907 /* Also call the generic arm routine. */
19908 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19909}
19910
95720a86
DJ		 19911/* Return address for Ith PLT stub in section PLT, for relocation REL
19912 or (bfd_vma) -1 if it should not be included. */
19913
19914static bfd_vma
19915elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19916 const arelent *rel ATTRIBUTE_UNUSED)
19917{
19918 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19919}
19920
8029a119 19921#undef elf32_bed
7f266840
DJ		 19922#define elf32_bed elf32_arm_symbian_bed
19923
19924/* The dynamic sections are not allocated on SymbianOS; the postlinker
19925 will process them and then discard them. */
906e58ca 19926#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19927#define ELF_DYNAMIC_SEC_FLAGS \
19928 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19929
9eaff861 19930#undef elf_backend_emit_relocs
c3c76620 19931
906e58ca
NC		 19932#undef bfd_elf32_bfd_link_hash_table_create
19933#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19934#undef elf_backend_special_sections
19935#define elf_backend_special_sections elf32_arm_symbian_special_sections
19936#undef elf_backend_begin_write_processing
19937#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19938#undef elf_backend_final_write_processing
19939#define elf_backend_final_write_processing elf32_arm_final_write_processing
19940
19941#undef elf_backend_modify_segment_map
7f266840
DJ		 19942#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19943
19944/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19945#undef elf_backend_got_header_size
7f266840
DJ		 19946#define elf_backend_got_header_size 0
19947
19948/* Similarly, there is no .got.plt section. */
906e58ca 19949#undef elf_backend_want_got_plt
7f266840
DJ		 19950#define elf_backend_want_got_plt 0
19951
906e58ca 19952#undef elf_backend_plt_sym_val
95720a86
DJ		 19953#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19954
906e58ca 19955#undef elf_backend_may_use_rel_p
00a97672 19956#define elf_backend_may_use_rel_p 1
906e58ca 19957#undef elf_backend_may_use_rela_p
00a97672 19958#define elf_backend_may_use_rela_p 0
906e58ca 19959#undef elf_backend_default_use_rela_p
00a97672 19960#define elf_backend_default_use_rela_p 0
906e58ca 19961#undef elf_backend_want_plt_sym
00a97672 19962#define elf_backend_want_plt_sym 0
64f52338
AM		 19963#undef elf_backend_dtrel_excludes_plt
19964#define elf_backend_dtrel_excludes_plt 0
906e58ca 19965#undef ELF_MAXPAGESIZE
00a97672 19966#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19967
7f266840 19968#include "elf32-target.h"
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