GDB Administrator [Sun, 21 Apr 2019 00:01:05 +0000 (00:01 +0000)]
Automatic date update in version.in
Philippe Waroquiers [Sat, 13 Apr 2019 08:22:41 +0000 (10:22 +0200)]
Fix GDB crash when registers cannot be modified.
This crash was detected when using GDB with the valgrind gdbserver.
To reproduce:
valgrind sleep 10000
In another window:
gdb
target remote | vgdb
p printf("make sleep print something\n")
=>
terminate called after throwing an instance of 'gdb_exception_error'
Aborted
The problem is that the valgrind gdbserver does not allow to change
registers when the inferior is blocked in a system call.
GDB then raises an exception. The exception causes the destructor
of
typedef std::unique_ptr<infcall_suspend_state, infcall_suspend_state_deleter>
infcall_suspend_state_up;
to be called. This destructor itself tries to restore the value of
the registers, and fails similarly. We must catch the exception in
the destructor to avoid crashing GDB.
If the destructor encounters a problem, no warning is produced if
there is an uncaught exception, as in this case, the user will already
be informed of a problem via this exception.
With this change, no crash anymore, and all the valgrind 3.15 tests
pass succesfully.
gdb/ChangeLog
2019-04-19 Philippe Waroquiers <philippe.waroquiers@skynet.be>
* inferior.h (struct infcall_suspend_state_deleter):
Catch exception in destructor to avoid crash.
GDB Administrator [Sat, 20 Apr 2019 00:00:21 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Sun, 7 Apr 2019 22:32:54 +0000 (16:32 -0600)]
Remove common/queue.h
gdb no longer needs common/queue.h, so this removes it.
gdb/ChangeLog
2019-04-19 Tom Tromey <tom@tromey.com>
* common/queue.h: Remove.
Tom Tromey [Sun, 7 Apr 2019 22:32:19 +0000 (16:32 -0600)]
Remove an include of common/queue.h
event-loop.c does not need to include common/queue.h, so this removes
it.
gdb/ChangeLog
2019-04-19 Tom Tromey <tom@tromey.com>
* event-loop.c: Don't include "common/queue.h".
Tom Tromey [Sun, 7 Apr 2019 22:31:01 +0000 (16:31 -0600)]
Use std::list for remote_notif_state::notif_queue
This changes remote_notif_state::notif_queue to be a std::list and
updates all the uses.
gdb/ChangeLog
2019-04-19 Tom Tromey <tom@tromey.com>
* remote.c (remote_target): Use delete.
* remote-notif.h: Include <list>, not "common/queue.h".
(notif_client_p): Remove typedef.
(remote_notif_state): Add constructor, destructor, initializer.
<notif_queue>: Now a std::list.
(remote_notif_state_xfree): Don't declare.
* remote-notif.c (remote_notif_process, handle_notification)
(remote_notif_state_allocate): Update.
(~remote_notif_state): Rename from remote_notif_state_xfree.
Tom Tromey [Sun, 7 Apr 2019 22:17:40 +0000 (16:17 -0600)]
Use std::list for event notifications in gdbserver
This changes gdbserver to use std::list rather than common/queue.h for
event notifications.
gdb/gdbserver/ChangeLog
2019-04-19 Tom Tromey <tom@tromey.com>
* server.c (struct vstop_notif): Derive from notif_event.
<base>: Remove.
(queue_stop_reply): Update.
(remove_all_on_match_ptid): Change type. Rewrite.
(discard_queued_stop_replies): Rewrite.
(in_queued_stop_replies_ptid): Change type.
(in_queued_stop_replies): Rewrite.
(notif_stop): Update.
(queue_stop_reply_callback): Update.
(captured_main): Don't call initialize_notif.
(push_stop_notification): Update.
* notif.c (notif_write_event, handle_notif_ack)
(notif_event_enque, notif_push): Update.
(notif_event_xfree, initialize_notif): Remove.
* notif.h (struct notif_event): Include <list>, not
"common/queue.h".
(struct notif_server) <queue>: Now a std::list.
(notif_event_p): Remove typedef.
(initialize_notif): Don't declare.
(struct notif_event): Add virtual destructor.
Tom Tromey [Sun, 7 Apr 2019 21:39:37 +0000 (15:39 -0600)]
Make objfile::static_links an htab_up
This changes objfile::static_links to be an htab_up, so that ~objfile
no longer has to explicitly destroy it.
Tested by the buildbot.
gdb/ChangeLog
2019-04-19 Tom Tromey <tom@tromey.com>
* symfile.c (reread_symbols): Update.
* objfiles.c (objfile_register_static_link)
(objfile_lookup_static_link): Update
(~objfile) Don't delete static_links.
* objfiles.h (struct objfile) <static_links>: Now an htab_up.
Tom Tromey [Sun, 7 Apr 2019 21:29:58 +0000 (15:29 -0600)]
Make copy_name return std::string
This changes copy_name to return a std::string, updating all the
callers. In some cases, an extra copy was removed. This also
required a little bit of constification.
Tested by the buildbot.
gdb/ChangeLog
2019-04-19 Tom Tromey <tom@tromey.com>
* type-stack.h (struct type_stack) <insert>: Constify string.
* type-stack.c (type_stack::insert): Constify string.
* gdbtypes.h (lookup_template_type): Update.
(address_space_name_to_int): Update.
* gdbtypes.c (address_space_name_to_int): Make space_identifier
const.
(lookup_template_type): Make name const.
* c-exp.y: Update rules.
(lex_one_token, classify_name, classify_inner_name)
(c_print_token): Update.
* p-exp.y: Update rules.
(yylex): Update.
* f-exp.y: Update rules.
(yylex): Update.
* d-exp.y: Update rules.
(lex_one_token, classify_name, classify_inner_name): Update.
* parse.c (write_dollar_variable, copy_name): Return std::string.
* parser-defs.h (copy_name): Change return type.
* m2-exp.y: Update rules.
(yylex): Update.
* go-exp.y (lex_one_token): Update.
Update rules.
(classify_unsafe_function, classify_packaged_name)
(classify_name, yylex): Update.
Sergei Trofimovich [Sun, 17 Mar 2019 22:48:02 +0000 (22:48 +0000)]
gdb/configure.ac: add --enable-source-highlight
Allow disabling source-highlight dependency autodetection even
it exists in the system. More details on problem of automatic
dependencies:
https://wiki.gentoo.org/wiki/Project:Quality_Assurance/Automagic_dependencies
Noticed by Jeroen Roovers in https://bugs.gentoo.org/680238
* configure.ac: add --enable-source-highlight switch.
* configure: Regenerate.
* top.c (print_gdb_version): plumb --enable-source-highlight
status to "show configuration".
gdb/ChangeLog
2019-04-19 Sergei Trofimovich <siarheit@google.com>
* configure.ac: add --enable-source-highlight switch.
* configure: Regenerate.
* top.c (print_gdb_version): plumb --enable-source-highlight
status to "show configuration".
Tom Tromey [Tue, 9 Apr 2019 13:46:39 +0000 (07:46 -0600)]
Print non-Ada unions without crashing
ada-lang.c is a bit too eager trying to decode unions in the Ada style
-- looking for discriminants and such. This causes crashes when
printing a non-Ada union in Ada mode, something that can easily happen
when printing a value from history or certain registers on AArch64.
This patch fixes the bug by changing ada-lang.c to only apply special
Ada treatment to types coming from an Ada CU. This in turn required a
couple of surprising changes.
First, some of the Ada code was already using HAVE_GNAT_AUX_INFO to
decide whether a type had already been fixed -- such types had
INIT_CPLUS_SPECIFIC called on them. This patch changes these spots to
use the "none" identifier instead.
This then required changing value_rtti_type to avoid changing the
language-specific object attached to an Ada type, which seems like a
good change regardless.
Tested on x86-64 Fedora 29.
gdb/ChangeLog
2019-04-19 Tom Tromey <tromey@adacore.com>
* ada-lang.c (ada_is_variant_part, ada_to_fixed_type_1):
Check ADA_TYPE_P.
(empty_record, ada_template_to_fixed_record_type_1)
(template_to_static_fixed_type)
(to_record_with_fixed_variant_part): Use INIT_NONE_SPECIFIC.
* cp-abi.c (value_rtti_type): Check HAVE_CPLUS_STRUCT.
* gdbtypes.h (INIT_NONE_SPECIFIC, ADA_TYPE_P): New
macros.
gdb/testsuite/ChangeLog
2019-04-19 Tom Tromey <tromey@adacore.com>
* gdb.ada/ptype_union.c: New file.
* gdb.ada/ptype_union.exp: New file.
Tom Tromey [Tue, 9 Apr 2019 18:52:46 +0000 (12:52 -0600)]
Fix "list" when control characters are seen
PR symtab/24423 points out that control characters in a source file
cause a hang in the "list" command, a regression introduced by the
styling changes.
This patch, from the PR, fixes the bug. I've included a minimal
change to the "list" test that exercises this code.
I recall that this bug was discussed on gdb-patches, and I thought
there was a patch there as well, but I was unable to find it.
gdb/ChangeLog
2019-04-19 Ilya Yu. Malakhov <malakhov@mcst.ru>
PR symtab/24423:
* source.c (print_source_lines_base): Advance "iter" when a
control character is seen.
gdb/testsuite/ChangeLog
2019-04-19 Tom Tromey <tromey@adacore.com>
PR symtab/24423:
* gdb.base/list0.h (foo): Add a control-l character.
Philippe Waroquiers [Sat, 13 Apr 2019 08:22:41 +0000 (10:22 +0200)]
Fix GDB crash when registers cannot be modified.
This crash was detected when using GDB with the valgrind gdbserver.
To reproduce:
valgrind sleep 10000
In another window:
gdb
target remote | vgdb
p printf("make sleep print something\n")
=>
terminate called after throwing an instance of 'gdb_exception_error'
Aborted
The problem is that the valgrind gdbserver does not allow to change
registers when the inferior is blocked in a system call.
GDB then raises an exception. The exception causes the destructor
of
typedef std::unique_ptr<infcall_suspend_state, infcall_suspend_state_deleter>
infcall_suspend_state_up;
to be called. This destructor itself tries to restore the value of
the registers, and fails similarly. We must catch the exception in
the destructor to avoid crashing GDB.
If the destructor encounters a problem, no warning is produced if
there is an uncaught exception, as in this case, the user will already
be informed of a problem via this exception.
With this change, no crash anymore, and all the valgrind 3.15 tests
pass succesfully.
gdb/ChangeLog
2019-04-19 Philippe Waroquiers <philippe.waroquiers@skynet.be>
* inferior.h (struct infcall_suspend_state_deleter):
Catch exception in destructor to avoid crash.
Philippe Waroquiers [Fri, 19 Apr 2019 11:45:00 +0000 (13:45 +0200)]
OBVIOUS move add_comm_alias "!" <=> "shell" near the add_com "shell"
gdb/ChangeLog
2019-04-19 Philippe Waroquiers <philippe.waroquiers@skynet.be>
* cli/cli-cmds.c (_initialize_cli_cmds): Move "shell" "!" alias
close to the add_com "shell".
Nick Clifton [Fri, 19 Apr 2019 09:39:47 +0000 (10:39 +0100)]
RX Assembler: Ensure that the internal limit on the number of relaxation iterations is not larger that the external limit.
PR 24464
* config/tc-rx.h (md_relax_frag): Pass the max_iterations variable
to the relaxation function.
* config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum
number of iterations. Make sure that our internal iteration limit
does not exceed this external iteration limit.
Alan Modra [Fri, 19 Apr 2019 03:03:46 +0000 (12:33 +0930)]
s12z and h8300 no-print-map-discarded fails
This tidies the remaining --no-print-map-discarded fails. h8300-elf
warns on a section without flags, and s12z doesn't support
--gc-sections.
bfd/
* elf32-s12z.c (elf_backend_can_gc_sections): Don't define
ld/
* testsuite/ld-gc/skip-map-discarded.s: Add section attributes.
* testsuite/lib/ld-lib.exp (check_gc_sections_available): Add
s12z to list of targets not supporting --gc-sections.
GDB Administrator [Fri, 19 Apr 2019 00:00:12 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom de Vries [Thu, 18 Apr 2019 21:37:33 +0000 (23:37 +0200)]
[gdb/testsuite] Fix gdb.base/break-probes.exp with native-gdbserver
When running break-probes.exp with native-gdbserver, we run into:
...
FAIL: gdb.base/break-probes.exp: run til our library loads (the program exited)
FAIL: gdb.base/break-probes.exp: call (int) foo(23)
...
due to the fact that we're trying to match:
...
Inferior loaded /data/gdb_versions/devel/build/gdb/testsuite/outputs/gdb.base\
/break-probes/break-probes-solib.so
...
using pattern:
...
Inferior loaded $sysroot$binfile_lib
...
which expands into:
...
Inferior loaded //data/gdb_versions/devel/build/gdb/testsuite/outputs/gdb.base\
/break-probes/break-probes-solib.so
...
Fix by setting sysroot to "" in local-board.exp.
Tested on x86_64-linux with native-gdbserver.
gdb/testsuite/ChangeLog:
2019-04-18 Tom de Vries <tdevries@suse.de>
PR gdb/24433
* boards/local-board.exp: Set sysroot to "".
Tom Tromey [Thu, 18 Apr 2019 15:42:46 +0000 (09:42 -0600)]
Make process_stratum_target::stratum "final"
It seemed to me that process_stratum_target::stratum ought to be
"final".
Tested by rebuilding, let me know what you think.
gdb/ChangeLog
2019-04-18 Tom Tromey <tromey@adacore.com>
* process-stratum-target.h (class process_stratum_target)
<stratum>: Add "final".
Matthew Fortune [Wed, 17 Apr 2019 04:07:19 +0000 (04:07 +0000)]
Improve warning message for $0 constraint on MIPSR6 branches
gas/
* config/tc-mips.c (match_non_zero_reg_operand): Update
warning message.
* testsuite/gas/mips/r6-branch-constraints.l: Likewise.
Tom de Vries [Thu, 18 Apr 2019 16:05:43 +0000 (17:05 +0100)]
[gdb] Handle vfork in thread with follow-fork-mode child
When debugging any of the testcases added by this commit, which do a
vfork in a thread with "set follow-fork-mode child" + "set
detach-on-fork on", we run into this assertion:
...
src/gdb/nat/x86-linux-dregs.c:146: internal-error: \
void x86_linux_update_debug_registers(lwp_info*): \
Assertion `lwp_is_stopped (lwp)' failed.
...
The assert is caused by the following: the vfork-child exit or exec
event is handled by handle_vfork_child_exec_or_exit, which calls
target_detach to detach from the vfork parent. During target_detach
we call linux_nat_target::detach, which:
#1 - stops all the threads
#2 - waits for all the threads to be stopped
#3 - detaches all the threads
However, during the second step we run into this code in
stop_wait_callback:
...
/* If this is a vfork parent, bail out, it is not going to report
any SIGSTOP until the vfork is done with. */
if (inf->vfork_child != NULL)
return 0;
...
and we don't wait for the threads to be stopped, which results in this
assert in x86_linux_update_debug_registers triggering during the third
step:
...
gdb_assert (lwp_is_stopped (lwp));
...
The fix is to reset the vfork parent's vfork_child field before
calling target_detach in handle_vfork_child_exec_or_exit. There's
already similar code for the other paths handled by
handle_vfork_child_exec_or_exit, so this commit refactors the code a
bit so that all paths share the same code.
The new tests cover both a vfork child exiting, and a vfork child
execing, since both cases would trigger the assertion.
The new testcases also exercise following the vfork children with "set
detach-on-fork off", since it doesn't seem to be tested anywhere.
Tested on x86_64-linux, using native and native-gdbserver.
gdb/ChangeLog:
2019-04-18 Tom de Vries <tdevries@suse.de>
Pedro Alves <palves@redhat.com>
PR gdb/24454
* infrun.c (handle_vfork_child_exec_or_exit): Reset vfork parent's
vfork_child field before calling target_detach.
gdb/testsuite/ChangeLog:
2019-04-18 Tom de Vries <tdevries@suse.de>
Pedro Alves <palves@redhat.com>
PR gdb/24454
* gdb.threads/vfork-follow-child-exec.c: New file.
* gdb.threads/vfork-follow-child-exec.exp: New file.
* gdb.threads/vfork-follow-child-exit.c: New file.
* gdb.threads/vfork-follow-child-exit.exp: New file.
Jozef Lawrynowicz [Thu, 18 Apr 2019 12:15:09 +0000 (13:15 +0100)]
MSP430 Assembler: Define symbols for functions to run through.
gas * config/tc-msp430.c (msp430_make_init_symbols): Define
__crt0_run_{preinit,init,fini}_array symbols if
.{preinit,init,fini}_array sections exist.
* testsuite/gas/msp430/fini-array.d: New test.
* testsuite/gas/msp430/init-array.d: New test.
* testsuite/gas/msp430/preinit-array.d: New test.
* testsuite/gas/msp430/fini-array.s: New test source.
* testsuite/gas/msp430/init-array.s: New test source.
* testsuite/gas/msp430/preinit-array.s: New test source.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
GDB Administrator [Thu, 18 Apr 2019 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Wed, 17 Apr 2019 17:22:19 +0000 (10:22 -0700)]
x86: Suggest -fPIE when not building shared object
When PIC is needed, linker should suggest -fPIE, instead of -fPIC, when
not building shared object.
bfd/
* elf64-x86-64.c (elf_x86_64_need_pic): Suggest -fPIE when not
building shared object.
* elfxx-x86.c (_bfd_x86_elf_size_dynamic_sections): Likewise.
ld/
* testsuite/ld-i386/i386.exp: Run pr18801a and pr18801b instead
of pr18801.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/pr18801.d: Removed.
* testsuite/ld-x86-64/pr18801.d: Likewise.
* testsuite/ld-i386/pr18801a.d: New file.
* testsuite/ld-i386/pr18801b.d: Likewise.
* testsuite/ld-x86-64/pr18801a.d: Likewise.
* testsuite/ld-x86-64/pr18801b.d: Likewise.
* testsuite/ld-x86-64/pie2.d: Suggest -fPIE instead of -fPIC.
* testsuite/ld-x86-64/pie2.d: Likewise.
* testsuite/ld-x86-64/pr19719.d: Likewise.
* testsuite/ld-x86-64/pr19807-2a.d: Likewise.
* testsuite/ld-x86-64/pr19969.d: Likewise.
* testsuite/ld-x86-64/pr21997-1a.err: Likewise.
* testsuite/ld-x86-64/pr21997-1b.err: Likewise.
* testsuite/ld-x86-64/pr22001-1a.err: Likewise.
* testsuite/ld-x86-64/pr22001-1b.err: Likewise.
* testsuite/ld-x86-64/pr22791-1.err: Likewise.
H.J. Lu [Wed, 17 Apr 2019 16:08:46 +0000 (09:08 -0700)]
x86: Also check x86 linker_def for non-shared definition
Since elf_x86_linker_defined sets linker_def in elf_x86_link_hash_entry
for linker defined symbols, SYMBOL_DEFINED_NON_SHARED_P should also check
linker_def in elf_x86_link_hash_entry.
bfd/
PR ld/24458
* elfxx-x86.h (SYMBOL_DEFINED_NON_SHARED_P): Also check x86
linker_def.
ld/
PR ld/24458
* testsuite/ld-x86-64/x86-64.exp: Run PR ld/24458 tests.
* testsuite/ld-x86-64/pr24458.s: New file.
* testsuite/ld-x86-64/pr24458a-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458a.d: Likewise.
* testsuite/ld-x86-64/pr24458b-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458b.d: Likewise.
* testsuite/ld-x86-64/pr24458c-x32.d: Likewise.
* testsuite/ld-x86-64/pr24458c.d: Likewise.
Jozef Lawrynowicz [Wed, 17 Apr 2019 14:05:08 +0000 (15:05 +0100)]
MSP430 Linker: Define __crt0_init_bss/__crt0_movedata symbols when .lower or .either prefixed sections are present.
ld * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss
symbol when .lower.bss or .either.bss sections exist.
Define __crt0_movedata when .lower.data or .either.data sections exist.
* testsuite/gas/msp430/either-data-bss-sym.d: New test.
* testsuite/gas/msp430/low-data-bss-sym.d: New test.
* testsuite/gas/msp430/either-data-bss-sym.s: New test source.
* testsuite/gas/msp430/low-data-bss-sym.s: New test source.
* testsuite/gas/msp430/msp430.exp: Run new tests.
Enable large code model when running -mdata-region={upper,either}
tests.
Jozef Lawrynowicz [Wed, 17 Apr 2019 14:03:27 +0000 (15:03 +0100)]
MSP430 Assembler: Leave placement of .lower and .upper sections to generic linker code.
* config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss
symbol when .lower.bss or .either.bss sections exist.
Define __crt0_movedata when .lower.data or .either.data sections exist.
* testsuite/gas/msp430/either-data-bss-sym.d: New test.
* testsuite/gas/msp430/low-data-bss-sym.d: New test.
* testsuite/gas/msp430/either-data-bss-sym.s: New test source.
* testsuite/gas/msp430/low-data-bss-sym.s: New test source.
* testsuite/gas/msp430/msp430.exp: Run new tests.
Enable large code model when running -mdata-region={upper,either}
tests.
Jozef Lawrynowicz [Wed, 17 Apr 2019 14:01:28 +0000 (15:01 +0100)]
MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for unknown interrupt state changes
gas * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,
OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.
(md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and
OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops
accordingly.
(md_show_usage): Likewise.
(md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and
"mU" for OPTION_NO_UNKNOWN_INTR_NOPS.
(md_longopts): Likewise.
(warn_eint_nop): Update comment.
(warn_unsure_interrupt): Don't warn if prev_insn_is_nop or
prev_insn_is_dint or we are assembling for 430 ISA.
(msp430_operands): Only call warn_unsure_interrupt if
do_unknown_interrupt_nops == TRUE.
* testsuite/gas/msp430/nop-unknown-intr.s: New test source file.
* testsuite/gas/msp430/nop-unknown-intr-430.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new
test.
* testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
Tom Tromey [Tue, 16 Apr 2019 18:12:09 +0000 (12:12 -0600)]
Avoid crash in dwarf2_init_complex_target_type
After commit
35add35 ("gdb: Fix failure in gdb.base/complex-parts.exp
for x86-32"), dwarf2_init_complex_target_type can crash if "tt" is
nullptr. This patch avoids the problem by checking for this case.
No test case because I don't know a good way to write one; it was
found by an internal AdaCore test case that apparently uses a 16 bit
floating point type.
gdb/ChangeLog:
* dwarf2read.c (dwarf2_init_complex_target_type): Check "tt"
against nullptr before use.
gdb/ChangeLog
2019-04-17 Tom Tromey <tromey@adacore.com>
* dwarf2read.c (dwarf2_init_complex_target_type): Check "tt"
against nullptr before use.
Alan Hayward [Tue, 16 Apr 2019 09:37:47 +0000 (10:37 +0100)]
gdbserver: Ensure all debug output uses debug functions
All debug output needs to go via debug functions to ensure it writes to the
correct output stream.
gdb/ChangeLog:
* nat/linux-waitpid.c (linux_debug): Call debug_vprintf.
gdb/gdbserver/ChangeLog:
* ax.c (ax_vdebug): Call debug_printf.
* debug.c (debug_write): New function.
* debug.h (debug_write): New declaration.
* linux-low.c (sigchld_handler): Call debug_write.
Alan Hayward [Fri, 12 Apr 2019 14:49:11 +0000 (15:49 +0100)]
gdbserver: Add debug-file option
Add command line option to send all debug output to a given file.
Always default back to stderr.
Add matching monitor command. Add documentation.
gdb/doc/ChangeLog:
* gdb.texinfo
(Other Command-Line Arguments for gdbserver): Add debug-file
option.
(Monitor Commands for gdbserver): Likewise.
(gdbserver man): Likewise.
gdb/gdbserver/ChangeLog:
* debug.c (debug_set_output): New function.
(debug_vprintf): Send output to debug_file.
(debug_flush): Likewise.
* debug.h (debug_set_output): New declaration.
* server.c (handle_monitor_command): Add debug-file option.
(captured_main): Likewise.
Alan Hayward [Fri, 12 Apr 2019 13:21:55 +0000 (14:21 +0100)]
gdbserver: Move remote_debug to a single place
A comment in debug.h (written in 2014) states: "We declare debug format
variables here, and debug_threads but no other debug content variables
(e.g., not remote_debug) because while this file is not currently used by
IPA it may be some day, and IPA may have its own set of debug content
variables".
This has resulted in remote_debug being declared in many .c/.h files
throughout gdbserver.
It would be much simplier to define it one place. The most logical place to
define it is in debug.h, surrounded by #define guards. If IPA is changed,
then at that point the variable can be moved elsewhere.
gdb/gdbserver/ChangeLog:
* debug.c (remote_debug): Add definition.
* debug.h (remote_debug): Add declaration.
* hostio.c (remote_debug): Remove declaration.
* remote-utils.c (struct ui_file): Likewise.
(remote_debug): Likewise.
* remote-utils.h (remote_debug): Likewise,
* server.c (remote_debug): Remove definition.
GDB Administrator [Wed, 17 Apr 2019 00:00:31 +0000 (00:00 +0000)]
Automatic date update in version.in
Andrew Burgess [Tue, 16 Apr 2019 23:31:43 +0000 (00:31 +0100)]
gdb/riscv: Allow breakpoints to be created at invalid addresses
Some testsuite cases (gdb.cp/nsalias.exp for example) construct dwarf2
debug info for fake functions to test that this debug info is handled
correctly.
We currently get an error trying to read from an invalid address while
creating breakpoints for these fake functions.
Other targets allow creating breakpoints on invalid addresses, and
only error when GDB actually tries to insert the breakpoints.
In order to make RISC-V behave in the same way as other targets, this
commit makes the failure to read memory during breakpoint creation
non-fatal, we then expect to see a failure when GDB tries to insert
the breakpoint, just like other targets.
Tested with a riscv64-linux native testsuite run.
gdb/ChangeLog:
* riscv-tdep.c (riscv_breakpoint_kind_from_pc): Hanndle case where
code read might fail, assume 4-byte breakpoint in that case.
Alan Modra [Tue, 16 Apr 2019 12:04:22 +0000 (21:34 +0930)]
xfail gas weakref1 test for nds32
Oops, I removed the wrong xfail from gas.exp in last commit, fix it
here.
* testsuite/gas/all/weakref1.d: xfail nds32.
Alan Modra [Tue, 16 Apr 2019 08:38:11 +0000 (18:08 +0930)]
ns32k testsuite tidy
Some of these tests were excluded for ns32k-netbsd, exclude for all
ns32k instead.
binutils/
* testsuite/binutils-all/copy-2.d: Don't run for ns32k-*-*.
* testsuite/binutils-all/copy-3.d: Likewise.
gas/
* testsuite/gas/all/gas.exp: Remove ns32k xfails.
* testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
ld/
* testsuite/ld-scripts/pr20302.d: Don't run for ns32k-*-*.
* testsuite/ld-scripts/section-match-1.d: Likewise.
* testsuite/ld-undefined/require-defined.exp: Likewise.
Alan Modra [Tue, 16 Apr 2019 06:17:02 +0000 (15:47 +0930)]
Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPE
These are only used by dlx and ns32k.
* write.h: Don't include bit_fix.h.
(struct fix): Rearrange some fields. Delete fx_im_disp and
fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.
* write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.
(fixup_segment): Don't exclude overflow checks on fx_bit_fixP.
(print_fixup): Don't print im_disp.
* config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP
and fx_im_disp.
* config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set
fx_no_overflow when fx_bit_fixP.
* config/tc-dlx.h: Include bit_fix.h.
(TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.
* config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set
fx_no_overflow when bit_fixP.
* config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.
(fix_im_disp, fix_bit_fixP): Adjust to suit.
(TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
Alan Modra [Tue, 16 Apr 2019 01:40:44 +0000 (11:10 +0930)]
Make fixup fx_where unsigned
Another field that only stores unsigned values.
* write.h (struct fix <fx_where>): Make unsigned.
(fix_new, fix_at_start, fix_new_exp): Adjust prototypes.
* write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and
"size" parameters unsigned long.
(fix_new_internal): Likewise. Adjust error format string to suit.
* config/tc-mips.c (md_convert_frag): Remove cast of fx_where.
* config/tc-sparc.c (md_apply_fix): Likewise.
* config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where.
* config/tc-score7.c (s7_convert_frag): Likewise.
Alan Modra [Mon, 15 Apr 2019 12:21:44 +0000 (21:51 +0930)]
Make frag fr_fix unsigned
The field only stores unsigned values, so let's make it unsigned to
stop people worrying about the possibility of negative values.
* frags.h (struct frag <fr_fix>): Use unsigned type.
* frags.c (frag_new): Assert that current size exceeds
old_frags_var_max_size.
* ehopt.c (get_cie_info): Adjust for unsigned fr_fix.
* listing.c (calc_hex): Likewise.
* write.c (cvt_frag_to_fill, write_relocs): Likewise.
* config/tc-arc.c (md_convert_frag): Likewise.
* config/tc-avr.c (avr_patch_gccisr_frag): Likewise.
* config/tc-mips.c (md_convert_frag): Likewise.
* config/tc-rl78.c (md_convert_frag): Likewise.
* config/tc-rx.c (md_convert_frag): Likewise.
* config/tc-sparc.c (md_apply_fix): Likewise.
* config/tc-xtensa.c (next_instrs_are_b_retw): Likewise.
(unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
GDB Administrator [Tue, 16 Apr 2019 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
Leszek Swirski [Mon, 15 Apr 2019 15:56:43 +0000 (11:56 -0400)]
Fix AMD64 return value ABI in expression evaluation
The AMD64 System V ABI specifies that when a function has a return type
classified as MEMORY, the caller provides space for the value and passes
the address to this space as the first argument to the function (before
even the "this" pointer). The classification of MEMORY is applied to
struct that are sufficiently large, or ones with unaligned fields.
The expression evaluator uses call_function_by_hand to call functions,
and the hand-built frame has to push arguments in a way that matches the
ABI of the called function. call_function_by_hand supports ABI-based
struct returns, based on the value of gdbarch_return_value, however on
AMD64 the implementation of the classifier incorrectly assumed that all
non-POD types (implemented as "all types with a base class") should be
classified as MEMORY and use the struct return.
This ABI mismatch resulted in issues when calling a function that returns
a class of size <16 bytes which has a base class, including issues such
as the "this" pointer being incorrect (as it was passed as the second
argument rather than the first).
This is now fixed by checking for field alignment rather than POD-ness,
and a testsuite is added to test expression evaluation for AMD64.
gdb/ChangeLog:
* amd64-tdep.c (amd64_classify_aggregate): Use cp_pass_by_reference
rather than a hand-rolled POD check when checking for forced MEMORY
classification.
gdb/testsuite/ChangeLog:
* gdb.arch/amd64-eval.cc: New file.
* gdb.arch/amd64-eval.exp: New file.
Faraz Shahbazker [Mon, 15 Apr 2019 15:48:42 +0000 (08:48 -0700)]
Skip print-map-discarded test for non-ELF targets
ld/
* testsuite/ld-gc/gc.exp: Skip print-map-discarded test
for non-ELF targets.
Alan Hayward [Mon, 15 Apr 2019 11:31:21 +0000 (12:31 +0100)]
AArch64 SVE: Support changing vector lengths for ptrace
When writing registers to the kernel, check if regcache VG has been changed. If
so then update the thread's vector length, then write back the registers.
When reading registers from the kernel, ensure regcache VG register is updated.
The regcache registers should already be of the correct length.
Remove all the checks that error if the vector length has changed.
gdb/ChangeLog:
* aarch64-linux-nat.c (store_sveregs_to_thread): Set vector length.
* nat/aarch64-sve-linux-ptrace.c (aarch64_sve_set_vq): New function.
(aarch64_sve_regs_copy_to_reg_buf): Remove VG checks.
(aarch64_sve_regs_copy_from_reg_buf): Likewise.
* nat/aarch64-sve-linux-ptrace.h (aarch64_sve_set_vq): New declaration.
Alan Hayward [Mon, 15 Apr 2019 11:29:40 +0000 (12:29 +0100)]
AArch64 SVE: Check for vector length change when getting gdbarch
Override the thread_architecture method, similar to SPU. If the vector
length has changed, then find the arch using info, making sure the vector
length is passed down to the init routine.
In the init routine, ensure the arch has the correct vector length.
Example output. Program is stopped in thread 2, just before it calls prctl
to change the vector length
(gdb) info threads
Id Target Id Frame
1 Thread 0xffffbf6f4000 (LWP 3188) "sve_change" 0x0000ffffbf6ae130 in pthread_join ()
* 2 Thread 0xffffbf55e200 (LWP 3189) "sve_change" thread1 (arg=0xfeedface) at sve_change_size.c:28
(gdb) print $vg
$1 = 8
(gdb) print $z0.s.u
$2 = {
623191333,
623191333,
623191333,
623191333, 0 <repeats 12 times>}
(gdb) n
29 int ret = prctl(PR_SVE_SET_VL, vl/2);
(gdb) n
30 printf ("Changed: ret\n", ret);
(gdb) print $vg
$4 = 4
(gdb) print $z0.s.u
$5 = {
623191333,
623191333,
623191333,
623191333, 0, 0, 0, 0}
(gdb) thr 1
[Switching to thread 1 (Thread 0xffffbf6f4000 (LWP 3181))]
(gdb) print $vg
$6 = 8
(gdb) print $z0.s.u
$7 = {
623191333,
623191333,
623191333,
623191333, 0 <repeats 12 times>}
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::thread_architecture): Add override.
* aarch64-tdep.c (aarch64_gdbarch_init): Ensure different tdesc for
each VQ.
Alan Hayward [Mon, 15 Apr 2019 11:27:31 +0000 (12:27 +0100)]
AArch64: Tidy up aarch64_gdbarch_init
Move the lookup_by_info to the top of the function to avoid unnecessarily
creating a new feature when the gdbarch already exists.
Add some additional cleanups that have no functional effect.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_gdbarch_init): Move gdbarch lookup.
Andre Vieira [Mon, 15 Apr 2019 11:23:24 +0000 (12:23 +0100)]
[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
Andre Vieira [Mon, 15 Apr 2019 11:18:16 +0000 (12:18 +0100)]
[binutils, ARM, 15/16] Add support for VSCCLRM
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types.
These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list.
The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message.
The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests.
It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction.
Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
enumerators.
(parse_vfp_reg_list): Add new partial_match parameter. Set
*partial_match to TRUE if at least one element in the register list has
matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
register lists which expect VPR as last element in the list.
(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
prototype.
(s_arm_unwind_save_vfp): Likewise.
(enum operand_parse_code): New OP_VRSDVLST enumerator.
(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
Handle new OP_VRSDVLST case.
(do_t_vscclrm): New function.
(insns): New entry for VSCCLRM instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
for above instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
for above instructions.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
Add new entries for VSCCLRM instruction.
(print_insn_coprocessor): Handle new %C format control code.
Andre Vieira [Mon, 15 Apr 2019 11:14:38 +0000 (12:14 +0100)]
[opcodes, ARM, 14/16] Add mode availability to coprocessor table entries
The coprocessor_opcodes table is used both to share commonalities in coprocessor-related instructions and to avoid duplication between Arm and Thumb mode. However, some instructions do have differences between Arm and Thumb. For instance, vldmia allows PC as base register in Arm mode but not in Thumb mode.
In that very case the distinction becomes necessary because the encoding with PC as base register is used in Thumb mode to denote a VSCCLRM. It is thus necessary to distinguish what is Arm or Thumb only from what is shared. This patch adds an extra field to the coprocessor_opcodes table entries to indicate what mode is a given instruction available in. The print_insn_coprocessor then uses that field to determine if an entry that matched the mark and value checked should be allowed to match or not given the current mode.
ChangeLog entry is as follows:
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (enum isa): New enum.
(struct sopcode32): New structure.
(coprocessor_opcodes): change type of entries to struct sopcode32 and
set isa field of all current entries to ANY.
(print_insn_coprocessor): Change type of insn to struct sopcode32.
Only match an entry if its isa field allows the current mode.
Andre Vieira [Mon, 15 Apr 2019 11:07:20 +0000 (12:07 +0100)]
[binutils, ARM, 13/16] Add support for CLRM
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions.
In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators.
parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand.
Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function.
Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (enum reg_list_els): Define earlier and add
REGLIST_RN and REGLIST_CLRM enumerators.
(parse_reg_list): Add etype parameter to distinguish between regular
core register list and CLRM register list. Add logic to
recognize CLRM register list.
(parse_vfp_reg_list): Assert type is not for core register list.
(s_arm_unwind_save_core): Update call to parse_reg_list to new
prototype.
(enum operand_parse_code): Declare OP_CLRMLST enumerator.
(parse_operands): Update call to parse_reg_list to new prototype. Add
logic for OP_CLRMLST.
(encode_thumb2_ldmstm): Rename into ...
(encode_thumb2_multi): This. Add do_io parameter. Add logic to
encode CLRM and guard LDM/STM only code by do_io.
(do_t_ldmstm): Adapt to use encode_thumb2_multi.
(do_t_push_pop): Likewise.
(do_t_clrm): New function.
(insns): Define CLRM.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
CLRM.
(print_insn_thumb32): Add logic to print %n CLRM register list.
Andre Vieira [Mon, 15 Apr 2019 10:58:47 +0000 (11:58 +0100)]
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
Andre Vieira [Mon, 15 Apr 2019 10:53:25 +0000 (11:53 +0100)]
[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum.
ChangeLog entries are as follows:
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
Andre Vieira [Mon, 15 Apr 2019 10:46:54 +0000 (11:46 +0100)]
[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
Andre Vieira [Mon, 15 Apr 2019 10:42:10 +0000 (11:42 +0100)]
[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BFL instruction.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
(do_t_v8_1_branch): New switch case for bfl.
(insns): New instruction for bfl.
* testsuite/gas/arm/armv8_1-m-bfl.d: New.
* testsuite/gas/arm/armv8_1-m-bfl.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfl.s: New.
* testsuite/ld-arm/bfl.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfl.
Andre Vieira [Mon, 15 Apr 2019 10:37:51 +0000 (11:37 +0100)]
[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
Andre Vieira [Mon, 15 Apr 2019 10:29:14 +0000 (11:29 +0100)]
[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFX and BFLX instructions.
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
Arm register with r13 and r15 unpredictable.
(thumb32_opcodes): New instructions for bfx and bflx.
Andre Vieira [Mon, 15 Apr 2019 10:25:12 +0000 (11:25 +0100)]
[binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This patch adds the BF instruction.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bf.s: New.
* testsuite/ld-arm/bf.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instructions for bf.
Andre Vieira [Mon, 15 Apr 2019 10:18:57 +0000 (11:18 +0100)]
[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
Andre Vieira [Mon, 15 Apr 2019 10:12:57 +0000 (11:12 +0100)]
[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it
This patch is part of a series of patches to add support for ARMv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL,
BFLX, BFCSEL).
These are the first instructions in ARM that have more than one relocations in
them. Their external relocations can be found in the 'ELF for the Arm
Architecture - ABI 2019Q1' document on developer.arm.com
This is the second infrastructure patch that adds support to allow up to
3 relocations in an instruction. This is done by changing the reloc member of
struct arm_it to an array instead (relocs[3]). All the previous occurrences of
reloc can now to referring to relocs[0].
ChangeLog entries are as follows :
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro.
(arm_it): Member reloc renamed relocs and updated to an array.
Rest: Replace all occurrences of reloc to relocs[0].
Andre Vieira [Mon, 15 Apr 2019 10:06:30 +0000 (11:06 +0100)]
[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX,
BFCSEL). These are the first instructions in ARM that have more than one
relocations in them.
This is the first infrastructure patch that adds a new bfd_reloc_code_real enum
for the fallback branch offset.
This is common for all such instructions and needs to be resolvable by the
assembler.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
Andre Vieira [Mon, 15 Apr 2019 10:00:21 +0000 (11:00 +0100)]
[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline.
This patch also removes the fp-armv8 check from the half-precision move
instructions 'do_neon_movhf', as checking that the FP16 instructions extension
feature bit is enabled 'ARM_EXT2_FP16_INST' is enough.
gas/ChangeLog:
2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
(armv8_1m_main_ext_table): New extension table.
(arm_archs): Use the new extension table.
* doc/c-arm.texi: Add missing arch and document new extensions.
* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
* testsuite/gas/arm/armv8.1-m.main-hp.d: New.
Andre Vieira [Mon, 15 Apr 2019 09:54:42 +0000 (10:54 +0100)]
[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI
The patch is straightforward, it does the following:
- support the new Tag_CPU_arch build attribute value, ie.:
+ declare the new value
+ update all the asserts forcing logic to be reviewed for new
architectures
+ create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and
add mapping from Tag_CPU_arch to it
+ teach readelf about new Tag_CPU_arch value
- declare armv8.1-m.main as a supported architecture value
- define Armv8.1-M Mainline in terms of feature bits available
- tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature
bits available
- update architecture-specific logic in gas and bfd guarded by the
asserts mentioned above.
- tests for all the above
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
and update assert.
(using_thumb2): Likewise.
(using_thumb2_bl): Update assert.
(arch_has_arm_nop): Likewise.
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
*** binutils/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
*** include/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
(MAX_TAG_CPU_ARCH): Set value to above macro.
* opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
(ARM_AEXT_V8_1M_MAIN): Likewise.
(ARM_AEXT2_V8_1M_MAIN): Likewise.
(ARM_ARCH_V8_1M_MAIN): Likewise.
*** ld/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* testsuite/ld-arm/attr-merge-13.attr: New test.
* testsuite/ld-arm/attr-merge-13a.s: New test.
* testsuite/ld-arm/attr-merge-13b.s: New test.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
GDB Administrator [Mon, 15 Apr 2019 00:00:16 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Sun, 14 Apr 2019 00:01:01 +0000 (00:01 +0000)]
Automatic date update in version.in
Andrew Burgess [Thu, 11 Apr 2019 22:17:31 +0000 (23:17 +0100)]
sim: Use host not target byte order for merging and splitting values
When using writes to memory through a struct to merge and extract
multi-word value, it is the endianness of the host, not the target
that affects which order the component words need to be written into
the structure.
Of the 5 functions adjusted here 4 of them are unused. The 5th,
JOINSIDF will soon be used by the or1k target.
For or1k, simulated on x86-64, this change fixes this function so that
the correct bytes are now returned.
sim/common/ChangeLog:
* cgen-ops.h (SUBWORDXFSI): Compare HOST_BYTE_ORDER not
CURRENT_TARGET_BYTE_ORDER.
(SUBWORDTFSI): Likewise.
(JOINSIDF): Likewise.
(JOINSIXF): Likewise.
(JOINSITF): Likewise.
Matthew Fortune [Tue, 9 Apr 2019 20:40:00 +0000 (20:40 +0000)]
[MIPS] Add i6500 CPU and fix i6400 default ASEs
gas/
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
default ASEs for i6400.
* doc/c-mips.texi (-march): Document i6500.
* testsuite/gas/mips/elf_mach_i6400.d: New test.
* testsuite/gas/mips/elf_mach_i6500.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
Matthew Fortune [Tue, 9 Apr 2019 17:34:48 +0000 (10:34 -0700)]
[MIPS] Apply ASE information for the selected processor
GAS does not enable implicit ASEs for most MIPS processors.
The rework of option handling done as part of .module implementation
left the implicit ASE logic broken and default enabled ASEs for
most processors did not get applied. This patch ensures the ASE
information is carried forward to the point where it is required.
gas/
* config/tc-mips.c (mips_set_options) <init_ase>: New field.
(file_mips_opts, mips_opts) <init_ase>: Initialize new field.
(file_mips_check_options): Propagate initial ASE settings.
(mips_after_parse_args, parse_code_option): Track the initial
ASE settings for a CPU.
(s_mipsset): Restore the initial ASE settings when reverting
to the default arch.
* testsuite/gas/mips/elf_mach_p6600.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Alan Modra [Fri, 12 Apr 2019 11:02:57 +0000 (20:32 +0930)]
makefile dependencies for generated ld/e*.c
This patch modifies genscripts.sh to emit dependency info along with
the generated emulation e*.c files. This is done by a new source_sh
function that records its arg to a file (.deps/e*.Tc), using the
function whenever a shell script is sourced. Entries in the file are
made unique and written to .deps/e*.Pc. These files are then
included by the Makefile.
* Makefile.am (GENSCRIPTS): Pass LIB_PATH as a parameter. Add
DEPDIR parameter.
(ELF_DEPS, ELF_GEN_DEPS, ELF_X86_DEPS): Delete.
(ALL_EMULATION_SOURCES, ALL_64_EMULATION_SOURCES): Depend on
$GEN_DEPENDS.
(e*.c): Delete all dependencies, instead include dependencies
from $DEPDIR/*.Pc.
* Makefile.in: Regenerate.
* configure.ac (source_sh): Define and use function.
* configure: Regenerate.
* emulparams/aarch64cloudabib.sh, * emulparams/aarch64elf32b.sh,
* emulparams/aarch64elfb.sh, * emulparams/aarch64fbsdb.sh,
* emulparams/aarch64linux32b.sh, * emulparams/aarch64linuxb.sh,
* emulparams/arcelf.sh, * emulparams/arcelf_prof.sh,
* emulparams/arclinux.sh, * emulparams/arclinux_nps.sh,
* emulparams/arclinux_prof.sh, * emulparams/arcv2elf.sh,
* emulparams/arcv2elfx.sh, * emulparams/armelf_fbsd.sh,
* emulparams/armelf_linux_eabi.sh,
* emulparams/armelf_linux_fdpiceabi.sh,
* emulparams/armelf_nacl.sh, * emulparams/armelf_nbsd.sh,
* emulparams/armelf_vxworks.sh, * emulparams/armelfb.sh,
* emulparams/armelfb_fbsd.sh, * emulparams/armelfb_fuchsia.sh,
* emulparams/armelfb_linux.sh, * emulparams/armelfb_linux_eabi.sh,
* emulparams/armelfb_linux_fdpiceabi.sh,
* emulparams/armelfb_nacl.sh, * emulparams/armelfb_nbsd.sh,
* emulparams/armsymbian.sh, * emulparams/cskyelf_linux.sh,
* emulparams/elf32_sparc_sol2.sh,
* emulparams/elf32_sparc_vxworks.sh, * emulparams/elf32_tic6x_be.sh,
* emulparams/elf32_tic6x_elf_be.sh,
* emulparams/elf32_tic6x_elf_le.sh,
* emulparams/elf32_tic6x_linux_be.sh,
* emulparams/elf32_tic6x_linux_le.sh,
* emulparams/elf32_x86_64.sh, * emulparams/elf32_x86_64_nacl.sh,
* emulparams/elf32b4300.sh, * emulparams/elf32bfinfd.sh,
* emulparams/elf32bmipn32.sh, * emulparams/elf32bsmip.sh,
* emulparams/elf32btsmip.sh, * emulparams/elf32btsmip_fbsd.sh,
* emulparams/elf32btsmipn32.sh, * emulparams/elf32btsmipn32_fbsd.sh,
* emulparams/elf32ebmip.sh, * emulparams/elf32ebmipvxworks.sh,
* emulparams/elf32elmip.sh, * emulparams/elf32elmipvxworks.sh,
* emulparams/elf32frvfd.sh, * emulparams/elf32l4300.sh,
* emulparams/elf32lm32fd.sh, * emulparams/elf32lmip.sh,
* emulparams/elf32lppc.sh, * emulparams/elf32lppclinux.sh,
* emulparams/elf32lppcnto.sh, * emulparams/elf32lppcsim.sh,
* emulparams/elf32lr5900.sh, * emulparams/elf32lr5900n32.sh,
* emulparams/elf32lriscv.sh, * emulparams/elf32lriscv_ilp32.sh,
* emulparams/elf32lriscv_ilp32f.sh, * emulparams/elf32lsmip.sh,
* emulparams/elf32ltsmip.sh, * emulparams/elf32ltsmip_fbsd.sh,
* emulparams/elf32ltsmipn32.sh, * emulparams/elf32ltsmipn32_fbsd.sh,
* emulparams/elf32microblazeel.sh, * emulparams/elf32or1k_linux.sh,
* emulparams/elf32ppc.sh, * emulparams/elf32ppc_fbsd.sh,
* emulparams/elf32ppccommon.sh, * emulparams/elf32ppclinux.sh,
* emulparams/elf32ppcnto.sh, * emulparams/elf32ppcsim.sh,
* emulparams/elf32ppcvxworks.sh, * emulparams/elf32ppcwindiss.sh,
* emulparams/elf32tilegx_be.sh, * emulparams/elf64_ia64_fbsd.sh,
* emulparams/elf64_sparc_fbsd.sh, * emulparams/elf64_sparc_sol2.sh,
* emulparams/elf64alpha_fbsd.sh, * emulparams/elf64alpha_nbsd.sh,
* emulparams/elf64bmip-defs.sh, * emulparams/elf64bmip.sh,
* emulparams/elf64btsmip.sh, * emulparams/elf64btsmip_fbsd.sh,
* emulparams/elf64lppc.sh, * emulparams/elf64lriscv-defs.sh,
* emulparams/elf64lriscv.sh, * emulparams/elf64lriscv_lp64.sh,
* emulparams/elf64lriscv_lp64f.sh, * emulparams/elf64ltsmip.sh,
* emulparams/elf64ltsmip_fbsd.sh, * emulparams/elf64ppc.sh,
* emulparams/elf64ppc_fbsd.sh, * emulparams/elf64rdos.sh,
* emulparams/elf64tilegx_be.sh, * emulparams/elf_i386.sh,
* emulparams/elf_i386_be.sh, * emulparams/elf_i386_fbsd.sh,
* emulparams/elf_i386_ldso.sh, * emulparams/elf_i386_nacl.sh,
* emulparams/elf_i386_sol2.sh, * emulparams/elf_i386_vxworks.sh,
* emulparams/elf_iamcu.sh, * emulparams/elf_k1om.sh,
* emulparams/elf_k1om_fbsd.sh, * emulparams/elf_l1om.sh,
* emulparams/elf_l1om_fbsd.sh, * emulparams/elf_x86_64.sh,
* emulparams/elf_x86_64_cloudabi.sh,
* emulparams/elf_x86_64_fbsd.sh, * emulparams/elf_x86_64_nacl.sh,
* emulparams/elf_x86_64_sol2.sh, * emulparams/h8300helf.sh,
* emulparams/h8300helf_linux.sh, * emulparams/h8300hnelf.sh,
* emulparams/h8300self.sh, * emulparams/h8300self_linux.sh,
* emulparams/h8300snelf.sh, * emulparams/h8300sxelf.sh,
* emulparams/h8300sxelf_linux.sh, * emulparams/h8300sxnelf.sh,
* emulparams/hppanbsd.sh, * emulparams/hppaobsd.sh,
* emulparams/m32rlelf.sh, * emulparams/m32rlelf_linux.sh,
* emulparams/m68kelfnbsd.sh, * emulparams/mn10300.sh,
* emulparams/msp430X.sh, * emulparams/nds32belf.sh,
* emulparams/nds32belf16m.sh, * emulparams/nds32belf_linux.sh,
* emulparams/pjlelf.sh, * emulparams/ppclynx.sh,
* emulparams/score7_elf.sh, * emulparams/shelf_fd.sh,
* emulparams/shelf_linux.sh, * emulparams/shelf_nbsd.sh,
* emulparams/shelf_uclinux.sh, * emulparams/shelf_vxworks.sh,
* emulparams/shl.sh, * emulparams/shlelf.sh,
* emulparams/shlelf_fd.sh, * emulparams/shlelf_nbsd.sh,
* emulparams/shlelf_vxworks.sh: Use source_sh.
* genscripts.sh: Adjust for changed parameters. Emit dependencies
for e*.c to .deps/*.Pc.
(source_sh): New function, use it throughout to source scripts.
* genscrba.sh (source_em): Use source_sh.
Alan Modra [Fri, 12 Apr 2019 09:32:44 +0000 (19:02 +0930)]
ld TDIRS substitution
It is no longer true that autoconf/automake cannot substitute vars
with embedded new-lines.
* configure.ac (TDIRS): Build up tdirs in this variable and
AC_SUBST, also using AM_SUBST_NOTMAKE.
* configure: Regenerate.
* Makefile.am (DISTCLEANFILES): Remove tdirs.
* Makefile.in: Regenerate.
Andrew Burgess [Fri, 12 Apr 2019 23:54:16 +0000 (00:54 +0100)]
gdb: Fix failure in gdb.base/complex-parts.exp for x86-32
The x86-32 ABI specifies 96-bit long double, this was causing a
failure on the test gdb.base/complex-parts.exp.
The problem is that GDB tries to find a builtin floating point type of
the correct size in order to reuse the name of that type as the name
for the components of the complex type being built.
Previously GDB was only aware of floating point types sized 32, 64, or
128 bits. This patch teaches GDB how to handle 96 bit floating point
type.
gdb/ChangeLog:
* dwarf2read.c (dwarf2_init_complex_target_type): Handle complex
target types of size 96-bits, add some additional comments, and
check that the builtin type we found was the correct size.
GDB Administrator [Sat, 13 Apr 2019 00:00:35 +0000 (00:00 +0000)]
Automatic date update in version.in
John Darrington [Fri, 12 Apr 2019 16:39:01 +0000 (18:39 +0200)]
GAS: S12Z: Remove definition of macro TC_M68K.
gas/config:
* tc-s12z.h: Remove inappropriate macro definition.
John Darrington [Fri, 12 Apr 2019 16:39:01 +0000 (18:39 +0200)]
S12Z: opcodes: Replace "operator" with "optr".
opcodes/
* s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace operator with optr.
John Darrington [Fri, 12 Apr 2019 16:39:01 +0000 (18:39 +0200)]
GAS: tc-s12z.c: int -> bfd_boolean
Use bfd_boolean where appropriate.
Eli Zaretskii [Fri, 12 Apr 2019 12:35:57 +0000 (15:35 +0300)]
Another fix for GDB styling
gdb/ChangeLog:
2019-04-12 Eli Zaretskii <eliz@gnu.org>
* utils.c (prompt_for_continue): Don't restore the styling at the
end, as applied_style has the wrong value. This fixes styling in
long lists of file names that are interrupted by the "Continue?"
prompt.
Nick Clifton [Fri, 12 Apr 2019 12:15:21 +0000 (13:15 +0100)]
Fix thinko in linker documentation.
PR 24450
* ld.texi (Output Section Attributes): Add ALIGN_WITH_INPUT to
example of section attributes.
Alan Hayward [Mon, 8 Apr 2019 15:02:55 +0000 (16:02 +0100)]
Testsuite: Add gdbserver sysroot test
The local board file ensures that the sysroot is always set to load
files from the local filesystem.
Add a gdbserver test to explicitly test the sysroot set to both the
remote target and the local filesystem.
gdb/testsuite/ChangeLog:
* gdb.server/sysroot.c: New test.
* gdb.server/sysroot.exp: New file.
* lib/gdbserver-support.exp (gdb_target_cmd): Add additional text
matching param.
Andrew Burgess [Thu, 11 Apr 2019 22:51:48 +0000 (23:51 +0100)]
gdb: Remove LANG_MAGIC
The language_defn structure has an la_magic field, this used to be
used as a basic check that the language_defn structure had the
expected layout - at least the end of the structure was where we
expected it to be.
This feature only really makes sense if we imagine GDB dynamically
loading language support from dynamic libraries, where a version
mismatch might cause problems.
However, in current GDB language support is statically built into GDB,
and since this commit:
commit
47e77640be31fc1a4eb3718f594ed5fd0faff065
Date: Thu Jul 20 18:28:01 2017 +0100
Make language_def O(1)
the existing (if pointless) check of the la_magic field was removed.
There now appears to be no use of the la_magic field, and I propose
that we delete it.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* ada-lang.c (ada_language_defn): Remove use of LANG_MAGIC.
* c-lang.c (c_language_defn): Likewise.
(cplus_language_defn): Likewise.
(asm_language_defn): Likewise.
(minimal_language_defn): Likewise.
* d-lang.c (d_language_defn): Likewise.
* f-lang.c (f_language_defn): Likewise.
* go-lang.c (go_language_defn): Likewise.
* language.c (unknown_language_defn): Likewise.
(auto_language_defn): Likewise.
* language.h (struct language_defn): Remove la_magic field.
(LANG_MAGIC): Delete.
* m2-lang.c (m2_language_defn): Remove use of LANG_MAGIC.
* objc-lang.c (objc_language_defn): Likewise.
* opencl-lang.c (opencl_language_defn): Likewise.
* p-lang.c (pascal_language_defn): Likewise.
* rust-lang.c (rust_language_defn): Likewise.
GDB Administrator [Fri, 12 Apr 2019 00:00:26 +0000 (00:00 +0000)]
Automatic date update in version.in
Andrew Burgess [Sun, 7 Apr 2019 21:30:37 +0000 (22:30 +0100)]
gdb/riscv: Remove riscv_type_alignment function
Make use of the type_align function and remove riscv_type_alignment as
it is no longer needed. I tested this against a number of RV32 and
RV64 targets, and I also ran the tests with an assertion in place
checking that the old riscv_type_alignment function gives the same
answer as the common type_align function - it does, and all the tests
still pass.
gdb/ChangeLog:
* riscv-tdep.c (riscv_type_align): New function.
(riscv_type_alignment): Delete.
(riscv_arg_location): Use 'type_align'.
(riscv_gdbarch_init): Register riscv_type_align gdbarch function.
Andrew Burgess [Sat, 6 Apr 2019 10:02:04 +0000 (11:02 +0100)]
gdb: Fix alignment computation for structs with only static fields
The current code in gdbtypes.c:type_align incorrectly returns 0 as the
alignment for a structure containing only static fields. After this
patch the correct value of 1 is returned. The gdb.base/align.exp test
is extended to cover this case.
gdb/ChangeLog:
* gdbtypes.c (type_align): A struct with no non-static fields also
has alignment of 1.
gdb/testsuite/ChangeLog:
* gdb.base/align.exp: Extend test to cover structures containing
only static fields.
Andrew Burgess [Fri, 5 Apr 2019 12:50:19 +0000 (13:50 +0100)]
gdb/riscv: Handle empty C++ structs during argument passing
This commit resolves a large number of failures in the test script
gdb.base/infcall-nested-structs.exp which were caused by GDB (for
RISC-V) incorrectly handling empty C++ structures when preparing
arguments for a dummy call, or collecting a return value.
The issue is further complicated in that there was a bug in GCC, such
that in some cases GCC would generate incorrect code when passing a
small structure that contained empty sub-structures. This was fixed
in GCC trunk on 5-March-2019, so in order to see the best results with
this patch you'll need a recent version of GCC.
Anything that used to work should continue to work after this patch,
regardless of GCC version being used.
The fix in this commit is that GDB now pays more attention to the
offset of fields within a structure when preparing arguments as in C++
an empty structure has a non-zero size, this is an example:
struct s1 { struct s2 { } empty; int f; };
We previously assumed that 'f' was at offset 0 inside type 's1',
however this is not the case in C++ as 's2' has size 1, and with
alignment 'f' is likely at some even bigger offset inside 's1'.
gdb/ChangeLog:
* riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first
component to 0.
(riscv_struct_info::riscv_struct_info): Initialise m_offsets
member.
(riscv_struct_info::analyse): New implementation using new
analyse_inner member function.
(riscv_struct_info::field_offset): New member function.
(riscv_struct_info::m_offsets): New member variable.
(riscv_struct_info::analyse_inner): New private member function,
takes the old implementation of riscv_struct_info::analyse but
extended to track field offsets.
(riscv_call_arg_struct): Update the struct folding special cases
to handle cases where empty C++ structs, which are non-zero
length, are found.
(riscv_arg_location): Initialise the length of each location, a
non-zero length now indicates the location is in use.
(riscv_push_dummy_call): Allow for the first location having a
non-zero offset when setting up arguments.
(riscv_return_value): Likewise, but for return values.
Tom Tromey [Thu, 11 Apr 2019 19:00:48 +0000 (13:00 -0600)]
Make "msg" const in internal_vproblem
I noticed that the "msg" variable in internal_vproblem could be
"const". This seems like an improvement because it can wind up in
rodata.
Tested by rebuilding.
gdb/ChangeLog
2019-04-11 Tom Tromey <tromey@adacore.com>
* utils.c (internal_vproblem): Make "msg" const.
Max Filippov [Fri, 5 Apr 2019 00:06:57 +0000 (17:06 -0700)]
xtensa: gas: add relaxations tests
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/loop-relax-2.d: New test definition.
* testsuite/gas/xtensa/loop-relax.d: New test definition.
* testsuite/gas/xtensa/loop-relax.s: New test source.
* testsuite/gas/xtensa/text-section-literals-1a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-2a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-4.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4a.d: New test
definition.
Max Filippov [Fri, 5 Apr 2019 00:51:00 +0000 (17:51 -0700)]
xtensa: gas: convert tests to run_dump_tests
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/all.exp: Remove all expect-based
tests and all explicit run_dump_test / run_list_test
invocations. Add run_dump_tests for all .d files in the
test subdirectory.
* testsuite/gas/xtensa/entry_align.d: New test definition.
* testsuite/gas/xtensa/entry_align.l: New test output.
* testsuite/gas/xtensa/entry_misalign.d: New test definition.
* testsuite/gas/xtensa/entry_misalign2.d: New test definition.
* testsuite/gas/xtensa/j_too_far.d: New test definition.
* testsuite/gas/xtensa/j_too_far.l: New test output.
* testsuite/gas/xtensa/loop_align.d: New test definition.
* testsuite/gas/xtensa/loop_misalign.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
* testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
Max Filippov [Wed, 10 Apr 2019 08:18:01 +0000 (01:18 -0700)]
xtensa: gas: clean up literal management code
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has
no effect.
(get_literal_pool_location): Only search for the literal pool
when auto litpools is used, otherwise take one recorded in the
tc_segment_info_data.
(xtensa_assign_litpool_addresses): New function.
(xtensa_move_literals): Don't duplicate 'literal pool location
required...' error message. Call xtensa_assign_litpool_addresses.
Max Filippov [Mon, 8 Apr 2019 20:47:18 +0000 (13:47 -0700)]
xtensa: gas: put .literal_position at section start
Provide literal position at the beginning of each section for literal
space reserved by relaxations when text-section-literals or
auto-litpools options are used. Remove code that adds fill frag to the
literal section for every .literal_position directive to avoid creation
of empty literal sections.
Fix auto-litpools tests that got literal pool address changes.
gas/
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
(xtensa_mark_literal_pool_location): Don't add fill frag to literal
section that records literal pool location.
(md_begin): Call xtensa_mark_literal_pool_location when text
section literals or auto litpools are used.
(xtensa_elf_section_change_hook): Call
xtensa_mark_literal_pool_location when text section literals or
auto litpools are used, there's no literal pool location defined
for the current section and it's not .init or .fini.
* testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
* testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
* testsuite/gas/xtensa/auto-litpools.d: Likewise.
Faraz Shahbazker [Tue, 2 Apr 2019 20:17:16 +0000 (20:17 +0000)]
ld: Add --no-print-map-discarded option
Add a new option to disable the listing of discarded sections
in map file output. The use case stems from a large application
built with -ffunction-sections --gc-sections where the list of
discarded sections blows up the map file output. The default
behaviour remains to print discarded sections, but the new option
allows us to disable it.
ld/
* NEWS: Mention new option --no-print-map-discarded.
* ld.h (ld_config_type) <print_map_discarded>: New field.
* ldlang.c (lang_map): Conditionally output discarded sections
in map files based on configuration option.
* ldlex.h (option_values) <OPTION_PRINT_MAP_DISCARDED,
OPTION_NO_PRINT_MAP_DISCARDED>: New.
* ldmain.c (main): Enabled print_map_discarded by default.
* lexsup.c (ld_options): Add new command-line options.
(parse_args) <OPTION_NO_PRINT_MAP_DISCARDED,
OPTION_PRINT_MAP_DISCARDED>: New cases.
* ld.texi: Document new options.
* testsuite/ld-gc/gc.exp: Add new test.
* testsuite/ld-gc/skip-map-discarded.s: New file.
* testsuite/ld-gc/skip-map-discarded.d: New file.
* testsuite/ld-gc/skip-map-discarded.map: New file.
Tom de Vries [Thu, 11 Apr 2019 17:13:05 +0000 (19:13 +0200)]
[gdb/testsuite] Add cc-with-dwz.exp and cc-with-dwz-m.exp
We can use CC_WITH_TWEAKS_FLAGS when cd-ing into the gdb build subdir and
invoking make check:
...
$ cd $objdir/gdb
$ make check \
RUNTESTFLAGS='--target_board=cc-with-tweaks' \
CC_WITH_TWEAKS_FLAGS='-z'
...
But when cd-ing into the top-level build dir and invoking make check-gdb
instead:
...
$ cd $objdir
$ make check-gdb \
RUNTESTFLAGS='--target_board=cc-with-tweaks' \
CC_WITH_TWEAKS_FLAGS='-z'
...
using CC_WITH_TWEAKS_FLAGS has no effect, because CC_WITH_TWEAKS_FLAGS is not
passed down from the top level Makefile.
Add cc-with-dwz.exp and cc-with-dwz-m.exp, that don't require
CC_WITH_TWEAKS_FLAGS to be set in the make invocation, allowing us to run these
test configurations from the toplevel build dir:
...
$ cd $objdir
$ make check-gdb \
RUNTESTFLAGS='--target_board=cc-with-dwz'
...
Tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2019-04-11 Tom de Vries <tdevries@suse.de>
* boards/cc-with-dwz-m.exp: New file.
* boards/cc-with-dwz.exp: New file.
* boards/cc-with-tweaks.exp: Note that check-gdb doesn't work.
H.J. Lu [Thu, 11 Apr 2019 15:18:51 +0000 (08:18 -0700)]
x86: Add -z cet-report=[none|warning|error]
Add -z cet-report=[none|warning|error] to report the missing Intel
Indirect Branch Tracking (IBT) and Shadow Stack (SHSTK) properties
in input .note.gnu.property section. -z cet-report=none, which is
the default, will make the linker not report missing properties in
input files. -z cet-report=warning will make the linker issue a
warning for missing properties in input files. -z cet-report=error
will make the linker issue an error for missing properties in input
files. Note that -z ibt will turn off the missing IBT property report
and -z shstk will turn off the missing SHSTK property report.
Supported for Linux/i386 and Linux/x86_64.
bfd/
* elf-linker-x86.h (elf_x86_cet_report): New.
(elf_linker_x86_params): Add cet_report.
* elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): Report
missing IBT and SHSTK properties if needed.
ld/
* ld.texi: Document -z cet-report=[none|warning|error].
* emulparams/cet.sh: Add -z cet-report=[none|warning|error].
* testsuite/ld-i386/i386.exp: Run -z cet-report=[warning|error]
tests.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/property-x86-cet1.d: New file.
* testsuite/ld-i386/property-x86-cet2a.d: Likewise.
* testsuite/ld-i386/property-x86-cet2b.d: Likewise.
* testsuite/ld-i386/property-x86-cet3a.d: Likewise.
* testsuite/ld-i386/property-x86-cet3b.d: Likewise.
* testsuite/ld-i386/property-x86-cet4a.d: Likewise.
* testsuite/ld-i386/property-x86-cet4b.d: Likewise.
* testsuite/ld-i386/property-x86-cet5a.d: Likewise.
* testsuite/ld-i386/property-x86-cet5b.d: Likewise.
* testsuite/ld-i386/property-x86-cet6.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet.s: Likewise.
* testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet1.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet2b.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet4a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet4a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet4b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet4b.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5a.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet5b.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet6-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-cet6.d: Likewise.
H.J. Lu [Thu, 11 Apr 2019 14:53:55 +0000 (07:53 -0700)]
Add PR ld/24436 to ChangeLog entry
H.J. Lu [Thu, 11 Apr 2019 13:52:03 +0000 (06:52 -0700)]
ld: Add -static-pie tests
Add -static-pie tests for DT_INIT_ARRAY, DT_FINI_ARRAY, DT_PREINIT_ARRAY
and IFUNC.
* testsuite/config/default.exp (STATIC_PIE_LDFLAGS): New. Set
to "-static-pie" if target compiler supports it.
* testsuite/ld-elf/elf.exp: Run -static-pie tests if
$STATIC_PIE_LDFLAGS isn't empty.
* testsuite/ld-ifunc/ifunc.exp: Likewise.
H.J. Lu [Thu, 11 Apr 2019 13:44:53 +0000 (06:44 -0700)]
Check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry
Instead of BFD_ASSERT (h != NULL) with
ld: BFD ... assertion fail .../bfd/elf64-x86-64.c:2562
ld: bad.o: invalid string offset
50331648 >= 371 for section `nterp'
check corrupt VTENTRY entry in bfd_elf_gc_record_vtentry with
ld: bad.o: section 'g': corrupt VTENTRY entry
* elf-m10300.c (mn10300_elf_check_relocs): Remove BFD_ASSERT of
"h != NULL". Don't check "h != NULL" before calling.
bfd_elf_gc_record_vtentry.
* elf32-arm.c (elf32_arm_check_relocs): Likewise.
* elf32-bfin.c (bfin_check_relocs): Likewise.
* elf32-cris.c (cris_elf_check_relocs): Likewise.
* elf32-csky.c (csky_elf_check_relocs): Likewise.
* elf32-d10v.c (elf32_d10v_check_relocs): Likewise.
* elf32-dlx.c (elf32_dlx_check_relocs): Likewise.
* elf32-fr30.c (fr30_elf_check_relocs): Likewise.
* elf32-frv.c (elf32_frv_check_relocs): Likewise.
* elf32-hppa.c (elf32_hppa_check_relocs): Likewise.
* elf32-i386.c (elf_i386_check_relocs): Likewise.
* elf32-iq2000.c (iq2000_elf_check_relocs): Likewise.
* elf32-m32r.c (m32r_elf_check_relocs): Likewise.
* elf32-m68hc1x.c (elf32_m68hc11_check_relocs): Likewise.
* elf32-m68k.c (elf_m68k_check_relocs): Likewise.
* elf32-mcore.c (mcore_elf_check_relocs): Likewise.
* elf32-metag.c (elf_metag_check_relocs): Likewise.
* elf32-or1k.c (or1k_elf_check_relocs): Likewise.
* elf32-ppc.c (ppc_elf_check_relocs): Likewise.
* elf32-s390.c (elf_s390_check_relocs): Likewise.
* elf32-sh.c (sh_elf_check_relocs): Likewise.
* elf32-v850.c (v850_elf_check_relocs): Likewise.
* elf32-vax.c (elf_vax_check_relocs): Likewise.
* elf32-xstormy16.c (xstormy16_elf_check_relocs): Likewise.
* elf32-xtensa.c (elf_xtensa_check_relocs): Likewise.
* elf64-mmix.c (mmix_elf_check_relocs): Likewise.
* elf64-ppc.c (ppc64_elf_check_relocs): Likewise.
* elf64-s390.c (elf_s390_check_relocs): Likewise.
* elf64-x86-64.c (elf_s390_check_relocs): Likewise.
* elfxx-mips.c (_bfd_mips_elf_check_relocs): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise.
* elflink.c (bfd_elf_gc_record_vtinherit): Check for corrupt
VTENTRY entry.
Alan Modra [Thu, 11 Apr 2019 10:12:31 +0000 (19:42 +0930)]
PR24435, buffer overflow reading dynamic entries
PR 24435
* elflink.c (elf_link_add_object_symbols): Don't read partial
dynamic entries from fuzzed objects.
Tamar Christina [Thu, 11 Apr 2019 10:27:28 +0000 (11:27 +0100)]
AArch64: When DF_BIND_NOW don't use TLSDESC GOT value.
When using DF_BIND_NOW on AArch64 we don't reserve the GOT slot for a TLSDESC,
but we still emitted DT_TLSDESC_GOT and DT_TLSDESC_PLT. This caused random
memory corruption as the "special" value of (bfd_vma)-1 would be set for
dt_tlsdesc_got.
Since we don't have a value of dt_tlsdesc_got I also don't emit DT_TLSDESC_PLT
now becuase it would point to an incomplete PLT. To be able to write the PLT
entry DT_TLSDESC_GOT is needed and since we don't have one we can't write the
PLT entry either.
It is my understanding that GLIBC doesn't need these two entries when not lazy
loading. Conversely AArch32 does not reserve neither the GOT not the PLT slot
when doing DF_BIND_NOW.
AArch32 does not need these checks because these values are initialized to 0
and so the if (...) checks don't pass, but on AArch64 these are initialized
to (bfd_vma)-1 and thus we need some extra checks.
bfd/ChangeLog:
PR ld/24302
* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Don't emit
DT_TLSDESC_GOT and DT_TLSDESC_PLT when DF_BIND_NOW.
(elfNN_aarch64_finish_dynamic_sections): Don't write PLT if DF_BIND_NOW.
ld/ChangeLog:
PR ld/24302
* testsuite/ld-aarch64/aarch64-elf.exp: Add new test.
* testsuite/ld-aarch64/tls-relax-gdesc-le-now.d: New test.
Sudakshina Das [Thu, 11 Apr 2019 09:19:37 +0000 (10:19 +0100)]
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions
This patch updates the Store allocation tags instructions in
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
All of these instructions have an updated register operand (Xt -> <Xt|SP>)
- STG <Xt|SP>, [<Xn|SP>, #<simm>]
- STG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STG <Xt|SP>, [<Xn|SP>], #<simm>
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]
- STZG <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZG <Xt|SP>, [<Xn|SP>], #<simm>
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]
- ST2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- ST2G <Xt|SP>, [<Xn|SP>], #<simm>
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]
- STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
- STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has
the same field as FLD_Rt but follows other semantics of Rn_SP.
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** include/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_print_operand): Add case for
AARCH64_OPND_Rt_SP.
(verify_constraints): Likewise.
* aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
(struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
to accept Rt|SP as first operand.
(AARCH64_OPERANDS): Add new Rt_SP.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Sudakshina Das [Thu, 11 Apr 2019 09:13:23 +0000 (10:13 +0100)]
[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction
This patch adds the new LDGM/STGM instructions of the
Armv8.5-A Memory Tagging Extension. This is part of the changes
that have been introduced recently in the 00bet10 release
The instructions are as follows:
LDGM Xt, [<Xn|SP>]
STGM Xt, [<Xn|SP>]
*** gas/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
Alan Hayward [Wed, 10 Apr 2019 14:58:27 +0000 (15:58 +0100)]
AArch64: Ensure regcache is reset between tests
A recent change made the AArch64 self tests resuse the saved regs
cache, rather than creating a new one. Ensure it is reset to default
values between tests.
Do this by splitting the reset functionality from trad_frame_alloc_saved_regs
into a new function.
Fixes selftest on AArch64.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_analyze_prologue_test): Reset saved regs.
* trad-frame.c (trad_frame_reset_saved_regs): New function.
(trad_frame_alloc_saved_regs): Call trad_frame_reset_saved_regs.
* trad-frame.h (trad_frame_reset_saved_regs): New declaration.
H.J. Lu [Thu, 11 Apr 2019 01:36:05 +0000 (18:36 -0700)]
ld: Don't define __rel[a]_iplt_start/__rel[a]_iplt_end in PIE
__rel[a]_iplt_start and __rel[a]_iplt_end are defined to handle IFUNC in
static executables. For PIE, since IFUNC is handled as the part of the
normal dynamic relocation processing, there is no need to define these
symbols in PIE.
* scripttempl/elf.sc (CREATE_PIC): New. Set for CREATE_SHLIB or
CREATE_PIE.
(__rel_iplt_start): Don't define for CREATE_PIC.
(__rel_iplt_end): Likewise.
(__rela_iplt_start): Likewise.
(__rela_iplt_end): Likewise.
Kevin Buettner [Sat, 16 Mar 2019 19:40:01 +0000 (12:40 -0700)]
Fix amd64->i386 linux syscall restart problem
This commit fixes some failures in gdb.base/interrupt.exp
when debugging a 32-bit i386 linux inferior from an amd64 host.
When running the following test...
make check RUNTESTFLAGS="--target_board unix/-m32 interrupt.exp"
... without this commit, I see the following output:
FAIL: gdb.base/interrupt.exp: continue (the program exited)
FAIL: gdb.base/interrupt.exp: echo data
FAIL: gdb.base/interrupt.exp: Send Control-C, second time
FAIL: gdb.base/interrupt.exp: signal SIGINT (the program is no longer running)
ERROR: Undefined command "".
ERROR: GDB process no longer exists
=== gdb Summary ===
When the test is run with this commit in place, we see 12 passes
instead. This is the desired behavior.
Analysis:
On Linux, when a syscall is interrupted by a signal, the syscall
may return -ERESTARTSYS when a signal occurs. Doing so indicates that
the syscall is restartable. Then, depending on settings associated
with the signal handler, and after the signal handler is called, the
kernel can then either return -EINTR or can cause the syscall to be
restarted. In this discussion, we are concerned with the latter
case.
On i386, the kernel returns this status via the EAX register.
When debugging a 32-bit (i386) process from a 64-bit (amd64)
GDB, the debugger fetches 64-bit registers even though the
process being debugged is 32-bit. Since we're debugging a 32-bit
target, only 32 bits are being saved in the register cache.
Now, ideally, GDB would save all 64-bits in the regcache and
then would be able to restore those same values when it comes
time to continue the target. I've looked into doing this, but
it's not easy and I don't see many benefits to doing so. One
benefit, however, would be that EAX would appear as a negative
value for doing syscall restarts.
At the moment, GDB is setting the high 32 bits of RAX (and other
registers too) to 0. So, when GDB restores EAX just prior to
a syscall restart, the high 32 bits of RAX are zeroed, thus making
it look like a positive value. For this particular purpose, we
need to sign extend EAX so that RAX will appear as a negative
value when EAX is set to -ERESTARTSYS. This in turn will cause
the signal handling code in the kernel to recognize -ERESTARTSYS
which will in turn cause the syscall to be restarted.
This commit is based on work by Jan Kratochvil from 2009:
https://sourceware.org/ml/gdb-patches/2009-11/msg00592.html
Jan's patch had the sign extension code in amd64-nat.c. Several
other native targets make use of this code, so it seemed better
to move the sign extension code to a linux specific file. I
also added similar code to gdbserver.
Another approach is to fix the problem in the kernel. Hui Zhu
tried to get a fix into the kernel back in 2014, but it was not
accepted. Discussion regarding this approach may be found here:
https://lore.kernel.org/patchwork/patch/457841/
Even if a fix were to be put into the kernel, we'd still need
some kind of fix in GDB in order to support older kernels.
Finally, I'll note that Fedora has been carrying a similar patch for
at least nine years. Other distributions, including RHEL and CentOS
have picked up this change and have been using it too.
gdb/ChangeLog:
* amd64-linux-nat.c (amd64_linux_collect_native_gregset): New
function.
(fill_gregset): Call amd64_linux_collect_native_gregset instead
of amd64_collect_native_gregset.
(amd64_linux_nat_target::store_registers): Likewise.
gdb/gdbserver/ChangeLog:
* linux-x86-low.c (x86_fill_gregset): Sign extend EAX value
when using a 64-bit gdbserver.
GDB Administrator [Thu, 11 Apr 2019 00:00:28 +0000 (00:00 +0000)]
Automatic date update in version.in
git://git.ipfire.org / thirdparty / binutils-gdb.git / log