[people/ms/u-boot.git] / board / ti / am335x / board.c

/*
 * board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;

/* MII mode defines */
#define MII_MODE_ENABLE		0x0
#define RGMII_MODE_ENABLE	0x3A

/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN		7

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

static struct am335x_baseboard_id __attribute__((section (".data"))) header;

static inline int board_is_bone(void)
{
	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
}

static inline int board_is_bone_lt(void)
{
	return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
}

static inline int board_is_evm_sk(void)
{
	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}

static inline int board_is_idk(void)
{
	return !strncmp(header.config, "SKU#02", 6);
}

static int __maybe_unused board_is_gp_evm(void)
{
	return !strncmp("A33515BB", header.name, 8);
}

int board_is_evm_15_or_later(void)
{
	return (!strncmp("A33515BB", header.name, 8) &&
		strncmp("1.5", header.version, 3) <= 0);
}

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(void)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		puts("Could not probe the EEPROM; something fundamentally "
			"wrong on the I2C bus.\n");
		return -ENODEV;
	}

	/* read the eeprom using i2c */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
							sizeof(header))) {
		puts("Could not read the EEPROM; something fundamentally"
			" wrong on the I2C bus.\n");
		return -EIO;
	}

	if (header.magic != 0xEE3355AA) {
		/*
		 * read the eeprom using i2c again,
		 * but use only a 1 byte address
		 */
		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
					(uchar *)&header, sizeof(header))) {
			puts("Could not read the EEPROM; something "
				"fundamentally wrong on the I2C bus.\n");
			return -EIO;
		}

		if (header.magic != 0xEE3355AA) {
			printf("Incorrect magic number (0x%x) in EEPROM\n",
					header.magic);
			return -EINVAL;
		}
	}

	return 0;
}

#ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr2_data = {
	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
			  (MT47H128M16RT25E_RD_DQS<<20) |
			  (MT47H128M16RT25E_RD_DQS<<10) |
			  (MT47H128M16RT25E_RD_DQS<<0)),
	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
			  (MT47H128M16RT25E_WR_DQS<<20) |
			  (MT47H128M16RT25E_WR_DQS<<10) |
			  (MT47H128M16RT25E_WR_DQS<<0)),
	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr2_cmd_ctrl_data = {
	.cmd0csratio = MT47H128M16RT25E_RATIO,
	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd1csratio = MT47H128M16RT25E_RATIO,
	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd2csratio = MT47H128M16RT25E_RATIO,
	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};

static const struct emif_regs ddr2_emif_reg_data = {
	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};

static const struct ddr_data ddr3_data = {
	.datardsratio0 = MT41J128MJT125_RD_DQS,
	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct ddr_data ddr3_beagleblack_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct ddr_data ddr3_evm_data = {
	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = MT41J128MJT125_RATIO,
	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd1csratio = MT41J128MJT125_RATIO,
	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd2csratio = MT41J128MJT125_RATIO,
	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	.cmd0csratio = MT41J512M8RH125_RATIO,
	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd1csratio = MT41J512M8RH125_RATIO,
	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd2csratio = MT41J512M8RH125_RATIO,
	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	.zq_config = MT41J128MJT125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

static struct emif_regs ddr3_evm_emif_reg_data = {
	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	.zq_config = MT41J512M8RH125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};
#endif

/*
 * early system init of muxing and clocks.
 */
void s_init(void)
{
	/*
	 * Save the boot parameters passed from romcode.
	 * We cannot delay the saving further than this,
	 * to prevent overwrites.
	 */
#ifdef CONFIG_SPL_BUILD
	save_omap_boot_params();
#endif

	/* WDT1 is already running when the bootloader gets control
	 * Disable it to avoid "random" resets
	 */
	writel(0xAAAA, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;
	writel(0x5555, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;

#ifdef CONFIG_SPL_BUILD
	/* Setup the PLLs and the clocks for the peripherals */
	pll_init();

	/* Enable RTC32K clock */
	rtc32k_enable();

#ifdef CONFIG_SERIAL1
	enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
	enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
	enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
	enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
	enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
	enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */

	uart_soft_reset();

	gd = &gdata;

	preloader_console_init();

	/* Initalize the board header */
	enable_i2c0_pin_mux();
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	if (read_eeprom() < 0)
		puts("Could not get board ID.\n");

	enable_board_pin_mux(&header);
	if (board_is_evm_sk()) {
		/*
		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
		 * This is safe enough to do on older revs.
		 */
		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	}

	if (board_is_evm_sk())
		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
	else if (board_is_bone_lt())
		config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
			   &ddr3_beagleblack_data,
			   &ddr3_beagleblack_cmd_ctrl_data,
			   &ddr3_beagleblack_emif_reg_data, 0);
	else if (board_is_evm_15_or_later())
		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
	else
		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
#endif
}

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	if (read_eeprom() < 0)
		puts("Could not get board ID.\n");

	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;

	gpmc_init();

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	char safe_string[HDR_NAME_LEN + 1];

	/* Now set variables based on the header. */
	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	safe_string[sizeof(header.name)] = 0;
	setenv("board_name", safe_string);

	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	safe_string[sizeof(header.version)] = 0;
	setenv("board_rev", safe_string);
#endif

	return 0;
}
#endif

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_id		= 0,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_id		= 1,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	int rv, n = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

#ifdef CONFIG_DRIVER_TI_CPSW
	if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
		writel(MII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_MII;
	} else {
		writel(RGMII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_RGMII;
	}

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;
#endif

	/*
	 *
	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
	 * operating points.  So we must set the TX clock delay feature
	 * in the AR8051 PHY.  Since we only support a single ethernet
	 * device in U-Boot, we only do this for the first instance.
	 */
#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
#define AR8051_PHY_DEBUG_DATA_REG	0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
#define AR8051_RGMII_TX_CLK_DLY		0x100

	if (board_is_evm_sk() || board_is_gp_evm()) {
		const char *devname;
		devname = miiphy_get_current_dev();

		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
				AR8051_DEBUG_RGMII_CLK_DLY_REG);
		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
				AR8051_RGMII_TX_CLK_DLY);
	}
#endif
#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
	if (is_valid_ether_addr(mac_addr))
		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);

	rv = usb_eth_initialize(bis);
	if (rv < 0)
		printf("Error %d registering USB_ETHER\n", rv);
	else
		n += rv;
#endif
	return n;
}
#endif
Commit	Line	Data
e363426e PK	1	/*
	2	* board.c
	3	*
	4	* Board functions for TI AM335X based boards
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <common.h>
	20	#include <errno.h>
	21	#include <spl.h>
	22	#include <asm/arch/cpu.h>
	23	#include <asm/arch/hardware.h>
	24	#include <asm/arch/omap.h>
	25	#include <asm/arch/ddr_defs.h>
	26	#include <asm/arch/clock.h>
	27	#include <asm/arch/gpio.h>
	28	#include <asm/arch/mmc_host_def.h>
	29	#include <asm/arch/sys_proto.h>
	30	#include <asm/io.h>
	31	#include <asm/emif.h>
	32	#include <asm/gpio.h>
	33	#include <i2c.h>
	34	#include <miiphy.h>
	35	#include <cpsw.h>
	36	#include "board.h"
	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	static struct wd_timer wdtimer = (struct wd_timer )WDT_BASE;
e363426e PK	41
	42	/* MII mode defines */
	43	#define MII_MODE_ENABLE 0x0
cfd4ff6f	44	#define RGMII_MODE_ENABLE 0x3A
e363426e PK	45
	46	/* GPIO that controls power to DDR on EVM-SK */
	47	#define GPIO_DDR_VTT_EN 7
	48
	49	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	50
	51	static struct am335x_baseboard_id __attribute__((section (".data"))) header;
	52
	53	static inline int board_is_bone(void)
	54	{
	55	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
	56	}
	57
	58	static inline int board_is_bone_lt(void)
	59	{
	60	return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
	61	}
	62
	63	static inline int board_is_evm_sk(void)
	64	{
	65	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
	66	}
	67
a956bdcb MF	68	static inline int board_is_idk(void)
	69	{
	70	return !strncmp(header.config, "SKU#02", 6);
	71	}
	72
98bc1228	73	static int __maybe_unused board_is_gp_evm(void)
1634e969 TR	74	{
	75	return !strncmp("A33515BB", header.name, 8);
	76	}
	77
13526f71 JL	78	int board_is_evm_15_or_later(void)
	79	{
	80	return (!strncmp("A33515BB", header.name, 8) &&
	81	strncmp("1.5", header.version, 3) <= 0);
	82	}
	83
e363426e PK	84	/*
	85	* Read header information from EEPROM into global structure.
	86	*/
	87	static int read_eeprom(void)
	88	{
	89	/* Check if baseboard eeprom is available */
	90	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	91	puts("Could not probe the EEPROM; something fundamentally "
	92	"wrong on the I2C bus.\n");
	93	return -ENODEV;
	94	}
	95
	96	/* read the eeprom using i2c */
	97	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
	98	sizeof(header))) {
	99	puts("Could not read the EEPROM; something fundamentally"
	100	" wrong on the I2C bus.\n");
	101	return -EIO;
	102	}
	103
	104	if (header.magic != 0xEE3355AA) {
	105	/*
	106	* read the eeprom using i2c again,
	107	* but use only a 1 byte address
	108	*/
	109	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
	110	(uchar *)&header, sizeof(header))) {
	111	puts("Could not read the EEPROM; something "
	112	"fundamentally wrong on the I2C bus.\n");
	113	return -EIO;
	114	}
	115
	116	if (header.magic != 0xEE3355AA) {
	117	printf("Incorrect magic number (0x%x) in EEPROM\n",
	118	header.magic);
	119	return -EINVAL;
	120	}
	121	}
	122
	123	return 0;
	124	}
	125
e363426e	126	#ifdef CONFIG_SPL_BUILD
c00f69db	127	static const struct ddr_data ddr2_data = {
c7d35bef PK	128	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) \|
	129	(MT47H128M16RT25E_RD_DQS<<20) \|
	130	(MT47H128M16RT25E_RD_DQS<<10) \|
	131	(MT47H128M16RT25E_RD_DQS<<0)),
	132	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) \|
	133	(MT47H128M16RT25E_WR_DQS<<20) \|
	134	(MT47H128M16RT25E_WR_DQS<<10) \|
	135	(MT47H128M16RT25E_WR_DQS<<0)),
	136	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) \|
	137	(MT47H128M16RT25E_PHY_WRLVL<<20) \|
	138	(MT47H128M16RT25E_PHY_WRLVL<<10) \|
	139	(MT47H128M16RT25E_PHY_WRLVL<<0)),
	140	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) \|
	141	(MT47H128M16RT25E_PHY_GATELVL<<20) \|
	142	(MT47H128M16RT25E_PHY_GATELVL<<10) \|
	143	(MT47H128M16RT25E_PHY_GATELVL<<0)),
	144	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) \|
	145	(MT47H128M16RT25E_PHY_FIFO_WE<<20) \|
	146	(MT47H128M16RT25E_PHY_FIFO_WE<<10) \|
	147	(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	148	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) \|
	149	(MT47H128M16RT25E_PHY_WR_DATA<<20) \|
	150	(MT47H128M16RT25E_PHY_WR_DATA<<10) \|
	151	(MT47H128M16RT25E_PHY_WR_DATA<<0)),
	152	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
c00f69db PK	153	.datadldiff0 = PHY_DLL_LOCK_DIFF,
c00f69db PK	154	};
e363426e	155
c00f69db	156	static const struct cmd_control ddr2_cmd_ctrl_data = {
c7d35bef PK	157	.cmd0csratio = MT47H128M16RT25E_RATIO,
	158	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	159	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	160
c7d35bef PK	161	.cmd1csratio = MT47H128M16RT25E_RATIO,
	162	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	163	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	164
c7d35bef PK	165	.cmd2csratio = MT47H128M16RT25E_RATIO,
	166	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	167	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db PK	168	};
	169
	170	static const struct emif_regs ddr2_emif_reg_data = {
c7d35bef PK	171	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	172	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	173	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	174	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	175	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	176	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
c00f69db PK	177	};
	178
	179	static const struct ddr_data ddr3_data = {
c7d35bef PK	180	.datardsratio0 = MT41J128MJT125_RD_DQS,
	181	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	182	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	183	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
c00f69db PK	184	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	185	};
	186
c7ba18ad TR	187	static const struct ddr_data ddr3_beagleblack_data = {
	188	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	189	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	190	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	191	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	192	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	193	};
	194
13526f71 JL	195	static const struct ddr_data ddr3_evm_data = {
	196	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	197	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	198	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	199	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
	200	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	201	};
	202
c00f69db	203	static const struct cmd_control ddr3_cmd_ctrl_data = {
c7d35bef PK	204	.cmd0csratio = MT41J128MJT125_RATIO,
	205	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	206	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	207
c7d35bef PK	208	.cmd1csratio = MT41J128MJT125_RATIO,
	209	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	210	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	211
c7d35bef PK	212	.cmd2csratio = MT41J128MJT125_RATIO,
	213	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	214	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db PK	215	};
c00f69db PK	216
c7ba18ad TR	217	static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
	218	.cmd0csratio = MT41K256M16HA125E_RATIO,
	219	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	220	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	221
	222	.cmd1csratio = MT41K256M16HA125E_RATIO,
	223	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	224	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	225
	226	.cmd2csratio = MT41K256M16HA125E_RATIO,
	227	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
	228	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	229	};
	230
13526f71 JL	231	static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	232	.cmd0csratio = MT41J512M8RH125_RATIO,
	233	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	234	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	235
	236	.cmd1csratio = MT41J512M8RH125_RATIO,
	237	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	238	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	239
	240	.cmd2csratio = MT41J512M8RH125_RATIO,
	241	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	242	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	243	};
	244
c00f69db	245	static struct emif_regs ddr3_emif_reg_data = {
c7d35bef PK	246	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	247	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	248	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	249	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	250	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	251	.zq_config = MT41J128MJT125_ZQ_CFG,
59dcf970 VH	252	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY \|
59dcf970 VH	253	PHY_EN_DYN_PWRDN,
c00f69db	254	};
13526f71	255
c7ba18ad TR	256	static struct emif_regs ddr3_beagleblack_emif_reg_data = {
	257	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	258	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	259	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	260	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	261	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	262	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	263	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	264	};
	265
13526f71 JL	266	static struct emif_regs ddr3_evm_emif_reg_data = {
	267	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	268	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	269	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	270	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	271	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	272	.zq_config = MT41J512M8RH125_ZQ_CFG,
59dcf970 VH	273	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY \|
59dcf970 VH	274	PHY_EN_DYN_PWRDN,
13526f71	275	};
c00f69db	276	#endif
e363426e PK	277
	278	/*
	279	* early system init of muxing and clocks.
	280	*/
	281	void s_init(void)
	282	{
4596dcc1 TR	283	/*
	284	* Save the boot parameters passed from romcode.
	285	* We cannot delay the saving further than this,
	286	* to prevent overwrites.
	287	*/
	288	#ifdef CONFIG_SPL_BUILD
	289	save_omap_boot_params();
	290	#endif
	291
e363426e PK	292	/* WDT1 is already running when the bootloader gets control
	293	* Disable it to avoid "random" resets
	294	*/
	295	writel(0xAAAA, &wdtimer->wdtwspr);
	296	while (readl(&wdtimer->wdtwwps) != 0x0)
	297	;
	298	writel(0x5555, &wdtimer->wdtwspr);
	299	while (readl(&wdtimer->wdtwwps) != 0x0)
	300	;
	301
	302	#ifdef CONFIG_SPL_BUILD
	303	/* Setup the PLLs and the clocks for the peripherals */
	304	pll_init();
	305
	306	/* Enable RTC32K clock */
	307	rtc32k_enable();
	308
6422b70b	309	#ifdef CONFIG_SERIAL1
e363426e	310	enable_uart0_pin_mux();
6422b70b AB	311	#endif /* CONFIG_SERIAL1 */
	312	#ifdef CONFIG_SERIAL2
	313	enable_uart1_pin_mux();
	314	#endif /* CONFIG_SERIAL2 */
	315	#ifdef CONFIG_SERIAL3
	316	enable_uart2_pin_mux();
	317	#endif /* CONFIG_SERIAL3 */
	318	#ifdef CONFIG_SERIAL4
	319	enable_uart3_pin_mux();
	320	#endif /* CONFIG_SERIAL4 */
	321	#ifdef CONFIG_SERIAL5
	322	enable_uart4_pin_mux();
	323	#endif /* CONFIG_SERIAL5 */
	324	#ifdef CONFIG_SERIAL6
	325	enable_uart5_pin_mux();
	326	#endif /* CONFIG_SERIAL6 */
e363426e	327
7ea7f689	328	uart_soft_reset();
e363426e PK	329
	330	gd = &gdata;
	331
	332	preloader_console_init();
	333
	334	/* Initalize the board header */
	335	enable_i2c0_pin_mux();
	336	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	337	if (read_eeprom() < 0)
	338	puts("Could not get board ID.\n");
	339
	340	enable_board_pin_mux(&header);
	341	if (board_is_evm_sk()) {
	342	/*
	343	* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
	344	* This is safe enough to do on older revs.
	345	*/
	346	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	347	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	348	}
	349
c7ba18ad	350	if (board_is_evm_sk())
c7d35bef	351	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
3ba65f97	352	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
c7ba18ad	353	else if (board_is_bone_lt())
b996a3e9	354	config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
c7ba18ad TR	355	&ddr3_beagleblack_data,
	356	&ddr3_beagleblack_cmd_ctrl_data,
	357	&ddr3_beagleblack_emif_reg_data, 0);
13526f71 JL	358	else if (board_is_evm_15_or_later())
13526f71 JL	359	config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
3ba65f97	360	&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
c00f69db	361	else
c7d35bef	362	config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
3ba65f97	363	&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
e363426e PK	364	#endif
	365	}
	366
	367	/*
	368	* Basic board specific setup. Pinmux has been handled already.
	369	*/
	370	int board_init(void)
	371	{
	372	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	373	if (read_eeprom() < 0)
	374	puts("Could not get board ID.\n");
	375
	376	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
	377
98b5c269 IY	378	gpmc_init();
98b5c269 IY	379
e363426e PK	380	return 0;
	381	}
	382
044fc14b TR	383	#ifdef CONFIG_BOARD_LATE_INIT
	384	int board_late_init(void)
	385	{
	386	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	387	char safe_string[HDR_NAME_LEN + 1];
	388
	389	/* Now set variables based on the header. */
	390	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	391	safe_string[sizeof(header.name)] = 0;
	392	setenv("board_name", safe_string);
	393
	394	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	395	safe_string[sizeof(header.version)] = 0;
	396	setenv("board_rev", safe_string);
	397	#endif
	398
	399	return 0;
	400	}
	401	#endif
	402
c0e66793 IY	403	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
c0e66793 IY	404	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e PK	405	static void cpsw_control(int enabled)
	406	{
	407	/* VTP can be added here */
	408
	409	return;
	410	}
	411
	412	static struct cpsw_slave_data cpsw_slaves[] = {
	413	{
	414	.slave_reg_ofs = 0x208,
	415	.sliver_reg_ofs = 0xd80,
	416	.phy_id = 0,
	417	},
	418	{
	419	.slave_reg_ofs = 0x308,
	420	.sliver_reg_ofs = 0xdc0,
	421	.phy_id = 1,
	422	},
	423	};
	424
	425	static struct cpsw_platform_data cpsw_data = {
81df2bab MP	426	.mdio_base = CPSW_MDIO_BASE,
81df2bab MP	427	.cpsw_base = CPSW_BASE,
e363426e PK	428	.mdio_div = 0xff,
	429	.channels = 8,
	430	.cpdma_reg_ofs = 0x800,
	431	.slaves = 1,
	432	.slave_data = cpsw_slaves,
	433	.ale_reg_ofs = 0xd00,
	434	.ale_entries = 1024,
	435	.host_port_reg_ofs = 0x108,
	436	.hw_stats_reg_ofs = 0x900,
	437	.mac_control = (1 << 5),
	438	.control = cpsw_control,
	439	.host_port_num = 0,
	440	.version = CPSW_CTRL_VERSION_2,
	441	};
d2aa1154	442	#endif
e363426e	443
d2aa1154 IY	444	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
d2aa1154 IY	445	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
e363426e PK	446	int board_eth_init(bd_t *bis)
e363426e PK	447	{
d2aa1154	448	int rv, n = 0;
e363426e PK	449	uint8_t mac_addr[6];
	450	uint32_t mac_hi, mac_lo;
	451
c0e66793 IY	452	/* try reading mac address from efuse */
	453	mac_lo = readl(&cdev->macid0l);
	454	mac_hi = readl(&cdev->macid0h);
	455	mac_addr[0] = mac_hi & 0xFF;
	456	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	457	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	458	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	459	mac_addr[4] = mac_lo & 0xFF;
	460	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
	461
	462	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	463	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	464	if (!getenv("ethaddr")) {
	465	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
e363426e PK	466
	467	if (is_valid_ether_addr(mac_addr))
	468	eth_setenv_enetaddr("ethaddr", mac_addr);
e363426e PK	469	}
e363426e PK	470
a662e0c3	471	#ifdef CONFIG_DRIVER_TI_CPSW
a956bdcb	472	if (board_is_bone() \|\| board_is_bone_lt() \|\| board_is_idk()) {
e363426e PK	473	writel(MII_MODE_ENABLE, &cdev->miisel);
	474	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	475	PHY_INTERFACE_MODE_MII;
	476	} else {
	477	writel(RGMII_MODE_ENABLE, &cdev->miisel);
	478	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	479	PHY_INTERFACE_MODE_RGMII;
	480	}
	481
d2aa1154 IY	482	rv = cpsw_register(&cpsw_data);
	483	if (rv < 0)
	484	printf("Error %d registering CPSW switch\n", rv);
	485	else
	486	n += rv;
a662e0c3	487	#endif
1634e969 TR	488
	489	/*
	490	*
	491	* CPSW RGMII Internal Delay Mode is not supported in all PVT
	492	* operating points. So we must set the TX clock delay feature
	493	* in the AR8051 PHY. Since we only support a single ethernet
	494	* device in U-Boot, we only do this for the first instance.
	495	*/
	496	#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
	497	#define AR8051_PHY_DEBUG_DATA_REG 0x1e
	498	#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
	499	#define AR8051_RGMII_TX_CLK_DLY 0x100
	500
	501	if (board_is_evm_sk() \|\| board_is_gp_evm()) {
	502	const char *devname;
	503	devname = miiphy_get_current_dev();
	504
	505	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
	506	AR8051_DEBUG_RGMII_CLK_DLY_REG);
	507	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
	508	AR8051_RGMII_TX_CLK_DLY);
	509	}
d2aa1154	510	#endif
c0e66793 IY	511	#if defined(CONFIG_USB_ETHER) && \
	512	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_USBETH_SUPPORT))
	513	if (is_valid_ether_addr(mac_addr))
	514	eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
	515
d2aa1154 IY	516	rv = usb_eth_initialize(bis);
	517	if (rv < 0)
	518	printf("Error %d registering USB_ETHER\n", rv);
	519	else
	520	n += rv;
	521	#endif
	522	return n;
e363426e PK	523	}
e363426e PK	524	#endif