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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
84c7204b MS |
2 | /* |
3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. | |
4 | * Michal Simek <michal.simek@xilinx.com> | |
84c7204b MS |
5 | */ |
6 | ||
7 | #include <common.h> | |
62270f43 | 8 | #include <cpu_func.h> |
c0adba57 | 9 | #include <debug_uart.h> |
9fb625ce | 10 | #include <env.h> |
5255932f | 11 | #include <init.h> |
90526e9f | 12 | #include <net.h> |
679b994a | 13 | #include <sata.h> |
6fe6f135 MS |
14 | #include <ahci.h> |
15 | #include <scsi.h> | |
b72894f1 | 16 | #include <malloc.h> |
4490e013 | 17 | #include <wdt.h> |
0785dfd8 | 18 | #include <asm/arch/clk.h> |
84c7204b MS |
19 | #include <asm/arch/hardware.h> |
20 | #include <asm/arch/sys_proto.h> | |
2ad341ed | 21 | #include <asm/arch/psu_init_gpl.h> |
90526e9f | 22 | #include <asm/cache.h> |
84c7204b | 23 | #include <asm/io.h> |
2882b39d | 24 | #include <dm/device.h> |
4490e013 | 25 | #include <dm/uclass.h> |
16fa00a7 SDPP |
26 | #include <usb.h> |
27 | #include <dwc3-uboot.h> | |
47e60cbd | 28 | #include <zynqmppl.h> |
009ab7b9 | 29 | #include <zynqmp_firmware.h> |
9feff385 | 30 | #include <g_dnl.h> |
80fdef12 | 31 | #include "../common/board.h" |
84c7204b | 32 | |
c28a9cfa LC |
33 | #include "pm_cfg_obj.h" |
34 | ||
84c7204b MS |
35 | DECLARE_GLOBAL_DATA_PTR; |
36 | ||
47e60cbd MS |
37 | #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ |
38 | !defined(CONFIG_SPL_BUILD) | |
39 | static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; | |
40 | ||
41 | static const struct { | |
8ebdf9ef | 42 | u32 id; |
494fffe7 | 43 | u32 ver; |
47e60cbd | 44 | char *name; |
83bf2ff0 | 45 | bool evexists; |
47e60cbd MS |
46 | } zynqmp_devices[] = { |
47 | { | |
48 | .id = 0x10, | |
49 | .name = "3eg", | |
50 | }, | |
494fffe7 MS |
51 | { |
52 | .id = 0x10, | |
53 | .ver = 0x2c, | |
54 | .name = "3cg", | |
55 | }, | |
47e60cbd MS |
56 | { |
57 | .id = 0x11, | |
58 | .name = "2eg", | |
59 | }, | |
494fffe7 MS |
60 | { |
61 | .id = 0x11, | |
62 | .ver = 0x2c, | |
63 | .name = "2cg", | |
64 | }, | |
47e60cbd MS |
65 | { |
66 | .id = 0x20, | |
67 | .name = "5ev", | |
83bf2ff0 | 68 | .evexists = 1, |
47e60cbd | 69 | }, |
494fffe7 MS |
70 | { |
71 | .id = 0x20, | |
72 | .ver = 0x100, | |
73 | .name = "5eg", | |
83bf2ff0 | 74 | .evexists = 1, |
494fffe7 MS |
75 | }, |
76 | { | |
77 | .id = 0x20, | |
78 | .ver = 0x12c, | |
79 | .name = "5cg", | |
5473f245 | 80 | .evexists = 1, |
494fffe7 | 81 | }, |
47e60cbd MS |
82 | { |
83 | .id = 0x21, | |
84 | .name = "4ev", | |
83bf2ff0 | 85 | .evexists = 1, |
47e60cbd | 86 | }, |
494fffe7 MS |
87 | { |
88 | .id = 0x21, | |
89 | .ver = 0x100, | |
90 | .name = "4eg", | |
83bf2ff0 | 91 | .evexists = 1, |
494fffe7 MS |
92 | }, |
93 | { | |
94 | .id = 0x21, | |
95 | .ver = 0x12c, | |
96 | .name = "4cg", | |
5473f245 | 97 | .evexists = 1, |
494fffe7 | 98 | }, |
47e60cbd MS |
99 | { |
100 | .id = 0x30, | |
101 | .name = "7ev", | |
83bf2ff0 | 102 | .evexists = 1, |
47e60cbd | 103 | }, |
494fffe7 MS |
104 | { |
105 | .id = 0x30, | |
106 | .ver = 0x100, | |
107 | .name = "7eg", | |
83bf2ff0 | 108 | .evexists = 1, |
494fffe7 MS |
109 | }, |
110 | { | |
111 | .id = 0x30, | |
112 | .ver = 0x12c, | |
113 | .name = "7cg", | |
5473f245 | 114 | .evexists = 1, |
494fffe7 | 115 | }, |
47e60cbd MS |
116 | { |
117 | .id = 0x38, | |
118 | .name = "9eg", | |
119 | }, | |
494fffe7 MS |
120 | { |
121 | .id = 0x38, | |
122 | .ver = 0x2c, | |
123 | .name = "9cg", | |
124 | }, | |
47e60cbd MS |
125 | { |
126 | .id = 0x39, | |
127 | .name = "6eg", | |
128 | }, | |
494fffe7 MS |
129 | { |
130 | .id = 0x39, | |
131 | .ver = 0x2c, | |
132 | .name = "6cg", | |
133 | }, | |
47e60cbd MS |
134 | { |
135 | .id = 0x40, | |
136 | .name = "11eg", | |
137 | }, | |
494fffe7 MS |
138 | { /* For testing purpose only */ |
139 | .id = 0x50, | |
140 | .ver = 0x2c, | |
141 | .name = "15cg", | |
142 | }, | |
47e60cbd MS |
143 | { |
144 | .id = 0x50, | |
145 | .name = "15eg", | |
146 | }, | |
147 | { | |
148 | .id = 0x58, | |
149 | .name = "19eg", | |
150 | }, | |
151 | { | |
152 | .id = 0x59, | |
153 | .name = "17eg", | |
154 | }, | |
b030fedf MS |
155 | { |
156 | .id = 0x61, | |
157 | .name = "21dr", | |
158 | }, | |
159 | { | |
160 | .id = 0x63, | |
161 | .name = "23dr", | |
162 | }, | |
163 | { | |
164 | .id = 0x65, | |
165 | .name = "25dr", | |
166 | }, | |
167 | { | |
168 | .id = 0x64, | |
169 | .name = "27dr", | |
170 | }, | |
171 | { | |
172 | .id = 0x60, | |
173 | .name = "28dr", | |
174 | }, | |
175 | { | |
176 | .id = 0x62, | |
177 | .name = "29dr", | |
178 | }, | |
c7490907 SDPP |
179 | { |
180 | .id = 0x66, | |
181 | .name = "39dr", | |
182 | }, | |
134b0c8d SDPP |
183 | { |
184 | .id = 0x7b, | |
185 | .name = "48dr", | |
186 | }, | |
187 | { | |
188 | .id = 0x7e, | |
189 | .name = "49dr", | |
190 | }, | |
47e60cbd | 191 | }; |
74ba69db | 192 | #endif |
47e60cbd | 193 | |
f52bf5a3 | 194 | int chip_id(unsigned char id) |
47e60cbd MS |
195 | { |
196 | struct pt_regs regs; | |
db3123b4 | 197 | int val = -EINVAL; |
47e60cbd | 198 | |
74ba69db SDPP |
199 | if (current_el() != 3) { |
200 | regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID; | |
201 | regs.regs[1] = 0; | |
202 | regs.regs[2] = 0; | |
203 | regs.regs[3] = 0; | |
204 | ||
205 | smc_call(®s); | |
206 | ||
207 | /* | |
208 | * SMC returns: | |
209 | * regs[0][31:0] = status of the operation | |
210 | * regs[0][63:32] = CSU.IDCODE register | |
211 | * regs[1][31:0] = CSU.version register | |
494fffe7 | 212 | * regs[1][63:32] = CSU.IDCODE2 register |
74ba69db SDPP |
213 | */ |
214 | switch (id) { | |
215 | case IDCODE: | |
216 | regs.regs[0] = upper_32_bits(regs.regs[0]); | |
217 | regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | | |
218 | ZYNQMP_CSU_IDCODE_SVD_MASK; | |
219 | regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; | |
220 | val = regs.regs[0]; | |
221 | break; | |
222 | case VERSION: | |
223 | regs.regs[1] = lower_32_bits(regs.regs[1]); | |
224 | regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK; | |
225 | val = regs.regs[1]; | |
226 | break; | |
494fffe7 MS |
227 | case IDCODE2: |
228 | regs.regs[1] = lower_32_bits(regs.regs[1]); | |
229 | regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT; | |
230 | val = regs.regs[1]; | |
231 | break; | |
74ba69db SDPP |
232 | default: |
233 | printf("%s, Invalid Req:0x%x\n", __func__, id); | |
234 | } | |
235 | } else { | |
236 | switch (id) { | |
237 | case IDCODE: | |
238 | val = readl(ZYNQMP_CSU_IDCODE_ADDR); | |
239 | val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | | |
240 | ZYNQMP_CSU_IDCODE_SVD_MASK; | |
241 | val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; | |
242 | break; | |
243 | case VERSION: | |
244 | val = readl(ZYNQMP_CSU_VER_ADDR); | |
245 | val &= ZYNQMP_CSU_SILICON_VER_MASK; | |
246 | break; | |
247 | default: | |
248 | printf("%s, Invalid Req:0x%x\n", __func__, id); | |
249 | } | |
db3123b4 | 250 | } |
0cba6abb | 251 | |
db3123b4 | 252 | return val; |
47e60cbd MS |
253 | } |
254 | ||
83bf2ff0 SDPP |
255 | #define ZYNQMP_VERSION_SIZE 9 |
256 | #define ZYNQMP_PL_STATUS_BIT 9 | |
5473f245 | 257 | #define ZYNQMP_IPDIS_VCU_BIT 8 |
83bf2ff0 SDPP |
258 | #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT) |
259 | #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK) | |
5473f245 SDPP |
260 | #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \ |
261 | ~BIT(ZYNQMP_IPDIS_VCU_BIT) | |
262 | #define MAX_VARIANTS_EV 3 | |
83bf2ff0 | 263 | |
74ba69db SDPP |
264 | #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ |
265 | !defined(CONFIG_SPL_BUILD) | |
47e60cbd MS |
266 | static char *zynqmp_get_silicon_idcode_name(void) |
267 | { | |
5473f245 | 268 | u32 i, id, ver, j; |
83bf2ff0 SDPP |
269 | char *buf; |
270 | static char name[ZYNQMP_VERSION_SIZE]; | |
47e60cbd | 271 | |
db3123b4 | 272 | id = chip_id(IDCODE); |
494fffe7 MS |
273 | ver = chip_id(IDCODE2); |
274 | ||
47e60cbd | 275 | for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { |
5473f245 SDPP |
276 | if (zynqmp_devices[i].id == id) { |
277 | if (zynqmp_devices[i].evexists && | |
278 | !(ver & ZYNQMP_PL_STATUS_MASK)) | |
279 | break; | |
280 | if (zynqmp_devices[i].ver == (ver & | |
281 | ZYNQMP_CSU_VERSION_MASK)) | |
282 | break; | |
83bf2ff0 | 283 | } |
47e60cbd | 284 | } |
83bf2ff0 SDPP |
285 | |
286 | if (i >= ARRAY_SIZE(zynqmp_devices)) | |
287 | return "unknown"; | |
288 | ||
5473f245 SDPP |
289 | strncat(name, "zu", 2); |
290 | if (!zynqmp_devices[i].evexists || | |
291 | (ver & ZYNQMP_PL_STATUS_MASK)) { | |
292 | strncat(name, zynqmp_devices[i].name, | |
293 | ZYNQMP_VERSION_SIZE - 3); | |
83bf2ff0 | 294 | return name; |
5473f245 | 295 | } |
83bf2ff0 | 296 | |
5473f245 SDPP |
297 | /* |
298 | * Here we are means, PL not powered up and ev variant | |
299 | * exists. So, we need to ignore VCU disable bit(8) in | |
300 | * version and findout if its CG or EG/EV variant. | |
301 | */ | |
302 | for (j = 0; j < MAX_VARIANTS_EV; j++, i++) { | |
303 | if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) == | |
304 | (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) { | |
305 | strncat(name, zynqmp_devices[i].name, | |
306 | ZYNQMP_VERSION_SIZE - 3); | |
307 | break; | |
308 | } | |
309 | } | |
310 | ||
311 | if (j >= MAX_VARIANTS_EV) | |
312 | return "unknown"; | |
83bf2ff0 SDPP |
313 | |
314 | if (strstr(name, "eg") || strstr(name, "ev")) { | |
315 | buf = strstr(name, "e"); | |
316 | *buf = '\0'; | |
317 | } | |
318 | ||
319 | return name; | |
47e60cbd MS |
320 | } |
321 | #endif | |
322 | ||
fb4000e8 MS |
323 | int board_early_init_f(void) |
324 | { | |
88f05a92 | 325 | #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED) |
c0adba57 MS |
326 | int ret; |
327 | ||
f32e79f1 | 328 | ret = psu_init(); |
c0adba57 MS |
329 | if (ret) |
330 | return ret; | |
f8451f14 MS |
331 | |
332 | /* Delay is required for clocks to be propagated */ | |
333 | udelay(1000000); | |
55de0929 MS |
334 | #endif |
335 | ||
c0adba57 MS |
336 | #ifdef CONFIG_DEBUG_UART |
337 | /* Uart debug for sure */ | |
338 | debug_uart_init(); | |
339 | puts("Debug uart enabled\n"); /* or printch() */ | |
340 | #endif | |
341 | ||
342 | return 0; | |
fb4000e8 MS |
343 | } |
344 | ||
c5143013 MS |
345 | static int multi_boot(void) |
346 | { | |
347 | u32 multiboot; | |
348 | ||
349 | multiboot = readl(&csu_base->multi_boot); | |
350 | ||
351 | printf("Multiboot:\t%x\n", multiboot); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
84c7204b MS |
356 | int board_init(void) |
357 | { | |
66ef85da | 358 | #if defined(CONFIG_ZYNQMP_FIRMWARE) |
325a22dc IE |
359 | struct udevice *dev; |
360 | ||
361 | uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev); | |
362 | if (!dev) | |
363 | panic("PMU Firmware device not found - Enable it"); | |
66ef85da | 364 | #endif |
325a22dc | 365 | |
c28a9cfa LC |
366 | #if defined(CONFIG_SPL_BUILD) |
367 | /* Check *at build time* if the filename is an non-empty string */ | |
368 | if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) | |
369 | zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, | |
370 | zynqmp_pm_cfg_obj_size); | |
371 | #endif | |
372 | ||
a0736efb MS |
373 | printf("EL Level:\tEL%d\n", current_el()); |
374 | ||
47e60cbd MS |
375 | #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ |
376 | !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ | |
377 | defined(CONFIG_SPL_BUILD)) | |
378 | if (current_el() != 3) { | |
83bf2ff0 | 379 | zynqmppl.name = zynqmp_get_silicon_idcode_name(); |
47e60cbd MS |
380 | printf("Chip ID:\t%s\n", zynqmppl.name); |
381 | fpga_init(); | |
382 | fpga_add(fpga_xilinx, &zynqmppl); | |
383 | } | |
384 | #endif | |
385 | ||
c5143013 MS |
386 | if (current_el() == 3) |
387 | multi_boot(); | |
388 | ||
84c7204b MS |
389 | return 0; |
390 | } | |
391 | ||
392 | int board_early_init_r(void) | |
393 | { | |
394 | u32 val; | |
395 | ||
ec60a279 SDPP |
396 | if (current_el() != 3) |
397 | return 0; | |
398 | ||
90a35db4 MS |
399 | val = readl(&crlapb_base->timestamp_ref_ctrl); |
400 | val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; | |
401 | ||
ec60a279 | 402 | if (!val) { |
0785dfd8 MS |
403 | val = readl(&crlapb_base->timestamp_ref_ctrl); |
404 | val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; | |
405 | writel(val, &crlapb_base->timestamp_ref_ctrl); | |
84c7204b | 406 | |
0785dfd8 MS |
407 | /* Program freq register in System counter */ |
408 | writel(zynqmp_get_system_timer_freq(), | |
409 | &iou_scntr_secure->base_frequency_id_register); | |
410 | /* And enable system counter */ | |
411 | writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, | |
412 | &iou_scntr_secure->counter_control_register); | |
413 | } | |
84c7204b MS |
414 | return 0; |
415 | } | |
416 | ||
51916864 NJ |
417 | unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, |
418 | char * const argv[]) | |
419 | { | |
420 | int ret = 0; | |
421 | ||
422 | if (current_el() > 1) { | |
423 | smp_kick_all_cpus(); | |
424 | dcache_disable(); | |
425 | armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry, | |
426 | ES_TO_AARCH64); | |
427 | } else { | |
428 | printf("FAIL: current EL is not above EL1\n"); | |
429 | ret = EINVAL; | |
430 | } | |
431 | return ret; | |
432 | } | |
433 | ||
8d59d7f6 | 434 | #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) |
76b00aca | 435 | int dram_init_banksize(void) |
361a8799 | 436 | { |
0678941a NJ |
437 | int ret; |
438 | ||
439 | ret = fdtdec_setup_memory_banksize(); | |
440 | if (ret) | |
441 | return ret; | |
442 | ||
443 | mem_map_fill(); | |
444 | ||
445 | return 0; | |
8a5db0ab | 446 | } |
8d59d7f6 | 447 | |
361a8799 | 448 | int dram_init(void) |
8a5db0ab | 449 | { |
12308b12 | 450 | if (fdtdec_setup_mem_size_base() != 0) |
950f86ca | 451 | return -EINVAL; |
8a5db0ab | 452 | |
361a8799 | 453 | return 0; |
8d59d7f6 MS |
454 | } |
455 | #else | |
0678941a NJ |
456 | int dram_init_banksize(void) |
457 | { | |
458 | #if defined(CONFIG_NR_DRAM_BANKS) | |
459 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
460 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
461 | #endif | |
462 | ||
463 | mem_map_fill(); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
84c7204b MS |
468 | int dram_init(void) |
469 | { | |
61dc92a2 MS |
470 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
471 | CONFIG_SYS_SDRAM_SIZE); | |
84c7204b MS |
472 | |
473 | return 0; | |
474 | } | |
8d59d7f6 | 475 | #endif |
84c7204b | 476 | |
84c7204b MS |
477 | void reset_cpu(ulong addr) |
478 | { | |
479 | } | |
480 | ||
0bf3f9cb | 481 | #if defined(CONFIG_BOARD_LATE_INIT) |
d348beaa MS |
482 | static const struct { |
483 | u32 bit; | |
484 | const char *name; | |
485 | } reset_reasons[] = { | |
486 | { RESET_REASON_DEBUG_SYS, "DEBUG" }, | |
487 | { RESET_REASON_SOFT, "SOFT" }, | |
488 | { RESET_REASON_SRST, "SRST" }, | |
489 | { RESET_REASON_PSONLY, "PS-ONLY" }, | |
490 | { RESET_REASON_PMU, "PMU" }, | |
491 | { RESET_REASON_INTERNAL, "INTERNAL" }, | |
492 | { RESET_REASON_EXTERNAL, "EXTERNAL" }, | |
493 | {} | |
494 | }; | |
495 | ||
be52372f | 496 | static int reset_reason(void) |
d348beaa | 497 | { |
be52372f KR |
498 | u32 reg; |
499 | int i, ret; | |
d348beaa MS |
500 | const char *reason = NULL; |
501 | ||
be52372f KR |
502 | ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®); |
503 | if (ret) | |
504 | return -EINVAL; | |
d348beaa MS |
505 | |
506 | puts("Reset reason:\t"); | |
507 | ||
508 | for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) { | |
be52372f | 509 | if (reg & reset_reasons[i].bit) { |
d348beaa MS |
510 | reason = reset_reasons[i].name; |
511 | printf("%s ", reset_reasons[i].name); | |
512 | break; | |
513 | } | |
514 | } | |
515 | ||
516 | puts("\n"); | |
517 | ||
518 | env_set("reset_reason", reason); | |
519 | ||
3d037524 | 520 | ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0); |
be52372f KR |
521 | if (ret) |
522 | return -EINVAL; | |
d348beaa MS |
523 | |
524 | return ret; | |
525 | } | |
526 | ||
91d7e0c4 MS |
527 | static int set_fdtfile(void) |
528 | { | |
529 | char *compatible, *fdtfile; | |
530 | const char *suffix = ".dtb"; | |
531 | const char *vendor = "xilinx/"; | |
532 | ||
533 | if (env_get("fdtfile")) | |
534 | return 0; | |
535 | ||
536 | compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL); | |
537 | if (compatible) { | |
538 | debug("Compatible: %s\n", compatible); | |
539 | ||
540 | /* Discard vendor prefix */ | |
541 | strsep(&compatible, ","); | |
542 | ||
543 | fdtfile = calloc(1, strlen(vendor) + strlen(compatible) + | |
544 | strlen(suffix) + 1); | |
545 | if (!fdtfile) | |
546 | return -ENOMEM; | |
547 | ||
548 | sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix); | |
549 | ||
550 | env_set("fdtfile", fdtfile); | |
551 | free(fdtfile); | |
552 | } | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
51f6c52e | 557 | static u8 zynqmp_get_bootmode(void) |
84c7204b | 558 | { |
51f6c52e | 559 | u8 bootmode; |
84c7204b | 560 | u32 reg = 0; |
51f6c52e MS |
561 | int ret; |
562 | ||
563 | ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®); | |
564 | if (ret) | |
565 | return -EINVAL; | |
566 | ||
567 | if (reg >> BOOT_MODE_ALT_SHIFT) | |
568 | reg >>= BOOT_MODE_ALT_SHIFT; | |
569 | ||
570 | bootmode = reg & BOOT_MODES_MASK; | |
571 | ||
572 | return bootmode; | |
573 | } | |
574 | ||
575 | int board_late_init(void) | |
576 | { | |
84c7204b | 577 | u8 bootmode; |
2882b39d MS |
578 | struct udevice *dev; |
579 | int bootseq = -1; | |
580 | int bootseq_len = 0; | |
0478b0b9 | 581 | int env_targets_len = 0; |
b72894f1 MS |
582 | const char *mode; |
583 | char *new_targets; | |
01c42d3d | 584 | char *env_targets; |
d1db89f4 | 585 | int ret; |
b72894f1 | 586 | |
e615f39e MS |
587 | #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD) |
588 | usb_ether_init(); | |
589 | #endif | |
590 | ||
b72894f1 MS |
591 | if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { |
592 | debug("Saved variables - Skipping\n"); | |
593 | return 0; | |
594 | } | |
84c7204b | 595 | |
91d7e0c4 MS |
596 | ret = set_fdtfile(); |
597 | if (ret) | |
598 | return ret; | |
599 | ||
51f6c52e | 600 | bootmode = zynqmp_get_bootmode(); |
84c7204b | 601 | |
fb90917c | 602 | puts("Bootmode: "); |
84c7204b | 603 | switch (bootmode) { |
d58fc12e MS |
604 | case USB_MODE: |
605 | puts("USB_MODE\n"); | |
606 | mode = "usb"; | |
07656ba5 | 607 | env_set("modeboot", "usb_dfu_spl"); |
d58fc12e | 608 | break; |
0a5bcc8c | 609 | case JTAG_MODE: |
fb90917c | 610 | puts("JTAG_MODE\n"); |
5d2274c0 | 611 | mode = "jtag pxe dhcp"; |
07656ba5 | 612 | env_set("modeboot", "jtagboot"); |
0a5bcc8c SDPP |
613 | break; |
614 | case QSPI_MODE_24BIT: | |
615 | case QSPI_MODE_32BIT: | |
b72894f1 | 616 | mode = "qspi0"; |
fb90917c | 617 | puts("QSPI_MODE\n"); |
07656ba5 | 618 | env_set("modeboot", "qspiboot"); |
0a5bcc8c | 619 | break; |
39c56f55 | 620 | case EMMC_MODE: |
78678fee | 621 | puts("EMMC_MODE\n"); |
18be60b8 KR |
622 | if (uclass_get_device_by_name(UCLASS_MMC, |
623 | "mmc@ff160000", &dev) && | |
624 | uclass_get_device_by_name(UCLASS_MMC, | |
625 | "sdhci@ff160000", &dev)) { | |
626 | puts("Boot from EMMC but without SD0 enabled!\n"); | |
627 | return -1; | |
628 | } | |
629 | debug("mmc0 device found at %p, seq %d\n", dev, dev->seq); | |
630 | ||
631 | mode = "mmc"; | |
632 | bootseq = dev->seq; | |
78678fee MS |
633 | break; |
634 | case SD_MODE: | |
fb90917c | 635 | puts("SD_MODE\n"); |
2882b39d | 636 | if (uclass_get_device_by_name(UCLASS_MMC, |
e7c9de66 SDPP |
637 | "mmc@ff160000", &dev) && |
638 | uclass_get_device_by_name(UCLASS_MMC, | |
2882b39d MS |
639 | "sdhci@ff160000", &dev)) { |
640 | puts("Boot from SD0 but without SD0 enabled!\n"); | |
641 | return -1; | |
642 | } | |
643 | debug("mmc0 device found at %p, seq %d\n", dev, dev->seq); | |
644 | ||
645 | mode = "mmc"; | |
646 | bootseq = dev->seq; | |
07656ba5 | 647 | env_set("modeboot", "sdboot"); |
84c7204b | 648 | break; |
e1992276 SDPP |
649 | case SD1_LSHFT_MODE: |
650 | puts("LVL_SHFT_"); | |
651 | /* fall through */ | |
af813acd | 652 | case SD_MODE1: |
fb90917c | 653 | puts("SD_MODE1\n"); |
2882b39d | 654 | if (uclass_get_device_by_name(UCLASS_MMC, |
e7c9de66 SDPP |
655 | "mmc@ff170000", &dev) && |
656 | uclass_get_device_by_name(UCLASS_MMC, | |
2882b39d MS |
657 | "sdhci@ff170000", &dev)) { |
658 | puts("Boot from SD1 but without SD1 enabled!\n"); | |
659 | return -1; | |
660 | } | |
661 | debug("mmc1 device found at %p, seq %d\n", dev, dev->seq); | |
662 | ||
663 | mode = "mmc"; | |
664 | bootseq = dev->seq; | |
07656ba5 | 665 | env_set("modeboot", "sdboot"); |
af813acd MS |
666 | break; |
667 | case NAND_MODE: | |
fb90917c | 668 | puts("NAND_MODE\n"); |
b72894f1 | 669 | mode = "nand0"; |
07656ba5 | 670 | env_set("modeboot", "nandboot"); |
af813acd | 671 | break; |
84c7204b | 672 | default: |
b72894f1 | 673 | mode = ""; |
84c7204b MS |
674 | printf("Invalid Boot Mode:0x%x\n", bootmode); |
675 | break; | |
676 | } | |
677 | ||
2882b39d MS |
678 | if (bootseq >= 0) { |
679 | bootseq_len = snprintf(NULL, 0, "%i", bootseq); | |
680 | debug("Bootseq len: %x\n", bootseq_len); | |
681 | } | |
682 | ||
b72894f1 MS |
683 | /* |
684 | * One terminating char + one byte for space between mode | |
685 | * and default boot_targets | |
686 | */ | |
01c42d3d | 687 | env_targets = env_get("boot_targets"); |
0478b0b9 MS |
688 | if (env_targets) |
689 | env_targets_len = strlen(env_targets); | |
690 | ||
2882b39d MS |
691 | new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + |
692 | bootseq_len); | |
1e3e68f1 MS |
693 | if (!new_targets) |
694 | return -ENOMEM; | |
0478b0b9 | 695 | |
2882b39d MS |
696 | if (bootseq >= 0) |
697 | sprintf(new_targets, "%s%x %s", mode, bootseq, | |
698 | env_targets ? env_targets : ""); | |
699 | else | |
700 | sprintf(new_targets, "%s %s", mode, | |
701 | env_targets ? env_targets : ""); | |
b72894f1 | 702 | |
382bee57 | 703 | env_set("boot_targets", new_targets); |
b72894f1 | 704 | |
d348beaa MS |
705 | reset_reason(); |
706 | ||
80fdef12 | 707 | return board_late_init_xilinx(); |
84c7204b | 708 | } |
0bf3f9cb | 709 | #endif |
84696ff5 SDPP |
710 | |
711 | int checkboard(void) | |
712 | { | |
5af08556 | 713 | puts("Board: Xilinx ZynqMP\n"); |
84696ff5 SDPP |
714 | return 0; |
715 | } |