[thirdparty/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <wdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/psu_init_gpl.h>
#include <asm/io.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <i2c.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
static struct udevice *watchdog_dev;
#endif

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	u32 id;
	u32 ver;
	char *name;
	bool evexists;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x10,
		.ver = 0x2c,
		.name = "3cg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x11,
		.ver = 0x2c,
		.name = "2cg",
	},
	{
		.id = 0x20,
		.name = "5ev",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x100,
		.name = "5eg",
		.evexists = 1,
	},
	{
		.id = 0x20,
		.ver = 0x12c,
		.name = "5cg",
	},
	{
		.id = 0x21,
		.name = "4ev",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x100,
		.name = "4eg",
		.evexists = 1,
	},
	{
		.id = 0x21,
		.ver = 0x12c,
		.name = "4cg",
	},
	{
		.id = 0x30,
		.name = "7ev",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x100,
		.name = "7eg",
		.evexists = 1,
	},
	{
		.id = 0x30,
		.ver = 0x12c,
		.name = "7cg",
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x38,
		.ver = 0x2c,
		.name = "9cg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x39,
		.ver = 0x2c,
		.name = "6cg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{ /* For testing purpose only */
		.id = 0x50,
		.ver = 0x2c,
		.name = "15cg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
	{
		.id = 0x61,
		.name = "21dr",
	},
	{
		.id = 0x63,
		.name = "23dr",
	},
	{
		.id = 0x65,
		.name = "25dr",
	},
	{
		.id = 0x64,
		.name = "27dr",
	},
	{
		.id = 0x60,
		.name = "28dr",
	},
	{
		.id = 0x62,
		.name = "29dr",
	},
};
#endif

int chip_id(unsigned char id)
{
	struct pt_regs regs;
	int val = -EINVAL;

	if (current_el() != 3) {
		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
		regs.regs[1] = 0;
		regs.regs[2] = 0;
		regs.regs[3] = 0;

		smc_call(&regs);

		/*
		 * SMC returns:
		 * regs[0][31:0]  = status of the operation
		 * regs[0][63:32] = CSU.IDCODE register
		 * regs[1][31:0]  = CSU.version register
		 * regs[1][63:32] = CSU.IDCODE2 register
		 */
		switch (id) {
		case IDCODE:
			regs.regs[0] = upper_32_bits(regs.regs[0]);
			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
					ZYNQMP_CSU_IDCODE_SVD_MASK;
			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			val = regs.regs[0];
			break;
		case VERSION:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
			val = regs.regs[1];
			break;
		case IDCODE2:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
			val = regs.regs[1];
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	} else {
		switch (id) {
		case IDCODE:
			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			       ZYNQMP_CSU_IDCODE_SVD_MASK;
			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			break;
		case VERSION:
			val = readl(ZYNQMP_CSU_VER_ADDR);
			val &= ZYNQMP_CSU_SILICON_VER_MASK;
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	}

	return val;
}

#define ZYNQMP_VERSION_SIZE		9
#define ZYNQMP_PL_STATUS_BIT		9
#define ZYNQMP_PL_STATUS_MASK		BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK		~(ZYNQMP_PL_STATUS_MASK)

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
	u32 i, id, ver;
	char *buf;
	static char name[ZYNQMP_VERSION_SIZE];

	id = chip_id(IDCODE);
	ver = chip_id(IDCODE2);

	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if ((zynqmp_devices[i].id == id) &&
		    (zynqmp_devices[i].ver == (ver &
		    ZYNQMP_CSU_VERSION_MASK))) {
			strncat(name, "zu", 2);
			strncat(name, zynqmp_devices[i].name,
				ZYNQMP_VERSION_SIZE - 3);
			break;
		}
	}

	if (i >= ARRAY_SIZE(zynqmp_devices))
		return "unknown";

	if (!zynqmp_devices[i].evexists)
		return name;

	if (ver & ZYNQMP_PL_STATUS_MASK)
		return name;

	if (strstr(name, "eg") || strstr(name, "ev")) {
		buf = strstr(name, "e");
		*buf = '\0';
	}

	return name;
}
#endif

int board_early_init_f(void)
{
	int ret = 0;
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	zynqmp_pmufw_version();
#endif

#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
	ret = psu_init();
#endif

#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
	/* bss is not cleared at time when watchdog_reset() is called */
	watchdog_dev = NULL;
#endif

	return ret;
}

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		zynqmppl.name = zynqmp_get_silicon_idcode_name();
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
		debug("Watchdog: Not found by seq!\n");
		if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
			puts("Watchdog: Not found!\n");
			return 0;
		}
	}

	wdt_start(watchdog_dev, 0, 0);
	puts("Watchdog: Started\n");
#endif

	return 0;
}

#ifdef CONFIG_WATCHDOG
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
# if !defined(CONFIG_SPL_BUILD)
	static ulong next_reset;
	ulong now;

	if (!watchdog_dev)
		return;

	now = timer_get_us();

	/* Do not reset the watchdog too often */
	if (now > next_reset) {
		wdt_reset(watchdog_dev);
		next_reset = now + 1000;
	}
# endif
}
#endif

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;

	if (!val) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	return 0;
}

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
    defined(CONFIG_ZYNQ_EEPROM_BUS)
	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);

	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
			 char * const argv[])
{
	int ret = 0;

	if (current_el() > 1) {
		smp_kick_all_cpus();
		dcache_disable();
		armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
				    ES_TO_AARCH64);
	} else {
		printf("FAIL: current EL is not above EL1\n");
		ret = EINVAL;
	}
	return ret;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}
#else
int dram_init_banksize(void)
{
#if defined(CONFIG_NR_DRAM_BANKS)
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = get_effective_memsize();
#endif

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

static const struct {
	u32 bit;
	const char *name;
} reset_reasons[] = {
	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
	{ RESET_REASON_SOFT, "SOFT" },
	{ RESET_REASON_SRST, "SRST" },
	{ RESET_REASON_PSONLY, "PS-ONLY" },
	{ RESET_REASON_PMU, "PMU" },
	{ RESET_REASON_INTERNAL, "INTERNAL" },
	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
	{}
};

static u32 reset_reason(void)
{
	u32 ret;
	int i;
	const char *reason = NULL;

	ret = readl(&crlapb_base->reset_reason);

	puts("Reset reason:\t");

	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
		if (ret & reset_reasons[i].bit) {
			reason = reset_reasons[i].name;
			printf("%s ", reset_reasons[i].name);
			break;
		}
	}

	puts("\n");

	env_set("reset_reason", reason);

	writel(~0, &crlapb_base->reset_reason);

	return ret;
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode;
	char *new_targets;
	char *env_targets;
	int ret;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	if (ret)
		return -EINVAL;

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		env_set("modeboot", "usb_dfu_spl");
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		env_set("modeboot", "jtagboot");
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		env_set("modeboot", "qspiboot");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		env_set("modeboot", "emmcboot");
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@ff160000", &dev)) {
			puts("Boot from SD0 but without SD0 enabled!\n");
			return -1;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		env_set("modeboot", "sdboot");
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@ff170000", &dev)) {
			puts("Boot from SD1 but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		env_set("modeboot", "sdboot");
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		env_set("modeboot", "nandboot");
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (bootseq >= 0) {
		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
		debug("Bootseq len: %x\n", bootseq_len);
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets)
		env_targets_len = strlen(env_targets);

	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
			     bootseq_len);
	if (!new_targets)
		return -ENOMEM;

	if (bootseq >= 0)
		sprintf(new_targets, "%s%x %s", mode, bootseq,
			env_targets ? env_targets : "");
	else
		sprintf(new_targets, "%s %s", mode,
			env_targets ? env_targets : "");

	env_set("boot_targets", new_targets);

	reset_reason();

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
84c7204b MS	2	/*
	3	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
84c7204b MS	5	*/
	6
	7	#include <common.h>
679b994a	8	#include <sata.h>
6fe6f135 MS	9	#include <ahci.h>
6fe6f135 MS	10	#include <scsi.h>
b72894f1	11	#include <malloc.h>
4490e013	12	#include <wdt.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
84c7204b MS	15	#include <asm/arch/sys_proto.h>
2ad341ed	16	#include <asm/arch/psu_init_gpl.h>
84c7204b	17	#include <asm/io.h>
2882b39d	18	#include <dm/device.h>
4490e013	19	#include <dm/uclass.h>
16fa00a7 SDPP	20	#include <usb.h>
16fa00a7 SDPP	21	#include <dwc3-uboot.h>
47e60cbd	22	#include <zynqmppl.h>
6919b4bf	23	#include <i2c.h>
9feff385	24	#include <g_dnl.h>
84c7204b MS	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
4490e013 MS	28	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
	29	static struct udevice *watchdog_dev;
	30	#endif
	31
47e60cbd MS	32	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	33	!defined(CONFIG_SPL_BUILD)
	34	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	35
	36	static const struct {
8ebdf9ef	37	u32 id;
494fffe7	38	u32 ver;
47e60cbd	39	char *name;
83bf2ff0	40	bool evexists;
47e60cbd MS	41	} zynqmp_devices[] = {
	42	{
	43	.id = 0x10,
	44	.name = "3eg",
	45	},
494fffe7 MS	46	{
	47	.id = 0x10,
	48	.ver = 0x2c,
	49	.name = "3cg",
	50	},
47e60cbd MS	51	{
	52	.id = 0x11,
	53	.name = "2eg",
	54	},
494fffe7 MS	55	{
	56	.id = 0x11,
	57	.ver = 0x2c,
	58	.name = "2cg",
	59	},
47e60cbd MS	60	{
	61	.id = 0x20,
	62	.name = "5ev",
83bf2ff0	63	.evexists = 1,
47e60cbd	64	},
494fffe7 MS	65	{
	66	.id = 0x20,
	67	.ver = 0x100,
	68	.name = "5eg",
83bf2ff0	69	.evexists = 1,
494fffe7 MS	70	},
	71	{
	72	.id = 0x20,
	73	.ver = 0x12c,
	74	.name = "5cg",
	75	},
47e60cbd MS	76	{
	77	.id = 0x21,
	78	.name = "4ev",
83bf2ff0	79	.evexists = 1,
47e60cbd	80	},
494fffe7 MS	81	{
	82	.id = 0x21,
	83	.ver = 0x100,
	84	.name = "4eg",
83bf2ff0	85	.evexists = 1,
494fffe7 MS	86	},
	87	{
	88	.id = 0x21,
	89	.ver = 0x12c,
	90	.name = "4cg",
	91	},
47e60cbd MS	92	{
	93	.id = 0x30,
	94	.name = "7ev",
83bf2ff0	95	.evexists = 1,
47e60cbd	96	},
494fffe7 MS	97	{
	98	.id = 0x30,
	99	.ver = 0x100,
	100	.name = "7eg",
83bf2ff0	101	.evexists = 1,
494fffe7 MS	102	},
	103	{
	104	.id = 0x30,
	105	.ver = 0x12c,
	106	.name = "7cg",
	107	},
47e60cbd MS	108	{
	109	.id = 0x38,
	110	.name = "9eg",
	111	},
494fffe7 MS	112	{
	113	.id = 0x38,
	114	.ver = 0x2c,
	115	.name = "9cg",
	116	},
47e60cbd MS	117	{
	118	.id = 0x39,
	119	.name = "6eg",
	120	},
494fffe7 MS	121	{
	122	.id = 0x39,
	123	.ver = 0x2c,
	124	.name = "6cg",
	125	},
47e60cbd MS	126	{
	127	.id = 0x40,
	128	.name = "11eg",
	129	},
494fffe7 MS	130	{ /* For testing purpose only */
	131	.id = 0x50,
	132	.ver = 0x2c,
	133	.name = "15cg",
	134	},
47e60cbd MS	135	{
	136	.id = 0x50,
	137	.name = "15eg",
	138	},
	139	{
	140	.id = 0x58,
	141	.name = "19eg",
	142	},
	143	{
	144	.id = 0x59,
	145	.name = "17eg",
	146	},
b030fedf MS	147	{
	148	.id = 0x61,
	149	.name = "21dr",
	150	},
	151	{
	152	.id = 0x63,
	153	.name = "23dr",
	154	},
	155	{
	156	.id = 0x65,
	157	.name = "25dr",
	158	},
	159	{
	160	.id = 0x64,
	161	.name = "27dr",
	162	},
	163	{
	164	.id = 0x60,
	165	.name = "28dr",
	166	},
	167	{
	168	.id = 0x62,
	169	.name = "29dr",
	170	},
47e60cbd	171	};
74ba69db	172	#endif
47e60cbd	173
f52bf5a3	174	int chip_id(unsigned char id)
47e60cbd MS	175	{
47e60cbd MS	176	struct pt_regs regs;
db3123b4	177	int val = -EINVAL;
47e60cbd	178
74ba69db SDPP	179	if (current_el() != 3) {
	180	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	181	regs.regs[1] = 0;
	182	regs.regs[2] = 0;
	183	regs.regs[3] = 0;
	184
	185	smc_call(&regs);
	186
	187	/*
	188	* SMC returns:
	189	* regs[0][31:0] = status of the operation
	190	* regs[0][63:32] = CSU.IDCODE register
	191	* regs[1][31:0] = CSU.version register
494fffe7	192	* regs[1][63:32] = CSU.IDCODE2 register
74ba69db SDPP	193	*/
	194	switch (id) {
	195	case IDCODE:
	196	regs.regs[0] = upper_32_bits(regs.regs[0]);
	197	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	198	ZYNQMP_CSU_IDCODE_SVD_MASK;
	199	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	200	val = regs.regs[0];
	201	break;
	202	case VERSION:
	203	regs.regs[1] = lower_32_bits(regs.regs[1]);
	204	regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
	205	val = regs.regs[1];
	206	break;
494fffe7 MS	207	case IDCODE2:
	208	regs.regs[1] = lower_32_bits(regs.regs[1]);
	209	regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
	210	val = regs.regs[1];
	211	break;
74ba69db SDPP	212	default:
	213	printf("%s, Invalid Req:0x%x\n", __func__, id);
	214	}
	215	} else {
	216	switch (id) {
	217	case IDCODE:
	218	val = readl(ZYNQMP_CSU_IDCODE_ADDR);
	219	val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	220	ZYNQMP_CSU_IDCODE_SVD_MASK;
	221	val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	222	break;
	223	case VERSION:
	224	val = readl(ZYNQMP_CSU_VER_ADDR);
	225	val &= ZYNQMP_CSU_SILICON_VER_MASK;
	226	break;
	227	default:
	228	printf("%s, Invalid Req:0x%x\n", __func__, id);
	229	}
db3123b4	230	}
0cba6abb	231
db3123b4	232	return val;
47e60cbd MS	233	}
47e60cbd MS	234
83bf2ff0 SDPP	235	#define ZYNQMP_VERSION_SIZE 9
	236	#define ZYNQMP_PL_STATUS_BIT 9
	237	#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
	238	#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
	239
74ba69db SDPP	240	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
74ba69db SDPP	241	!defined(CONFIG_SPL_BUILD)
47e60cbd MS	242	static char *zynqmp_get_silicon_idcode_name(void)
47e60cbd MS	243	{
494fffe7	244	u32 i, id, ver;
83bf2ff0 SDPP	245	char *buf;
83bf2ff0 SDPP	246	static char name[ZYNQMP_VERSION_SIZE];
47e60cbd	247
db3123b4	248	id = chip_id(IDCODE);
494fffe7 MS	249	ver = chip_id(IDCODE2);
494fffe7 MS	250
47e60cbd	251	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
83bf2ff0 SDPP	252	if ((zynqmp_devices[i].id == id) &&
	253	(zynqmp_devices[i].ver == (ver &
	254	ZYNQMP_CSU_VERSION_MASK))) {
	255	strncat(name, "zu", 2);
	256	strncat(name, zynqmp_devices[i].name,
	257	ZYNQMP_VERSION_SIZE - 3);
	258	break;
	259	}
47e60cbd	260	}
83bf2ff0 SDPP	261
	262	if (i >= ARRAY_SIZE(zynqmp_devices))
	263	return "unknown";
	264
	265	if (!zynqmp_devices[i].evexists)
	266	return name;
	267
	268	if (ver & ZYNQMP_PL_STATUS_MASK)
	269	return name;
	270
	271	if (strstr(name, "eg") \|\| strstr(name, "ev")) {
	272	buf = strstr(name, "e");
	273	*buf = '\0';
	274	}
	275
	276	return name;
47e60cbd MS	277	}
	278	#endif
	279
fb4000e8 MS	280	int board_early_init_f(void)
fb4000e8 MS	281	{
f32e79f1	282	int ret = 0;
fb4000e8 MS	283	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	284	zynqmp_pmufw_version();
	285	#endif
55de0929	286
88f05a92	287	#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
f32e79f1	288	ret = psu_init();
55de0929 MS	289	#endif
55de0929 MS	290
4490e013 MS	291	#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
	292	/* bss is not cleared at time when watchdog_reset() is called */
	293	watchdog_dev = NULL;
	294	#endif
	295
f32e79f1	296	return ret;
fb4000e8 MS	297	}
fb4000e8 MS	298
84c7204b MS	299	int board_init(void)
84c7204b MS	300	{
a0736efb MS	301	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	302
47e60cbd MS	303	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	304	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	305	defined(CONFIG_SPL_BUILD))
	306	if (current_el() != 3) {
83bf2ff0	307	zynqmppl.name = zynqmp_get_silicon_idcode_name();
47e60cbd MS	308	printf("Chip ID:\t%s\n", zynqmppl.name);
	309	fpga_init();
	310	fpga_add(fpga_xilinx, &zynqmppl);
	311	}
	312	#endif
	313
4490e013	314	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
1fbca0db MS	315	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
	316	debug("Watchdog: Not found by seq!\n");
	317	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
	318	puts("Watchdog: Not found!\n");
	319	return 0;
	320	}
4490e013	321	}
1fbca0db MS	322
	323	wdt_start(watchdog_dev, 0, 0);
	324	puts("Watchdog: Started\n");
4490e013 MS	325	#endif
4490e013 MS	326
84c7204b MS	327	return 0;
	328	}
	329
4490e013 MS	330	#ifdef CONFIG_WATCHDOG
	331	/* Called by macro WATCHDOG_RESET */
	332	void watchdog_reset(void)
	333	{
	334	# if !defined(CONFIG_SPL_BUILD)
	335	static ulong next_reset;
	336	ulong now;
	337
	338	if (!watchdog_dev)
	339	return;
	340
	341	now = timer_get_us();
	342
	343	/* Do not reset the watchdog too often */
	344	if (now > next_reset) {
	345	wdt_reset(watchdog_dev);
	346	next_reset = now + 1000;
	347	}
	348	# endif
	349	}
	350	#endif
	351
84c7204b MS	352	int board_early_init_r(void)
	353	{
	354	u32 val;
	355
ec60a279 SDPP	356	if (current_el() != 3)
	357	return 0;
	358
90a35db4 MS	359	val = readl(&crlapb_base->timestamp_ref_ctrl);
	360	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	361
ec60a279	362	if (!val) {
0785dfd8 MS	363	val = readl(&crlapb_base->timestamp_ref_ctrl);
	364	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	365	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	366
0785dfd8 MS	367	/* Program freq register in System counter */
	368	writel(zynqmp_get_system_timer_freq(),
	369	&iou_scntr_secure->base_frequency_id_register);
	370	/* And enable system counter */
	371	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	372	&iou_scntr_secure->counter_control_register);
	373	}
84c7204b MS	374	return 0;
	375	}
	376
6919b4bf MS	377	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	378	{
	379	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	380	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
	381	defined(CONFIG_ZYNQ_EEPROM_BUS)
	382	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
	383
	384	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	385	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	386	ethaddr, 6))
	387	printf("I2C EEPROM MAC address read failed\n");
	388	#endif
	389
	390	return 0;
	391	}
	392
51916864 NJ	393	unsigned long do_go_exec(ulong (entry)(int, char const []), int argc,
	394	char * const argv[])
	395	{
	396	int ret = 0;
	397
	398	if (current_el() > 1) {
	399	smp_kick_all_cpus();
	400	dcache_disable();
	401	armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
	402	ES_TO_AARCH64);
	403	} else {
	404	printf("FAIL: current EL is not above EL1\n");
	405	ret = EINVAL;
	406	}
	407	return ret;
	408	}
	409
8d59d7f6	410	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	411	int dram_init_banksize(void)
361a8799	412	{
0678941a NJ	413	int ret;
	414
	415	ret = fdtdec_setup_memory_banksize();
	416	if (ret)
	417	return ret;
	418
	419	mem_map_fill();
	420
	421	return 0;
8a5db0ab	422	}
8d59d7f6	423
361a8799	424	int dram_init(void)
8a5db0ab	425	{
12308b12	426	if (fdtdec_setup_mem_size_base() != 0)
950f86ca	427	return -EINVAL;
8a5db0ab	428
361a8799	429	return 0;
8d59d7f6 MS	430	}
8d59d7f6 MS	431	#else
0678941a NJ	432	int dram_init_banksize(void)
	433	{
	434	#if defined(CONFIG_NR_DRAM_BANKS)
	435	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	436	gd->bd->bi_dram[0].size = get_effective_memsize();
	437	#endif
	438
	439	mem_map_fill();
	440
	441	return 0;
	442	}
	443
84c7204b MS	444	int dram_init(void)
84c7204b MS	445	{
61dc92a2 MS	446	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
61dc92a2 MS	447	CONFIG_SYS_SDRAM_SIZE);
84c7204b MS	448
	449	return 0;
	450	}
8d59d7f6	451	#endif
84c7204b	452
84c7204b MS	453	void reset_cpu(ulong addr)
	454	{
	455	}
	456
d348beaa MS	457	static const struct {
	458	u32 bit;
	459	const char *name;
	460	} reset_reasons[] = {
	461	{ RESET_REASON_DEBUG_SYS, "DEBUG" },
	462	{ RESET_REASON_SOFT, "SOFT" },
	463	{ RESET_REASON_SRST, "SRST" },
	464	{ RESET_REASON_PSONLY, "PS-ONLY" },
	465	{ RESET_REASON_PMU, "PMU" },
	466	{ RESET_REASON_INTERNAL, "INTERNAL" },
	467	{ RESET_REASON_EXTERNAL, "EXTERNAL" },
	468	{}
	469	};
	470
	471	static u32 reset_reason(void)
	472	{
	473	u32 ret;
	474	int i;
	475	const char *reason = NULL;
	476
	477	ret = readl(&crlapb_base->reset_reason);
	478
	479	puts("Reset reason:\t");
	480
	481	for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
	482	if (ret & reset_reasons[i].bit) {
	483	reason = reset_reasons[i].name;
	484	printf("%s ", reset_reasons[i].name);
	485	break;
	486	}
	487	}
	488
	489	puts("\n");
	490
	491	env_set("reset_reason", reason);
	492
	493	writel(~0, &crlapb_base->reset_reason);
	494
	495	return ret;
	496	}
	497
84c7204b MS	498	int board_late_init(void)
	499	{
	500	u32 reg = 0;
	501	u8 bootmode;
2882b39d MS	502	struct udevice *dev;
	503	int bootseq = -1;
	504	int bootseq_len = 0;
0478b0b9	505	int env_targets_len = 0;
b72894f1 MS	506	const char *mode;
b72894f1 MS	507	char *new_targets;
01c42d3d	508	char *env_targets;
d1db89f4	509	int ret;
b72894f1 MS	510
	511	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	512	debug("Saved variables - Skipping\n");
	513	return 0;
	514	}
84c7204b	515
d1db89f4 SDPP	516	ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
	517	if (ret)
	518	return -EINVAL;
	519
47359a03 MS	520	if (reg >> BOOT_MODE_ALT_SHIFT)
	521	reg >>= BOOT_MODE_ALT_SHIFT;
	522
84c7204b MS	523	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	524
fb90917c	525	puts("Bootmode: ");
84c7204b	526	switch (bootmode) {
d58fc12e MS	527	case USB_MODE:
	528	puts("USB_MODE\n");
	529	mode = "usb";
07656ba5	530	env_set("modeboot", "usb_dfu_spl");
d58fc12e	531	break;
0a5bcc8c	532	case JTAG_MODE:
fb90917c	533	puts("JTAG_MODE\n");
b72894f1	534	mode = "pxe dhcp";
07656ba5	535	env_set("modeboot", "jtagboot");
0a5bcc8c SDPP	536	break;
	537	case QSPI_MODE_24BIT:
	538	case QSPI_MODE_32BIT:
b72894f1	539	mode = "qspi0";
fb90917c	540	puts("QSPI_MODE\n");
07656ba5	541	env_set("modeboot", "qspiboot");
0a5bcc8c	542	break;
39c56f55	543	case EMMC_MODE:
78678fee	544	puts("EMMC_MODE\n");
b72894f1	545	mode = "mmc0";
07656ba5	546	env_set("modeboot", "emmcboot");
78678fee MS	547	break;
78678fee MS	548	case SD_MODE:
fb90917c	549	puts("SD_MODE\n");
2882b39d MS	550	if (uclass_get_device_by_name(UCLASS_MMC,
	551	"sdhci@ff160000", &dev)) {
	552	puts("Boot from SD0 but without SD0 enabled!\n");
	553	return -1;
	554	}
	555	debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
	556
	557	mode = "mmc";
	558	bootseq = dev->seq;
07656ba5	559	env_set("modeboot", "sdboot");
84c7204b	560	break;
e1992276 SDPP	561	case SD1_LSHFT_MODE:
	562	puts("LVL_SHFT_");
	563	/* fall through */
af813acd	564	case SD_MODE1:
fb90917c	565	puts("SD_MODE1\n");
2882b39d MS	566	if (uclass_get_device_by_name(UCLASS_MMC,
	567	"sdhci@ff170000", &dev)) {
	568	puts("Boot from SD1 but without SD1 enabled!\n");
	569	return -1;
	570	}
	571	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	572
	573	mode = "mmc";
	574	bootseq = dev->seq;
07656ba5	575	env_set("modeboot", "sdboot");
af813acd MS	576	break;
af813acd MS	577	case NAND_MODE:
fb90917c	578	puts("NAND_MODE\n");
b72894f1	579	mode = "nand0";
07656ba5	580	env_set("modeboot", "nandboot");
af813acd	581	break;
84c7204b	582	default:
b72894f1	583	mode = "";
84c7204b MS	584	printf("Invalid Boot Mode:0x%x\n", bootmode);
	585	break;
	586	}
	587
2882b39d MS	588	if (bootseq >= 0) {
	589	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	590	debug("Bootseq len: %x\n", bootseq_len);
	591	}
	592
b72894f1 MS	593	/*
	594	* One terminating char + one byte for space between mode
	595	* and default boot_targets
	596	*/
01c42d3d	597	env_targets = env_get("boot_targets");
0478b0b9 MS	598	if (env_targets)
	599	env_targets_len = strlen(env_targets);
	600
2882b39d MS	601	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
2882b39d MS	602	bootseq_len);
1e3e68f1 MS	603	if (!new_targets)
1e3e68f1 MS	604	return -ENOMEM;
0478b0b9	605
2882b39d MS	606	if (bootseq >= 0)
	607	sprintf(new_targets, "%s%x %s", mode, bootseq,
	608	env_targets ? env_targets : "");
	609	else
	610	sprintf(new_targets, "%s %s", mode,
	611	env_targets ? env_targets : "");
b72894f1	612
382bee57	613	env_set("boot_targets", new_targets);
b72894f1	614
d348beaa MS	615	reset_reason();
d348beaa MS	616
84c7204b MS	617	return 0;
84c7204b MS	618	}
84696ff5 SDPP	619
	620	int checkboard(void)
	621	{
5af08556	622	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	623	return 0;
84696ff5 SDPP	624	}