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cmd/bdinfo: extract print_bi_boot_params
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CommitLineData
8bde7f77
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
8bde7f77
WD
6 */
7
8/*
9 * Boot support
10 */
11#include <common.h>
12#include <command.h>
d88af4da 13#include <linux/compiler.h>
8bde7f77 14
d87080b7 15DECLARE_GLOBAL_DATA_PTR;
8bde7f77 16
d88af4da
MF
17__maybe_unused
18static void print_num(const char *name, ulong value)
19{
20 printf("%-12s= 0x%08lX\n", name, value);
21}
8bde7f77 22
5f3dfadc 23__maybe_unused
d88af4da
MF
24static void print_eth(int idx)
25{
26 char name[10], *val;
27 if (idx)
28 sprintf(name, "eth%iaddr", idx);
29 else
30 strcpy(name, "ethaddr");
31 val = getenv(name);
32 if (!val)
33 val = "(not set)";
34 printf("%-12s= %s\n", name, val);
35}
de2dff6f 36
05c3e68f 37#ifndef CONFIG_DM_ETH
9fc6a06a
MS
38__maybe_unused
39static void print_eths(void)
40{
41 struct eth_device *dev;
42 int i = 0;
43
44 do {
45 dev = eth_get_dev_by_index(i);
46 if (dev) {
47 printf("eth%dname = %s\n", i, dev->name);
48 print_eth(i);
49 i++;
50 }
51 } while (dev);
52
53 printf("current eth = %s\n", eth_get_name());
54 printf("ip_addr = %s\n", getenv("ipaddr"));
55}
05c3e68f 56#endif
9fc6a06a 57
d88af4da 58__maybe_unused
47708457 59static void print_lnum(const char *name, unsigned long long value)
d88af4da
MF
60{
61 printf("%-12s= 0x%.8llX\n", name, value);
62}
63
64__maybe_unused
65static void print_mhz(const char *name, unsigned long hz)
66{
67 char buf[32];
68
69 printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
70}
8bde7f77 71
171e5396
MF
72
73static inline void print_bi_boot_params(const bd_t *bd)
74{
75 print_num("boot_params", (ulong)bd->bi_boot_params);
76}
77
c99ea790 78#if defined(CONFIG_PPC)
e7939464
YS
79void __weak board_detail(void)
80{
81 /* Please define boot_detail() for your platform */
82}
8bde7f77 83
5902e8f7 84int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 85{
8bde7f77 86 bd_t *bd = gd->bd;
8bde7f77
WD
87
88#ifdef DEBUG
5902e8f7
ML
89 print_num("bd address", (ulong)bd);
90#endif
91 print_num("memstart", bd->bi_memstart);
92 print_lnum("memsize", bd->bi_memsize);
93 print_num("flashstart", bd->bi_flashstart);
94 print_num("flashsize", bd->bi_flashsize);
95 print_num("flashoffset", bd->bi_flashoffset);
96 print_num("sramstart", bd->bi_sramstart);
97 print_num("sramsize", bd->bi_sramsize);
98#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
58dac327 99 defined(CONFIG_MPC8260) || defined(CONFIG_E500)
5902e8f7
ML
100 print_num("immr_base", bd->bi_immr_base);
101#endif
102 print_num("bootflags", bd->bi_bootflags);
3fb85889 103#if defined(CONFIG_405EP) || \
5902e8f7
ML
104 defined(CONFIG_405GP) || \
105 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
106 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
107 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
108 defined(CONFIG_XILINX_405)
0c277ef9
TT
109 print_mhz("procfreq", bd->bi_procfreq);
110 print_mhz("plb_busfreq", bd->bi_plb_busfreq);
5902e8f7
ML
111#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
112 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
113 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
114 defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
0c277ef9 115 print_mhz("pci_busfreq", bd->bi_pci_busfreq);
8bde7f77 116#endif
3fb85889 117#else /* ! CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
9c4c5ae3 118#if defined(CONFIG_CPM2)
0c277ef9
TT
119 print_mhz("vco", bd->bi_vco);
120 print_mhz("sccfreq", bd->bi_sccfreq);
121 print_mhz("brgfreq", bd->bi_brgfreq);
8bde7f77 122#endif
0c277ef9 123 print_mhz("intfreq", bd->bi_intfreq);
9c4c5ae3 124#if defined(CONFIG_CPM2)
0c277ef9 125 print_mhz("cpmfreq", bd->bi_cpmfreq);
8bde7f77 126#endif
0c277ef9 127 print_mhz("busfreq", bd->bi_busfreq);
3fb85889 128#endif /* CONFIG_405GP, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
03f5c550 129
34e210f5
TT
130#ifdef CONFIG_ENABLE_36BIT_PHYS
131#ifdef CONFIG_PHYS_64BIT
132 puts("addressing = 36-bit\n");
133#else
134 puts("addressing = 32-bit\n");
135#endif
136#endif
137
de2dff6f 138 print_eth(0);
e2ffd59b 139#if defined(CONFIG_HAS_ETH1)
de2dff6f 140 print_eth(1);
03f5c550 141#endif
e2ffd59b 142#if defined(CONFIG_HAS_ETH2)
de2dff6f 143 print_eth(2);
42d1f039 144#endif
e2ffd59b 145#if defined(CONFIG_HAS_ETH3)
de2dff6f 146 print_eth(3);
03f5c550 147#endif
c68a05fe 148#if defined(CONFIG_HAS_ETH4)
de2dff6f 149 print_eth(4);
c68a05fe 150#endif
c68a05fe 151#if defined(CONFIG_HAS_ETH5)
de2dff6f 152 print_eth(5);
c68a05fe 153#endif
154
50a47d05 155 printf("IP addr = %s\n", getenv("ipaddr"));
8e261575 156 printf("baudrate = %6u bps\n", gd->baudrate);
5902e8f7 157 print_num("relocaddr", gd->relocaddr);
e7939464 158 board_detail();
8bde7f77
WD
159 return 0;
160}
161
c99ea790 162#elif defined(CONFIG_NIOS2)
5c952cf0 163
5902e8f7 164int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
5c952cf0 165{
744b57b8 166 int i;
5c952cf0
WD
167 bd_t *bd = gd->bd;
168
744b57b8
TC
169 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
170 print_num("DRAM bank", i);
171 print_num("-> start", bd->bi_dram[i].start);
172 print_num("-> size", bd->bi_dram[i].size);
173 }
174
5902e8f7
ML
175 print_num("flash start", (ulong)bd->bi_flashstart);
176 print_num("flash size", (ulong)bd->bi_flashsize);
177 print_num("flash offset", (ulong)bd->bi_flashoffset);
5c952cf0 178
6d0f6bcf 179#if defined(CONFIG_SYS_SRAM_BASE)
5c952cf0
WD
180 print_num ("sram start", (ulong)bd->bi_sramstart);
181 print_num ("sram size", (ulong)bd->bi_sramsize);
182#endif
183
90253178 184#if defined(CONFIG_CMD_NET)
de2dff6f 185 print_eth(0);
50a47d05 186 printf("ip_addr = %s\n", getenv("ipaddr"));
5c952cf0
WD
187#endif
188
8e261575 189 printf("baudrate = %u bps\n", gd->baudrate);
5c952cf0
WD
190
191 return 0;
192}
c99ea790
RM
193
194#elif defined(CONFIG_MICROBLAZE)
cfc67116 195
5902e8f7 196int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cfc67116 197{
cfc67116 198 bd_t *bd = gd->bd;
e945f6dc
MS
199 int i;
200
201 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
202 print_num("DRAM bank", i);
203 print_num("-> start", bd->bi_dram[i].start);
204 print_num("-> size", bd->bi_dram[i].size);
205 }
206
5902e8f7
ML
207 print_num("flash start ", (ulong)bd->bi_flashstart);
208 print_num("flash size ", (ulong)bd->bi_flashsize);
209 print_num("flash offset ", (ulong)bd->bi_flashoffset);
6d0f6bcf 210#if defined(CONFIG_SYS_SRAM_BASE)
5902e8f7
ML
211 print_num("sram start ", (ulong)bd->bi_sramstart);
212 print_num("sram size ", (ulong)bd->bi_sramsize);
cfc67116 213#endif
062f078c 214#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
9fc6a06a 215 print_eths();
cfc67116 216#endif
8e261575 217 printf("baudrate = %u bps\n", gd->baudrate);
e945f6dc
MS
218 print_num("relocaddr", gd->relocaddr);
219 print_num("reloc off", gd->reloc_off);
de86765b
MS
220 print_num("fdt_blob", (ulong)gd->fdt_blob);
221 print_num("new_fdt", (ulong)gd->new_fdt);
222 print_num("fdt_size", (ulong)gd->fdt_size);
e945f6dc 223
cfc67116
MS
224 return 0;
225}
4a551709 226
c99ea790
RM
227#elif defined(CONFIG_SPARC)
228
54841ab5 229int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
00ab32c8
DH
230{
231 bd_t *bd = gd->bd;
00ab32c8
DH
232
233#ifdef DEBUG
234 print_num("bd address ", (ulong) bd);
235#endif
236 print_num("memstart ", bd->bi_memstart);
b57ca3e1 237 print_lnum("memsize ", bd->bi_memsize);
00ab32c8 238 print_num("flashstart ", bd->bi_flashstart);
6d0f6bcf 239 print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
0e8d1586 240 print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
d97f01a6 241 printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%x (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
6d0f6bcf 242 CONFIG_SYS_MONITOR_LEN);
d97f01a6 243 printf("CONFIG_SYS_MALLOC_BASE = 0x%x (%d)\n", CONFIG_SYS_MALLOC_BASE,
6d0f6bcf 244 CONFIG_SYS_MALLOC_LEN);
d97f01a6 245 printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%x (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
6d0f6bcf 246 CONFIG_SYS_STACK_SIZE);
d97f01a6 247 printf("CONFIG_SYS_PROM_OFFSET = 0x%x (%d)\n", CONFIG_SYS_PROM_OFFSET,
6d0f6bcf 248 CONFIG_SYS_PROM_SIZE);
d97f01a6 249 printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%x (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
25ddd1fb 250 GENERATED_GBL_DATA_SIZE);
00ab32c8
DH
251
252#if defined(CONFIG_CMD_NET)
de2dff6f 253 print_eth(0);
50a47d05 254 printf("ip_addr = %s\n", getenv("ipaddr"));
00ab32c8 255#endif
8e261575 256 printf("baudrate = %6u bps\n", gd->baudrate);
00ab32c8
DH
257 return 0;
258}
259
c99ea790
RM
260#elif defined(CONFIG_M68K)
261
5902e8f7 262int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8e585f02 263{
8e585f02 264 bd_t *bd = gd->bd;
8ae158cd 265
5902e8f7
ML
266 print_num("memstart", (ulong)bd->bi_memstart);
267 print_lnum("memsize", (u64)bd->bi_memsize);
268 print_num("flashstart", (ulong)bd->bi_flashstart);
269 print_num("flashsize", (ulong)bd->bi_flashsize);
270 print_num("flashoffset", (ulong)bd->bi_flashoffset);
6d0f6bcf 271#if defined(CONFIG_SYS_INIT_RAM_ADDR)
5902e8f7
ML
272 print_num("sramstart", (ulong)bd->bi_sramstart);
273 print_num("sramsize", (ulong)bd->bi_sramsize);
8e585f02 274#endif
6d0f6bcf 275#if defined(CONFIG_SYS_MBAR)
5902e8f7 276 print_num("mbar", bd->bi_mbar_base);
8e585f02 277#endif
0c277ef9
TT
278 print_mhz("cpufreq", bd->bi_intfreq);
279 print_mhz("busfreq", bd->bi_busfreq);
8ae158cd 280#ifdef CONFIG_PCI
0c277ef9 281 print_mhz("pcifreq", bd->bi_pcifreq);
8ae158cd
TL
282#endif
283#ifdef CONFIG_EXTRA_CLOCK
0c277ef9
TT
284 print_mhz("flbfreq", bd->bi_flbfreq);
285 print_mhz("inpfreq", bd->bi_inpfreq);
286 print_mhz("vcofreq", bd->bi_vcofreq);
8ae158cd 287#endif
26667b7f 288#if defined(CONFIG_CMD_NET)
de2dff6f 289 print_eth(0);
8e585f02 290#if defined(CONFIG_HAS_ETH1)
de2dff6f 291 print_eth(1);
8e585f02 292#endif
8e585f02 293#if defined(CONFIG_HAS_ETH2)
de2dff6f 294 print_eth(2);
8e585f02 295#endif
8e585f02 296#if defined(CONFIG_HAS_ETH3)
de2dff6f 297 print_eth(3);
8e585f02
TL
298#endif
299
50a47d05 300 printf("ip_addr = %s\n", getenv("ipaddr"));
26667b7f 301#endif
8e261575 302 printf("baudrate = %u bps\n", gd->baudrate);
8e585f02
TL
303
304 return 0;
305}
306
8dc48d71 307#elif defined(CONFIG_BLACKFIN)
c99ea790 308
54841ab5 309int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8dc48d71 310{
8dc48d71
MF
311 bd_t *bd = gd->bd;
312
313 printf("U-Boot = %s\n", bd->bi_r_version);
314 printf("CPU = %s\n", bd->bi_cpu);
315 printf("Board = %s\n", bd->bi_board_name);
0c277ef9
TT
316 print_mhz("VCO", bd->bi_vco);
317 print_mhz("CCLK", bd->bi_cclk);
318 print_mhz("SCLK", bd->bi_sclk);
8dc48d71 319
171e5396 320 print_bi_boot_params(bd);
5902e8f7
ML
321 print_num("memstart", (ulong)bd->bi_memstart);
322 print_lnum("memsize", (u64)bd->bi_memsize);
323 print_num("flashstart", (ulong)bd->bi_flashstart);
324 print_num("flashsize", (ulong)bd->bi_flashsize);
325 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8dc48d71 326
de2dff6f 327 print_eth(0);
50a47d05 328 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 329 printf("baudrate = %u bps\n", gd->baudrate);
8dc48d71
MF
330
331 return 0;
332}
333
c99ea790 334#elif defined(CONFIG_MIPS)
8bde7f77 335
5902e8f7 336int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 337{
8bde7f77
WD
338 bd_t *bd = gd->bd;
339
171e5396 340 print_bi_boot_params(bd);
5902e8f7
ML
341 print_num("memstart", (ulong)bd->bi_memstart);
342 print_lnum("memsize", (u64)bd->bi_memsize);
343 print_num("flashstart", (ulong)bd->bi_flashstart);
344 print_num("flashsize", (ulong)bd->bi_flashsize);
345 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8bde7f77 346
de2dff6f 347 print_eth(0);
50a47d05 348 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 349 printf("baudrate = %u bps\n", gd->baudrate);
8cf7a418
TC
350 print_num("relocaddr", gd->relocaddr);
351 print_num("reloc off", gd->reloc_off);
8bde7f77
WD
352
353 return 0;
354}
8bde7f77 355
c99ea790
RM
356#elif defined(CONFIG_AVR32)
357
5902e8f7 358int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c99ea790
RM
359{
360 bd_t *bd = gd->bd;
361
171e5396 362 print_bi_boot_params(bd);
a752a8b4
AB
363 print_num("memstart", (ulong)bd->bi_dram[0].start);
364 print_lnum("memsize", (u64)bd->bi_dram[0].size);
5902e8f7
ML
365 print_num("flashstart", (ulong)bd->bi_flashstart);
366 print_num("flashsize", (ulong)bd->bi_flashsize);
367 print_num("flashoffset", (ulong)bd->bi_flashoffset);
c99ea790
RM
368
369 print_eth(0);
50a47d05 370 printf("ip_addr = %s\n", getenv("ipaddr"));
8e261575 371 printf("baudrate = %u bps\n", gd->baudrate);
c99ea790
RM
372
373 return 0;
374}
375
376#elif defined(CONFIG_ARM)
8bde7f77 377
0e350f81
JH
378static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
379 char * const argv[])
8bde7f77 380{
8bde7f77
WD
381 int i;
382 bd_t *bd = gd->bd;
383
5902e8f7 384 print_num("arch_number", bd->bi_arch_number);
171e5396 385 print_bi_boot_params(bd);
8bde7f77 386
5902e8f7 387 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
8bde7f77
WD
388 print_num("DRAM bank", i);
389 print_num("-> start", bd->bi_dram[i].start);
390 print_num("-> size", bd->bi_dram[i].size);
391 }
392
e8149522 393#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
e61a7534 394 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
e8149522 395 print_num("Secure ram",
e61a7534 396 gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK);
e8149522
YS
397 }
398#endif
ff973800 399#if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH)
9fc6a06a 400 print_eths();
a41dbbd9 401#endif
8e261575 402 printf("baudrate = %u bps\n", gd->baudrate);
e47f2db5 403#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
34fd5d25 404 print_num("TLB addr", gd->arch.tlb_addr);
f1d2b313 405#endif
5902e8f7
ML
406 print_num("relocaddr", gd->relocaddr);
407 print_num("reloc off", gd->reloc_off);
408 print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
409 print_num("sp start ", gd->start_addr_sp);
c8fcd0f2 410#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
5902e8f7 411 print_num("FB base ", gd->fb_base);
c8fcd0f2 412#endif
8f5d4687
HM
413 /*
414 * TODO: Currently only support for davinci SOC's is added.
415 * Remove this check once all the board implement this.
416 */
417#ifdef CONFIG_CLOCKS
418 printf("ARM frequency = %ld MHz\n", gd->bd->bi_arm_freq);
419 printf("DSP frequency = %ld MHz\n", gd->bd->bi_dsp_freq);
420 printf("DDR frequency = %ld MHz\n", gd->bd->bi_ddr_freq);
7bb7d672
HS
421#endif
422#ifdef CONFIG_BOARD_TYPES
423 printf("Board Type = %ld\n", gd->board_type);
8f5d4687 424#endif
7f7ddf2a
SG
425#ifdef CONFIG_SYS_MALLOC_F
426 printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
427 CONFIG_SYS_MALLOC_F_LEN);
428#endif
429
8bde7f77
WD
430 return 0;
431}
432
ebd0d062
NI
433#elif defined(CONFIG_SH)
434
5902e8f7 435int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ebd0d062
NI
436{
437 bd_t *bd = gd->bd;
5902e8f7
ML
438 print_num("mem start ", (ulong)bd->bi_memstart);
439 print_lnum("mem size ", (u64)bd->bi_memsize);
440 print_num("flash start ", (ulong)bd->bi_flashstart);
441 print_num("flash size ", (ulong)bd->bi_flashsize);
442 print_num("flash offset ", (ulong)bd->bi_flashoffset);
ebd0d062
NI
443
444#if defined(CONFIG_CMD_NET)
445 print_eth(0);
50a47d05 446 printf("ip_addr = %s\n", getenv("ipaddr"));
ebd0d062 447#endif
8e261575 448 printf("baudrate = %u bps\n", gd->baudrate);
ebd0d062
NI
449 return 0;
450}
451
a806ee6f
GR
452#elif defined(CONFIG_X86)
453
5902e8f7 454int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a806ee6f
GR
455{
456 int i;
457 bd_t *bd = gd->bd;
a806ee6f 458
171e5396 459 print_bi_boot_params(bd);
5902e8f7
ML
460 print_num("bi_memstart", bd->bi_memstart);
461 print_num("bi_memsize", bd->bi_memsize);
462 print_num("bi_flashstart", bd->bi_flashstart);
463 print_num("bi_flashsize", bd->bi_flashsize);
464 print_num("bi_flashoffset", bd->bi_flashoffset);
465 print_num("bi_sramstart", bd->bi_sramstart);
466 print_num("bi_sramsize", bd->bi_sramsize);
467 print_num("bi_bootflags", bd->bi_bootflags);
0c277ef9
TT
468 print_mhz("cpufreq", bd->bi_intfreq);
469 print_mhz("busfreq", bd->bi_busfreq);
5902e8f7
ML
470
471 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
a806ee6f
GR
472 print_num("DRAM bank", i);
473 print_num("-> start", bd->bi_dram[i].start);
474 print_num("-> size", bd->bi_dram[i].size);
475 }
476
477#if defined(CONFIG_CMD_NET)
478 print_eth(0);
50a47d05 479 printf("ip_addr = %s\n", getenv("ipaddr"));
0c277ef9 480 print_mhz("ethspeed", bd->bi_ethspeed);
a806ee6f 481#endif
8e261575 482 printf("baudrate = %u bps\n", gd->baudrate);
a806ee6f
GR
483
484 return 0;
485}
486
6fcc3be4
SG
487#elif defined(CONFIG_SANDBOX)
488
489int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
490{
491 int i;
492 bd_t *bd = gd->bd;
493
171e5396 494 print_bi_boot_params(bd);
6fcc3be4
SG
495
496 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
497 print_num("DRAM bank", i);
498 print_num("-> start", bd->bi_dram[i].start);
499 print_num("-> size", bd->bi_dram[i].size);
500 }
501
502#if defined(CONFIG_CMD_NET)
503 print_eth(0);
50a47d05 504 printf("ip_addr = %s\n", getenv("ipaddr"));
6fcc3be4 505#endif
c8fcd0f2 506#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
6fcc3be4 507 print_num("FB base ", gd->fb_base);
c8fcd0f2 508#endif
6fcc3be4
SG
509 return 0;
510}
511
64d61461
ML
512#elif defined(CONFIG_NDS32)
513
514int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
515{
516 int i;
517 bd_t *bd = gd->bd;
518
519 print_num("arch_number", bd->bi_arch_number);
171e5396 520 print_bi_boot_params(bd);
64d61461
ML
521
522 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
523 print_num("DRAM bank", i);
524 print_num("-> start", bd->bi_dram[i].start);
525 print_num("-> size", bd->bi_dram[i].size);
526 }
527
528#if defined(CONFIG_CMD_NET)
529 print_eth(0);
50a47d05 530 printf("ip_addr = %s\n", getenv("ipaddr"));
64d61461 531#endif
8e261575 532 printf("baudrate = %u bps\n", gd->baudrate);
64d61461
ML
533
534 return 0;
535}
536
2be9fdbf
SK
537#elif defined(CONFIG_OPENRISC)
538
539int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
540{
541 bd_t *bd = gd->bd;
542
543 print_num("mem start", (ulong)bd->bi_memstart);
544 print_lnum("mem size", (u64)bd->bi_memsize);
545 print_num("flash start", (ulong)bd->bi_flashstart);
546 print_num("flash size", (ulong)bd->bi_flashsize);
547 print_num("flash offset", (ulong)bd->bi_flashoffset);
548
549#if defined(CONFIG_CMD_NET)
550 print_eth(0);
50a47d05 551 printf("ip_addr = %s\n", getenv("ipaddr"));
2be9fdbf
SK
552#endif
553
8e261575 554 printf("baudrate = %u bps\n", gd->baudrate);
2be9fdbf
SK
555
556 return 0;
557}
558
946f6f24 559#elif defined(CONFIG_ARC)
bc5d5428
AB
560
561int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
562{
563 bd_t *bd = gd->bd;
564
565 print_num("mem start", bd->bi_memstart);
566 print_lnum("mem size", bd->bi_memsize);
567
568#if defined(CONFIG_CMD_NET)
569 print_eth(0);
570 printf("ip_addr = %s\n", getenv("ipaddr"));
571#endif
8e261575 572 printf("baudrate = %d bps\n", gd->baudrate);
bc5d5428
AB
573
574 return 0;
575}
576
c99ea790
RM
577#else
578 #error "a case for this architecture does not exist!"
579#endif
8bde7f77 580
8bde7f77
WD
581/* -------------------------------------------------------------------- */
582
0d498393
WD
583U_BOOT_CMD(
584 bdinfo, 1, 1, do_bdinfo,
2fb2604d 585 "print Board Info structure",
a89c33db 586 ""
8bde7f77 587);