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ba56f625 WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
265817c7 WD |
3 | * This source code has been made available to you by IBM on an AS-IS |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 9 | * |
265817c7 WD |
10 | * Any user of this software should understand that IBM cannot provide |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
ba56f625 | 13 | * |
265817c7 WD |
14 | * Any person who transfers this source code or any derivative work |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 17 | * |
265817c7 WD |
18 | * COPYRIGHT I B M CORPORATION 1995 |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
20 | *-----------------------------------------------------------------------------*/ |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
265817c7 | 23 | * File Name: enetemac.c |
ba56f625 | 24 | * |
265817c7 | 25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 26 | * |
265817c7 | 27 | * Author: Mark Wisner |
ba56f625 WD |
28 | * |
29 | * Change Activity- | |
30 | * | |
265817c7 WD |
31 | * Date Description of Change BY |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 70 | *-----------------------------------------------------------------------------* |
265817c7 WD |
71 | * 17-Nov-03 travis.sawyer@sandburst.com |
72 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
73 | * in the 440GX. This port should work with the 440GP | |
74 | * (2 EMACs) also | |
75 | * 15-Aug-05 sr@denx.de | |
76 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
77 | now handling all 4xx cpu's. | |
ba56f625 WD |
78 | *-----------------------------------------------------------------------------*/ |
79 | ||
80 | #include <config.h> | |
ba56f625 WD |
81 | #include <common.h> |
82 | #include <net.h> | |
83 | #include <asm/processor.h> | |
2d83476a | 84 | #include <asm/io.h> |
ff768cb1 SR |
85 | #include <asm/cache.h> |
86 | #include <asm/mmu.h> | |
ba56f625 | 87 | #include <commproc.h> |
d6c61aab SR |
88 | #include <ppc4xx.h> |
89 | #include <ppc4xx_enet.h> | |
ba56f625 WD |
90 | #include <405_mal.h> |
91 | #include <miiphy.h> | |
92 | #include <malloc.h> | |
6e9233d3 | 93 | #include <asm/ppc4xx-intvec.h> |
ba56f625 | 94 | |
d6c61aab | 95 | /* |
0c8721a4 | 96 | * Only compile for platform with AMCC EMAC ethernet controller and |
d6c61aab SR |
97 | * network support enabled. |
98 | * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! | |
99 | */ | |
3a1ed1e1 | 100 | #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) |
d6c61aab | 101 | |
3a1ed1e1 | 102 | #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) |
d6c61aab SR |
103 | #error "CONFIG_MII has to be defined!" |
104 | #endif | |
ba56f625 | 105 | |
1e25f957 SR |
106 | #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) |
107 | #error "CONFIG_NET_MULTI has to be defined for NetConsole" | |
108 | #endif | |
109 | ||
265817c7 | 110 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
1338e6a8 | 111 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ |
ba56f625 | 112 | |
ba56f625 WD |
113 | /* Ethernet Transmit and Receive Buffers */ |
114 | /* AS.HARNOIS | |
115 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
116 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
117 | */ | |
265817c7 | 118 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
119 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
120 | ||
ba56f625 WD |
121 | /*-----------------------------------------------------------------------------+ |
122 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
123 | * Interrupt Controller). | |
124 | *-----------------------------------------------------------------------------*/ | |
125 | #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
126 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
127 | #define EMAC_UIC_DEF UIC_ENET | |
d6c61aab SR |
128 | #define EMAC_UIC_DEF1 UIC_ENET1 |
129 | #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) | |
ba56f625 | 130 | |
d6c61aab | 131 | #undef INFO_4XX_ENET |
ba56f625 | 132 | |
265817c7 WD |
133 | #define BI_PHYMODE_NONE 0 |
134 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a | 135 | #define BI_PHYMODE_RGMII 2 |
887e2ec9 SR |
136 | #define BI_PHYMODE_GMII 3 |
137 | #define BI_PHYMODE_RTBI 4 | |
138 | #define BI_PHYMODE_TBI 5 | |
dbbd1257 | 139 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 140 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 141 | defined(CONFIG_405EX) |
887e2ec9 SR |
142 | #define BI_PHYMODE_SMII 6 |
143 | #define BI_PHYMODE_MII 7 | |
8ac41e3e SR |
144 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
145 | #define BI_PHYMODE_RMII 8 | |
146 | #endif | |
887e2ec9 | 147 | #endif |
3c74e32a | 148 | |
1941cce7 | 149 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 150 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 151 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 152 | defined(CONFIG_405EX) |
887e2ec9 SR |
153 | #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) |
154 | #endif | |
d6c61aab | 155 | |
8ac41e3e SR |
156 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
157 | #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) | |
158 | #endif | |
159 | ||
160 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
161 | #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ | |
162 | #else | |
163 | #define MAL_RX_CHAN_MUL 1 | |
164 | #endif | |
165 | ||
ba56f625 WD |
166 | /*-----------------------------------------------------------------------------+ |
167 | * Global variables. TX and RX descriptors and buffers. | |
168 | *-----------------------------------------------------------------------------*/ | |
169 | /* IER globals */ | |
170 | static uint32_t mal_ier; | |
171 | ||
d6c61aab | 172 | #if !defined(CONFIG_NET_MULTI) |
4f92ac36 | 173 | struct eth_device *emac0_dev = NULL; |
d6c61aab SR |
174 | #endif |
175 | ||
1e25f957 SR |
176 | /* |
177 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
178 | * supported by the cpu) | |
353f2688 SR |
179 | * |
180 | * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the | |
181 | * EMAC count is possible. As it is needed for the Kilauea/Haleakala | |
182 | * 405EX/405EXr eval board, using the same binary. | |
1e25f957 | 183 | */ |
353f2688 SR |
184 | #if defined(CONFIG_BOARD_EMAC_COUNT) |
185 | #define LAST_EMAC_NUM board_emac_count() | |
186 | #else /* CONFIG_BOARD_EMAC_COUNT */ | |
1e25f957 SR |
187 | #if defined(CONFIG_HAS_ETH3) |
188 | #define LAST_EMAC_NUM 4 | |
189 | #elif defined(CONFIG_HAS_ETH2) | |
190 | #define LAST_EMAC_NUM 3 | |
191 | #elif defined(CONFIG_HAS_ETH1) | |
192 | #define LAST_EMAC_NUM 2 | |
193 | #else | |
194 | #define LAST_EMAC_NUM 1 | |
195 | #endif | |
353f2688 | 196 | #endif /* CONFIG_BOARD_EMAC_COUNT */ |
d6c61aab | 197 | |
5fb692ca SR |
198 | /* normal boards start with EMAC0 */ |
199 | #if !defined(CONFIG_EMAC_NR_START) | |
200 | #define CONFIG_EMAC_NR_START 0 | |
201 | #endif | |
202 | ||
dbbd1257 SR |
203 | #if defined(CONFIG_405EX) || defined(CONFIG_440EPX) |
204 | #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev))) | |
205 | #else | |
206 | #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2)) | |
207 | #endif | |
208 | ||
ff768cb1 SR |
209 | #define MAL_RX_DESC_SIZE 2048 |
210 | #define MAL_TX_DESC_SIZE 2048 | |
211 | #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) | |
212 | ||
ba56f625 WD |
213 | /*-----------------------------------------------------------------------------+ |
214 | * Prototypes and externals. | |
215 | *-----------------------------------------------------------------------------*/ | |
216 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
217 | ||
218 | int enetInt (struct eth_device *dev); | |
219 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
220 | unsigned long uic, unsigned long maldef, | |
221 | unsigned long mal_errr); | |
222 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
223 | ||
63ff004c MB |
224 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
225 | extern int emac4xx_miiphy_read (char *devname, unsigned char addr, | |
226 | unsigned char reg, unsigned short *value); | |
227 | extern int emac4xx_miiphy_write (char *devname, unsigned char addr, | |
228 | unsigned char reg, unsigned short value); | |
d6c61aab | 229 | |
353f2688 SR |
230 | int board_emac_count(void); |
231 | ||
8ac41e3e SR |
232 | static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) |
233 | { | |
234 | #if defined(CONFIG_440SPE) || \ | |
235 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
236 | defined(CONFIG_405EX) | |
237 | u32 val; | |
238 | ||
239 | mfsdr(sdr_mfr, val); | |
240 | val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); | |
241 | mtsdr(sdr_mfr, val); | |
242 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
243 | u32 val; | |
244 | ||
245 | mfsdr(SDR0_ETH_CFG, val); | |
246 | val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
247 | mtsdr(SDR0_ETH_CFG, val); | |
248 | #endif | |
249 | } | |
250 | ||
251 | static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) | |
252 | { | |
253 | #if defined(CONFIG_440SPE) || \ | |
254 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
255 | defined(CONFIG_405EX) | |
256 | u32 val; | |
257 | ||
258 | mfsdr(sdr_mfr, val); | |
259 | val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); | |
260 | mtsdr(sdr_mfr, val); | |
261 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
262 | u32 val; | |
263 | ||
264 | mfsdr(SDR0_ETH_CFG, val); | |
265 | val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); | |
266 | mtsdr(SDR0_ETH_CFG, val); | |
267 | #endif | |
268 | } | |
269 | ||
ba56f625 | 270 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 271 | | ppc_4xx_eth_halt |
ba56f625 | 272 | | Disable MAL channel, and EMACn |
ba56f625 | 273 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 274 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 275 | { |
d6c61aab | 276 | EMAC_4XX_HW_PST hw_p = dev->priv; |
9ad31989 | 277 | u32 val = 10000; |
ba56f625 | 278 | |
2d83476a | 279 | out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ |
ba56f625 WD |
280 | |
281 | /* 1st reset MAL channel */ | |
282 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab SR |
283 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
284 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
285 | #else | |
ba56f625 | 286 | mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 287 | #endif |
ba56f625 WD |
288 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
289 | ||
290 | /* wait for reset */ | |
d6c61aab | 291 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 | 292 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
9ad31989 SR |
293 | val--; |
294 | if (val == 0) | |
ba56f625 | 295 | break; |
ba56f625 WD |
296 | } |
297 | ||
6c5879f3 | 298 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 299 | emac_loopback_enable(hw_p); |
6c5879f3 | 300 | |
8ac41e3e | 301 | /* EMAC RESET */ |
2d83476a | 302 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
ba56f625 | 303 | |
6c5879f3 | 304 | /* remove clocks for EMAC internal loopback */ |
8ac41e3e | 305 | emac_loopback_disable(hw_p); |
6c5879f3 | 306 | |
a93316c5 | 307 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 308 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 309 | #endif |
c157d8e2 | 310 | |
4c9e8557 SR |
311 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
312 | /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ | |
9ad31989 SR |
313 | mfsdr(SDR0_ETH_CFG, val); |
314 | val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
315 | mtsdr(SDR0_ETH_CFG, val); | |
4c9e8557 SR |
316 | #endif |
317 | ||
ba56f625 WD |
318 | return; |
319 | } | |
320 | ||
846b0dd2 | 321 | #if defined (CONFIG_440GX) |
d6c61aab | 322 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
323 | { |
324 | unsigned long pfc1; | |
325 | unsigned long zmiifer; | |
326 | unsigned long rmiifer; | |
327 | ||
328 | mfsdr(sdr_pfc1, pfc1); | |
329 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); | |
330 | ||
331 | zmiifer = 0; | |
332 | rmiifer = 0; | |
333 | ||
334 | switch (pfc1) { | |
335 | case 1: | |
336 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
337 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
338 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
339 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
340 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
341 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
342 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
343 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
344 | break; | |
345 | case 2: | |
f6e495f5 SR |
346 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); |
347 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
348 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
349 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
855a496f WD |
350 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
351 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
352 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
353 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
354 | break; | |
355 | case 3: | |
356 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
357 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
358 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
359 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
360 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
361 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
362 | break; | |
363 | case 4: | |
364 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
365 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
366 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
367 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
368 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
369 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
370 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
371 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
372 | break; | |
373 | case 5: | |
374 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
375 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
376 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
377 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
378 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
379 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
380 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
381 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
382 | break; | |
383 | case 6: | |
384 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
385 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
386 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
387 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
388 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
389 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
390 | break; |
391 | case 0: | |
392 | default: | |
393 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
394 | rmiifer = 0x0; | |
395 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
396 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
397 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
398 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
399 | break; | |
400 | } | |
401 | ||
402 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
403 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
404 | ||
ff768cb1 SR |
405 | out_be32((void *)ZMII_FER, zmiifer); |
406 | out_be32((void *)RGMII_FER, rmiifer); | |
855a496f WD |
407 | |
408 | return ((int)pfc1); | |
855a496f | 409 | } |
6c5879f3 | 410 | #endif /* CONFIG_440_GX */ |
855a496f | 411 | |
887e2ec9 SR |
412 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
413 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
414 | { | |
415 | unsigned long zmiifer=0x0; | |
37ed6cdd | 416 | unsigned long pfc1; |
887e2ec9 | 417 | |
37ed6cdd MF |
418 | mfsdr(sdr_pfc1, pfc1); |
419 | pfc1 &= SDR0_PFC1_SELECT_MASK; | |
420 | ||
2f15278c | 421 | switch (pfc1) { |
37ed6cdd | 422 | case SDR0_PFC1_SELECT_CONFIG_2: |
887e2ec9 | 423 | /* 1 x GMII port */ |
2d83476a SR |
424 | out_be32((void *)ZMII_FER, 0x00); |
425 | out_be32((void *)RGMII_FER, 0x00000037); | |
887e2ec9 SR |
426 | bis->bi_phymode[0] = BI_PHYMODE_GMII; |
427 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
428 | break; | |
37ed6cdd | 429 | case SDR0_PFC1_SELECT_CONFIG_4: |
887e2ec9 | 430 | /* 2 x RGMII ports */ |
2d83476a SR |
431 | out_be32((void *)ZMII_FER, 0x00); |
432 | out_be32((void *)RGMII_FER, 0x00000055); | |
887e2ec9 SR |
433 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
434 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
435 | break; | |
37ed6cdd | 436 | case SDR0_PFC1_SELECT_CONFIG_6: |
887e2ec9 | 437 | /* 2 x SMII ports */ |
2d83476a SR |
438 | out_be32((void *)ZMII_FER, |
439 | ((ZMII_FER_SMII) << ZMII_FER_V(0)) | | |
440 | ((ZMII_FER_SMII) << ZMII_FER_V(1))); | |
441 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
442 | bis->bi_phymode[0] = BI_PHYMODE_SMII; |
443 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
444 | break; | |
445 | case SDR0_PFC1_SELECT_CONFIG_1_2: | |
446 | /* only 1 x MII supported */ | |
2d83476a SR |
447 | out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); |
448 | out_be32((void *)RGMII_FER, 0x00000000); | |
37ed6cdd MF |
449 | bis->bi_phymode[0] = BI_PHYMODE_MII; |
450 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
887e2ec9 SR |
451 | break; |
452 | default: | |
453 | break; | |
454 | } | |
455 | ||
456 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
2d83476a | 457 | zmiifer = in_be32((void *)ZMII_FER); |
887e2ec9 | 458 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); |
2d83476a | 459 | out_be32((void *)ZMII_FER, zmiifer); |
887e2ec9 SR |
460 | |
461 | return ((int)0x0); | |
462 | } | |
463 | #endif /* CONFIG_440EPX */ | |
464 | ||
dbbd1257 SR |
465 | #if defined(CONFIG_405EX) |
466 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
467 | { | |
1740c1bf | 468 | u32 rgmiifer = 0; |
dbbd1257 SR |
469 | |
470 | /* | |
1740c1bf GE |
471 | * The 405EX(r)'s RGMII bridge can operate in one of several |
472 | * modes, only one of which (2 x RGMII) allows the | |
473 | * simultaneous use of both EMACs on the 405EX. | |
dbbd1257 | 474 | */ |
1740c1bf GE |
475 | |
476 | switch (CONFIG_EMAC_PHY_MODE) { | |
477 | ||
478 | case EMAC_PHY_MODE_NONE: | |
479 | /* No ports */ | |
480 | rgmiifer |= RGMII_FER_DIS << 0; | |
481 | rgmiifer |= RGMII_FER_DIS << 4; | |
482 | out_be32((void *)RGMII_FER, rgmiifer); | |
483 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
484 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
485 | break; | |
486 | case EMAC_PHY_MODE_NONE_RGMII: | |
487 | /* 1 x RGMII port on channel 0 */ | |
488 | rgmiifer |= RGMII_FER_RGMII << 0; | |
489 | rgmiifer |= RGMII_FER_DIS << 4; | |
490 | out_be32((void *)RGMII_FER, rgmiifer); | |
491 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
492 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
493 | break; | |
494 | case EMAC_PHY_MODE_RGMII_NONE: | |
495 | /* 1 x RGMII port on channel 1 */ | |
496 | rgmiifer |= RGMII_FER_DIS << 0; | |
497 | rgmiifer |= RGMII_FER_RGMII << 4; | |
498 | out_be32((void *)RGMII_FER, rgmiifer); | |
499 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
500 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
501 | break; | |
502 | case EMAC_PHY_MODE_RGMII_RGMII: | |
dbbd1257 | 503 | /* 2 x RGMII ports */ |
1740c1bf GE |
504 | rgmiifer |= RGMII_FER_RGMII << 0; |
505 | rgmiifer |= RGMII_FER_RGMII << 4; | |
506 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
507 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
508 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
509 | break; | |
1740c1bf GE |
510 | case EMAC_PHY_MODE_NONE_GMII: |
511 | /* 1 x GMII port on channel 0 */ | |
512 | rgmiifer |= RGMII_FER_GMII << 0; | |
513 | rgmiifer |= RGMII_FER_DIS << 4; | |
514 | out_be32((void *)RGMII_FER, rgmiifer); | |
515 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
516 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
517 | break; | |
518 | case EMAC_PHY_MODE_NONE_MII: | |
519 | /* 1 x MII port on channel 0 */ | |
520 | rgmiifer |= RGMII_FER_MII << 0; | |
521 | rgmiifer |= RGMII_FER_DIS << 4; | |
522 | out_be32((void *)RGMII_FER, rgmiifer); | |
523 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
524 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
525 | break; | |
526 | case EMAC_PHY_MODE_GMII_NONE: | |
527 | /* 1 x GMII port on channel 1 */ | |
528 | rgmiifer |= RGMII_FER_DIS << 0; | |
529 | rgmiifer |= RGMII_FER_GMII << 4; | |
530 | out_be32((void *)RGMII_FER, rgmiifer); | |
531 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
532 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
533 | break; | |
534 | case EMAC_PHY_MODE_MII_NONE: | |
535 | /* 1 x MII port on channel 1 */ | |
536 | rgmiifer |= RGMII_FER_DIS << 0; | |
537 | rgmiifer |= RGMII_FER_MII << 4; | |
538 | out_be32((void *)RGMII_FER, rgmiifer); | |
539 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
540 | bis->bi_phymode[1] = BI_PHYMODE_MII; | |
dbbd1257 SR |
541 | break; |
542 | default: | |
543 | break; | |
544 | } | |
545 | ||
546 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
1740c1bf GE |
547 | rgmiifer = in_be32((void *)RGMII_FER); |
548 | rgmiifer |= (1 << (19-devnum)); | |
549 | out_be32((void *)RGMII_FER, rgmiifer); | |
dbbd1257 SR |
550 | |
551 | return ((int)0x0); | |
552 | } | |
553 | #endif /* CONFIG_405EX */ | |
554 | ||
8ac41e3e SR |
555 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
556 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
557 | { | |
558 | u32 eth_cfg; | |
559 | u32 zmiifer; /* ZMII0_FER reg. */ | |
560 | u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ | |
561 | u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ | |
4c9e8557 | 562 | int mode; |
8ac41e3e SR |
563 | |
564 | zmiifer = 0; | |
565 | rmiifer = 0; | |
566 | rmiifer1 = 0; | |
567 | ||
4c9e8557 SR |
568 | #if defined(CONFIG_460EX) |
569 | mode = 9; | |
570 | #else | |
571 | mode = 10; | |
572 | #endif | |
573 | ||
8ac41e3e SR |
574 | /* TODO: |
575 | * NOTE: 460GT has 2 RGMII bridge cores: | |
576 | * emac0 ------ RGMII0_BASE | |
577 | * | | |
578 | * emac1 -----+ | |
579 | * | |
580 | * emac2 ------ RGMII1_BASE | |
581 | * | | |
582 | * emac3 -----+ | |
583 | * | |
584 | * 460EX has 1 RGMII bridge core: | |
585 | * and RGMII1_BASE is disabled | |
586 | * emac0 ------ RGMII0_BASE | |
587 | * | | |
588 | * emac1 -----+ | |
589 | */ | |
590 | ||
591 | /* | |
592 | * Right now only 2*RGMII is supported. Please extend when needed. | |
593 | * sr - 2008-02-19 | |
594 | */ | |
4c9e8557 | 595 | switch (mode) { |
8ac41e3e SR |
596 | case 1: |
597 | /* 1 MII - 460EX */ | |
598 | /* GMC0 EMAC4_0, ZMII Bridge */ | |
599 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
600 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
601 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
602 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
603 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
604 | break; | |
605 | case 2: | |
606 | /* 2 MII - 460GT */ | |
607 | /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ | |
608 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); | |
609 | zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); | |
610 | bis->bi_phymode[0] = BI_PHYMODE_MII; | |
611 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
612 | bis->bi_phymode[2] = BI_PHYMODE_MII; | |
613 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
614 | break; | |
615 | case 3: | |
616 | /* 2 RMII - 460EX */ | |
617 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
618 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
619 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
620 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
621 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
622 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
623 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
624 | break; | |
625 | case 4: | |
626 | /* 4 RMII - 460GT */ | |
627 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ | |
628 | /* ZMII Bridge */ | |
629 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
630 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
631 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
632 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
633 | bis->bi_phymode[0] = BI_PHYMODE_RMII; | |
634 | bis->bi_phymode[1] = BI_PHYMODE_RMII; | |
635 | bis->bi_phymode[2] = BI_PHYMODE_RMII; | |
636 | bis->bi_phymode[3] = BI_PHYMODE_RMII; | |
637 | break; | |
638 | case 5: | |
639 | /* 2 SMII - 460EX */ | |
640 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ | |
641 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
642 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
643 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
644 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
645 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
646 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
647 | break; | |
648 | case 6: | |
649 | /* 4 SMII - 460GT */ | |
650 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ | |
651 | /* ZMII Bridge */ | |
652 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
653 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
654 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
655 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
656 | bis->bi_phymode[0] = BI_PHYMODE_SMII; | |
657 | bis->bi_phymode[1] = BI_PHYMODE_SMII; | |
658 | bis->bi_phymode[2] = BI_PHYMODE_SMII; | |
659 | bis->bi_phymode[3] = BI_PHYMODE_SMII; | |
660 | break; | |
661 | case 7: | |
662 | /* This is the default mode that we want for board bringup - Maple */ | |
663 | /* 1 GMII - 460EX */ | |
664 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
665 | rmiifer |= RGMII_FER_MDIO(0); | |
666 | ||
667 | if (devnum == 0) { | |
668 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
669 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
670 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
671 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
672 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
673 | } else { | |
674 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ | |
675 | bis->bi_phymode[0] = BI_PHYMODE_NONE; | |
676 | bis->bi_phymode[1] = BI_PHYMODE_GMII; | |
677 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
678 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
679 | } | |
680 | break; | |
681 | case 8: | |
682 | /* 2 GMII - 460GT */ | |
683 | /* GMC0 EMAC4_0, RGMII Bridge 0 */ | |
684 | /* GMC1 EMAC4_2, RGMII Bridge 1 */ | |
685 | rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ | |
686 | rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ | |
687 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
688 | rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ | |
689 | ||
690 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
691 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
692 | bis->bi_phymode[2] = BI_PHYMODE_GMII; | |
693 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
694 | break; | |
695 | case 9: | |
696 | /* 2 RGMII - 460EX */ | |
697 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
698 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
699 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
700 | rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ | |
701 | ||
702 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
703 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
704 | bis->bi_phymode[2] = BI_PHYMODE_NONE; | |
705 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
706 | break; | |
707 | case 10: | |
708 | /* 4 RGMII - 460GT */ | |
709 | /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ | |
710 | /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ | |
711 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
712 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
713 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
714 | rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
715 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
716 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
717 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
718 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
719 | break; | |
720 | default: | |
721 | break; | |
722 | } | |
723 | ||
724 | /* Set EMAC for MDIO */ | |
725 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
726 | eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; | |
727 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
728 | ||
729 | out_be32((void *)RGMII_FER, rmiifer); | |
730 | #if defined(CONFIG_460GT) | |
731 | out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); | |
732 | #endif | |
733 | ||
734 | /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ | |
735 | mfsdr(SDR0_ETH_CFG, eth_cfg); | |
736 | eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); | |
737 | mtsdr(SDR0_ETH_CFG, eth_cfg); | |
738 | ||
739 | return 0; | |
740 | } | |
741 | #endif /* CONFIG_460EX || CONFIG_460GT */ | |
742 | ||
ff768cb1 SR |
743 | static inline void *malloc_aligned(u32 size, u32 align) |
744 | { | |
745 | return (void *)(((u32)malloc(size + align) + align - 1) & | |
746 | ~(align - 1)); | |
747 | } | |
748 | ||
d6c61aab | 749 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 750 | { |
ff768cb1 | 751 | int i; |
d6c61aab | 752 | unsigned long reg = 0; |
ba56f625 WD |
753 | unsigned long msr; |
754 | unsigned long speed; | |
755 | unsigned long duplex; | |
756 | unsigned long failsafe; | |
757 | unsigned mode_reg; | |
758 | unsigned short devnum; | |
759 | unsigned short reg_short; | |
887e2ec9 SR |
760 | #if defined(CONFIG_440GX) || \ |
761 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 762 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 763 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 764 | defined(CONFIG_405EX) |
d6c61aab | 765 | sys_info_t sysinfo; |
887e2ec9 | 766 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
dbbd1257 | 767 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 768 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 769 | defined(CONFIG_405EX) |
6e7fb6ea SR |
770 | int ethgroup = -1; |
771 | #endif | |
6c5879f3 | 772 | #endif |
ff768cb1 SR |
773 | u32 bd_cached; |
774 | u32 bd_uncached = 0; | |
4fae35a5 AG |
775 | #ifdef CONFIG_4xx_DCACHE |
776 | static u32 last_used_ea = 0; | |
777 | #endif | |
e54ec0f0 SR |
778 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
779 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ | |
780 | defined(CONFIG_405EX) | |
781 | int rgmii_channel; | |
782 | #endif | |
6c5879f3 | 783 | |
d6c61aab | 784 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
785 | |
786 | /* before doing anything, figure out if we have a MAC address */ | |
787 | /* if not, bail */ | |
4f92ac36 SR |
788 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
789 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 790 | return -1; |
4f92ac36 | 791 | } |
ba56f625 | 792 | |
887e2ec9 SR |
793 | #if defined(CONFIG_440GX) || \ |
794 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 795 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 796 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 797 | defined(CONFIG_405EX) |
ba56f625 WD |
798 | /* Need to get the OPB frequency so we can access the PHY */ |
799 | get_sys_info (&sysinfo); | |
d6c61aab | 800 | #endif |
ba56f625 | 801 | |
ba56f625 WD |
802 | msr = mfmsr (); |
803 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
804 | ||
805 | devnum = hw_p->devnum; | |
806 | ||
d6c61aab | 807 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
808 | /* AS.HARNOIS |
809 | * We should have : | |
265817c7 | 810 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
811 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
812 | * is possible that new packets (without relationship with | |
813 | * current transfer) have got the time to arrived before | |
814 | * netloop calls eth_halt | |
815 | */ | |
816 | printf ("About preceeding transfer (eth%d):\n" | |
817 | "- Sent packet number %d\n" | |
818 | "- Received packet number %d\n" | |
819 | "- Handled packet number %d\n", | |
820 | hw_p->devnum, | |
821 | hw_p->stats.pkts_tx, | |
822 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
823 | ||
824 | hw_p->stats.pkts_tx = 0; | |
825 | hw_p->stats.pkts_rx = 0; | |
826 | hw_p->stats.pkts_handled = 0; | |
6c5879f3 | 827 | hw_p->print_speed = 1; /* print speed message again next time */ |
ba56f625 WD |
828 | #endif |
829 | ||
265817c7 WD |
830 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
831 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
832 | |
833 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
834 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
835 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
836 | ||
837 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
838 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
839 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
840 | ||
6c5879f3 | 841 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
842 | /* set RMII mode */ |
843 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
844 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
845 | /* NOTE: only one emac at a time */ | |
846 | reg = 0; | |
2d83476a | 847 | out_be32((void *)ZMII_FER, 0); |
ba56f625 | 848 | udelay (100); |
ba56f625 | 849 | |
8ac41e3e | 850 | #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
2d83476a | 851 | out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
8ac41e3e SR |
852 | #elif defined(CONFIG_440GX) || \ |
853 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
854 | defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
d6c61aab | 855 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
0e6d798c | 856 | #endif |
c57c7980 | 857 | |
2d83476a | 858 | out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
6e7fb6ea | 859 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
dbbd1257 SR |
860 | #if defined(CONFIG_405EX) |
861 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); | |
862 | #endif | |
d6c61aab | 863 | |
8ac41e3e | 864 | sync(); |
0e6d798c | 865 | |
6c5879f3 | 866 | /* provide clocks for EMAC internal loopback */ |
8ac41e3e | 867 | emac_loopback_enable(hw_p); |
0e6d798c | 868 | |
8ac41e3e | 869 | /* EMAC RESET */ |
2d83476a | 870 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
ba56f625 | 871 | |
8ac41e3e SR |
872 | /* remove clocks for EMAC internal loopback */ |
873 | emac_loopback_disable(hw_p); | |
874 | ||
ba56f625 | 875 | failsafe = 1000; |
2d83476a | 876 | while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { |
ba56f625 WD |
877 | udelay (1000); |
878 | failsafe--; | |
879 | } | |
887e2ec9 SR |
880 | if (failsafe <= 0) |
881 | printf("\nProblem resetting EMAC!\n"); | |
ba56f625 | 882 | |
887e2ec9 SR |
883 | #if defined(CONFIG_440GX) || \ |
884 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 885 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 886 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 887 | defined(CONFIG_405EX) |
ba56f625 WD |
888 | /* Whack the M1 register */ |
889 | mode_reg = 0x0; | |
890 | mode_reg &= ~0x00000038; | |
891 | if (sysinfo.freqOPB <= 50000000); | |
892 | else if (sysinfo.freqOPB <= 66666667) | |
893 | mode_reg |= EMAC_M1_OBCI_66; | |
894 | else if (sysinfo.freqOPB <= 83333333) | |
895 | mode_reg |= EMAC_M1_OBCI_83; | |
896 | else if (sysinfo.freqOPB <= 100000000) | |
897 | mode_reg |= EMAC_M1_OBCI_100; | |
898 | else | |
899 | mode_reg |= EMAC_M1_OBCI_GT100; | |
900 | ||
2d83476a | 901 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
6e7fb6ea | 902 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
ba56f625 WD |
903 | |
904 | /* wait for PHY to complete auto negotiation */ | |
905 | reg_short = 0; | |
906 | #ifndef CONFIG_CS8952_PHY | |
907 | switch (devnum) { | |
908 | case 0: | |
909 | reg = CONFIG_PHY_ADDR; | |
910 | break; | |
d6c61aab | 911 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
912 | case 1: |
913 | reg = CONFIG_PHY1_ADDR; | |
914 | break; | |
d6c61aab | 915 | #endif |
4c9e8557 | 916 | #if defined (CONFIG_PHY2_ADDR) |
ba56f625 WD |
917 | case 2: |
918 | reg = CONFIG_PHY2_ADDR; | |
919 | break; | |
4c9e8557 SR |
920 | #endif |
921 | #if defined (CONFIG_PHY3_ADDR) | |
ba56f625 WD |
922 | case 3: |
923 | reg = CONFIG_PHY3_ADDR; | |
924 | break; | |
925 | #endif | |
926 | default: | |
927 | reg = CONFIG_PHY_ADDR; | |
928 | break; | |
929 | } | |
930 | ||
3c74e32a WD |
931 | bis->bi_phynum[devnum] = reg; |
932 | ||
d6c61aab | 933 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
934 | /* |
935 | * Reset the phy, only if its the first time through | |
936 | * otherwise, just check the speeds & feeds | |
937 | */ | |
938 | if (hw_p->first_init == 0) { | |
ec0c2ec7 | 939 | #if defined(CONFIG_M88E1111_PHY) |
887e2ec9 SR |
940 | miiphy_write (dev->name, reg, 0x14, 0x0ce3); |
941 | miiphy_write (dev->name, reg, 0x18, 0x4101); | |
942 | miiphy_write (dev->name, reg, 0x09, 0x0e00); | |
943 | miiphy_write (dev->name, reg, 0x04, 0x01e1); | |
944 | #endif | |
63ff004c | 945 | miiphy_reset (dev->name, reg); |
ba56f625 | 946 | |
887e2ec9 SR |
947 | #if defined(CONFIG_440GX) || \ |
948 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 949 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 950 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 951 | defined(CONFIG_405EX) |
887e2ec9 | 952 | |
0e6d798c | 953 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 954 | /* |
17f50f22 SR |
955 | * Cicada 8201 PHY needs to have an extended register whacked |
956 | * for RGMII mode. | |
fc1cfcdb | 957 | */ |
887e2ec9 | 958 | if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { |
b79316f2 | 959 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 960 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 961 | #else |
63ff004c | 962 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 963 | #endif |
17f50f22 SR |
964 | /* |
965 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
966 | * Interoperability problem with Intel 82547EI phys | |
967 | * This work around (provided by Vitesse) changes | |
968 | * the default timer convergence from 8ms to 12ms | |
969 | */ | |
63ff004c MB |
970 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
971 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
972 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
973 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
974 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
975 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
976 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
977 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
978 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
979 | /* end Vitesse/Cicada errata */ |
980 | } | |
0e6d798c | 981 | #endif |
5fb692ca SR |
982 | |
983 | #if defined(CONFIG_ET1011C_PHY) | |
984 | /* | |
985 | * Agere ET1011c PHY needs to have an extended register whacked | |
986 | * for RGMII mode. | |
987 | */ | |
988 | if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { | |
989 | miiphy_read (dev->name, reg, 0x16, ®_short); | |
990 | reg_short &= ~(0x7); | |
991 | reg_short |= 0x6; /* RGMII DLL Delay*/ | |
992 | miiphy_write (dev->name, reg, 0x16, reg_short); | |
993 | ||
994 | miiphy_read (dev->name, reg, 0x17, ®_short); | |
995 | reg_short &= ~(0x40); | |
996 | miiphy_write (dev->name, reg, 0x17, reg_short); | |
997 | ||
998 | miiphy_write(dev->name, reg, 0x1c, 0x74f0); | |
999 | } | |
1000 | #endif | |
1001 | ||
855a496f | 1002 | #endif |
a06752e3 | 1003 | /* Start/Restart autonegotiation */ |
63ff004c | 1004 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
1005 | udelay (1000); |
1006 | } | |
d6c61aab | 1007 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 1008 | |
63ff004c | 1009 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
1010 | |
1011 | /* | |
0e6d798c | 1012 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 WD |
1013 | */ |
1014 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
1015 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
1016 | puts ("Waiting for PHY auto negotiation to complete"); | |
1017 | i = 0; | |
1018 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
1019 | /* | |
1020 | * Timeout reached ? | |
1021 | */ | |
1022 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
1023 | puts (" TIMEOUT !\n"); | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | if ((i++ % 1000) == 0) { | |
1028 | putc ('.'); | |
1029 | } | |
1030 | udelay (1000); /* 1 ms */ | |
63ff004c | 1031 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
1032 | |
1033 | } | |
1034 | puts (" done\n"); | |
1035 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
1036 | } | |
d6c61aab SR |
1037 | #endif /* #ifndef CONFIG_CS8952_PHY */ |
1038 | ||
63ff004c MB |
1039 | speed = miiphy_speed (dev->name, reg); |
1040 | duplex = miiphy_duplex (dev->name, reg); | |
ba56f625 WD |
1041 | |
1042 | if (hw_p->print_speed) { | |
1043 | hw_p->print_speed = 0; | |
5fb692ca SR |
1044 | printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", |
1045 | (int) speed, (duplex == HALF) ? "HALF" : "FULL", | |
1046 | hw_p->devnum); | |
ba56f625 WD |
1047 | } |
1048 | ||
8ac41e3e SR |
1049 | #if defined(CONFIG_440) && \ |
1050 | !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ | |
1051 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ | |
1052 | !defined(CONFIG_460EX) && !defined(CONFIG_460GT) | |
846b0dd2 | 1053 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
1054 | mfsdr(sdr_mfr, reg); |
1055 | if (speed == 100) { | |
1056 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
1057 | } else { | |
1058 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
1059 | } | |
1060 | mtsdr(sdr_mfr, reg); | |
1061 | #endif | |
c57c7980 | 1062 | |
ba56f625 | 1063 | /* Set ZMII/RGMII speed according to the phy link speed */ |
ff768cb1 | 1064 | reg = in_be32((void *)ZMII_SSR); |
855a496f | 1065 | if ( (speed == 100) || (speed == 1000) ) |
ff768cb1 | 1066 | out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
ba56f625 | 1067 | else |
ff768cb1 | 1068 | out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
ba56f625 WD |
1069 | |
1070 | if ((devnum == 2) || (devnum == 3)) { | |
1071 | if (speed == 1000) | |
1072 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
1073 | else if (speed == 100) | |
1074 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
887e2ec9 | 1075 | else if (speed == 10) |
ba56f625 | 1076 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); |
887e2ec9 SR |
1077 | else { |
1078 | printf("Error in RGMII Speed\n"); | |
1079 | return -1; | |
1080 | } | |
ff768cb1 | 1081 | out_be32((void *)RGMII_SSR, reg); |
ba56f625 | 1082 | } |
6e7fb6ea | 1083 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
ba56f625 | 1084 | |
dbbd1257 | 1085 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
8ac41e3e | 1086 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1087 | defined(CONFIG_405EX) |
e54ec0f0 SR |
1088 | if (devnum >= 2) |
1089 | rgmii_channel = devnum - 2; | |
1090 | else | |
1091 | rgmii_channel = devnum; | |
1092 | ||
887e2ec9 | 1093 | if (speed == 1000) |
e54ec0f0 | 1094 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1095 | else if (speed == 100) |
e54ec0f0 | 1096 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 | 1097 | else if (speed == 10) |
e54ec0f0 | 1098 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); |
887e2ec9 SR |
1099 | else { |
1100 | printf("Error in RGMII Speed\n"); | |
1101 | return -1; | |
1102 | } | |
2d83476a | 1103 | out_be32((void *)RGMII_SSR, reg); |
8ac41e3e SR |
1104 | #if defined(CONFIG_460GT) |
1105 | if ((devnum == 2) || (devnum == 3)) | |
1106 | out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); | |
1107 | #endif | |
887e2ec9 SR |
1108 | #endif |
1109 | ||
ba56f625 | 1110 | /* set the Mal configuration reg */ |
887e2ec9 SR |
1111 | #if defined(CONFIG_440GX) || \ |
1112 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
dbbd1257 | 1113 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
8ac41e3e | 1114 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 1115 | defined(CONFIG_405EX) |
17f50f22 SR |
1116 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
1117 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); | |
1118 | #else | |
1119 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
ba56f625 | 1120 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 SR |
1121 | if (get_pvr() == PVR_440GP_RB) { |
1122 | mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); | |
1123 | } | |
1124 | #endif | |
ba56f625 | 1125 | |
ba56f625 WD |
1126 | /* |
1127 | * Malloc MAL buffer desciptors, make sure they are | |
1128 | * aligned on cache line boundary size | |
1129 | * (401/403/IOP480 = 16, 405 = 32) | |
1130 | * and doesn't cross cache block boundaries. | |
1131 | */ | |
ff768cb1 SR |
1132 | if (hw_p->first_init == 0) { |
1133 | debug("*** Allocating descriptor memory ***\n"); | |
ba56f625 | 1134 | |
ff768cb1 SR |
1135 | bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); |
1136 | if (!bd_cached) { | |
b002144e | 1137 | printf("%s: Error allocating MAL descriptor buffers!\n", __func__); |
ff768cb1 SR |
1138 | return -1; |
1139 | } | |
b79316f2 | 1140 | |
ff768cb1 | 1141 | #ifdef CONFIG_4xx_DCACHE |
ba79fde5 | 1142 | flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); |
4fae35a5 | 1143 | if (!last_used_ea) |
5e3dca57 AG |
1144 | #if defined(CFG_MEM_TOP_HIDE) |
1145 | bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE; | |
1146 | #else | |
4fae35a5 | 1147 | bd_uncached = bis->bi_memsize; |
5e3dca57 | 1148 | #endif |
4fae35a5 AG |
1149 | else |
1150 | bd_uncached = last_used_ea + MAL_ALLOC_SIZE; | |
1151 | ||
1152 | last_used_ea = bd_uncached; | |
ff768cb1 SR |
1153 | program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, |
1154 | TLB_WORD2_I_ENABLE); | |
1155 | #else | |
1156 | bd_uncached = bd_cached; | |
1157 | #endif | |
1158 | hw_p->tx_phys = bd_cached; | |
1159 | hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; | |
1160 | hw_p->tx = (mal_desc_t *)(bd_uncached); | |
1161 | hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); | |
1162 | debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx); | |
ba56f625 WD |
1163 | } |
1164 | ||
1165 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
1166 | hw_p->tx[i].ctrl = 0; | |
1167 | hw_p->tx[i].data_len = 0; | |
ff768cb1 SR |
1168 | if (hw_p->first_init == 0) |
1169 | hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, | |
1170 | L1_CACHE_BYTES); | |
ba56f625 WD |
1171 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
1172 | if ((NUM_TX_BUFF - 1) == i) | |
1173 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
1174 | hw_p->tx_run[i] = -1; | |
ff768cb1 | 1175 | debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr); |
ba56f625 WD |
1176 | } |
1177 | ||
1178 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
1179 | hw_p->rx[i].ctrl = 0; | |
1180 | hw_p->rx[i].data_len = 0; | |
ff768cb1 | 1181 | hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; |
ba56f625 WD |
1182 | if ((NUM_RX_BUFF - 1) == i) |
1183 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
1184 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
1185 | hw_p->rx_ready[i] = -1; | |
ff768cb1 | 1186 | debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr); |
ba56f625 WD |
1187 | } |
1188 | ||
1189 | reg = 0x00000000; | |
1190 | ||
1191 | reg |= dev->enetaddr[0]; /* set high address */ | |
1192 | reg = reg << 8; | |
1193 | reg |= dev->enetaddr[1]; | |
1194 | ||
2d83476a | 1195 | out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); |
ba56f625 WD |
1196 | |
1197 | reg = 0x00000000; | |
1198 | reg |= dev->enetaddr[2]; /* set low address */ | |
1199 | reg = reg << 8; | |
1200 | reg |= dev->enetaddr[3]; | |
1201 | reg = reg << 8; | |
1202 | reg |= dev->enetaddr[4]; | |
1203 | reg = reg << 8; | |
1204 | reg |= dev->enetaddr[5]; | |
1205 | ||
2d83476a | 1206 | out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); |
ba56f625 WD |
1207 | |
1208 | switch (devnum) { | |
1209 | case 1: | |
1210 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1211 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
ff768cb1 | 1212 | mtdcr (maltxctp2r, hw_p->tx_phys); |
c157d8e2 | 1213 | #else |
ff768cb1 | 1214 | mtdcr (maltxctp1r, hw_p->tx_phys); |
c157d8e2 | 1215 | #endif |
d6c61aab | 1216 | #if defined(CONFIG_440) |
c157d8e2 | 1217 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 1218 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 1219 | #endif |
8ac41e3e SR |
1220 | |
1221 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
4c9e8557 | 1222 | mtdcr (malrxctp8r, hw_p->rx_phys); |
8ac41e3e SR |
1223 | /* set RX buffer size */ |
1224 | mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); | |
1225 | #else | |
ff768cb1 | 1226 | mtdcr (malrxctp1r, hw_p->rx_phys); |
ba56f625 WD |
1227 | /* set RX buffer size */ |
1228 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
8ac41e3e | 1229 | #endif |
ba56f625 | 1230 | break; |
846b0dd2 | 1231 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1232 | case 2: |
1233 | /* setup MAL tx & rx channel pointers */ | |
1234 | mtdcr (maltxbattr, 0x0); | |
ba56f625 | 1235 | mtdcr (malrxbattr, 0x0); |
ff768cb1 SR |
1236 | mtdcr (maltxctp2r, hw_p->tx_phys); |
1237 | mtdcr (malrxctp2r, hw_p->rx_phys); | |
ba56f625 WD |
1238 | /* set RX buffer size */ |
1239 | mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); | |
1240 | break; | |
1241 | case 3: | |
1242 | /* setup MAL tx & rx channel pointers */ | |
1243 | mtdcr (maltxbattr, 0x0); | |
ff768cb1 | 1244 | mtdcr (maltxctp3r, hw_p->tx_phys); |
ba56f625 | 1245 | mtdcr (malrxbattr, 0x0); |
ff768cb1 | 1246 | mtdcr (malrxctp3r, hw_p->rx_phys); |
ba56f625 WD |
1247 | /* set RX buffer size */ |
1248 | mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); | |
1249 | break; | |
c57c7980 | 1250 | #endif /* CONFIG_440GX */ |
4c9e8557 SR |
1251 | #if defined (CONFIG_460GT) |
1252 | case 2: | |
1253 | /* setup MAL tx & rx channel pointers */ | |
1254 | mtdcr (maltxbattr, 0x0); | |
1255 | mtdcr (malrxbattr, 0x0); | |
1256 | mtdcr (maltxctp2r, hw_p->tx_phys); | |
1257 | mtdcr (malrxctp16r, hw_p->rx_phys); | |
1258 | /* set RX buffer size */ | |
1259 | mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); | |
1260 | break; | |
1261 | case 3: | |
1262 | /* setup MAL tx & rx channel pointers */ | |
1263 | mtdcr (maltxbattr, 0x0); | |
1264 | mtdcr (malrxbattr, 0x0); | |
1265 | mtdcr (maltxctp3r, hw_p->tx_phys); | |
1266 | mtdcr (malrxctp24r, hw_p->rx_phys); | |
1267 | /* set RX buffer size */ | |
1268 | mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); | |
1269 | break; | |
1270 | #endif /* CONFIG_460GT */ | |
ba56f625 WD |
1271 | case 0: |
1272 | default: | |
1273 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 1274 | #if defined(CONFIG_440) |
ba56f625 | 1275 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 1276 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 1277 | #endif |
ff768cb1 SR |
1278 | mtdcr (maltxctp0r, hw_p->tx_phys); |
1279 | mtdcr (malrxctp0r, hw_p->rx_phys); | |
ba56f625 WD |
1280 | /* set RX buffer size */ |
1281 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
1282 | break; | |
1283 | } | |
1284 | ||
1285 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 1286 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
1287 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
1288 | #else | |
ba56f625 | 1289 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 1290 | #endif |
ba56f625 WD |
1291 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
1292 | ||
1293 | /* set transmit enable & receive enable */ | |
2d83476a | 1294 | out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
ba56f625 | 1295 | |
2d83476a | 1296 | mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); |
76957cb3 SR |
1297 | |
1298 | /* set rx-/tx-fifo size */ | |
1299 | mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; | |
ba56f625 WD |
1300 | |
1301 | /* set speed */ | |
6e7fb6ea | 1302 | if (speed == _1000BASET) { |
738815c0 SR |
1303 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
1304 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
6e7fb6ea | 1305 | unsigned long pfc1; |
887e2ec9 | 1306 | |
6e7fb6ea SR |
1307 | mfsdr (sdr_pfc1, pfc1); |
1308 | pfc1 |= SDR0_PFC1_EM_1000; | |
1309 | mtsdr (sdr_pfc1, pfc1); | |
1310 | #endif | |
855a496f | 1311 | mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; |
6e7fb6ea | 1312 | } else if (speed == _100BASET) |
ba56f625 WD |
1313 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; |
1314 | else | |
1315 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
1316 | if (duplex == FULL) | |
1317 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
1318 | ||
2d83476a | 1319 | out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
ba56f625 WD |
1320 | |
1321 | /* Enable broadcast and indvidual address */ | |
1322 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
2d83476a | 1323 | out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); |
ba56f625 WD |
1324 | |
1325 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
1326 | ||
1327 | /* set transmit request threshold register */ | |
2d83476a | 1328 | out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
ba56f625 | 1329 | |
265817c7 | 1330 | /* set receive low/high water mark register */ |
d6c61aab | 1331 | #if defined(CONFIG_440) |
6c5879f3 | 1332 | /* 440s has a 64 byte burst length */ |
2d83476a | 1333 | out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
d6c61aab SR |
1334 | #else |
1335 | /* 405s have a 16 byte burst length */ | |
2d83476a | 1336 | out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
d6c61aab | 1337 | #endif /* defined(CONFIG_440) */ |
2d83476a | 1338 | out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
ba56f625 WD |
1339 | |
1340 | /* Set fifo limit entry in tx mode 0 */ | |
2d83476a | 1341 | out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); |
ba56f625 | 1342 | /* Frame gap set */ |
2d83476a | 1343 | out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
ba56f625 WD |
1344 | |
1345 | /* Set EMAC IER */ | |
d6c61aab | 1346 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
1347 | if (speed == _100BASET) |
1348 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
1349 | ||
2d83476a SR |
1350 | out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ |
1351 | out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
ba56f625 WD |
1352 | |
1353 | if (hw_p->first_init == 0) { | |
1354 | /* | |
1355 | * Connect interrupt service routines | |
1356 | */ | |
dbbd1257 SR |
1357 | irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), |
1358 | (interrupt_handler_t *) enetInt, dev); | |
ba56f625 | 1359 | } |
ba56f625 WD |
1360 | |
1361 | mtmsr (msr); /* enable interrupts again */ | |
1362 | ||
1363 | hw_p->bis = bis; | |
1364 | hw_p->first_init = 1; | |
1365 | ||
802b769b | 1366 | return 0; |
ba56f625 WD |
1367 | } |
1368 | ||
1369 | ||
d6c61aab | 1370 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
ba56f625 WD |
1371 | int len) |
1372 | { | |
1373 | struct enet_frame *ef_ptr; | |
1374 | ulong time_start, time_now; | |
1375 | unsigned long temp_txm0; | |
d6c61aab | 1376 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1377 | |
1378 | ef_ptr = (struct enet_frame *) ptr; | |
1379 | ||
1380 | /*-----------------------------------------------------------------------+ | |
1381 | * Copy in our address into the frame. | |
1382 | *-----------------------------------------------------------------------*/ | |
1383 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
1384 | ||
1385 | /*-----------------------------------------------------------------------+ | |
1386 | * If frame is too long or too short, modify length. | |
1387 | *-----------------------------------------------------------------------*/ | |
1388 | /* TBS: where does the fragment go???? */ | |
1389 | if (len > ENET_MAX_MTU) | |
1390 | len = ENET_MAX_MTU; | |
1391 | ||
1392 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
1393 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
ba79fde5 | 1394 | flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); |
ba56f625 WD |
1395 | |
1396 | /*-----------------------------------------------------------------------+ | |
1397 | * set TX Buffer busy, and send it | |
1398 | *-----------------------------------------------------------------------*/ | |
1399 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
1400 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
1401 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
1402 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
1403 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
1404 | ||
1405 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
1406 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
1407 | ||
8ac41e3e | 1408 | sync(); |
ba56f625 | 1409 | |
2d83476a SR |
1410 | out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, |
1411 | in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
d6c61aab | 1412 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1413 | hw_p->stats.pkts_tx++; |
1414 | #endif | |
1415 | ||
1416 | /*-----------------------------------------------------------------------+ | |
1417 | * poll unitl the packet is sent and then make sure it is OK | |
1418 | *-----------------------------------------------------------------------*/ | |
1419 | time_start = get_timer (0); | |
1420 | while (1) { | |
2d83476a | 1421 | temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); |
ba56f625 WD |
1422 | /* loop until either TINT turns on or 3 seconds elapse */ |
1423 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
1424 | /* transmit is done, so now check for errors | |
1425 | * If there is an error, an interrupt should | |
1426 | * happen when we return | |
1427 | */ | |
1428 | time_now = get_timer (0); | |
1429 | if ((time_now - time_start) > 3000) { | |
1430 | return (-1); | |
1431 | } | |
1432 | } else { | |
1433 | return (len); | |
1434 | } | |
1435 | } | |
1436 | } | |
1437 | ||
6e7fb6ea | 1438 | |
dbbd1257 | 1439 | #if defined (CONFIG_440) || defined(CONFIG_405EX) |
ba56f625 | 1440 | |
6c5879f3 | 1441 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
6e7fb6ea SR |
1442 | /* |
1443 | * Hack: On 440SP all enet irq sources are located on UIC1 | |
1444 | * Needs some cleanup. --sr | |
1445 | */ | |
1446 | #define UIC0MSR uic1msr | |
1447 | #define UIC0SR uic1sr | |
8ac41e3e SR |
1448 | #define UIC1MSR uic1msr |
1449 | #define UIC1SR uic1sr | |
1450 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) | |
1451 | /* | |
1452 | * Hack: On 460EX/GT all enet irq sources are located on UIC2 | |
1453 | * Needs some cleanup. --ag | |
1454 | */ | |
1455 | #define UIC0MSR uic2msr | |
1456 | #define UIC0SR uic2sr | |
1457 | #define UIC1MSR uic2msr | |
1458 | #define UIC1SR uic2sr | |
6e7fb6ea SR |
1459 | #else |
1460 | #define UIC0MSR uic0msr | |
1461 | #define UIC0SR uic0sr | |
8ac41e3e SR |
1462 | #define UIC1MSR uic1msr |
1463 | #define UIC1SR uic1sr | |
6e7fb6ea SR |
1464 | #endif |
1465 | ||
dbbd1257 SR |
1466 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
1467 | defined(CONFIG_405EX) | |
887e2ec9 SR |
1468 | #define UICMSR_ETHX uic0msr |
1469 | #define UICSR_ETHX uic0sr | |
8ac41e3e SR |
1470 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
1471 | #define UICMSR_ETHX uic2msr | |
1472 | #define UICSR_ETHX uic2sr | |
887e2ec9 SR |
1473 | #else |
1474 | #define UICMSR_ETHX uic1msr | |
1475 | #define UICSR_ETHX uic1sr | |
1476 | #endif | |
1477 | ||
ba56f625 WD |
1478 | int enetInt (struct eth_device *dev) |
1479 | { | |
1480 | int serviced; | |
1481 | int rc = -1; /* default to not us */ | |
1482 | unsigned long mal_isr; | |
1483 | unsigned long emac_isr = 0; | |
1484 | unsigned long mal_rx_eob; | |
1485 | unsigned long my_uic0msr, my_uic1msr; | |
887e2ec9 | 1486 | unsigned long my_uicmsr_ethx; |
ba56f625 | 1487 | |
846b0dd2 | 1488 | #if defined(CONFIG_440GX) |
ba56f625 WD |
1489 | unsigned long my_uic2msr; |
1490 | #endif | |
d6c61aab | 1491 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
1492 | |
1493 | /* | |
1494 | * Because the mal is generic, we need to get the current | |
1495 | * eth device | |
1496 | */ | |
d6c61aab SR |
1497 | #if defined(CONFIG_NET_MULTI) |
1498 | dev = eth_get_dev(); | |
1499 | #else | |
1500 | dev = emac0_dev; | |
1501 | #endif | |
ba56f625 WD |
1502 | |
1503 | hw_p = dev->priv; | |
1504 | ||
ba56f625 WD |
1505 | /* enter loop that stays in interrupt code until nothing to service */ |
1506 | do { | |
1507 | serviced = 0; | |
1508 | ||
6e7fb6ea | 1509 | my_uic0msr = mfdcr (UIC0MSR); |
8ac41e3e | 1510 | my_uic1msr = mfdcr (UIC1MSR); |
846b0dd2 | 1511 | #if defined(CONFIG_440GX) |
ba56f625 WD |
1512 | my_uic2msr = mfdcr (uic2msr); |
1513 | #endif | |
887e2ec9 SR |
1514 | my_uicmsr_ethx = mfdcr (UICMSR_ETHX); |
1515 | ||
ba56f625 | 1516 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
887e2ec9 SR |
1517 | && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) |
1518 | && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { | |
ba56f625 WD |
1519 | /* not for us */ |
1520 | return (rc); | |
1521 | } | |
846b0dd2 | 1522 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1523 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
1524 | && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { | |
1525 | /* not for us */ | |
1526 | return (rc); | |
1527 | } | |
1528 | #endif | |
1529 | /* get and clear controller status interrupts */ | |
1530 | /* look at Mal and EMAC interrupts */ | |
1531 | if ((my_uic0msr & (UIC_MRE | UIC_MTE)) | |
1532 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
1533 | /* we have a MAL interrupt */ | |
1534 | mal_isr = mfdcr (malesr); | |
1535 | /* look for mal error */ | |
1536 | if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { | |
887e2ec9 | 1537 | mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); |
ba56f625 WD |
1538 | serviced = 1; |
1539 | rc = 0; | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | /* port by port dispatch of emac interrupts */ | |
1544 | if (hw_p->devnum == 0) { | |
887e2ec9 | 1545 | if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ |
2d83476a | 1546 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
ba56f625 WD |
1547 | if ((hw_p->emac_ier & emac_isr) != 0) { |
1548 | emac_err (dev, emac_isr); | |
1549 | serviced = 1; | |
1550 | rc = 0; | |
1551 | } | |
1552 | } | |
1553 | if ((hw_p->emac_ier & emac_isr) | |
1554 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1555 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
8ac41e3e | 1556 | mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
887e2ec9 | 1557 | mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ |
ba56f625 WD |
1558 | return (rc); /* we had errors so get out */ |
1559 | } | |
1560 | } | |
1561 | ||
6e7fb6ea | 1562 | #if !defined(CONFIG_440SP) |
ba56f625 | 1563 | if (hw_p->devnum == 1) { |
887e2ec9 | 1564 | if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ |
2d83476a | 1565 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
ba56f625 WD |
1566 | if ((hw_p->emac_ier & emac_isr) != 0) { |
1567 | emac_err (dev, emac_isr); | |
1568 | serviced = 1; | |
1569 | rc = 0; | |
1570 | } | |
1571 | } | |
1572 | if ((hw_p->emac_ier & emac_isr) | |
1573 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1574 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
8ac41e3e | 1575 | mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
887e2ec9 | 1576 | mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ |
ba56f625 WD |
1577 | return (rc); /* we had errors so get out */ |
1578 | } | |
1579 | } | |
846b0dd2 | 1580 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1581 | if (hw_p->devnum == 2) { |
1582 | if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ | |
2d83476a | 1583 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
ba56f625 WD |
1584 | if ((hw_p->emac_ier & emac_isr) != 0) { |
1585 | emac_err (dev, emac_isr); | |
1586 | serviced = 1; | |
1587 | rc = 0; | |
1588 | } | |
1589 | } | |
1590 | if ((hw_p->emac_ier & emac_isr) | |
1591 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1592 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
8ac41e3e | 1593 | mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
ba56f625 WD |
1594 | mtdcr (uic2sr, UIC_ETH2); |
1595 | return (rc); /* we had errors so get out */ | |
1596 | } | |
1597 | } | |
1598 | ||
1599 | if (hw_p->devnum == 3) { | |
1600 | if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ | |
2d83476a | 1601 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
ba56f625 WD |
1602 | if ((hw_p->emac_ier & emac_isr) != 0) { |
1603 | emac_err (dev, emac_isr); | |
1604 | serviced = 1; | |
1605 | rc = 0; | |
1606 | } | |
1607 | } | |
1608 | if ((hw_p->emac_ier & emac_isr) | |
1609 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1610 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
8ac41e3e | 1611 | mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
ba56f625 WD |
1612 | mtdcr (uic2sr, UIC_ETH3); |
1613 | return (rc); /* we had errors so get out */ | |
1614 | } | |
1615 | } | |
846b0dd2 | 1616 | #endif /* CONFIG_440GX */ |
6e7fb6ea SR |
1617 | #endif /* !CONFIG_440SP */ |
1618 | ||
ba56f625 WD |
1619 | /* handle MAX TX EOB interrupt from a tx */ |
1620 | if (my_uic0msr & UIC_MTE) { | |
1621 | mal_rx_eob = mfdcr (maltxeobisr); | |
1622 | mtdcr (maltxeobisr, mal_rx_eob); | |
6e7fb6ea | 1623 | mtdcr (UIC0SR, UIC_MTE); |
ba56f625 WD |
1624 | } |
1625 | /* handle MAL RX EOB interupt from a receive */ | |
fc1cfcdb | 1626 | /* check for EOB on valid channels */ |
ba56f625 WD |
1627 | if (my_uic0msr & UIC_MRE) { |
1628 | mal_rx_eob = mfdcr (malrxeobisr); | |
8ac41e3e SR |
1629 | if ((mal_rx_eob & |
1630 | (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) | |
1631 | != 0) { /* call emac routine for channel x */ | |
ba56f625 WD |
1632 | /* clear EOB |
1633 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1634 | enet_rcv (dev, emac_isr); | |
1635 | /* indicate that we serviced an interrupt */ | |
1636 | serviced = 1; | |
1637 | rc = 0; | |
1638 | } | |
1639 | } | |
6e7fb6ea SR |
1640 | |
1641 | mtdcr (UIC0SR, UIC_MRE); /* Clear */ | |
8ac41e3e | 1642 | mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
ba56f625 WD |
1643 | switch (hw_p->devnum) { |
1644 | case 0: | |
887e2ec9 | 1645 | mtdcr (UICSR_ETHX, UIC_ETH0); |
ba56f625 WD |
1646 | break; |
1647 | case 1: | |
887e2ec9 | 1648 | mtdcr (UICSR_ETHX, UIC_ETH1); |
ba56f625 | 1649 | break; |
846b0dd2 | 1650 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1651 | case 2: |
1652 | mtdcr (uic2sr, UIC_ETH2); | |
1653 | break; | |
1654 | case 3: | |
1655 | mtdcr (uic2sr, UIC_ETH3); | |
1656 | break; | |
846b0dd2 | 1657 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
1658 | default: |
1659 | break; | |
1660 | } | |
1661 | } while (serviced); | |
1662 | ||
1663 | return (rc); | |
1664 | } | |
1665 | ||
d6c61aab SR |
1666 | #else /* CONFIG_440 */ |
1667 | ||
1668 | int enetInt (struct eth_device *dev) | |
1669 | { | |
1670 | int serviced; | |
1671 | int rc = -1; /* default to not us */ | |
1672 | unsigned long mal_isr; | |
1673 | unsigned long emac_isr = 0; | |
1674 | unsigned long mal_rx_eob; | |
1675 | unsigned long my_uicmsr; | |
1676 | ||
1677 | EMAC_4XX_HW_PST hw_p; | |
1678 | ||
1679 | /* | |
1680 | * Because the mal is generic, we need to get the current | |
1681 | * eth device | |
1682 | */ | |
1683 | #if defined(CONFIG_NET_MULTI) | |
1684 | dev = eth_get_dev(); | |
1685 | #else | |
1686 | dev = emac0_dev; | |
1687 | #endif | |
1688 | ||
1689 | hw_p = dev->priv; | |
1690 | ||
1691 | /* enter loop that stays in interrupt code until nothing to service */ | |
1692 | do { | |
1693 | serviced = 0; | |
1694 | ||
1695 | my_uicmsr = mfdcr (uicmsr); | |
1696 | ||
1697 | if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ | |
1698 | return (rc); | |
1699 | } | |
1700 | /* get and clear controller status interrupts */ | |
1701 | /* look at Mal and EMAC interrupts */ | |
1702 | if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ | |
1703 | mal_isr = mfdcr (malesr); | |
1704 | /* look for mal error */ | |
1705 | if ((my_uicmsr & MAL_UIC_ERR) != 0) { | |
1706 | mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); | |
1707 | serviced = 1; | |
1708 | rc = 0; | |
1709 | } | |
1710 | } | |
1711 | ||
1712 | /* port by port dispatch of emac interrupts */ | |
1713 | ||
1714 | if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ | |
2d83476a | 1715 | emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
d6c61aab SR |
1716 | if ((hw_p->emac_ier & emac_isr) != 0) { |
1717 | emac_err (dev, emac_isr); | |
1718 | serviced = 1; | |
1719 | rc = 0; | |
1720 | } | |
1721 | } | |
1722 | if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { | |
1723 | mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ | |
1724 | return (rc); /* we had errors so get out */ | |
1725 | } | |
1726 | ||
1727 | /* handle MAX TX EOB interrupt from a tx */ | |
1728 | if (my_uicmsr & UIC_MAL_TXEOB) { | |
1729 | mal_rx_eob = mfdcr (maltxeobisr); | |
1730 | mtdcr (maltxeobisr, mal_rx_eob); | |
1731 | mtdcr (uicsr, UIC_MAL_TXEOB); | |
1732 | } | |
1733 | /* handle MAL RX EOB interupt from a receive */ | |
1734 | /* check for EOB on valid channels */ | |
1735 | if (my_uicmsr & UIC_MAL_RXEOB) | |
1736 | { | |
1737 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1738 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
d6c61aab SR |
1739 | /* clear EOB |
1740 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1741 | enet_rcv (dev, emac_isr); | |
1742 | /* indicate that we serviced an interrupt */ | |
1743 | serviced = 1; | |
1744 | rc = 0; | |
1745 | } | |
1746 | } | |
1747 | mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ | |
e01bd218 SR |
1748 | #if defined(CONFIG_405EZ) |
1749 | mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); | |
1750 | #endif /* defined(CONFIG_405EZ) */ | |
d6c61aab SR |
1751 | } |
1752 | while (serviced); | |
1753 | ||
1754 | return (rc); | |
1755 | } | |
1756 | ||
1757 | #endif /* CONFIG_440 */ | |
1758 | ||
ba56f625 WD |
1759 | /*-----------------------------------------------------------------------------+ |
1760 | * MAL Error Routine | |
1761 | *-----------------------------------------------------------------------------*/ | |
1762 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1763 | unsigned long uic, unsigned long maldef, | |
1764 | unsigned long mal_errr) | |
1765 | { | |
d6c61aab | 1766 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1767 | |
1768 | mtdcr (malesr, isr); /* clear interrupt */ | |
1769 | ||
1770 | /* clear DE interrupt */ | |
1771 | mtdcr (maltxdeir, 0xC0000000); | |
1772 | mtdcr (malrxdeir, 0x80000000); | |
1773 | ||
d6c61aab | 1774 | #ifdef INFO_4XX_ENET |
265817c7 | 1775 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1776 | #endif |
1777 | ||
1778 | eth_init (hw_p->bis); /* start again... */ | |
1779 | } | |
1780 | ||
1781 | /*-----------------------------------------------------------------------------+ | |
1782 | * EMAC Error Routine | |
1783 | *-----------------------------------------------------------------------------*/ | |
1784 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1785 | { | |
d6c61aab | 1786 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1787 | |
1788 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
2d83476a | 1789 | out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); |
ba56f625 WD |
1790 | } |
1791 | ||
1792 | /*-----------------------------------------------------------------------------+ | |
1793 | * enet_rcv() handles the ethernet receive data | |
1794 | *-----------------------------------------------------------------------------*/ | |
1795 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1796 | { | |
1797 | struct enet_frame *ef_ptr; | |
1798 | unsigned long data_len; | |
1799 | unsigned long rx_eob_isr; | |
d6c61aab | 1800 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1801 | |
1802 | int handled = 0; | |
1803 | int i; | |
1804 | int loop_count = 0; | |
1805 | ||
1806 | rx_eob_isr = mfdcr (malrxeobisr); | |
8ac41e3e | 1807 | if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { |
ba56f625 WD |
1808 | /* clear EOB */ |
1809 | mtdcr (malrxeobisr, rx_eob_isr); | |
1810 | ||
1811 | /* EMAC RX done */ | |
1812 | while (1) { /* do all */ | |
1813 | i = hw_p->rx_slot; | |
1814 | ||
1815 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1816 | || (loop_count >= NUM_RX_BUFF)) | |
1817 | break; | |
a2e1c709 | 1818 | |
ba56f625 | 1819 | loop_count++; |
ba56f625 | 1820 | handled++; |
8ac41e3e | 1821 | data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ |
ba56f625 WD |
1822 | if (data_len) { |
1823 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1824 | data_len = 0; | |
1825 | else { | |
1826 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1827 | data_len = 0; | |
1828 | hw_p->stats.rx_err_log[hw_p-> | |
1829 | rx_err_index] | |
1830 | = hw_p->rx[i].ctrl; | |
1831 | hw_p->rx_err_index++; | |
1832 | if (hw_p->rx_err_index == | |
1833 | MAX_ERR_LOG) | |
1834 | hw_p->rx_err_index = | |
1835 | 0; | |
fc1cfcdb | 1836 | } /* emac_erros */ |
ba56f625 | 1837 | } /* data_len < max mtu */ |
fc1cfcdb | 1838 | } /* if data_len */ |
ba56f625 WD |
1839 | if (!data_len) { /* no data */ |
1840 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1841 | ||
1842 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1843 | } | |
1844 | ||
1845 | /* !data_len */ | |
1846 | /* AS.HARNOIS */ | |
1847 | /* Check if user has already eaten buffer */ | |
1848 | /* if not => ERROR */ | |
1849 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1850 | if (hw_p->is_receiving) | |
1851 | printf ("ERROR : Receive buffers are full!\n"); | |
1852 | break; | |
1853 | } else { | |
1854 | hw_p->stats.rx_frames++; | |
1855 | hw_p->stats.rx += data_len; | |
1856 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
1857 | data_ptr; | |
d6c61aab | 1858 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1859 | hw_p->stats.pkts_rx++; |
1860 | #endif | |
1861 | /* AS.HARNOIS | |
1862 | * use ring buffer | |
1863 | */ | |
1864 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1865 | hw_p->rx_i_index++; | |
1866 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1867 | hw_p->rx_i_index = 0; | |
1868 | ||
a2e1c709 SR |
1869 | hw_p->rx_slot++; |
1870 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1871 | hw_p->rx_slot = 0; | |
1872 | ||
ba56f625 WD |
1873 | /* AS.HARNOIS |
1874 | * free receive buffer only when | |
1875 | * buffer has been handled (eth_rx) | |
1876 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1877 | */ | |
1878 | } /* if data_len */ | |
1879 | } /* while */ | |
1880 | } /* if EMACK_RXCHL */ | |
1881 | } | |
1882 | ||
1883 | ||
d6c61aab | 1884 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1885 | { |
1886 | int length; | |
1887 | int user_index; | |
1888 | unsigned long msr; | |
d6c61aab | 1889 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1890 | |
265817c7 | 1891 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1892 | |
1893 | for (;;) { | |
1894 | /* AS.HARNOIS | |
1895 | * use ring buffer and | |
1896 | * get index from rx buffer desciptor queue | |
1897 | */ | |
1898 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1899 | if (user_index == -1) { | |
1900 | length = -1; | |
1901 | break; /* nothing received - leave for() loop */ | |
1902 | } | |
1903 | ||
1904 | msr = mfmsr (); | |
1905 | mtmsr (msr & ~(MSR_EE)); | |
1906 | ||
8ac41e3e | 1907 | length = hw_p->rx[user_index].data_len & 0x0fff; |
ba56f625 WD |
1908 | |
1909 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1910 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1911 | /* NetReceive(NetRxPackets[i], length); */ | |
ff768cb1 SR |
1912 | invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, |
1913 | (u32)hw_p->rx[user_index].data_ptr + | |
ba79fde5 | 1914 | length - 4); |
ba56f625 WD |
1915 | NetReceive (NetRxPackets[user_index], length - 4); |
1916 | /* Free Recv Buffer */ | |
1917 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1918 | /* Free rx buffer descriptor queue */ | |
1919 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1920 | hw_p->rx_u_index++; | |
1921 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1922 | hw_p->rx_u_index = 0; | |
1923 | ||
d6c61aab | 1924 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1925 | hw_p->stats.pkts_handled++; |
1926 | #endif | |
1927 | ||
1928 | mtmsr (msr); /* Enable IRQ's */ | |
1929 | } | |
1930 | ||
265817c7 | 1931 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1932 | |
1933 | return length; | |
1934 | } | |
1935 | ||
d6c61aab | 1936 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1937 | { |
1938 | static int virgin = 0; | |
ba56f625 WD |
1939 | struct eth_device *dev; |
1940 | int eth_num = 0; | |
d6c61aab | 1941 | EMAC_4XX_HW_PST hw = NULL; |
5fb692ca SR |
1942 | u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; |
1943 | u32 hw_addr[4]; | |
ba56f625 | 1944 | |
846b0dd2 | 1945 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1946 | unsigned long pfc1; |
1947 | ||
ba56f625 WD |
1948 | mfsdr (sdr_pfc1, pfc1); |
1949 | pfc1 &= ~(0x01e00000); | |
1950 | pfc1 |= 0x01200000; | |
1951 | mtsdr (sdr_pfc1, pfc1); | |
c157d8e2 | 1952 | #endif |
6c5879f3 | 1953 | |
5fb692ca SR |
1954 | /* first clear all mac-addresses */ |
1955 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) | |
1956 | memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); | |
a06752e3 | 1957 | |
1e25f957 | 1958 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
ba56f625 | 1959 | switch (eth_num) { |
e2ffd59b | 1960 | default: /* fall through */ |
ba56f625 | 1961 | case 0: |
5fb692ca SR |
1962 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1963 | bis->bi_enetaddr, 6); | |
1964 | hw_addr[eth_num] = 0x0; | |
ba56f625 | 1965 | break; |
e2ffd59b | 1966 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1967 | case 1: |
5fb692ca SR |
1968 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1969 | bis->bi_enet1addr, 6); | |
1970 | hw_addr[eth_num] = 0x100; | |
ba56f625 | 1971 | break; |
e2ffd59b WD |
1972 | #endif |
1973 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1974 | case 2: |
5fb692ca SR |
1975 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1976 | bis->bi_enet2addr, 6); | |
4c9e8557 SR |
1977 | #if defined(CONFIG_460GT) |
1978 | hw_addr[eth_num] = 0x300; | |
1979 | #else | |
5fb692ca | 1980 | hw_addr[eth_num] = 0x400; |
4c9e8557 | 1981 | #endif |
ba56f625 | 1982 | break; |
e2ffd59b WD |
1983 | #endif |
1984 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1985 | case 3: |
5fb692ca SR |
1986 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1987 | bis->bi_enet3addr, 6); | |
4c9e8557 SR |
1988 | #if defined(CONFIG_460GT) |
1989 | hw_addr[eth_num] = 0x400; | |
1990 | #else | |
5fb692ca | 1991 | hw_addr[eth_num] = 0x600; |
4c9e8557 | 1992 | #endif |
ba56f625 | 1993 | break; |
e2ffd59b | 1994 | #endif |
ba56f625 | 1995 | } |
5fb692ca SR |
1996 | } |
1997 | ||
1998 | /* set phy num and mode */ | |
1999 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
2000 | bis->bi_phymode[0] = 0; | |
2001 | ||
2002 | #if defined(CONFIG_PHY1_ADDR) | |
2003 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; | |
2004 | bis->bi_phymode[1] = 0; | |
2005 | #endif | |
2006 | #if defined(CONFIG_440GX) | |
2007 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; | |
2008 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
2009 | bis->bi_phymode[2] = 2; | |
2010 | bis->bi_phymode[3] = 2; | |
dbbd1257 | 2011 | #endif |
5fb692ca | 2012 | |
dbbd1257 SR |
2013 | #if defined(CONFIG_440GX) || \ |
2014 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
2015 | defined(CONFIG_405EX) | |
5fb692ca SR |
2016 | ppc_4xx_eth_setup_bridge(0, bis); |
2017 | #endif | |
2018 | ||
2019 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { | |
2020 | /* | |
2021 | * See if we can actually bring up the interface, | |
2022 | * otherwise, skip it | |
2023 | */ | |
2024 | if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { | |
2025 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
2026 | continue; | |
2027 | } | |
ba56f625 WD |
2028 | |
2029 | /* Allocate device structure */ | |
2030 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
2031 | if (dev == NULL) { | |
d6c61aab | 2032 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2033 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
2034 | return (-1); |
2035 | } | |
b2532eff | 2036 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
2037 | |
2038 | /* Allocate our private use data */ | |
d6c61aab | 2039 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 2040 | if (hw == NULL) { |
d6c61aab | 2041 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 2042 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
2043 | eth_num); |
2044 | free (dev); | |
2045 | return (-1); | |
2046 | } | |
b2532eff | 2047 | memset(hw, 0, sizeof(*hw)); |
ba56f625 | 2048 | |
5fb692ca SR |
2049 | hw->hw_addr = hw_addr[eth_num]; |
2050 | memcpy (dev->enetaddr, ethaddr[eth_num], 6); | |
ba56f625 | 2051 | hw->devnum = eth_num; |
c157d8e2 | 2052 | hw->print_speed = 1; |
ba56f625 | 2053 | |
5fb692ca | 2054 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); |
ba56f625 | 2055 | dev->priv = (void *) hw; |
d6c61aab SR |
2056 | dev->init = ppc_4xx_eth_init; |
2057 | dev->halt = ppc_4xx_eth_halt; | |
2058 | dev->send = ppc_4xx_eth_send; | |
2059 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 WD |
2060 | |
2061 | if (0 == virgin) { | |
2062 | /* set the MAL IER ??? names may change with new spec ??? */ | |
dbbd1257 SR |
2063 | #if defined(CONFIG_440SPE) || \ |
2064 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
8ac41e3e | 2065 | defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ |
dbbd1257 | 2066 | defined(CONFIG_405EX) |
6c5879f3 MB |
2067 | mal_ier = |
2068 | MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | | |
2069 | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; | |
2070 | #else | |
ba56f625 WD |
2071 | mal_ier = |
2072 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
2073 | MAL_IER_OPBE | MAL_IER_PLBE; | |
6c5879f3 | 2074 | #endif |
ba56f625 WD |
2075 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ |
2076 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
2077 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
2078 | mtdcr (malier, mal_ier); | |
2079 | ||
2080 | /* install MAL interrupt handler */ | |
2081 | irq_install_handler (VECNUM_MS, | |
2082 | (interrupt_handler_t *) enetInt, | |
2083 | dev); | |
2084 | irq_install_handler (VECNUM_MTE, | |
2085 | (interrupt_handler_t *) enetInt, | |
2086 | dev); | |
2087 | irq_install_handler (VECNUM_MRE, | |
2088 | (interrupt_handler_t *) enetInt, | |
2089 | dev); | |
2090 | irq_install_handler (VECNUM_TXDE, | |
2091 | (interrupt_handler_t *) enetInt, | |
2092 | dev); | |
2093 | irq_install_handler (VECNUM_RXDE, | |
2094 | (interrupt_handler_t *) enetInt, | |
2095 | dev); | |
2096 | virgin = 1; | |
2097 | } | |
2098 | ||
d6c61aab | 2099 | #if defined(CONFIG_NET_MULTI) |
ba56f625 | 2100 | eth_register (dev); |
d6c61aab SR |
2101 | #else |
2102 | emac0_dev = dev; | |
2103 | #endif | |
6c5879f3 MB |
2104 | |
2105 | #if defined(CONFIG_NET_MULTI) | |
3a1ed1e1 | 2106 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c | 2107 | miiphy_register (dev->name, |
6e7fb6ea | 2108 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c | 2109 | #endif |
6c5879f3 | 2110 | #endif |
ba56f625 | 2111 | } /* end for each supported device */ |
802b769b SR |
2112 | |
2113 | return 0; | |
ba56f625 | 2114 | } |
d6c61aab | 2115 | |
d6c61aab SR |
2116 | #if !defined(CONFIG_NET_MULTI) |
2117 | void eth_halt (void) { | |
2118 | if (emac0_dev) { | |
2119 | ppc_4xx_eth_halt(emac0_dev); | |
2120 | free(emac0_dev); | |
2121 | emac0_dev = NULL; | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | int eth_init (bd_t *bis) | |
2126 | { | |
2127 | ppc_4xx_eth_initialize(bis); | |
4f92ac36 SR |
2128 | if (emac0_dev) { |
2129 | return ppc_4xx_eth_init(emac0_dev, bis); | |
2130 | } else { | |
2131 | printf("ERROR: ethaddr not set!\n"); | |
2132 | return -1; | |
2133 | } | |
d6c61aab SR |
2134 | } |
2135 | ||
2136 | int eth_send(volatile void *packet, int length) | |
2137 | { | |
d6c61aab SR |
2138 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); |
2139 | } | |
2140 | ||
2141 | int eth_rx(void) | |
2142 | { | |
2143 | return (ppc_4xx_eth_rx(emac0_dev)); | |
2144 | } | |
63ff004c MB |
2145 | |
2146 | int emac4xx_miiphy_initialize (bd_t * bis) | |
2147 | { | |
3a1ed1e1 | 2148 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c | 2149 | miiphy_register ("ppc_4xx_eth0", |
6e7fb6ea | 2150 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c MB |
2151 | #endif |
2152 | ||
2153 | return 0; | |
2154 | } | |
d6c61aab SR |
2155 | #endif /* !defined(CONFIG_NET_MULTI) */ |
2156 | ||
3a1ed1e1 | 2157 | #endif |