]>
Commit | Line | Data |
---|---|---|
ba56f625 WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
265817c7 WD |
3 | * This source code has been made available to you by IBM on an AS-IS |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 9 | * |
265817c7 WD |
10 | * Any user of this software should understand that IBM cannot provide |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
ba56f625 | 13 | * |
265817c7 WD |
14 | * Any person who transfers this source code or any derivative work |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 17 | * |
265817c7 WD |
18 | * COPYRIGHT I B M CORPORATION 1995 |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
20 | *-----------------------------------------------------------------------------*/ |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
265817c7 | 23 | * File Name: enetemac.c |
ba56f625 | 24 | * |
265817c7 | 25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 26 | * |
265817c7 | 27 | * Author: Mark Wisner |
ba56f625 WD |
28 | * |
29 | * Change Activity- | |
30 | * | |
265817c7 WD |
31 | * Date Description of Change BY |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 70 | *-----------------------------------------------------------------------------* |
265817c7 WD |
71 | * 17-Nov-03 travis.sawyer@sandburst.com |
72 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
73 | * in the 440GX. This port should work with the 440GP | |
74 | * (2 EMACs) also | |
75 | * 15-Aug-05 sr@denx.de | |
76 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
77 | now handling all 4xx cpu's. | |
ba56f625 WD |
78 | *-----------------------------------------------------------------------------*/ |
79 | ||
80 | #include <config.h> | |
ba56f625 WD |
81 | #include <common.h> |
82 | #include <net.h> | |
83 | #include <asm/processor.h> | |
ba56f625 | 84 | #include <commproc.h> |
d6c61aab SR |
85 | #include <ppc4xx.h> |
86 | #include <ppc4xx_enet.h> | |
ba56f625 WD |
87 | #include <405_mal.h> |
88 | #include <miiphy.h> | |
89 | #include <malloc.h> | |
90 | #include "vecnum.h" | |
91 | ||
d6c61aab | 92 | /* |
0c8721a4 | 93 | * Only compile for platform with AMCC EMAC ethernet controller and |
d6c61aab SR |
94 | * network support enabled. |
95 | * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! | |
96 | */ | |
97 | #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) | |
98 | ||
99 | #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) | |
100 | #error "CONFIG_MII has to be defined!" | |
101 | #endif | |
ba56f625 | 102 | |
1e25f957 SR |
103 | #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) |
104 | #error "CONFIG_NET_MULTI has to be defined for NetConsole" | |
105 | #endif | |
106 | ||
265817c7 | 107 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
ba56f625 WD |
108 | #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ |
109 | ||
ba56f625 WD |
110 | /* Ethernet Transmit and Receive Buffers */ |
111 | /* AS.HARNOIS | |
112 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
113 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
114 | */ | |
265817c7 | 115 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
116 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
117 | ||
ba56f625 WD |
118 | /*-----------------------------------------------------------------------------+ |
119 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
120 | * Interrupt Controller). | |
121 | *-----------------------------------------------------------------------------*/ | |
122 | #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
123 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
124 | #define EMAC_UIC_DEF UIC_ENET | |
d6c61aab SR |
125 | #define EMAC_UIC_DEF1 UIC_ENET1 |
126 | #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) | |
ba56f625 | 127 | |
d6c61aab | 128 | #undef INFO_4XX_ENET |
ba56f625 | 129 | |
265817c7 WD |
130 | #define BI_PHYMODE_NONE 0 |
131 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a | 132 | #define BI_PHYMODE_RGMII 2 |
887e2ec9 SR |
133 | #define BI_PHYMODE_GMII 3 |
134 | #define BI_PHYMODE_RTBI 4 | |
135 | #define BI_PHYMODE_TBI 5 | |
854bc8da | 136 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
887e2ec9 SR |
137 | #define BI_PHYMODE_SMII 6 |
138 | #define BI_PHYMODE_MII 7 | |
139 | #endif | |
3c74e32a | 140 | |
887e2ec9 SR |
141 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
142 | #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) | |
143 | #endif | |
d6c61aab | 144 | |
ba56f625 WD |
145 | /*-----------------------------------------------------------------------------+ |
146 | * Global variables. TX and RX descriptors and buffers. | |
147 | *-----------------------------------------------------------------------------*/ | |
148 | /* IER globals */ | |
149 | static uint32_t mal_ier; | |
150 | ||
d6c61aab | 151 | #if !defined(CONFIG_NET_MULTI) |
4f92ac36 | 152 | struct eth_device *emac0_dev = NULL; |
d6c61aab SR |
153 | #endif |
154 | ||
1e25f957 SR |
155 | /* |
156 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
157 | * supported by the cpu) | |
158 | */ | |
159 | #if defined(CONFIG_HAS_ETH3) | |
160 | #define LAST_EMAC_NUM 4 | |
161 | #elif defined(CONFIG_HAS_ETH2) | |
162 | #define LAST_EMAC_NUM 3 | |
163 | #elif defined(CONFIG_HAS_ETH1) | |
164 | #define LAST_EMAC_NUM 2 | |
165 | #else | |
166 | #define LAST_EMAC_NUM 1 | |
167 | #endif | |
d6c61aab | 168 | |
5fb692ca SR |
169 | /* normal boards start with EMAC0 */ |
170 | #if !defined(CONFIG_EMAC_NR_START) | |
171 | #define CONFIG_EMAC_NR_START 0 | |
172 | #endif | |
173 | ||
ba56f625 WD |
174 | /*-----------------------------------------------------------------------------+ |
175 | * Prototypes and externals. | |
176 | *-----------------------------------------------------------------------------*/ | |
177 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
178 | ||
179 | int enetInt (struct eth_device *dev); | |
180 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
181 | unsigned long uic, unsigned long maldef, | |
182 | unsigned long mal_errr); | |
183 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
184 | ||
63ff004c MB |
185 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
186 | extern int emac4xx_miiphy_read (char *devname, unsigned char addr, | |
187 | unsigned char reg, unsigned short *value); | |
188 | extern int emac4xx_miiphy_write (char *devname, unsigned char addr, | |
189 | unsigned char reg, unsigned short value); | |
d6c61aab | 190 | |
ba56f625 | 191 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 192 | | ppc_4xx_eth_halt |
ba56f625 | 193 | | Disable MAL channel, and EMACn |
ba56f625 | 194 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 195 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 196 | { |
d6c61aab | 197 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 198 | uint32_t failsafe = 10000; |
887e2ec9 | 199 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
200 | unsigned long mfr; |
201 | #endif | |
ba56f625 WD |
202 | |
203 | out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ | |
204 | ||
205 | /* 1st reset MAL channel */ | |
206 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab SR |
207 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
208 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
209 | #else | |
ba56f625 | 210 | mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 211 | #endif |
ba56f625 WD |
212 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
213 | ||
214 | /* wait for reset */ | |
d6c61aab | 215 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 WD |
216 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
217 | failsafe--; | |
218 | if (failsafe == 0) | |
219 | break; | |
ba56f625 WD |
220 | } |
221 | ||
222 | /* EMAC RESET */ | |
887e2ec9 | 223 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
224 | /* provide clocks for EMAC internal loopback */ |
225 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 226 | mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); |
6c5879f3 MB |
227 | mtsdr(sdr_mfr, mfr); |
228 | #endif | |
229 | ||
ba56f625 WD |
230 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
231 | ||
887e2ec9 | 232 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
233 | /* remove clocks for EMAC internal loopback */ |
234 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 235 | mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); |
6c5879f3 MB |
236 | mtsdr(sdr_mfr, mfr); |
237 | #endif | |
238 | ||
239 | ||
a93316c5 | 240 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 241 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 242 | #endif |
c157d8e2 | 243 | |
ba56f625 WD |
244 | return; |
245 | } | |
246 | ||
846b0dd2 | 247 | #if defined (CONFIG_440GX) |
d6c61aab | 248 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
249 | { |
250 | unsigned long pfc1; | |
251 | unsigned long zmiifer; | |
252 | unsigned long rmiifer; | |
253 | ||
254 | mfsdr(sdr_pfc1, pfc1); | |
255 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); | |
256 | ||
257 | zmiifer = 0; | |
258 | rmiifer = 0; | |
259 | ||
260 | switch (pfc1) { | |
261 | case 1: | |
262 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
263 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
264 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
265 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
266 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
267 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
268 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
269 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
270 | break; | |
271 | case 2: | |
f6e495f5 SR |
272 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); |
273 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
274 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); | |
275 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); | |
855a496f WD |
276 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
277 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
278 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
279 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
280 | break; | |
281 | case 3: | |
282 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
283 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
284 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
285 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
286 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
287 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
288 | break; | |
289 | case 4: | |
290 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
291 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
292 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
293 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
294 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
295 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
296 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
297 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
298 | break; | |
299 | case 5: | |
300 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
301 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
302 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
303 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
304 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
305 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
306 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
307 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
308 | break; | |
309 | case 6: | |
310 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
311 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
312 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
313 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
314 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
315 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
316 | break; |
317 | case 0: | |
318 | default: | |
319 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
320 | rmiifer = 0x0; | |
321 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
322 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
323 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
324 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
325 | break; | |
326 | } | |
327 | ||
328 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
329 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
330 | ||
331 | out32 (ZMII_FER, zmiifer); | |
332 | out32 (RGMII_FER, rmiifer); | |
333 | ||
334 | return ((int)pfc1); | |
855a496f | 335 | } |
6c5879f3 | 336 | #endif /* CONFIG_440_GX */ |
855a496f | 337 | |
887e2ec9 SR |
338 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
339 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
340 | { | |
341 | unsigned long zmiifer=0x0; | |
342 | ||
343 | /* | |
344 | * Right now only 2*RGMII is supported. Please extend when needed. | |
345 | * sr - 2006-08-29 | |
346 | */ | |
347 | switch (1) { | |
348 | case 0: | |
349 | /* 1 x GMII port */ | |
350 | out32 (ZMII_FER, 0x00); | |
351 | out32 (RGMII_FER, 0x00000037); | |
352 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
353 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
354 | break; | |
355 | case 1: | |
356 | /* 2 x RGMII ports */ | |
357 | out32 (ZMII_FER, 0x00); | |
358 | out32 (RGMII_FER, 0x00000055); | |
359 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
360 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
361 | break; | |
362 | case 2: | |
363 | /* 2 x SMII ports */ | |
364 | ||
365 | break; | |
366 | default: | |
367 | break; | |
368 | } | |
369 | ||
370 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
371 | zmiifer = in32 (ZMII_FER); | |
372 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
373 | out32 (ZMII_FER, zmiifer); | |
374 | ||
375 | return ((int)0x0); | |
376 | } | |
377 | #endif /* CONFIG_440EPX */ | |
378 | ||
d6c61aab | 379 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 380 | { |
b79316f2 | 381 | int i, j; |
d6c61aab | 382 | unsigned long reg = 0; |
ba56f625 WD |
383 | unsigned long msr; |
384 | unsigned long speed; | |
385 | unsigned long duplex; | |
386 | unsigned long failsafe; | |
387 | unsigned mode_reg; | |
388 | unsigned short devnum; | |
389 | unsigned short reg_short; | |
887e2ec9 SR |
390 | #if defined(CONFIG_440GX) || \ |
391 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
392 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
d6c61aab | 393 | sys_info_t sysinfo; |
887e2ec9 SR |
394 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
395 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
6e7fb6ea SR |
396 | int ethgroup = -1; |
397 | #endif | |
c157d8e2 | 398 | #endif |
887e2ec9 | 399 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) |
6c5879f3 MB |
400 | unsigned long mfr; |
401 | #endif | |
402 | ||
ba56f625 | 403 | |
d6c61aab | 404 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
405 | |
406 | /* before doing anything, figure out if we have a MAC address */ | |
407 | /* if not, bail */ | |
4f92ac36 SR |
408 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
409 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 410 | return -1; |
4f92ac36 | 411 | } |
ba56f625 | 412 | |
887e2ec9 SR |
413 | #if defined(CONFIG_440GX) || \ |
414 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
415 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
ba56f625 WD |
416 | /* Need to get the OPB frequency so we can access the PHY */ |
417 | get_sys_info (&sysinfo); | |
d6c61aab | 418 | #endif |
ba56f625 | 419 | |
ba56f625 WD |
420 | msr = mfmsr (); |
421 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
422 | ||
423 | devnum = hw_p->devnum; | |
424 | ||
d6c61aab | 425 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
426 | /* AS.HARNOIS |
427 | * We should have : | |
265817c7 | 428 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
429 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
430 | * is possible that new packets (without relationship with | |
431 | * current transfer) have got the time to arrived before | |
432 | * netloop calls eth_halt | |
433 | */ | |
434 | printf ("About preceeding transfer (eth%d):\n" | |
435 | "- Sent packet number %d\n" | |
436 | "- Received packet number %d\n" | |
437 | "- Handled packet number %d\n", | |
438 | hw_p->devnum, | |
439 | hw_p->stats.pkts_tx, | |
440 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
441 | ||
442 | hw_p->stats.pkts_tx = 0; | |
443 | hw_p->stats.pkts_rx = 0; | |
444 | hw_p->stats.pkts_handled = 0; | |
6c5879f3 | 445 | hw_p->print_speed = 1; /* print speed message again next time */ |
ba56f625 WD |
446 | #endif |
447 | ||
265817c7 WD |
448 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
449 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
450 | |
451 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
452 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
453 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
454 | ||
455 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
456 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
457 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
458 | ||
6c5879f3 | 459 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
460 | /* set RMII mode */ |
461 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
462 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
463 | /* NOTE: only one emac at a time */ | |
464 | reg = 0; | |
465 | out32 (ZMII_FER, 0); | |
466 | udelay (100); | |
ba56f625 | 467 | |
846b0dd2 | 468 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
265817c7 | 469 | out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
887e2ec9 | 470 | #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
d6c61aab | 471 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
4a3cd9e6 SR |
472 | #elif defined(CONFIG_440GP) |
473 | /* set RMII mode */ | |
474 | out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); | |
0e6d798c WD |
475 | #else |
476 | if ((devnum == 0) || (devnum == 1)) { | |
477 | out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); | |
1c2ce226 | 478 | } else { /* ((devnum == 2) || (devnum == 3)) */ |
0e6d798c | 479 | out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); |
ba56f625 WD |
480 | out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | |
481 | (RGMII_FER_RGMII << RGMII_FER_V (3)))); | |
0e6d798c WD |
482 | } |
483 | #endif | |
c57c7980 | 484 | |
0e6d798c | 485 | out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
6e7fb6ea | 486 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
d6c61aab | 487 | |
0e6d798c WD |
488 | __asm__ volatile ("eieio"); |
489 | ||
490 | /* reset emac so we have access to the phy */ | |
887e2ec9 | 491 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
492 | /* provide clocks for EMAC internal loopback */ |
493 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 494 | mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); |
6c5879f3 MB |
495 | mtsdr(sdr_mfr, mfr); |
496 | #endif | |
0e6d798c WD |
497 | |
498 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); | |
ba56f625 WD |
499 | __asm__ volatile ("eieio"); |
500 | ||
501 | failsafe = 1000; | |
502 | while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { | |
503 | udelay (1000); | |
504 | failsafe--; | |
505 | } | |
887e2ec9 SR |
506 | if (failsafe <= 0) |
507 | printf("\nProblem resetting EMAC!\n"); | |
ba56f625 | 508 | |
887e2ec9 | 509 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
510 | /* remove clocks for EMAC internal loopback */ |
511 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 512 | mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); |
6c5879f3 MB |
513 | mtsdr(sdr_mfr, mfr); |
514 | #endif | |
515 | ||
887e2ec9 SR |
516 | #if defined(CONFIG_440GX) || \ |
517 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
518 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
ba56f625 WD |
519 | /* Whack the M1 register */ |
520 | mode_reg = 0x0; | |
521 | mode_reg &= ~0x00000038; | |
522 | if (sysinfo.freqOPB <= 50000000); | |
523 | else if (sysinfo.freqOPB <= 66666667) | |
524 | mode_reg |= EMAC_M1_OBCI_66; | |
525 | else if (sysinfo.freqOPB <= 83333333) | |
526 | mode_reg |= EMAC_M1_OBCI_83; | |
527 | else if (sysinfo.freqOPB <= 100000000) | |
528 | mode_reg |= EMAC_M1_OBCI_100; | |
529 | else | |
530 | mode_reg |= EMAC_M1_OBCI_GT100; | |
531 | ||
532 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); | |
6e7fb6ea | 533 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
ba56f625 WD |
534 | |
535 | /* wait for PHY to complete auto negotiation */ | |
536 | reg_short = 0; | |
537 | #ifndef CONFIG_CS8952_PHY | |
538 | switch (devnum) { | |
539 | case 0: | |
540 | reg = CONFIG_PHY_ADDR; | |
541 | break; | |
d6c61aab | 542 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
543 | case 1: |
544 | reg = CONFIG_PHY1_ADDR; | |
545 | break; | |
d6c61aab | 546 | #endif |
846b0dd2 | 547 | #if defined (CONFIG_440GX) |
ba56f625 WD |
548 | case 2: |
549 | reg = CONFIG_PHY2_ADDR; | |
550 | break; | |
551 | case 3: | |
552 | reg = CONFIG_PHY3_ADDR; | |
553 | break; | |
554 | #endif | |
555 | default: | |
556 | reg = CONFIG_PHY_ADDR; | |
557 | break; | |
558 | } | |
559 | ||
3c74e32a WD |
560 | bis->bi_phynum[devnum] = reg; |
561 | ||
d6c61aab | 562 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
563 | /* |
564 | * Reset the phy, only if its the first time through | |
565 | * otherwise, just check the speeds & feeds | |
566 | */ | |
567 | if (hw_p->first_init == 0) { | |
ec0c2ec7 | 568 | #if defined(CONFIG_M88E1111_PHY) |
887e2ec9 SR |
569 | miiphy_write (dev->name, reg, 0x14, 0x0ce3); |
570 | miiphy_write (dev->name, reg, 0x18, 0x4101); | |
571 | miiphy_write (dev->name, reg, 0x09, 0x0e00); | |
572 | miiphy_write (dev->name, reg, 0x04, 0x01e1); | |
573 | #endif | |
63ff004c | 574 | miiphy_reset (dev->name, reg); |
ba56f625 | 575 | |
887e2ec9 SR |
576 | #if defined(CONFIG_440GX) || \ |
577 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
578 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
579 | ||
0e6d798c | 580 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 581 | /* |
17f50f22 SR |
582 | * Cicada 8201 PHY needs to have an extended register whacked |
583 | * for RGMII mode. | |
fc1cfcdb | 584 | */ |
887e2ec9 | 585 | if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { |
b79316f2 | 586 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 587 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 588 | #else |
63ff004c | 589 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 590 | #endif |
17f50f22 SR |
591 | /* |
592 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
593 | * Interoperability problem with Intel 82547EI phys | |
594 | * This work around (provided by Vitesse) changes | |
595 | * the default timer convergence from 8ms to 12ms | |
596 | */ | |
63ff004c MB |
597 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
598 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
599 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
600 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
601 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
602 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
603 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
604 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
605 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
606 | /* end Vitesse/Cicada errata */ |
607 | } | |
0e6d798c | 608 | #endif |
5fb692ca SR |
609 | |
610 | #if defined(CONFIG_ET1011C_PHY) | |
611 | /* | |
612 | * Agere ET1011c PHY needs to have an extended register whacked | |
613 | * for RGMII mode. | |
614 | */ | |
615 | if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { | |
616 | miiphy_read (dev->name, reg, 0x16, ®_short); | |
617 | reg_short &= ~(0x7); | |
618 | reg_short |= 0x6; /* RGMII DLL Delay*/ | |
619 | miiphy_write (dev->name, reg, 0x16, reg_short); | |
620 | ||
621 | miiphy_read (dev->name, reg, 0x17, ®_short); | |
622 | reg_short &= ~(0x40); | |
623 | miiphy_write (dev->name, reg, 0x17, reg_short); | |
624 | ||
625 | miiphy_write(dev->name, reg, 0x1c, 0x74f0); | |
626 | } | |
627 | #endif | |
628 | ||
855a496f | 629 | #endif |
a06752e3 | 630 | /* Start/Restart autonegotiation */ |
63ff004c | 631 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
632 | udelay (1000); |
633 | } | |
d6c61aab | 634 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 635 | |
63ff004c | 636 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
637 | |
638 | /* | |
0e6d798c | 639 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 WD |
640 | */ |
641 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
642 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
643 | puts ("Waiting for PHY auto negotiation to complete"); | |
644 | i = 0; | |
645 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
646 | /* | |
647 | * Timeout reached ? | |
648 | */ | |
649 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
650 | puts (" TIMEOUT !\n"); | |
651 | break; | |
652 | } | |
653 | ||
654 | if ((i++ % 1000) == 0) { | |
655 | putc ('.'); | |
656 | } | |
657 | udelay (1000); /* 1 ms */ | |
63ff004c | 658 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
659 | |
660 | } | |
661 | puts (" done\n"); | |
662 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
663 | } | |
d6c61aab SR |
664 | #endif /* #ifndef CONFIG_CS8952_PHY */ |
665 | ||
63ff004c MB |
666 | speed = miiphy_speed (dev->name, reg); |
667 | duplex = miiphy_duplex (dev->name, reg); | |
ba56f625 WD |
668 | |
669 | if (hw_p->print_speed) { | |
670 | hw_p->print_speed = 0; | |
5fb692ca SR |
671 | printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", |
672 | (int) speed, (duplex == HALF) ? "HALF" : "FULL", | |
673 | hw_p->devnum); | |
ba56f625 WD |
674 | } |
675 | ||
887e2ec9 SR |
676 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ |
677 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) | |
846b0dd2 | 678 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
679 | mfsdr(sdr_mfr, reg); |
680 | if (speed == 100) { | |
681 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
682 | } else { | |
683 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
684 | } | |
685 | mtsdr(sdr_mfr, reg); | |
686 | #endif | |
c57c7980 | 687 | |
ba56f625 WD |
688 | /* Set ZMII/RGMII speed according to the phy link speed */ |
689 | reg = in32 (ZMII_SSR); | |
855a496f | 690 | if ( (speed == 100) || (speed == 1000) ) |
ba56f625 WD |
691 | out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
692 | else | |
c57c7980 | 693 | out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
ba56f625 WD |
694 | |
695 | if ((devnum == 2) || (devnum == 3)) { | |
696 | if (speed == 1000) | |
697 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
698 | else if (speed == 100) | |
699 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
887e2ec9 | 700 | else if (speed == 10) |
ba56f625 | 701 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); |
887e2ec9 SR |
702 | else { |
703 | printf("Error in RGMII Speed\n"); | |
704 | return -1; | |
705 | } | |
ba56f625 WD |
706 | out32 (RGMII_SSR, reg); |
707 | } | |
6e7fb6ea | 708 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
ba56f625 | 709 | |
887e2ec9 SR |
710 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
711 | if (speed == 1000) | |
712 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
713 | else if (speed == 100) | |
714 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
715 | else if (speed == 10) | |
716 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); | |
717 | else { | |
718 | printf("Error in RGMII Speed\n"); | |
719 | return -1; | |
720 | } | |
721 | out32 (RGMII_SSR, reg); | |
722 | #endif | |
723 | ||
ba56f625 | 724 | /* set the Mal configuration reg */ |
887e2ec9 SR |
725 | #if defined(CONFIG_440GX) || \ |
726 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
727 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
17f50f22 SR |
728 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
729 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); | |
730 | #else | |
731 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
ba56f625 | 732 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 SR |
733 | if (get_pvr() == PVR_440GP_RB) { |
734 | mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); | |
735 | } | |
736 | #endif | |
ba56f625 WD |
737 | |
738 | /* Free "old" buffers */ | |
739 | if (hw_p->alloc_tx_buf) | |
740 | free (hw_p->alloc_tx_buf); | |
741 | if (hw_p->alloc_rx_buf) | |
742 | free (hw_p->alloc_rx_buf); | |
743 | ||
744 | /* | |
745 | * Malloc MAL buffer desciptors, make sure they are | |
746 | * aligned on cache line boundary size | |
747 | * (401/403/IOP480 = 16, 405 = 32) | |
748 | * and doesn't cross cache block boundaries. | |
749 | */ | |
750 | hw_p->alloc_tx_buf = | |
751 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + | |
752 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
b79316f2 SR |
753 | if (NULL == hw_p->alloc_tx_buf) |
754 | return -1; | |
ba56f625 WD |
755 | if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { |
756 | hw_p->tx = | |
757 | (mal_desc_t *) ((int) hw_p->alloc_tx_buf + | |
758 | CFG_CACHELINE_SIZE - | |
759 | ((int) hw_p-> | |
760 | alloc_tx_buf & CACHELINE_MASK)); | |
761 | } else { | |
762 | hw_p->tx = hw_p->alloc_tx_buf; | |
763 | } | |
764 | ||
765 | hw_p->alloc_rx_buf = | |
766 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + | |
767 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
b79316f2 SR |
768 | if (NULL == hw_p->alloc_rx_buf) { |
769 | free(hw_p->alloc_tx_buf); | |
770 | hw_p->alloc_tx_buf = NULL; | |
771 | return -1; | |
772 | } | |
773 | ||
ba56f625 WD |
774 | if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { |
775 | hw_p->rx = | |
776 | (mal_desc_t *) ((int) hw_p->alloc_rx_buf + | |
777 | CFG_CACHELINE_SIZE - | |
778 | ((int) hw_p-> | |
779 | alloc_rx_buf & CACHELINE_MASK)); | |
780 | } else { | |
781 | hw_p->rx = hw_p->alloc_rx_buf; | |
782 | } | |
783 | ||
784 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
785 | hw_p->tx[i].ctrl = 0; | |
786 | hw_p->tx[i].data_len = 0; | |
b79316f2 | 787 | if (hw_p->first_init == 0) { |
ba56f625 WD |
788 | hw_p->txbuf_ptr = |
789 | (char *) malloc (ENET_MAX_MTU_ALIGNED); | |
b79316f2 SR |
790 | if (NULL == hw_p->txbuf_ptr) { |
791 | free(hw_p->alloc_rx_buf); | |
792 | free(hw_p->alloc_tx_buf); | |
793 | hw_p->alloc_rx_buf = NULL; | |
794 | hw_p->alloc_tx_buf = NULL; | |
795 | for(j = 0; j < i; j++) { | |
796 | free(hw_p->tx[i].data_ptr); | |
797 | hw_p->tx[i].data_ptr = NULL; | |
798 | } | |
799 | } | |
800 | } | |
ba56f625 WD |
801 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
802 | if ((NUM_TX_BUFF - 1) == i) | |
803 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
804 | hw_p->tx_run[i] = -1; | |
805 | #if 0 | |
806 | printf ("TX_BUFF %d @ 0x%08lx\n", i, | |
807 | (ulong) hw_p->tx[i].data_ptr); | |
808 | #endif | |
809 | } | |
810 | ||
811 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
812 | hw_p->rx[i].ctrl = 0; | |
813 | hw_p->rx[i].data_len = 0; | |
265817c7 | 814 | /* rx[i].data_ptr = (char *) &rx_buff[i]; */ |
ba56f625 WD |
815 | hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; |
816 | if ((NUM_RX_BUFF - 1) == i) | |
817 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
818 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
819 | hw_p->rx_ready[i] = -1; | |
820 | #if 0 | |
1c2ce226 | 821 | printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); |
ba56f625 WD |
822 | #endif |
823 | } | |
824 | ||
825 | reg = 0x00000000; | |
826 | ||
827 | reg |= dev->enetaddr[0]; /* set high address */ | |
828 | reg = reg << 8; | |
829 | reg |= dev->enetaddr[1]; | |
830 | ||
831 | out32 (EMAC_IAH + hw_p->hw_addr, reg); | |
832 | ||
833 | reg = 0x00000000; | |
834 | reg |= dev->enetaddr[2]; /* set low address */ | |
835 | reg = reg << 8; | |
836 | reg |= dev->enetaddr[3]; | |
837 | reg = reg << 8; | |
838 | reg |= dev->enetaddr[4]; | |
839 | reg = reg << 8; | |
840 | reg |= dev->enetaddr[5]; | |
841 | ||
842 | out32 (EMAC_IAL + hw_p->hw_addr, reg); | |
843 | ||
844 | switch (devnum) { | |
845 | case 1: | |
846 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 847 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
c157d8e2 SR |
848 | mtdcr (maltxctp2r, hw_p->tx); |
849 | #else | |
ba56f625 | 850 | mtdcr (maltxctp1r, hw_p->tx); |
c157d8e2 | 851 | #endif |
d6c61aab | 852 | #if defined(CONFIG_440) |
c157d8e2 | 853 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 854 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 855 | #endif |
ba56f625 WD |
856 | mtdcr (malrxctp1r, hw_p->rx); |
857 | /* set RX buffer size */ | |
858 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
859 | break; | |
846b0dd2 | 860 | #if defined (CONFIG_440GX) |
ba56f625 WD |
861 | case 2: |
862 | /* setup MAL tx & rx channel pointers */ | |
863 | mtdcr (maltxbattr, 0x0); | |
ba56f625 | 864 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 865 | mtdcr (maltxctp2r, hw_p->tx); |
ba56f625 WD |
866 | mtdcr (malrxctp2r, hw_p->rx); |
867 | /* set RX buffer size */ | |
868 | mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); | |
869 | break; | |
870 | case 3: | |
871 | /* setup MAL tx & rx channel pointers */ | |
872 | mtdcr (maltxbattr, 0x0); | |
873 | mtdcr (maltxctp3r, hw_p->tx); | |
874 | mtdcr (malrxbattr, 0x0); | |
875 | mtdcr (malrxctp3r, hw_p->rx); | |
876 | /* set RX buffer size */ | |
877 | mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); | |
878 | break; | |
c57c7980 | 879 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
880 | case 0: |
881 | default: | |
882 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 883 | #if defined(CONFIG_440) |
ba56f625 | 884 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 885 | mtdcr (malrxbattr, 0x0); |
d6c61aab SR |
886 | #endif |
887 | mtdcr (maltxctp0r, hw_p->tx); | |
ba56f625 WD |
888 | mtdcr (malrxctp0r, hw_p->rx); |
889 | /* set RX buffer size */ | |
890 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
891 | break; | |
892 | } | |
893 | ||
894 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 895 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
896 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
897 | #else | |
ba56f625 | 898 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 899 | #endif |
ba56f625 WD |
900 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
901 | ||
902 | /* set transmit enable & receive enable */ | |
903 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); | |
904 | ||
905 | /* set receive fifo to 4k and tx fifo to 2k */ | |
906 | mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); | |
907 | mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; | |
908 | ||
909 | /* set speed */ | |
6e7fb6ea | 910 | if (speed == _1000BASET) { |
887e2ec9 SR |
911 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
912 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
6e7fb6ea | 913 | unsigned long pfc1; |
887e2ec9 | 914 | |
6e7fb6ea SR |
915 | mfsdr (sdr_pfc1, pfc1); |
916 | pfc1 |= SDR0_PFC1_EM_1000; | |
917 | mtsdr (sdr_pfc1, pfc1); | |
918 | #endif | |
855a496f | 919 | mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; |
6e7fb6ea | 920 | } else if (speed == _100BASET) |
ba56f625 WD |
921 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; |
922 | else | |
923 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
924 | if (duplex == FULL) | |
925 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
926 | ||
927 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); | |
928 | ||
929 | /* Enable broadcast and indvidual address */ | |
930 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
931 | out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); | |
932 | ||
933 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
934 | ||
935 | /* set transmit request threshold register */ | |
936 | out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ | |
937 | ||
265817c7 | 938 | /* set receive low/high water mark register */ |
d6c61aab | 939 | #if defined(CONFIG_440) |
6c5879f3 | 940 | /* 440s has a 64 byte burst length */ |
ba56f625 | 941 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
d6c61aab SR |
942 | #else |
943 | /* 405s have a 16 byte burst length */ | |
944 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); | |
945 | #endif /* defined(CONFIG_440) */ | |
ba56f625 WD |
946 | out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
947 | ||
948 | /* Set fifo limit entry in tx mode 0 */ | |
949 | out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); | |
950 | /* Frame gap set */ | |
951 | out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); | |
952 | ||
953 | /* Set EMAC IER */ | |
d6c61aab | 954 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
955 | if (speed == _100BASET) |
956 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
957 | ||
958 | out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ | |
959 | out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
960 | ||
961 | if (hw_p->first_init == 0) { | |
962 | /* | |
963 | * Connect interrupt service routines | |
964 | */ | |
ba56f625 WD |
965 | irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), |
966 | (interrupt_handler_t *) enetInt, dev); | |
967 | } | |
ba56f625 WD |
968 | |
969 | mtmsr (msr); /* enable interrupts again */ | |
970 | ||
971 | hw_p->bis = bis; | |
972 | hw_p->first_init = 1; | |
973 | ||
974 | return (1); | |
975 | } | |
976 | ||
977 | ||
d6c61aab | 978 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
ba56f625 WD |
979 | int len) |
980 | { | |
981 | struct enet_frame *ef_ptr; | |
982 | ulong time_start, time_now; | |
983 | unsigned long temp_txm0; | |
d6c61aab | 984 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
985 | |
986 | ef_ptr = (struct enet_frame *) ptr; | |
987 | ||
988 | /*-----------------------------------------------------------------------+ | |
989 | * Copy in our address into the frame. | |
990 | *-----------------------------------------------------------------------*/ | |
991 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
992 | ||
993 | /*-----------------------------------------------------------------------+ | |
994 | * If frame is too long or too short, modify length. | |
995 | *-----------------------------------------------------------------------*/ | |
996 | /* TBS: where does the fragment go???? */ | |
997 | if (len > ENET_MAX_MTU) | |
998 | len = ENET_MAX_MTU; | |
999 | ||
1000 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
1001 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
1002 | ||
1003 | /*-----------------------------------------------------------------------+ | |
1004 | * set TX Buffer busy, and send it | |
1005 | *-----------------------------------------------------------------------*/ | |
1006 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
1007 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
1008 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
1009 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
1010 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
1011 | ||
1012 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
1013 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
1014 | ||
1015 | __asm__ volatile ("eieio"); | |
1016 | ||
1017 | out32 (EMAC_TXM0 + hw_p->hw_addr, | |
1018 | in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
d6c61aab | 1019 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1020 | hw_p->stats.pkts_tx++; |
1021 | #endif | |
1022 | ||
1023 | /*-----------------------------------------------------------------------+ | |
1024 | * poll unitl the packet is sent and then make sure it is OK | |
1025 | *-----------------------------------------------------------------------*/ | |
1026 | time_start = get_timer (0); | |
1027 | while (1) { | |
1028 | temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); | |
1029 | /* loop until either TINT turns on or 3 seconds elapse */ | |
1030 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
1031 | /* transmit is done, so now check for errors | |
1032 | * If there is an error, an interrupt should | |
1033 | * happen when we return | |
1034 | */ | |
1035 | time_now = get_timer (0); | |
1036 | if ((time_now - time_start) > 3000) { | |
1037 | return (-1); | |
1038 | } | |
1039 | } else { | |
1040 | return (len); | |
1041 | } | |
1042 | } | |
1043 | } | |
1044 | ||
6e7fb6ea | 1045 | |
d6c61aab | 1046 | #if defined (CONFIG_440) |
ba56f625 | 1047 | |
6c5879f3 | 1048 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
6e7fb6ea SR |
1049 | /* |
1050 | * Hack: On 440SP all enet irq sources are located on UIC1 | |
1051 | * Needs some cleanup. --sr | |
1052 | */ | |
1053 | #define UIC0MSR uic1msr | |
1054 | #define UIC0SR uic1sr | |
1055 | #else | |
1056 | #define UIC0MSR uic0msr | |
1057 | #define UIC0SR uic0sr | |
1058 | #endif | |
1059 | ||
887e2ec9 SR |
1060 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1061 | #define UICMSR_ETHX uic0msr | |
1062 | #define UICSR_ETHX uic0sr | |
1063 | #else | |
1064 | #define UICMSR_ETHX uic1msr | |
1065 | #define UICSR_ETHX uic1sr | |
1066 | #endif | |
1067 | ||
ba56f625 WD |
1068 | int enetInt (struct eth_device *dev) |
1069 | { | |
1070 | int serviced; | |
1071 | int rc = -1; /* default to not us */ | |
1072 | unsigned long mal_isr; | |
1073 | unsigned long emac_isr = 0; | |
1074 | unsigned long mal_rx_eob; | |
1075 | unsigned long my_uic0msr, my_uic1msr; | |
887e2ec9 | 1076 | unsigned long my_uicmsr_ethx; |
ba56f625 | 1077 | |
846b0dd2 | 1078 | #if defined(CONFIG_440GX) |
ba56f625 WD |
1079 | unsigned long my_uic2msr; |
1080 | #endif | |
d6c61aab | 1081 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
1082 | |
1083 | /* | |
1084 | * Because the mal is generic, we need to get the current | |
1085 | * eth device | |
1086 | */ | |
d6c61aab SR |
1087 | #if defined(CONFIG_NET_MULTI) |
1088 | dev = eth_get_dev(); | |
1089 | #else | |
1090 | dev = emac0_dev; | |
1091 | #endif | |
ba56f625 WD |
1092 | |
1093 | hw_p = dev->priv; | |
1094 | ||
ba56f625 WD |
1095 | /* enter loop that stays in interrupt code until nothing to service */ |
1096 | do { | |
1097 | serviced = 0; | |
1098 | ||
6e7fb6ea | 1099 | my_uic0msr = mfdcr (UIC0MSR); |
ba56f625 | 1100 | my_uic1msr = mfdcr (uic1msr); |
846b0dd2 | 1101 | #if defined(CONFIG_440GX) |
ba56f625 WD |
1102 | my_uic2msr = mfdcr (uic2msr); |
1103 | #endif | |
887e2ec9 SR |
1104 | my_uicmsr_ethx = mfdcr (UICMSR_ETHX); |
1105 | ||
ba56f625 | 1106 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
887e2ec9 SR |
1107 | && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) |
1108 | && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { | |
ba56f625 WD |
1109 | /* not for us */ |
1110 | return (rc); | |
1111 | } | |
846b0dd2 | 1112 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1113 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
1114 | && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { | |
1115 | /* not for us */ | |
1116 | return (rc); | |
1117 | } | |
1118 | #endif | |
1119 | /* get and clear controller status interrupts */ | |
1120 | /* look at Mal and EMAC interrupts */ | |
1121 | if ((my_uic0msr & (UIC_MRE | UIC_MTE)) | |
1122 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
1123 | /* we have a MAL interrupt */ | |
1124 | mal_isr = mfdcr (malesr); | |
1125 | /* look for mal error */ | |
1126 | if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { | |
887e2ec9 | 1127 | mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); |
ba56f625 WD |
1128 | serviced = 1; |
1129 | rc = 0; | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | /* port by port dispatch of emac interrupts */ | |
1134 | if (hw_p->devnum == 0) { | |
887e2ec9 | 1135 | if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ |
ba56f625 WD |
1136 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
1137 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1138 | emac_err (dev, emac_isr); | |
1139 | serviced = 1; | |
1140 | rc = 0; | |
1141 | } | |
1142 | } | |
1143 | if ((hw_p->emac_ier & emac_isr) | |
1144 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1145 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
887e2ec9 SR |
1146 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1147 | mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ | |
ba56f625 WD |
1148 | return (rc); /* we had errors so get out */ |
1149 | } | |
1150 | } | |
1151 | ||
6e7fb6ea | 1152 | #if !defined(CONFIG_440SP) |
ba56f625 | 1153 | if (hw_p->devnum == 1) { |
887e2ec9 | 1154 | if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ |
ba56f625 WD |
1155 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
1156 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1157 | emac_err (dev, emac_isr); | |
1158 | serviced = 1; | |
1159 | rc = 0; | |
1160 | } | |
1161 | } | |
1162 | if ((hw_p->emac_ier & emac_isr) | |
1163 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1164 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
887e2ec9 SR |
1165 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1166 | mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ | |
ba56f625 WD |
1167 | return (rc); /* we had errors so get out */ |
1168 | } | |
1169 | } | |
846b0dd2 | 1170 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1171 | if (hw_p->devnum == 2) { |
1172 | if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ | |
1173 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1174 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1175 | emac_err (dev, emac_isr); | |
1176 | serviced = 1; | |
1177 | rc = 0; | |
1178 | } | |
1179 | } | |
1180 | if ((hw_p->emac_ier & emac_isr) | |
1181 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1182 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
ba56f625 WD |
1183 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1184 | mtdcr (uic2sr, UIC_ETH2); | |
1185 | return (rc); /* we had errors so get out */ | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | if (hw_p->devnum == 3) { | |
1190 | if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ | |
1191 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1192 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1193 | emac_err (dev, emac_isr); | |
1194 | serviced = 1; | |
1195 | rc = 0; | |
1196 | } | |
1197 | } | |
1198 | if ((hw_p->emac_ier & emac_isr) | |
1199 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1200 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
ba56f625 WD |
1201 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1202 | mtdcr (uic2sr, UIC_ETH3); | |
1203 | return (rc); /* we had errors so get out */ | |
1204 | } | |
1205 | } | |
846b0dd2 | 1206 | #endif /* CONFIG_440GX */ |
6e7fb6ea SR |
1207 | #endif /* !CONFIG_440SP */ |
1208 | ||
ba56f625 WD |
1209 | /* handle MAX TX EOB interrupt from a tx */ |
1210 | if (my_uic0msr & UIC_MTE) { | |
1211 | mal_rx_eob = mfdcr (maltxeobisr); | |
1212 | mtdcr (maltxeobisr, mal_rx_eob); | |
6e7fb6ea | 1213 | mtdcr (UIC0SR, UIC_MTE); |
ba56f625 WD |
1214 | } |
1215 | /* handle MAL RX EOB interupt from a receive */ | |
fc1cfcdb | 1216 | /* check for EOB on valid channels */ |
ba56f625 WD |
1217 | if (my_uic0msr & UIC_MRE) { |
1218 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1219 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
ba56f625 WD |
1220 | /* clear EOB |
1221 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1222 | enet_rcv (dev, emac_isr); | |
1223 | /* indicate that we serviced an interrupt */ | |
1224 | serviced = 1; | |
1225 | rc = 0; | |
1226 | } | |
1227 | } | |
6e7fb6ea SR |
1228 | |
1229 | mtdcr (UIC0SR, UIC_MRE); /* Clear */ | |
ba56f625 WD |
1230 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1231 | switch (hw_p->devnum) { | |
1232 | case 0: | |
887e2ec9 | 1233 | mtdcr (UICSR_ETHX, UIC_ETH0); |
ba56f625 WD |
1234 | break; |
1235 | case 1: | |
887e2ec9 | 1236 | mtdcr (UICSR_ETHX, UIC_ETH1); |
ba56f625 | 1237 | break; |
846b0dd2 | 1238 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1239 | case 2: |
1240 | mtdcr (uic2sr, UIC_ETH2); | |
1241 | break; | |
1242 | case 3: | |
1243 | mtdcr (uic2sr, UIC_ETH3); | |
1244 | break; | |
846b0dd2 | 1245 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
1246 | default: |
1247 | break; | |
1248 | } | |
1249 | } while (serviced); | |
1250 | ||
1251 | return (rc); | |
1252 | } | |
1253 | ||
d6c61aab SR |
1254 | #else /* CONFIG_440 */ |
1255 | ||
1256 | int enetInt (struct eth_device *dev) | |
1257 | { | |
1258 | int serviced; | |
1259 | int rc = -1; /* default to not us */ | |
1260 | unsigned long mal_isr; | |
1261 | unsigned long emac_isr = 0; | |
1262 | unsigned long mal_rx_eob; | |
1263 | unsigned long my_uicmsr; | |
1264 | ||
1265 | EMAC_4XX_HW_PST hw_p; | |
1266 | ||
1267 | /* | |
1268 | * Because the mal is generic, we need to get the current | |
1269 | * eth device | |
1270 | */ | |
1271 | #if defined(CONFIG_NET_MULTI) | |
1272 | dev = eth_get_dev(); | |
1273 | #else | |
1274 | dev = emac0_dev; | |
1275 | #endif | |
1276 | ||
1277 | hw_p = dev->priv; | |
1278 | ||
1279 | /* enter loop that stays in interrupt code until nothing to service */ | |
1280 | do { | |
1281 | serviced = 0; | |
1282 | ||
1283 | my_uicmsr = mfdcr (uicmsr); | |
1284 | ||
1285 | if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ | |
1286 | return (rc); | |
1287 | } | |
1288 | /* get and clear controller status interrupts */ | |
1289 | /* look at Mal and EMAC interrupts */ | |
1290 | if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ | |
1291 | mal_isr = mfdcr (malesr); | |
1292 | /* look for mal error */ | |
1293 | if ((my_uicmsr & MAL_UIC_ERR) != 0) { | |
1294 | mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); | |
1295 | serviced = 1; | |
1296 | rc = 0; | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | /* port by port dispatch of emac interrupts */ | |
1301 | ||
1302 | if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ | |
1303 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1304 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1305 | emac_err (dev, emac_isr); | |
1306 | serviced = 1; | |
1307 | rc = 0; | |
1308 | } | |
1309 | } | |
1310 | if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { | |
1311 | mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ | |
1312 | return (rc); /* we had errors so get out */ | |
1313 | } | |
1314 | ||
1315 | /* handle MAX TX EOB interrupt from a tx */ | |
1316 | if (my_uicmsr & UIC_MAL_TXEOB) { | |
1317 | mal_rx_eob = mfdcr (maltxeobisr); | |
1318 | mtdcr (maltxeobisr, mal_rx_eob); | |
1319 | mtdcr (uicsr, UIC_MAL_TXEOB); | |
1320 | } | |
1321 | /* handle MAL RX EOB interupt from a receive */ | |
1322 | /* check for EOB on valid channels */ | |
1323 | if (my_uicmsr & UIC_MAL_RXEOB) | |
1324 | { | |
1325 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1326 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
d6c61aab SR |
1327 | /* clear EOB |
1328 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1329 | enet_rcv (dev, emac_isr); | |
1330 | /* indicate that we serviced an interrupt */ | |
1331 | serviced = 1; | |
1332 | rc = 0; | |
1333 | } | |
1334 | } | |
1335 | mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ | |
1336 | } | |
1337 | while (serviced); | |
1338 | ||
1339 | return (rc); | |
1340 | } | |
1341 | ||
1342 | #endif /* CONFIG_440 */ | |
1343 | ||
ba56f625 WD |
1344 | /*-----------------------------------------------------------------------------+ |
1345 | * MAL Error Routine | |
1346 | *-----------------------------------------------------------------------------*/ | |
1347 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1348 | unsigned long uic, unsigned long maldef, | |
1349 | unsigned long mal_errr) | |
1350 | { | |
d6c61aab | 1351 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1352 | |
1353 | mtdcr (malesr, isr); /* clear interrupt */ | |
1354 | ||
1355 | /* clear DE interrupt */ | |
1356 | mtdcr (maltxdeir, 0xC0000000); | |
1357 | mtdcr (malrxdeir, 0x80000000); | |
1358 | ||
d6c61aab | 1359 | #ifdef INFO_4XX_ENET |
265817c7 | 1360 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1361 | #endif |
1362 | ||
1363 | eth_init (hw_p->bis); /* start again... */ | |
1364 | } | |
1365 | ||
1366 | /*-----------------------------------------------------------------------------+ | |
1367 | * EMAC Error Routine | |
1368 | *-----------------------------------------------------------------------------*/ | |
1369 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1370 | { | |
d6c61aab | 1371 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1372 | |
1373 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
1374 | out32 (EMAC_ISR + hw_p->hw_addr, isr); | |
1375 | } | |
1376 | ||
1377 | /*-----------------------------------------------------------------------------+ | |
1378 | * enet_rcv() handles the ethernet receive data | |
1379 | *-----------------------------------------------------------------------------*/ | |
1380 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1381 | { | |
1382 | struct enet_frame *ef_ptr; | |
1383 | unsigned long data_len; | |
1384 | unsigned long rx_eob_isr; | |
d6c61aab | 1385 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1386 | |
1387 | int handled = 0; | |
1388 | int i; | |
1389 | int loop_count = 0; | |
1390 | ||
1391 | rx_eob_isr = mfdcr (malrxeobisr); | |
1392 | if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { | |
1393 | /* clear EOB */ | |
1394 | mtdcr (malrxeobisr, rx_eob_isr); | |
1395 | ||
1396 | /* EMAC RX done */ | |
1397 | while (1) { /* do all */ | |
1398 | i = hw_p->rx_slot; | |
1399 | ||
1400 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1401 | || (loop_count >= NUM_RX_BUFF)) | |
1402 | break; | |
1403 | loop_count++; | |
1404 | hw_p->rx_slot++; | |
1405 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1406 | hw_p->rx_slot = 0; | |
1407 | handled++; | |
1408 | data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ | |
1409 | if (data_len) { | |
1410 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1411 | data_len = 0; | |
1412 | else { | |
1413 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1414 | data_len = 0; | |
1415 | hw_p->stats.rx_err_log[hw_p-> | |
1416 | rx_err_index] | |
1417 | = hw_p->rx[i].ctrl; | |
1418 | hw_p->rx_err_index++; | |
1419 | if (hw_p->rx_err_index == | |
1420 | MAX_ERR_LOG) | |
1421 | hw_p->rx_err_index = | |
1422 | 0; | |
fc1cfcdb | 1423 | } /* emac_erros */ |
ba56f625 | 1424 | } /* data_len < max mtu */ |
fc1cfcdb | 1425 | } /* if data_len */ |
ba56f625 WD |
1426 | if (!data_len) { /* no data */ |
1427 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1428 | ||
1429 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1430 | } | |
1431 | ||
1432 | /* !data_len */ | |
1433 | /* AS.HARNOIS */ | |
1434 | /* Check if user has already eaten buffer */ | |
1435 | /* if not => ERROR */ | |
1436 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1437 | if (hw_p->is_receiving) | |
1438 | printf ("ERROR : Receive buffers are full!\n"); | |
1439 | break; | |
1440 | } else { | |
1441 | hw_p->stats.rx_frames++; | |
1442 | hw_p->stats.rx += data_len; | |
1443 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
1444 | data_ptr; | |
d6c61aab | 1445 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1446 | hw_p->stats.pkts_rx++; |
1447 | #endif | |
1448 | /* AS.HARNOIS | |
1449 | * use ring buffer | |
1450 | */ | |
1451 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1452 | hw_p->rx_i_index++; | |
1453 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1454 | hw_p->rx_i_index = 0; | |
1455 | ||
ba56f625 WD |
1456 | /* AS.HARNOIS |
1457 | * free receive buffer only when | |
1458 | * buffer has been handled (eth_rx) | |
1459 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1460 | */ | |
1461 | } /* if data_len */ | |
1462 | } /* while */ | |
1463 | } /* if EMACK_RXCHL */ | |
1464 | } | |
1465 | ||
1466 | ||
d6c61aab | 1467 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1468 | { |
1469 | int length; | |
1470 | int user_index; | |
1471 | unsigned long msr; | |
d6c61aab | 1472 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1473 | |
265817c7 | 1474 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1475 | |
1476 | for (;;) { | |
1477 | /* AS.HARNOIS | |
1478 | * use ring buffer and | |
1479 | * get index from rx buffer desciptor queue | |
1480 | */ | |
1481 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1482 | if (user_index == -1) { | |
1483 | length = -1; | |
1484 | break; /* nothing received - leave for() loop */ | |
1485 | } | |
1486 | ||
1487 | msr = mfmsr (); | |
1488 | mtmsr (msr & ~(MSR_EE)); | |
1489 | ||
1490 | length = hw_p->rx[user_index].data_len; | |
1491 | ||
1492 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1493 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1494 | /* NetReceive(NetRxPackets[i], length); */ | |
ba56f625 WD |
1495 | NetReceive (NetRxPackets[user_index], length - 4); |
1496 | /* Free Recv Buffer */ | |
1497 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1498 | /* Free rx buffer descriptor queue */ | |
1499 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1500 | hw_p->rx_u_index++; | |
1501 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1502 | hw_p->rx_u_index = 0; | |
1503 | ||
d6c61aab | 1504 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1505 | hw_p->stats.pkts_handled++; |
1506 | #endif | |
1507 | ||
1508 | mtmsr (msr); /* Enable IRQ's */ | |
1509 | } | |
1510 | ||
265817c7 | 1511 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1512 | |
1513 | return length; | |
1514 | } | |
1515 | ||
d6c61aab | 1516 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1517 | { |
1518 | static int virgin = 0; | |
ba56f625 WD |
1519 | struct eth_device *dev; |
1520 | int eth_num = 0; | |
d6c61aab | 1521 | EMAC_4XX_HW_PST hw = NULL; |
5fb692ca SR |
1522 | u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; |
1523 | u32 hw_addr[4]; | |
ba56f625 | 1524 | |
846b0dd2 | 1525 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1526 | unsigned long pfc1; |
1527 | ||
ba56f625 WD |
1528 | mfsdr (sdr_pfc1, pfc1); |
1529 | pfc1 &= ~(0x01e00000); | |
1530 | pfc1 |= 0x01200000; | |
1531 | mtsdr (sdr_pfc1, pfc1); | |
c157d8e2 | 1532 | #endif |
6c5879f3 | 1533 | |
5fb692ca SR |
1534 | /* first clear all mac-addresses */ |
1535 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) | |
1536 | memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); | |
a06752e3 | 1537 | |
1e25f957 | 1538 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
ba56f625 | 1539 | switch (eth_num) { |
e2ffd59b | 1540 | default: /* fall through */ |
ba56f625 | 1541 | case 0: |
5fb692ca SR |
1542 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1543 | bis->bi_enetaddr, 6); | |
1544 | hw_addr[eth_num] = 0x0; | |
ba56f625 | 1545 | break; |
e2ffd59b | 1546 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1547 | case 1: |
5fb692ca SR |
1548 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1549 | bis->bi_enet1addr, 6); | |
1550 | hw_addr[eth_num] = 0x100; | |
ba56f625 | 1551 | break; |
e2ffd59b WD |
1552 | #endif |
1553 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1554 | case 2: |
5fb692ca SR |
1555 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1556 | bis->bi_enet2addr, 6); | |
1557 | hw_addr[eth_num] = 0x400; | |
ba56f625 | 1558 | break; |
e2ffd59b WD |
1559 | #endif |
1560 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1561 | case 3: |
5fb692ca SR |
1562 | memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], |
1563 | bis->bi_enet3addr, 6); | |
1564 | hw_addr[eth_num] = 0x600; | |
ba56f625 | 1565 | break; |
e2ffd59b | 1566 | #endif |
ba56f625 | 1567 | } |
5fb692ca SR |
1568 | } |
1569 | ||
1570 | /* set phy num and mode */ | |
1571 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
1572 | bis->bi_phymode[0] = 0; | |
1573 | ||
1574 | #if defined(CONFIG_PHY1_ADDR) | |
1575 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; | |
1576 | bis->bi_phymode[1] = 0; | |
1577 | #endif | |
1578 | #if defined(CONFIG_440GX) | |
1579 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; | |
1580 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
1581 | bis->bi_phymode[2] = 2; | |
1582 | bis->bi_phymode[3] = 2; | |
1583 | ||
1584 | ppc_4xx_eth_setup_bridge(0, bis); | |
1585 | #endif | |
1586 | ||
1587 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { | |
1588 | /* | |
1589 | * See if we can actually bring up the interface, | |
1590 | * otherwise, skip it | |
1591 | */ | |
1592 | if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { | |
1593 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
1594 | continue; | |
1595 | } | |
ba56f625 WD |
1596 | |
1597 | /* Allocate device structure */ | |
1598 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
1599 | if (dev == NULL) { | |
d6c61aab | 1600 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 1601 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
1602 | return (-1); |
1603 | } | |
b2532eff | 1604 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
1605 | |
1606 | /* Allocate our private use data */ | |
d6c61aab | 1607 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 1608 | if (hw == NULL) { |
d6c61aab | 1609 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 1610 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
1611 | eth_num); |
1612 | free (dev); | |
1613 | return (-1); | |
1614 | } | |
b2532eff | 1615 | memset(hw, 0, sizeof(*hw)); |
ba56f625 | 1616 | |
5fb692ca SR |
1617 | hw->hw_addr = hw_addr[eth_num]; |
1618 | memcpy (dev->enetaddr, ethaddr[eth_num], 6); | |
ba56f625 | 1619 | hw->devnum = eth_num; |
c157d8e2 | 1620 | hw->print_speed = 1; |
ba56f625 | 1621 | |
5fb692ca | 1622 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); |
ba56f625 | 1623 | dev->priv = (void *) hw; |
d6c61aab SR |
1624 | dev->init = ppc_4xx_eth_init; |
1625 | dev->halt = ppc_4xx_eth_halt; | |
1626 | dev->send = ppc_4xx_eth_send; | |
1627 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 WD |
1628 | |
1629 | if (0 == virgin) { | |
1630 | /* set the MAL IER ??? names may change with new spec ??? */ | |
887e2ec9 | 1631 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
1632 | mal_ier = |
1633 | MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | | |
1634 | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; | |
1635 | #else | |
ba56f625 WD |
1636 | mal_ier = |
1637 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
1638 | MAL_IER_OPBE | MAL_IER_PLBE; | |
6c5879f3 | 1639 | #endif |
ba56f625 WD |
1640 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ |
1641 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
1642 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
1643 | mtdcr (malier, mal_ier); | |
1644 | ||
1645 | /* install MAL interrupt handler */ | |
1646 | irq_install_handler (VECNUM_MS, | |
1647 | (interrupt_handler_t *) enetInt, | |
1648 | dev); | |
1649 | irq_install_handler (VECNUM_MTE, | |
1650 | (interrupt_handler_t *) enetInt, | |
1651 | dev); | |
1652 | irq_install_handler (VECNUM_MRE, | |
1653 | (interrupt_handler_t *) enetInt, | |
1654 | dev); | |
1655 | irq_install_handler (VECNUM_TXDE, | |
1656 | (interrupt_handler_t *) enetInt, | |
1657 | dev); | |
1658 | irq_install_handler (VECNUM_RXDE, | |
1659 | (interrupt_handler_t *) enetInt, | |
1660 | dev); | |
1661 | virgin = 1; | |
1662 | } | |
1663 | ||
d6c61aab | 1664 | #if defined(CONFIG_NET_MULTI) |
ba56f625 | 1665 | eth_register (dev); |
d6c61aab SR |
1666 | #else |
1667 | emac0_dev = dev; | |
1668 | #endif | |
6c5879f3 MB |
1669 | |
1670 | #if defined(CONFIG_NET_MULTI) | |
63ff004c MB |
1671 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) |
1672 | miiphy_register (dev->name, | |
6e7fb6ea | 1673 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c | 1674 | #endif |
6c5879f3 | 1675 | #endif |
ba56f625 WD |
1676 | } /* end for each supported device */ |
1677 | return (1); | |
1678 | } | |
d6c61aab | 1679 | |
d6c61aab SR |
1680 | #if !defined(CONFIG_NET_MULTI) |
1681 | void eth_halt (void) { | |
1682 | if (emac0_dev) { | |
1683 | ppc_4xx_eth_halt(emac0_dev); | |
1684 | free(emac0_dev); | |
1685 | emac0_dev = NULL; | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | int eth_init (bd_t *bis) | |
1690 | { | |
1691 | ppc_4xx_eth_initialize(bis); | |
4f92ac36 SR |
1692 | if (emac0_dev) { |
1693 | return ppc_4xx_eth_init(emac0_dev, bis); | |
1694 | } else { | |
1695 | printf("ERROR: ethaddr not set!\n"); | |
1696 | return -1; | |
1697 | } | |
d6c61aab SR |
1698 | } |
1699 | ||
1700 | int eth_send(volatile void *packet, int length) | |
1701 | { | |
d6c61aab SR |
1702 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); |
1703 | } | |
1704 | ||
1705 | int eth_rx(void) | |
1706 | { | |
1707 | return (ppc_4xx_eth_rx(emac0_dev)); | |
1708 | } | |
63ff004c MB |
1709 | |
1710 | int emac4xx_miiphy_initialize (bd_t * bis) | |
1711 | { | |
1712 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) | |
1713 | miiphy_register ("ppc_4xx_eth0", | |
6e7fb6ea | 1714 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c MB |
1715 | #endif |
1716 | ||
1717 | return 0; | |
1718 | } | |
d6c61aab SR |
1719 | #endif /* !defined(CONFIG_NET_MULTI) */ |
1720 | ||
1721 | #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ |