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ba56f625 WD |
1 | /*-----------------------------------------------------------------------------+ |
2 | * | |
265817c7 WD |
3 | * This source code has been made available to you by IBM on an AS-IS |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
ba56f625 | 9 | * |
265817c7 WD |
10 | * Any user of this software should understand that IBM cannot provide |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
ba56f625 | 13 | * |
265817c7 WD |
14 | * Any person who transfers this source code or any derivative work |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
ba56f625 | 17 | * |
265817c7 WD |
18 | * COPYRIGHT I B M CORPORATION 1995 |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
ba56f625 WD |
20 | *-----------------------------------------------------------------------------*/ |
21 | /*-----------------------------------------------------------------------------+ | |
22 | * | |
265817c7 | 23 | * File Name: enetemac.c |
ba56f625 | 24 | * |
265817c7 | 25 | * Function: Device driver for the ethernet EMAC3 macro on the 405GP. |
ba56f625 | 26 | * |
265817c7 | 27 | * Author: Mark Wisner |
ba56f625 WD |
28 | * |
29 | * Change Activity- | |
30 | * | |
265817c7 WD |
31 | * Date Description of Change BY |
32 | * --------- --------------------- --- | |
33 | * 05-May-99 Created MKW | |
34 | * 27-Jun-99 Clean up JWB | |
35 | * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW | |
36 | * 29-Jul-99 Added Full duplex support MKW | |
37 | * 06-Aug-99 Changed names for Mal CR reg MKW | |
38 | * 23-Aug-99 Turned off SYE when running at 10Mbs MKW | |
39 | * 24-Aug-99 Marked descriptor empty after call_xlc MKW | |
40 | * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG | |
41 | * to avoid chaining maximum sized packets. Push starting | |
42 | * RX descriptor address up to the next cache line boundary. | |
43 | * 16-Jan-00 Added support for booting with IP of 0x0 MKW | |
44 | * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the | |
45 | * EMAC_RXM register. JWB | |
46 | * 12-Mar-01 anne-sophie.harnois@nextream.fr | |
47 | * - Variables are compatible with those already defined in | |
48 | * include/net.h | |
49 | * - Receive buffer descriptor ring is used to send buffers | |
50 | * to the user | |
51 | * - Info print about send/received/handled packet number if | |
52 | * INFO_405_ENET is set | |
53 | * 17-Apr-01 stefan.roese@esd-electronics.com | |
54 | * - MAL reset in "eth_halt" included | |
55 | * - Enet speed and duplex output now in one line | |
56 | * 08-May-01 stefan.roese@esd-electronics.com | |
57 | * - MAL error handling added (eth_init called again) | |
58 | * 13-Nov-01 stefan.roese@esd-electronics.com | |
59 | * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex | |
60 | * 04-Jan-02 stefan.roese@esd-electronics.com | |
61 | * - Wait for PHY auto negotiation to complete added | |
62 | * 06-Feb-02 stefan.roese@esd-electronics.com | |
63 | * - Bug fixed in waiting for auto negotiation to complete | |
64 | * 26-Feb-02 stefan.roese@esd-electronics.com | |
65 | * - rx and tx buffer descriptors now allocated (no fixed address | |
66 | * used anymore) | |
67 | * 17-Jun-02 stefan.roese@esd-electronics.com | |
68 | * - MAL error debug printf 'M' removed (rx de interrupt may | |
69 | * occur upon many incoming packets with only 4 rx buffers). | |
ba56f625 | 70 | *-----------------------------------------------------------------------------* |
265817c7 WD |
71 | * 17-Nov-03 travis.sawyer@sandburst.com |
72 | * - ported from 405gp_enet.c to utilized upto 4 EMAC ports | |
73 | * in the 440GX. This port should work with the 440GP | |
74 | * (2 EMACs) also | |
75 | * 15-Aug-05 sr@denx.de | |
76 | * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c | |
77 | now handling all 4xx cpu's. | |
ba56f625 WD |
78 | *-----------------------------------------------------------------------------*/ |
79 | ||
80 | #include <config.h> | |
ba56f625 WD |
81 | #include <common.h> |
82 | #include <net.h> | |
83 | #include <asm/processor.h> | |
ba56f625 | 84 | #include <commproc.h> |
d6c61aab SR |
85 | #include <ppc4xx.h> |
86 | #include <ppc4xx_enet.h> | |
ba56f625 WD |
87 | #include <405_mal.h> |
88 | #include <miiphy.h> | |
89 | #include <malloc.h> | |
90 | #include "vecnum.h" | |
91 | ||
d6c61aab | 92 | /* |
0c8721a4 | 93 | * Only compile for platform with AMCC EMAC ethernet controller and |
d6c61aab SR |
94 | * network support enabled. |
95 | * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! | |
96 | */ | |
97 | #if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) | |
98 | ||
99 | #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) | |
100 | #error "CONFIG_MII has to be defined!" | |
101 | #endif | |
ba56f625 | 102 | |
1e25f957 SR |
103 | #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI) |
104 | #error "CONFIG_NET_MULTI has to be defined for NetConsole" | |
105 | #endif | |
106 | ||
265817c7 | 107 | #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ |
ba56f625 WD |
108 | #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ |
109 | ||
ba56f625 WD |
110 | /* Ethernet Transmit and Receive Buffers */ |
111 | /* AS.HARNOIS | |
112 | * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from | |
113 | * PKTSIZE and PKTSIZE_ALIGN (include/net.h) | |
114 | */ | |
265817c7 | 115 | #define ENET_MAX_MTU PKTSIZE |
ba56f625 WD |
116 | #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN |
117 | ||
ba56f625 WD |
118 | /*-----------------------------------------------------------------------------+ |
119 | * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal | |
120 | * Interrupt Controller). | |
121 | *-----------------------------------------------------------------------------*/ | |
122 | #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) | |
123 | #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) | |
124 | #define EMAC_UIC_DEF UIC_ENET | |
d6c61aab SR |
125 | #define EMAC_UIC_DEF1 UIC_ENET1 |
126 | #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) | |
ba56f625 | 127 | |
d6c61aab | 128 | #undef INFO_4XX_ENET |
ba56f625 | 129 | |
265817c7 WD |
130 | #define BI_PHYMODE_NONE 0 |
131 | #define BI_PHYMODE_ZMII 1 | |
3c74e32a | 132 | #define BI_PHYMODE_RGMII 2 |
887e2ec9 SR |
133 | #define BI_PHYMODE_GMII 3 |
134 | #define BI_PHYMODE_RTBI 4 | |
135 | #define BI_PHYMODE_TBI 5 | |
854bc8da | 136 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
887e2ec9 SR |
137 | #define BI_PHYMODE_SMII 6 |
138 | #define BI_PHYMODE_MII 7 | |
139 | #endif | |
3c74e32a | 140 | |
887e2ec9 SR |
141 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
142 | #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) | |
143 | #endif | |
d6c61aab | 144 | |
ba56f625 WD |
145 | /*-----------------------------------------------------------------------------+ |
146 | * Global variables. TX and RX descriptors and buffers. | |
147 | *-----------------------------------------------------------------------------*/ | |
148 | /* IER globals */ | |
149 | static uint32_t mal_ier; | |
150 | ||
d6c61aab | 151 | #if !defined(CONFIG_NET_MULTI) |
4f92ac36 | 152 | struct eth_device *emac0_dev = NULL; |
d6c61aab SR |
153 | #endif |
154 | ||
1e25f957 SR |
155 | /* |
156 | * Get count of EMAC devices (doesn't have to be the max. possible number | |
157 | * supported by the cpu) | |
158 | */ | |
159 | #if defined(CONFIG_HAS_ETH3) | |
160 | #define LAST_EMAC_NUM 4 | |
161 | #elif defined(CONFIG_HAS_ETH2) | |
162 | #define LAST_EMAC_NUM 3 | |
163 | #elif defined(CONFIG_HAS_ETH1) | |
164 | #define LAST_EMAC_NUM 2 | |
165 | #else | |
166 | #define LAST_EMAC_NUM 1 | |
167 | #endif | |
d6c61aab | 168 | |
ba56f625 WD |
169 | /*-----------------------------------------------------------------------------+ |
170 | * Prototypes and externals. | |
171 | *-----------------------------------------------------------------------------*/ | |
172 | static void enet_rcv (struct eth_device *dev, unsigned long malisr); | |
173 | ||
174 | int enetInt (struct eth_device *dev); | |
175 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
176 | unsigned long uic, unsigned long maldef, | |
177 | unsigned long mal_errr); | |
178 | static void emac_err (struct eth_device *dev, unsigned long isr); | |
179 | ||
63ff004c MB |
180 | extern int phy_setup_aneg (char *devname, unsigned char addr); |
181 | extern int emac4xx_miiphy_read (char *devname, unsigned char addr, | |
182 | unsigned char reg, unsigned short *value); | |
183 | extern int emac4xx_miiphy_write (char *devname, unsigned char addr, | |
184 | unsigned char reg, unsigned short value); | |
d6c61aab | 185 | |
ba56f625 | 186 | /*-----------------------------------------------------------------------------+ |
d6c61aab | 187 | | ppc_4xx_eth_halt |
ba56f625 | 188 | | Disable MAL channel, and EMACn |
ba56f625 | 189 | +-----------------------------------------------------------------------------*/ |
d6c61aab | 190 | static void ppc_4xx_eth_halt (struct eth_device *dev) |
ba56f625 | 191 | { |
d6c61aab | 192 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 193 | uint32_t failsafe = 10000; |
887e2ec9 | 194 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
195 | unsigned long mfr; |
196 | #endif | |
ba56f625 WD |
197 | |
198 | out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ | |
199 | ||
200 | /* 1st reset MAL channel */ | |
201 | /* Note: writing a 0 to a channel has no effect */ | |
d6c61aab SR |
202 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
203 | mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); | |
204 | #else | |
ba56f625 | 205 | mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
d6c61aab | 206 | #endif |
ba56f625 WD |
207 | mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); |
208 | ||
209 | /* wait for reset */ | |
d6c61aab | 210 | while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { |
ba56f625 WD |
211 | udelay (1000); /* Delay 1 MS so as not to hammer the register */ |
212 | failsafe--; | |
213 | if (failsafe == 0) | |
214 | break; | |
ba56f625 WD |
215 | } |
216 | ||
217 | /* EMAC RESET */ | |
887e2ec9 | 218 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
219 | /* provide clocks for EMAC internal loopback */ |
220 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 221 | mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); |
6c5879f3 MB |
222 | mtsdr(sdr_mfr, mfr); |
223 | #endif | |
224 | ||
ba56f625 WD |
225 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
226 | ||
887e2ec9 | 227 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
228 | /* remove clocks for EMAC internal loopback */ |
229 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 230 | mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); |
6c5879f3 MB |
231 | mtsdr(sdr_mfr, mfr); |
232 | #endif | |
233 | ||
234 | ||
a93316c5 | 235 | #ifndef CONFIG_NETCONSOLE |
c157d8e2 | 236 | hw_p->print_speed = 1; /* print speed message again next time */ |
a93316c5 | 237 | #endif |
c157d8e2 | 238 | |
ba56f625 WD |
239 | return; |
240 | } | |
241 | ||
846b0dd2 | 242 | #if defined (CONFIG_440GX) |
d6c61aab | 243 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
855a496f WD |
244 | { |
245 | unsigned long pfc1; | |
246 | unsigned long zmiifer; | |
247 | unsigned long rmiifer; | |
248 | ||
249 | mfsdr(sdr_pfc1, pfc1); | |
250 | pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); | |
251 | ||
252 | zmiifer = 0; | |
253 | rmiifer = 0; | |
254 | ||
255 | switch (pfc1) { | |
256 | case 1: | |
257 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
258 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); | |
259 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); | |
260 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); | |
261 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
262 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
263 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
264 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
265 | break; | |
266 | case 2: | |
267 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); | |
268 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); | |
269 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); | |
270 | zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); | |
271 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
272 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
273 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
274 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
275 | break; | |
276 | case 3: | |
277 | zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); | |
278 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
279 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
280 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
281 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
282 | bis->bi_phymode[3] = BI_PHYMODE_NONE; | |
283 | break; | |
284 | case 4: | |
285 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); | |
286 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); | |
287 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); | |
288 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); | |
289 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
290 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
291 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
292 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
293 | break; | |
294 | case 5: | |
295 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
296 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
297 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); | |
298 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); | |
299 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
300 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
301 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
302 | bis->bi_phymode[3] = BI_PHYMODE_RGMII; | |
303 | break; | |
304 | case 6: | |
305 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); | |
306 | zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); | |
307 | rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); | |
855a496f WD |
308 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; |
309 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
310 | bis->bi_phymode[2] = BI_PHYMODE_RGMII; | |
855a496f WD |
311 | break; |
312 | case 0: | |
313 | default: | |
314 | zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); | |
315 | rmiifer = 0x0; | |
316 | bis->bi_phymode[0] = BI_PHYMODE_ZMII; | |
317 | bis->bi_phymode[1] = BI_PHYMODE_ZMII; | |
318 | bis->bi_phymode[2] = BI_PHYMODE_ZMII; | |
319 | bis->bi_phymode[3] = BI_PHYMODE_ZMII; | |
320 | break; | |
321 | } | |
322 | ||
323 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
324 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
325 | ||
326 | out32 (ZMII_FER, zmiifer); | |
327 | out32 (RGMII_FER, rmiifer); | |
328 | ||
329 | return ((int)pfc1); | |
855a496f | 330 | } |
6c5879f3 | 331 | #endif /* CONFIG_440_GX */ |
855a496f | 332 | |
887e2ec9 SR |
333 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
334 | int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) | |
335 | { | |
336 | unsigned long zmiifer=0x0; | |
337 | ||
338 | /* | |
339 | * Right now only 2*RGMII is supported. Please extend when needed. | |
340 | * sr - 2006-08-29 | |
341 | */ | |
342 | switch (1) { | |
343 | case 0: | |
344 | /* 1 x GMII port */ | |
345 | out32 (ZMII_FER, 0x00); | |
346 | out32 (RGMII_FER, 0x00000037); | |
347 | bis->bi_phymode[0] = BI_PHYMODE_GMII; | |
348 | bis->bi_phymode[1] = BI_PHYMODE_NONE; | |
349 | break; | |
350 | case 1: | |
351 | /* 2 x RGMII ports */ | |
352 | out32 (ZMII_FER, 0x00); | |
353 | out32 (RGMII_FER, 0x00000055); | |
354 | bis->bi_phymode[0] = BI_PHYMODE_RGMII; | |
355 | bis->bi_phymode[1] = BI_PHYMODE_RGMII; | |
356 | break; | |
357 | case 2: | |
358 | /* 2 x SMII ports */ | |
359 | ||
360 | break; | |
361 | default: | |
362 | break; | |
363 | } | |
364 | ||
365 | /* Ensure we setup mdio for this devnum and ONLY this devnum */ | |
366 | zmiifer = in32 (ZMII_FER); | |
367 | zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); | |
368 | out32 (ZMII_FER, zmiifer); | |
369 | ||
370 | return ((int)0x0); | |
371 | } | |
372 | #endif /* CONFIG_440EPX */ | |
373 | ||
d6c61aab | 374 | static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
ba56f625 | 375 | { |
b79316f2 | 376 | int i, j; |
d6c61aab | 377 | unsigned long reg = 0; |
ba56f625 WD |
378 | unsigned long msr; |
379 | unsigned long speed; | |
380 | unsigned long duplex; | |
381 | unsigned long failsafe; | |
382 | unsigned mode_reg; | |
383 | unsigned short devnum; | |
384 | unsigned short reg_short; | |
887e2ec9 SR |
385 | #if defined(CONFIG_440GX) || \ |
386 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
387 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
d6c61aab | 388 | sys_info_t sysinfo; |
887e2ec9 SR |
389 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
390 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
6e7fb6ea SR |
391 | int ethgroup = -1; |
392 | #endif | |
c157d8e2 | 393 | #endif |
887e2ec9 | 394 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) |
6c5879f3 MB |
395 | unsigned long mfr; |
396 | #endif | |
397 | ||
ba56f625 | 398 | |
d6c61aab | 399 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
400 | |
401 | /* before doing anything, figure out if we have a MAC address */ | |
402 | /* if not, bail */ | |
4f92ac36 SR |
403 | if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
404 | printf("ERROR: ethaddr not set!\n"); | |
ba56f625 | 405 | return -1; |
4f92ac36 | 406 | } |
ba56f625 | 407 | |
887e2ec9 SR |
408 | #if defined(CONFIG_440GX) || \ |
409 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
410 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
ba56f625 WD |
411 | /* Need to get the OPB frequency so we can access the PHY */ |
412 | get_sys_info (&sysinfo); | |
d6c61aab | 413 | #endif |
ba56f625 | 414 | |
ba56f625 WD |
415 | msr = mfmsr (); |
416 | mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ | |
417 | ||
418 | devnum = hw_p->devnum; | |
419 | ||
d6c61aab | 420 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
421 | /* AS.HARNOIS |
422 | * We should have : | |
265817c7 | 423 | * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX |
ba56f625 WD |
424 | * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it |
425 | * is possible that new packets (without relationship with | |
426 | * current transfer) have got the time to arrived before | |
427 | * netloop calls eth_halt | |
428 | */ | |
429 | printf ("About preceeding transfer (eth%d):\n" | |
430 | "- Sent packet number %d\n" | |
431 | "- Received packet number %d\n" | |
432 | "- Handled packet number %d\n", | |
433 | hw_p->devnum, | |
434 | hw_p->stats.pkts_tx, | |
435 | hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); | |
436 | ||
437 | hw_p->stats.pkts_tx = 0; | |
438 | hw_p->stats.pkts_rx = 0; | |
439 | hw_p->stats.pkts_handled = 0; | |
6c5879f3 | 440 | hw_p->print_speed = 1; /* print speed message again next time */ |
ba56f625 WD |
441 | #endif |
442 | ||
265817c7 WD |
443 | hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ |
444 | hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ | |
ba56f625 WD |
445 | |
446 | hw_p->rx_slot = 0; /* MAL Receive Slot */ | |
447 | hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ | |
448 | hw_p->rx_u_index = 0; /* Receive User Queue Index */ | |
449 | ||
450 | hw_p->tx_slot = 0; /* MAL Transmit Slot */ | |
451 | hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ | |
452 | hw_p->tx_u_index = 0; /* Transmit User Queue Index */ | |
453 | ||
6c5879f3 | 454 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) |
ba56f625 WD |
455 | /* set RMII mode */ |
456 | /* NOTE: 440GX spec states that mode is mutually exclusive */ | |
457 | /* NOTE: Therefore, disable all other EMACS, since we handle */ | |
458 | /* NOTE: only one emac at a time */ | |
459 | reg = 0; | |
460 | out32 (ZMII_FER, 0); | |
461 | udelay (100); | |
ba56f625 | 462 | |
846b0dd2 | 463 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
265817c7 | 464 | out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
887e2ec9 | 465 | #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
d6c61aab | 466 | ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
4a3cd9e6 SR |
467 | #elif defined(CONFIG_440GP) |
468 | /* set RMII mode */ | |
469 | out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); | |
0e6d798c WD |
470 | #else |
471 | if ((devnum == 0) || (devnum == 1)) { | |
472 | out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); | |
473 | } | |
474 | else { /* ((devnum == 2) || (devnum == 3)) */ | |
475 | out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); | |
ba56f625 WD |
476 | out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | |
477 | (RGMII_FER_RGMII << RGMII_FER_V (3)))); | |
0e6d798c WD |
478 | } |
479 | #endif | |
c57c7980 | 480 | |
0e6d798c | 481 | out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
6e7fb6ea | 482 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
d6c61aab | 483 | |
0e6d798c WD |
484 | __asm__ volatile ("eieio"); |
485 | ||
486 | /* reset emac so we have access to the phy */ | |
887e2ec9 | 487 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
488 | /* provide clocks for EMAC internal loopback */ |
489 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 490 | mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); |
6c5879f3 MB |
491 | mtsdr(sdr_mfr, mfr); |
492 | #endif | |
0e6d798c WD |
493 | |
494 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); | |
ba56f625 WD |
495 | __asm__ volatile ("eieio"); |
496 | ||
497 | failsafe = 1000; | |
498 | while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { | |
499 | udelay (1000); | |
500 | failsafe--; | |
501 | } | |
887e2ec9 SR |
502 | if (failsafe <= 0) |
503 | printf("\nProblem resetting EMAC!\n"); | |
ba56f625 | 504 | |
887e2ec9 | 505 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
506 | /* remove clocks for EMAC internal loopback */ |
507 | mfsdr (sdr_mfr, mfr); | |
887e2ec9 | 508 | mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); |
6c5879f3 MB |
509 | mtsdr(sdr_mfr, mfr); |
510 | #endif | |
511 | ||
887e2ec9 SR |
512 | #if defined(CONFIG_440GX) || \ |
513 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
514 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
ba56f625 WD |
515 | /* Whack the M1 register */ |
516 | mode_reg = 0x0; | |
517 | mode_reg &= ~0x00000038; | |
518 | if (sysinfo.freqOPB <= 50000000); | |
519 | else if (sysinfo.freqOPB <= 66666667) | |
520 | mode_reg |= EMAC_M1_OBCI_66; | |
521 | else if (sysinfo.freqOPB <= 83333333) | |
522 | mode_reg |= EMAC_M1_OBCI_83; | |
523 | else if (sysinfo.freqOPB <= 100000000) | |
524 | mode_reg |= EMAC_M1_OBCI_100; | |
525 | else | |
526 | mode_reg |= EMAC_M1_OBCI_GT100; | |
527 | ||
528 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); | |
6e7fb6ea | 529 | #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
ba56f625 WD |
530 | |
531 | /* wait for PHY to complete auto negotiation */ | |
532 | reg_short = 0; | |
533 | #ifndef CONFIG_CS8952_PHY | |
534 | switch (devnum) { | |
535 | case 0: | |
536 | reg = CONFIG_PHY_ADDR; | |
537 | break; | |
d6c61aab | 538 | #if defined (CONFIG_PHY1_ADDR) |
ba56f625 WD |
539 | case 1: |
540 | reg = CONFIG_PHY1_ADDR; | |
541 | break; | |
d6c61aab | 542 | #endif |
846b0dd2 | 543 | #if defined (CONFIG_440GX) |
ba56f625 WD |
544 | case 2: |
545 | reg = CONFIG_PHY2_ADDR; | |
546 | break; | |
547 | case 3: | |
548 | reg = CONFIG_PHY3_ADDR; | |
549 | break; | |
550 | #endif | |
551 | default: | |
552 | reg = CONFIG_PHY_ADDR; | |
553 | break; | |
554 | } | |
555 | ||
3c74e32a WD |
556 | bis->bi_phynum[devnum] = reg; |
557 | ||
d6c61aab | 558 | #if defined(CONFIG_PHY_RESET) |
a06752e3 WD |
559 | /* |
560 | * Reset the phy, only if its the first time through | |
561 | * otherwise, just check the speeds & feeds | |
562 | */ | |
563 | if (hw_p->first_init == 0) { | |
887e2ec9 SR |
564 | #if defined(CONFIG_88E1111_CLK_DELAY) |
565 | /* | |
566 | * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs | |
567 | * the "RGMII transmit timing control" and "RGMII receive | |
568 | * timing control" bits set, so that Gbit communication works | |
569 | * without problems. | |
570 | * Also set the "Transmitter disable" to 1 to enable the | |
571 | * transmitter. | |
572 | * After setting these bits a soft-reset must occur for this | |
573 | * change to become active. | |
574 | */ | |
575 | miiphy_read (dev->name, reg, 0x14, ®_short); | |
576 | reg_short |= (1 << 7) | (1 << 1) | (1 << 0); | |
577 | miiphy_write (dev->name, reg, 0x14, reg_short); | |
578 | #endif | |
579 | #if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ | |
580 | miiphy_write (dev->name, reg, 0x14, 0x0ce3); | |
581 | miiphy_write (dev->name, reg, 0x18, 0x4101); | |
582 | miiphy_write (dev->name, reg, 0x09, 0x0e00); | |
583 | miiphy_write (dev->name, reg, 0x04, 0x01e1); | |
584 | #endif | |
63ff004c | 585 | miiphy_reset (dev->name, reg); |
ba56f625 | 586 | |
887e2ec9 SR |
587 | #if defined(CONFIG_440GX) || \ |
588 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
589 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
590 | ||
0e6d798c | 591 | #if defined(CONFIG_CIS8201_PHY) |
fc1cfcdb | 592 | /* |
17f50f22 SR |
593 | * Cicada 8201 PHY needs to have an extended register whacked |
594 | * for RGMII mode. | |
fc1cfcdb | 595 | */ |
887e2ec9 | 596 | if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { |
b79316f2 | 597 | #if defined(CONFIG_CIS8201_SHORT_ETCH) |
63ff004c | 598 | miiphy_write (dev->name, reg, 23, 0x1300); |
b79316f2 | 599 | #else |
63ff004c | 600 | miiphy_write (dev->name, reg, 23, 0x1000); |
b79316f2 | 601 | #endif |
17f50f22 SR |
602 | /* |
603 | * Vitesse VSC8201/Cicada CIS8201 errata: | |
604 | * Interoperability problem with Intel 82547EI phys | |
605 | * This work around (provided by Vitesse) changes | |
606 | * the default timer convergence from 8ms to 12ms | |
607 | */ | |
63ff004c MB |
608 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); |
609 | miiphy_write (dev->name, reg, 0x08, 0x0200); | |
610 | miiphy_write (dev->name, reg, 0x1f, 0x52b5); | |
611 | miiphy_write (dev->name, reg, 0x02, 0x0004); | |
612 | miiphy_write (dev->name, reg, 0x01, 0x0671); | |
613 | miiphy_write (dev->name, reg, 0x00, 0x8fae); | |
614 | miiphy_write (dev->name, reg, 0x1f, 0x2a30); | |
615 | miiphy_write (dev->name, reg, 0x08, 0x0000); | |
616 | miiphy_write (dev->name, reg, 0x1f, 0x0000); | |
17f50f22 SR |
617 | /* end Vitesse/Cicada errata */ |
618 | } | |
0e6d798c | 619 | #endif |
855a496f | 620 | #endif |
a06752e3 | 621 | /* Start/Restart autonegotiation */ |
63ff004c | 622 | phy_setup_aneg (dev->name, reg); |
a06752e3 WD |
623 | udelay (1000); |
624 | } | |
d6c61aab | 625 | #endif /* defined(CONFIG_PHY_RESET) */ |
ba56f625 | 626 | |
63ff004c | 627 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
628 | |
629 | /* | |
0e6d798c | 630 | * Wait if PHY is capable of autonegotiation and autonegotiation is not complete |
ba56f625 WD |
631 | */ |
632 | if ((reg_short & PHY_BMSR_AUTN_ABLE) | |
633 | && !(reg_short & PHY_BMSR_AUTN_COMP)) { | |
634 | puts ("Waiting for PHY auto negotiation to complete"); | |
635 | i = 0; | |
636 | while (!(reg_short & PHY_BMSR_AUTN_COMP)) { | |
637 | /* | |
638 | * Timeout reached ? | |
639 | */ | |
640 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { | |
641 | puts (" TIMEOUT !\n"); | |
642 | break; | |
643 | } | |
644 | ||
645 | if ((i++ % 1000) == 0) { | |
646 | putc ('.'); | |
647 | } | |
648 | udelay (1000); /* 1 ms */ | |
63ff004c | 649 | miiphy_read (dev->name, reg, PHY_BMSR, ®_short); |
ba56f625 WD |
650 | |
651 | } | |
652 | puts (" done\n"); | |
653 | udelay (500000); /* another 500 ms (results in faster booting) */ | |
654 | } | |
d6c61aab SR |
655 | #endif /* #ifndef CONFIG_CS8952_PHY */ |
656 | ||
63ff004c MB |
657 | speed = miiphy_speed (dev->name, reg); |
658 | duplex = miiphy_duplex (dev->name, reg); | |
ba56f625 WD |
659 | |
660 | if (hw_p->print_speed) { | |
661 | hw_p->print_speed = 0; | |
662 | printf ("ENET Speed is %d Mbps - %s duplex connection\n", | |
663 | (int) speed, (duplex == HALF) ? "HALF" : "FULL"); | |
664 | } | |
665 | ||
887e2ec9 SR |
666 | #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ |
667 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) | |
846b0dd2 | 668 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
669 | mfsdr(sdr_mfr, reg); |
670 | if (speed == 100) { | |
671 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; | |
672 | } else { | |
673 | reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; | |
674 | } | |
675 | mtsdr(sdr_mfr, reg); | |
676 | #endif | |
c57c7980 | 677 | |
ba56f625 WD |
678 | /* Set ZMII/RGMII speed according to the phy link speed */ |
679 | reg = in32 (ZMII_SSR); | |
855a496f | 680 | if ( (speed == 100) || (speed == 1000) ) |
ba56f625 WD |
681 | out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
682 | else | |
c57c7980 | 683 | out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
ba56f625 WD |
684 | |
685 | if ((devnum == 2) || (devnum == 3)) { | |
686 | if (speed == 1000) | |
687 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
688 | else if (speed == 100) | |
689 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
887e2ec9 | 690 | else if (speed == 10) |
ba56f625 | 691 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); |
887e2ec9 SR |
692 | else { |
693 | printf("Error in RGMII Speed\n"); | |
694 | return -1; | |
695 | } | |
ba56f625 WD |
696 | out32 (RGMII_SSR, reg); |
697 | } | |
6e7fb6ea | 698 | #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
ba56f625 | 699 | |
887e2ec9 SR |
700 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
701 | if (speed == 1000) | |
702 | reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); | |
703 | else if (speed == 100) | |
704 | reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); | |
705 | else if (speed == 10) | |
706 | reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); | |
707 | else { | |
708 | printf("Error in RGMII Speed\n"); | |
709 | return -1; | |
710 | } | |
711 | out32 (RGMII_SSR, reg); | |
712 | #endif | |
713 | ||
ba56f625 | 714 | /* set the Mal configuration reg */ |
887e2ec9 SR |
715 | #if defined(CONFIG_440GX) || \ |
716 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ | |
717 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) | |
17f50f22 SR |
718 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | |
719 | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); | |
720 | #else | |
721 | mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); | |
ba56f625 | 722 | /* Errata 1.12: MAL_1 -- Disable MAL bursting */ |
17f50f22 SR |
723 | if (get_pvr() == PVR_440GP_RB) { |
724 | mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); | |
725 | } | |
726 | #endif | |
ba56f625 WD |
727 | |
728 | /* Free "old" buffers */ | |
729 | if (hw_p->alloc_tx_buf) | |
730 | free (hw_p->alloc_tx_buf); | |
731 | if (hw_p->alloc_rx_buf) | |
732 | free (hw_p->alloc_rx_buf); | |
733 | ||
734 | /* | |
735 | * Malloc MAL buffer desciptors, make sure they are | |
736 | * aligned on cache line boundary size | |
737 | * (401/403/IOP480 = 16, 405 = 32) | |
738 | * and doesn't cross cache block boundaries. | |
739 | */ | |
740 | hw_p->alloc_tx_buf = | |
741 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + | |
742 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
b79316f2 SR |
743 | if (NULL == hw_p->alloc_tx_buf) |
744 | return -1; | |
ba56f625 WD |
745 | if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { |
746 | hw_p->tx = | |
747 | (mal_desc_t *) ((int) hw_p->alloc_tx_buf + | |
748 | CFG_CACHELINE_SIZE - | |
749 | ((int) hw_p-> | |
750 | alloc_tx_buf & CACHELINE_MASK)); | |
751 | } else { | |
752 | hw_p->tx = hw_p->alloc_tx_buf; | |
753 | } | |
754 | ||
755 | hw_p->alloc_rx_buf = | |
756 | (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + | |
757 | ((2 * CFG_CACHELINE_SIZE) - 2)); | |
b79316f2 SR |
758 | if (NULL == hw_p->alloc_rx_buf) { |
759 | free(hw_p->alloc_tx_buf); | |
760 | hw_p->alloc_tx_buf = NULL; | |
761 | return -1; | |
762 | } | |
763 | ||
ba56f625 WD |
764 | if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { |
765 | hw_p->rx = | |
766 | (mal_desc_t *) ((int) hw_p->alloc_rx_buf + | |
767 | CFG_CACHELINE_SIZE - | |
768 | ((int) hw_p-> | |
769 | alloc_rx_buf & CACHELINE_MASK)); | |
770 | } else { | |
771 | hw_p->rx = hw_p->alloc_rx_buf; | |
772 | } | |
773 | ||
774 | for (i = 0; i < NUM_TX_BUFF; i++) { | |
775 | hw_p->tx[i].ctrl = 0; | |
776 | hw_p->tx[i].data_len = 0; | |
b79316f2 | 777 | if (hw_p->first_init == 0) { |
ba56f625 WD |
778 | hw_p->txbuf_ptr = |
779 | (char *) malloc (ENET_MAX_MTU_ALIGNED); | |
b79316f2 SR |
780 | if (NULL == hw_p->txbuf_ptr) { |
781 | free(hw_p->alloc_rx_buf); | |
782 | free(hw_p->alloc_tx_buf); | |
783 | hw_p->alloc_rx_buf = NULL; | |
784 | hw_p->alloc_tx_buf = NULL; | |
785 | for(j = 0; j < i; j++) { | |
786 | free(hw_p->tx[i].data_ptr); | |
787 | hw_p->tx[i].data_ptr = NULL; | |
788 | } | |
789 | } | |
790 | } | |
ba56f625 WD |
791 | hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; |
792 | if ((NUM_TX_BUFF - 1) == i) | |
793 | hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; | |
794 | hw_p->tx_run[i] = -1; | |
795 | #if 0 | |
796 | printf ("TX_BUFF %d @ 0x%08lx\n", i, | |
797 | (ulong) hw_p->tx[i].data_ptr); | |
798 | #endif | |
799 | } | |
800 | ||
801 | for (i = 0; i < NUM_RX_BUFF; i++) { | |
802 | hw_p->rx[i].ctrl = 0; | |
803 | hw_p->rx[i].data_len = 0; | |
265817c7 | 804 | /* rx[i].data_ptr = (char *) &rx_buff[i]; */ |
ba56f625 WD |
805 | hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; |
806 | if ((NUM_RX_BUFF - 1) == i) | |
807 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; | |
808 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; | |
809 | hw_p->rx_ready[i] = -1; | |
810 | #if 0 | |
811 | printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); | |
812 | #endif | |
813 | } | |
814 | ||
815 | reg = 0x00000000; | |
816 | ||
817 | reg |= dev->enetaddr[0]; /* set high address */ | |
818 | reg = reg << 8; | |
819 | reg |= dev->enetaddr[1]; | |
820 | ||
821 | out32 (EMAC_IAH + hw_p->hw_addr, reg); | |
822 | ||
823 | reg = 0x00000000; | |
824 | reg |= dev->enetaddr[2]; /* set low address */ | |
825 | reg = reg << 8; | |
826 | reg |= dev->enetaddr[3]; | |
827 | reg = reg << 8; | |
828 | reg |= dev->enetaddr[4]; | |
829 | reg = reg << 8; | |
830 | reg |= dev->enetaddr[5]; | |
831 | ||
832 | out32 (EMAC_IAL + hw_p->hw_addr, reg); | |
833 | ||
834 | switch (devnum) { | |
835 | case 1: | |
836 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 837 | #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) |
c157d8e2 SR |
838 | mtdcr (maltxctp2r, hw_p->tx); |
839 | #else | |
ba56f625 | 840 | mtdcr (maltxctp1r, hw_p->tx); |
c157d8e2 | 841 | #endif |
d6c61aab | 842 | #if defined(CONFIG_440) |
c157d8e2 | 843 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 844 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 845 | #endif |
ba56f625 WD |
846 | mtdcr (malrxctp1r, hw_p->rx); |
847 | /* set RX buffer size */ | |
848 | mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); | |
849 | break; | |
846b0dd2 | 850 | #if defined (CONFIG_440GX) |
ba56f625 WD |
851 | case 2: |
852 | /* setup MAL tx & rx channel pointers */ | |
853 | mtdcr (maltxbattr, 0x0); | |
ba56f625 | 854 | mtdcr (malrxbattr, 0x0); |
d6c61aab | 855 | mtdcr (maltxctp2r, hw_p->tx); |
ba56f625 WD |
856 | mtdcr (malrxctp2r, hw_p->rx); |
857 | /* set RX buffer size */ | |
858 | mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); | |
859 | break; | |
860 | case 3: | |
861 | /* setup MAL tx & rx channel pointers */ | |
862 | mtdcr (maltxbattr, 0x0); | |
863 | mtdcr (maltxctp3r, hw_p->tx); | |
864 | mtdcr (malrxbattr, 0x0); | |
865 | mtdcr (malrxctp3r, hw_p->rx); | |
866 | /* set RX buffer size */ | |
867 | mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); | |
868 | break; | |
c57c7980 | 869 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
870 | case 0: |
871 | default: | |
872 | /* setup MAL tx & rx channel pointers */ | |
d6c61aab | 873 | #if defined(CONFIG_440) |
ba56f625 | 874 | mtdcr (maltxbattr, 0x0); |
ba56f625 | 875 | mtdcr (malrxbattr, 0x0); |
d6c61aab SR |
876 | #endif |
877 | mtdcr (maltxctp0r, hw_p->tx); | |
ba56f625 WD |
878 | mtdcr (malrxctp0r, hw_p->rx); |
879 | /* set RX buffer size */ | |
880 | mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); | |
881 | break; | |
882 | } | |
883 | ||
884 | /* Enable MAL transmit and receive channels */ | |
d6c61aab | 885 | #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) |
c157d8e2 SR |
886 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); |
887 | #else | |
ba56f625 | 888 | mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
c157d8e2 | 889 | #endif |
ba56f625 WD |
890 | mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
891 | ||
892 | /* set transmit enable & receive enable */ | |
893 | out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); | |
894 | ||
895 | /* set receive fifo to 4k and tx fifo to 2k */ | |
896 | mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); | |
897 | mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; | |
898 | ||
899 | /* set speed */ | |
6e7fb6ea | 900 | if (speed == _1000BASET) { |
887e2ec9 SR |
901 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
902 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
6e7fb6ea | 903 | unsigned long pfc1; |
887e2ec9 | 904 | |
6e7fb6ea SR |
905 | mfsdr (sdr_pfc1, pfc1); |
906 | pfc1 |= SDR0_PFC1_EM_1000; | |
907 | mtsdr (sdr_pfc1, pfc1); | |
908 | #endif | |
855a496f | 909 | mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; |
6e7fb6ea | 910 | } else if (speed == _100BASET) |
ba56f625 WD |
911 | mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; |
912 | else | |
913 | mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ | |
914 | if (duplex == FULL) | |
915 | mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; | |
916 | ||
917 | out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); | |
918 | ||
919 | /* Enable broadcast and indvidual address */ | |
920 | /* TBS: enabling runts as some misbehaved nics will send runts */ | |
921 | out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); | |
922 | ||
923 | /* we probably need to set the tx mode1 reg? maybe at tx time */ | |
924 | ||
925 | /* set transmit request threshold register */ | |
926 | out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ | |
927 | ||
265817c7 | 928 | /* set receive low/high water mark register */ |
d6c61aab | 929 | #if defined(CONFIG_440) |
6c5879f3 | 930 | /* 440s has a 64 byte burst length */ |
ba56f625 | 931 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
d6c61aab SR |
932 | #else |
933 | /* 405s have a 16 byte burst length */ | |
934 | out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); | |
935 | #endif /* defined(CONFIG_440) */ | |
ba56f625 WD |
936 | out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
937 | ||
938 | /* Set fifo limit entry in tx mode 0 */ | |
939 | out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); | |
940 | /* Frame gap set */ | |
941 | out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); | |
942 | ||
943 | /* Set EMAC IER */ | |
d6c61aab | 944 | hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
ba56f625 WD |
945 | if (speed == _100BASET) |
946 | hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; | |
947 | ||
948 | out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ | |
949 | out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); | |
950 | ||
951 | if (hw_p->first_init == 0) { | |
952 | /* | |
953 | * Connect interrupt service routines | |
954 | */ | |
ba56f625 WD |
955 | irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), |
956 | (interrupt_handler_t *) enetInt, dev); | |
957 | } | |
ba56f625 WD |
958 | |
959 | mtmsr (msr); /* enable interrupts again */ | |
960 | ||
961 | hw_p->bis = bis; | |
962 | hw_p->first_init = 1; | |
963 | ||
964 | return (1); | |
965 | } | |
966 | ||
967 | ||
d6c61aab | 968 | static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
ba56f625 WD |
969 | int len) |
970 | { | |
971 | struct enet_frame *ef_ptr; | |
972 | ulong time_start, time_now; | |
973 | unsigned long temp_txm0; | |
d6c61aab | 974 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
975 | |
976 | ef_ptr = (struct enet_frame *) ptr; | |
977 | ||
978 | /*-----------------------------------------------------------------------+ | |
979 | * Copy in our address into the frame. | |
980 | *-----------------------------------------------------------------------*/ | |
981 | (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); | |
982 | ||
983 | /*-----------------------------------------------------------------------+ | |
984 | * If frame is too long or too short, modify length. | |
985 | *-----------------------------------------------------------------------*/ | |
986 | /* TBS: where does the fragment go???? */ | |
987 | if (len > ENET_MAX_MTU) | |
988 | len = ENET_MAX_MTU; | |
989 | ||
990 | /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ | |
991 | memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); | |
992 | ||
993 | /*-----------------------------------------------------------------------+ | |
994 | * set TX Buffer busy, and send it | |
995 | *-----------------------------------------------------------------------*/ | |
996 | hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | | |
997 | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & | |
998 | ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); | |
999 | if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) | |
1000 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; | |
1001 | ||
1002 | hw_p->tx[hw_p->tx_slot].data_len = (short) len; | |
1003 | hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; | |
1004 | ||
1005 | __asm__ volatile ("eieio"); | |
1006 | ||
1007 | out32 (EMAC_TXM0 + hw_p->hw_addr, | |
1008 | in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); | |
d6c61aab | 1009 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1010 | hw_p->stats.pkts_tx++; |
1011 | #endif | |
1012 | ||
1013 | /*-----------------------------------------------------------------------+ | |
1014 | * poll unitl the packet is sent and then make sure it is OK | |
1015 | *-----------------------------------------------------------------------*/ | |
1016 | time_start = get_timer (0); | |
1017 | while (1) { | |
1018 | temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); | |
1019 | /* loop until either TINT turns on or 3 seconds elapse */ | |
1020 | if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { | |
1021 | /* transmit is done, so now check for errors | |
1022 | * If there is an error, an interrupt should | |
1023 | * happen when we return | |
1024 | */ | |
1025 | time_now = get_timer (0); | |
1026 | if ((time_now - time_start) > 3000) { | |
1027 | return (-1); | |
1028 | } | |
1029 | } else { | |
1030 | return (len); | |
1031 | } | |
1032 | } | |
1033 | } | |
1034 | ||
6e7fb6ea | 1035 | |
d6c61aab | 1036 | #if defined (CONFIG_440) |
ba56f625 | 1037 | |
6c5879f3 | 1038 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
6e7fb6ea SR |
1039 | /* |
1040 | * Hack: On 440SP all enet irq sources are located on UIC1 | |
1041 | * Needs some cleanup. --sr | |
1042 | */ | |
1043 | #define UIC0MSR uic1msr | |
1044 | #define UIC0SR uic1sr | |
1045 | #else | |
1046 | #define UIC0MSR uic0msr | |
1047 | #define UIC0SR uic0sr | |
1048 | #endif | |
1049 | ||
887e2ec9 SR |
1050 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
1051 | #define UICMSR_ETHX uic0msr | |
1052 | #define UICSR_ETHX uic0sr | |
1053 | #else | |
1054 | #define UICMSR_ETHX uic1msr | |
1055 | #define UICSR_ETHX uic1sr | |
1056 | #endif | |
1057 | ||
ba56f625 WD |
1058 | int enetInt (struct eth_device *dev) |
1059 | { | |
1060 | int serviced; | |
1061 | int rc = -1; /* default to not us */ | |
1062 | unsigned long mal_isr; | |
1063 | unsigned long emac_isr = 0; | |
1064 | unsigned long mal_rx_eob; | |
1065 | unsigned long my_uic0msr, my_uic1msr; | |
887e2ec9 | 1066 | unsigned long my_uicmsr_ethx; |
ba56f625 | 1067 | |
846b0dd2 | 1068 | #if defined(CONFIG_440GX) |
ba56f625 WD |
1069 | unsigned long my_uic2msr; |
1070 | #endif | |
d6c61aab | 1071 | EMAC_4XX_HW_PST hw_p; |
ba56f625 WD |
1072 | |
1073 | /* | |
1074 | * Because the mal is generic, we need to get the current | |
1075 | * eth device | |
1076 | */ | |
d6c61aab SR |
1077 | #if defined(CONFIG_NET_MULTI) |
1078 | dev = eth_get_dev(); | |
1079 | #else | |
1080 | dev = emac0_dev; | |
1081 | #endif | |
ba56f625 WD |
1082 | |
1083 | hw_p = dev->priv; | |
1084 | ||
ba56f625 WD |
1085 | /* enter loop that stays in interrupt code until nothing to service */ |
1086 | do { | |
1087 | serviced = 0; | |
1088 | ||
6e7fb6ea | 1089 | my_uic0msr = mfdcr (UIC0MSR); |
ba56f625 | 1090 | my_uic1msr = mfdcr (uic1msr); |
846b0dd2 | 1091 | #if defined(CONFIG_440GX) |
ba56f625 WD |
1092 | my_uic2msr = mfdcr (uic2msr); |
1093 | #endif | |
887e2ec9 SR |
1094 | my_uicmsr_ethx = mfdcr (UICMSR_ETHX); |
1095 | ||
ba56f625 | 1096 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
887e2ec9 SR |
1097 | && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) |
1098 | && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { | |
ba56f625 WD |
1099 | /* not for us */ |
1100 | return (rc); | |
1101 | } | |
846b0dd2 | 1102 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1103 | if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) |
1104 | && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { | |
1105 | /* not for us */ | |
1106 | return (rc); | |
1107 | } | |
1108 | #endif | |
1109 | /* get and clear controller status interrupts */ | |
1110 | /* look at Mal and EMAC interrupts */ | |
1111 | if ((my_uic0msr & (UIC_MRE | UIC_MTE)) | |
1112 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
1113 | /* we have a MAL interrupt */ | |
1114 | mal_isr = mfdcr (malesr); | |
1115 | /* look for mal error */ | |
1116 | if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { | |
887e2ec9 | 1117 | mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); |
ba56f625 WD |
1118 | serviced = 1; |
1119 | rc = 0; | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | /* port by port dispatch of emac interrupts */ | |
1124 | if (hw_p->devnum == 0) { | |
887e2ec9 | 1125 | if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ |
ba56f625 WD |
1126 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
1127 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1128 | emac_err (dev, emac_isr); | |
1129 | serviced = 1; | |
1130 | rc = 0; | |
1131 | } | |
1132 | } | |
1133 | if ((hw_p->emac_ier & emac_isr) | |
1134 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1135 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
887e2ec9 SR |
1136 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1137 | mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ | |
ba56f625 WD |
1138 | return (rc); /* we had errors so get out */ |
1139 | } | |
1140 | } | |
1141 | ||
6e7fb6ea | 1142 | #if !defined(CONFIG_440SP) |
ba56f625 | 1143 | if (hw_p->devnum == 1) { |
887e2ec9 | 1144 | if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ |
ba56f625 WD |
1145 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
1146 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1147 | emac_err (dev, emac_isr); | |
1148 | serviced = 1; | |
1149 | rc = 0; | |
1150 | } | |
1151 | } | |
1152 | if ((hw_p->emac_ier & emac_isr) | |
1153 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1154 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
887e2ec9 SR |
1155 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1156 | mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ | |
ba56f625 WD |
1157 | return (rc); /* we had errors so get out */ |
1158 | } | |
1159 | } | |
846b0dd2 | 1160 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1161 | if (hw_p->devnum == 2) { |
1162 | if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ | |
1163 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1164 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1165 | emac_err (dev, emac_isr); | |
1166 | serviced = 1; | |
1167 | rc = 0; | |
1168 | } | |
1169 | } | |
1170 | if ((hw_p->emac_ier & emac_isr) | |
1171 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1172 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
ba56f625 WD |
1173 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1174 | mtdcr (uic2sr, UIC_ETH2); | |
1175 | return (rc); /* we had errors so get out */ | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | if (hw_p->devnum == 3) { | |
1180 | if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ | |
1181 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1182 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1183 | emac_err (dev, emac_isr); | |
1184 | serviced = 1; | |
1185 | rc = 0; | |
1186 | } | |
1187 | } | |
1188 | if ((hw_p->emac_ier & emac_isr) | |
1189 | || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { | |
6e7fb6ea | 1190 | mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ |
ba56f625 WD |
1191 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1192 | mtdcr (uic2sr, UIC_ETH3); | |
1193 | return (rc); /* we had errors so get out */ | |
1194 | } | |
1195 | } | |
846b0dd2 | 1196 | #endif /* CONFIG_440GX */ |
6e7fb6ea SR |
1197 | #endif /* !CONFIG_440SP */ |
1198 | ||
ba56f625 WD |
1199 | /* handle MAX TX EOB interrupt from a tx */ |
1200 | if (my_uic0msr & UIC_MTE) { | |
1201 | mal_rx_eob = mfdcr (maltxeobisr); | |
1202 | mtdcr (maltxeobisr, mal_rx_eob); | |
6e7fb6ea | 1203 | mtdcr (UIC0SR, UIC_MTE); |
ba56f625 WD |
1204 | } |
1205 | /* handle MAL RX EOB interupt from a receive */ | |
fc1cfcdb | 1206 | /* check for EOB on valid channels */ |
ba56f625 WD |
1207 | if (my_uic0msr & UIC_MRE) { |
1208 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1209 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
ba56f625 WD |
1210 | /* clear EOB |
1211 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1212 | enet_rcv (dev, emac_isr); | |
1213 | /* indicate that we serviced an interrupt */ | |
1214 | serviced = 1; | |
1215 | rc = 0; | |
1216 | } | |
1217 | } | |
6e7fb6ea SR |
1218 | |
1219 | mtdcr (UIC0SR, UIC_MRE); /* Clear */ | |
ba56f625 WD |
1220 | mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ |
1221 | switch (hw_p->devnum) { | |
1222 | case 0: | |
887e2ec9 | 1223 | mtdcr (UICSR_ETHX, UIC_ETH0); |
ba56f625 WD |
1224 | break; |
1225 | case 1: | |
887e2ec9 | 1226 | mtdcr (UICSR_ETHX, UIC_ETH1); |
ba56f625 | 1227 | break; |
846b0dd2 | 1228 | #if defined (CONFIG_440GX) |
ba56f625 WD |
1229 | case 2: |
1230 | mtdcr (uic2sr, UIC_ETH2); | |
1231 | break; | |
1232 | case 3: | |
1233 | mtdcr (uic2sr, UIC_ETH3); | |
1234 | break; | |
846b0dd2 | 1235 | #endif /* CONFIG_440GX */ |
ba56f625 WD |
1236 | default: |
1237 | break; | |
1238 | } | |
1239 | } while (serviced); | |
1240 | ||
1241 | return (rc); | |
1242 | } | |
1243 | ||
d6c61aab SR |
1244 | #else /* CONFIG_440 */ |
1245 | ||
1246 | int enetInt (struct eth_device *dev) | |
1247 | { | |
1248 | int serviced; | |
1249 | int rc = -1; /* default to not us */ | |
1250 | unsigned long mal_isr; | |
1251 | unsigned long emac_isr = 0; | |
1252 | unsigned long mal_rx_eob; | |
1253 | unsigned long my_uicmsr; | |
1254 | ||
1255 | EMAC_4XX_HW_PST hw_p; | |
1256 | ||
1257 | /* | |
1258 | * Because the mal is generic, we need to get the current | |
1259 | * eth device | |
1260 | */ | |
1261 | #if defined(CONFIG_NET_MULTI) | |
1262 | dev = eth_get_dev(); | |
1263 | #else | |
1264 | dev = emac0_dev; | |
1265 | #endif | |
1266 | ||
1267 | hw_p = dev->priv; | |
1268 | ||
1269 | /* enter loop that stays in interrupt code until nothing to service */ | |
1270 | do { | |
1271 | serviced = 0; | |
1272 | ||
1273 | my_uicmsr = mfdcr (uicmsr); | |
1274 | ||
1275 | if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */ | |
1276 | return (rc); | |
1277 | } | |
1278 | /* get and clear controller status interrupts */ | |
1279 | /* look at Mal and EMAC interrupts */ | |
1280 | if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */ | |
1281 | mal_isr = mfdcr (malesr); | |
1282 | /* look for mal error */ | |
1283 | if ((my_uicmsr & MAL_UIC_ERR) != 0) { | |
1284 | mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR); | |
1285 | serviced = 1; | |
1286 | rc = 0; | |
1287 | } | |
1288 | } | |
1289 | ||
1290 | /* port by port dispatch of emac interrupts */ | |
1291 | ||
1292 | if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ | |
1293 | emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); | |
1294 | if ((hw_p->emac_ier & emac_isr) != 0) { | |
1295 | emac_err (dev, emac_isr); | |
1296 | serviced = 1; | |
1297 | rc = 0; | |
1298 | } | |
1299 | } | |
1300 | if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) { | |
1301 | mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */ | |
1302 | return (rc); /* we had errors so get out */ | |
1303 | } | |
1304 | ||
1305 | /* handle MAX TX EOB interrupt from a tx */ | |
1306 | if (my_uicmsr & UIC_MAL_TXEOB) { | |
1307 | mal_rx_eob = mfdcr (maltxeobisr); | |
1308 | mtdcr (maltxeobisr, mal_rx_eob); | |
1309 | mtdcr (uicsr, UIC_MAL_TXEOB); | |
1310 | } | |
1311 | /* handle MAL RX EOB interupt from a receive */ | |
1312 | /* check for EOB on valid channels */ | |
1313 | if (my_uicmsr & UIC_MAL_RXEOB) | |
1314 | { | |
1315 | mal_rx_eob = mfdcr (malrxeobisr); | |
265817c7 | 1316 | if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ |
d6c61aab SR |
1317 | /* clear EOB |
1318 | mtdcr(malrxeobisr, mal_rx_eob); */ | |
1319 | enet_rcv (dev, emac_isr); | |
1320 | /* indicate that we serviced an interrupt */ | |
1321 | serviced = 1; | |
1322 | rc = 0; | |
1323 | } | |
1324 | } | |
1325 | mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ | |
1326 | } | |
1327 | while (serviced); | |
1328 | ||
1329 | return (rc); | |
1330 | } | |
1331 | ||
1332 | #endif /* CONFIG_440 */ | |
1333 | ||
ba56f625 WD |
1334 | /*-----------------------------------------------------------------------------+ |
1335 | * MAL Error Routine | |
1336 | *-----------------------------------------------------------------------------*/ | |
1337 | static void mal_err (struct eth_device *dev, unsigned long isr, | |
1338 | unsigned long uic, unsigned long maldef, | |
1339 | unsigned long mal_errr) | |
1340 | { | |
d6c61aab | 1341 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1342 | |
1343 | mtdcr (malesr, isr); /* clear interrupt */ | |
1344 | ||
1345 | /* clear DE interrupt */ | |
1346 | mtdcr (maltxdeir, 0xC0000000); | |
1347 | mtdcr (malrxdeir, 0x80000000); | |
1348 | ||
d6c61aab | 1349 | #ifdef INFO_4XX_ENET |
265817c7 | 1350 | printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); |
ba56f625 WD |
1351 | #endif |
1352 | ||
1353 | eth_init (hw_p->bis); /* start again... */ | |
1354 | } | |
1355 | ||
1356 | /*-----------------------------------------------------------------------------+ | |
1357 | * EMAC Error Routine | |
1358 | *-----------------------------------------------------------------------------*/ | |
1359 | static void emac_err (struct eth_device *dev, unsigned long isr) | |
1360 | { | |
d6c61aab | 1361 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1362 | |
1363 | printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); | |
1364 | out32 (EMAC_ISR + hw_p->hw_addr, isr); | |
1365 | } | |
1366 | ||
1367 | /*-----------------------------------------------------------------------------+ | |
1368 | * enet_rcv() handles the ethernet receive data | |
1369 | *-----------------------------------------------------------------------------*/ | |
1370 | static void enet_rcv (struct eth_device *dev, unsigned long malisr) | |
1371 | { | |
1372 | struct enet_frame *ef_ptr; | |
1373 | unsigned long data_len; | |
1374 | unsigned long rx_eob_isr; | |
d6c61aab | 1375 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 WD |
1376 | |
1377 | int handled = 0; | |
1378 | int i; | |
1379 | int loop_count = 0; | |
1380 | ||
1381 | rx_eob_isr = mfdcr (malrxeobisr); | |
1382 | if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { | |
1383 | /* clear EOB */ | |
1384 | mtdcr (malrxeobisr, rx_eob_isr); | |
1385 | ||
1386 | /* EMAC RX done */ | |
1387 | while (1) { /* do all */ | |
1388 | i = hw_p->rx_slot; | |
1389 | ||
1390 | if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) | |
1391 | || (loop_count >= NUM_RX_BUFF)) | |
1392 | break; | |
1393 | loop_count++; | |
1394 | hw_p->rx_slot++; | |
1395 | if (NUM_RX_BUFF == hw_p->rx_slot) | |
1396 | hw_p->rx_slot = 0; | |
1397 | handled++; | |
1398 | data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ | |
1399 | if (data_len) { | |
1400 | if (data_len > ENET_MAX_MTU) /* Check len */ | |
1401 | data_len = 0; | |
1402 | else { | |
1403 | if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ | |
1404 | data_len = 0; | |
1405 | hw_p->stats.rx_err_log[hw_p-> | |
1406 | rx_err_index] | |
1407 | = hw_p->rx[i].ctrl; | |
1408 | hw_p->rx_err_index++; | |
1409 | if (hw_p->rx_err_index == | |
1410 | MAX_ERR_LOG) | |
1411 | hw_p->rx_err_index = | |
1412 | 0; | |
fc1cfcdb | 1413 | } /* emac_erros */ |
ba56f625 | 1414 | } /* data_len < max mtu */ |
fc1cfcdb | 1415 | } /* if data_len */ |
ba56f625 WD |
1416 | if (!data_len) { /* no data */ |
1417 | hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ | |
1418 | ||
1419 | hw_p->stats.data_len_err++; /* Error at Rx */ | |
1420 | } | |
1421 | ||
1422 | /* !data_len */ | |
1423 | /* AS.HARNOIS */ | |
1424 | /* Check if user has already eaten buffer */ | |
1425 | /* if not => ERROR */ | |
1426 | else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { | |
1427 | if (hw_p->is_receiving) | |
1428 | printf ("ERROR : Receive buffers are full!\n"); | |
1429 | break; | |
1430 | } else { | |
1431 | hw_p->stats.rx_frames++; | |
1432 | hw_p->stats.rx += data_len; | |
1433 | ef_ptr = (struct enet_frame *) hw_p->rx[i]. | |
1434 | data_ptr; | |
d6c61aab | 1435 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1436 | hw_p->stats.pkts_rx++; |
1437 | #endif | |
1438 | /* AS.HARNOIS | |
1439 | * use ring buffer | |
1440 | */ | |
1441 | hw_p->rx_ready[hw_p->rx_i_index] = i; | |
1442 | hw_p->rx_i_index++; | |
1443 | if (NUM_RX_BUFF == hw_p->rx_i_index) | |
1444 | hw_p->rx_i_index = 0; | |
1445 | ||
ba56f625 WD |
1446 | /* AS.HARNOIS |
1447 | * free receive buffer only when | |
1448 | * buffer has been handled (eth_rx) | |
1449 | rx[i].ctrl |= MAL_RX_CTRL_EMPTY; | |
1450 | */ | |
1451 | } /* if data_len */ | |
1452 | } /* while */ | |
1453 | } /* if EMACK_RXCHL */ | |
1454 | } | |
1455 | ||
1456 | ||
d6c61aab | 1457 | static int ppc_4xx_eth_rx (struct eth_device *dev) |
ba56f625 WD |
1458 | { |
1459 | int length; | |
1460 | int user_index; | |
1461 | unsigned long msr; | |
d6c61aab | 1462 | EMAC_4XX_HW_PST hw_p = dev->priv; |
ba56f625 | 1463 | |
265817c7 | 1464 | hw_p->is_receiving = 1; /* tell driver */ |
ba56f625 WD |
1465 | |
1466 | for (;;) { | |
1467 | /* AS.HARNOIS | |
1468 | * use ring buffer and | |
1469 | * get index from rx buffer desciptor queue | |
1470 | */ | |
1471 | user_index = hw_p->rx_ready[hw_p->rx_u_index]; | |
1472 | if (user_index == -1) { | |
1473 | length = -1; | |
1474 | break; /* nothing received - leave for() loop */ | |
1475 | } | |
1476 | ||
1477 | msr = mfmsr (); | |
1478 | mtmsr (msr & ~(MSR_EE)); | |
1479 | ||
1480 | length = hw_p->rx[user_index].data_len; | |
1481 | ||
1482 | /* Pass the packet up to the protocol layers. */ | |
265817c7 WD |
1483 | /* NetReceive(NetRxPackets[rxIdx], length - 4); */ |
1484 | /* NetReceive(NetRxPackets[i], length); */ | |
ba56f625 WD |
1485 | NetReceive (NetRxPackets[user_index], length - 4); |
1486 | /* Free Recv Buffer */ | |
1487 | hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; | |
1488 | /* Free rx buffer descriptor queue */ | |
1489 | hw_p->rx_ready[hw_p->rx_u_index] = -1; | |
1490 | hw_p->rx_u_index++; | |
1491 | if (NUM_RX_BUFF == hw_p->rx_u_index) | |
1492 | hw_p->rx_u_index = 0; | |
1493 | ||
d6c61aab | 1494 | #ifdef INFO_4XX_ENET |
ba56f625 WD |
1495 | hw_p->stats.pkts_handled++; |
1496 | #endif | |
1497 | ||
1498 | mtmsr (msr); /* Enable IRQ's */ | |
1499 | } | |
1500 | ||
265817c7 | 1501 | hw_p->is_receiving = 0; /* tell driver */ |
ba56f625 WD |
1502 | |
1503 | return length; | |
1504 | } | |
1505 | ||
d6c61aab | 1506 | int ppc_4xx_eth_initialize (bd_t * bis) |
ba56f625 WD |
1507 | { |
1508 | static int virgin = 0; | |
ba56f625 WD |
1509 | struct eth_device *dev; |
1510 | int eth_num = 0; | |
d6c61aab | 1511 | EMAC_4XX_HW_PST hw = NULL; |
ba56f625 | 1512 | |
846b0dd2 | 1513 | #if defined(CONFIG_440GX) |
c157d8e2 SR |
1514 | unsigned long pfc1; |
1515 | ||
ba56f625 WD |
1516 | mfsdr (sdr_pfc1, pfc1); |
1517 | pfc1 &= ~(0x01e00000); | |
1518 | pfc1 |= 0x01200000; | |
1519 | mtsdr (sdr_pfc1, pfc1); | |
c157d8e2 | 1520 | #endif |
3c74e32a WD |
1521 | /* set phy num and mode */ |
1522 | bis->bi_phynum[0] = CONFIG_PHY_ADDR; | |
6c5879f3 MB |
1523 | bis->bi_phymode[0] = 0; |
1524 | ||
c157d8e2 | 1525 | #if defined(CONFIG_PHY1_ADDR) |
3c74e32a | 1526 | bis->bi_phynum[1] = CONFIG_PHY1_ADDR; |
6c5879f3 | 1527 | bis->bi_phymode[1] = 0; |
c157d8e2 | 1528 | #endif |
846b0dd2 | 1529 | #if defined(CONFIG_440GX) |
3c74e32a WD |
1530 | bis->bi_phynum[2] = CONFIG_PHY2_ADDR; |
1531 | bis->bi_phynum[3] = CONFIG_PHY3_ADDR; | |
3c74e32a WD |
1532 | bis->bi_phymode[2] = 2; |
1533 | bis->bi_phymode[3] = 2; | |
ba56f625 | 1534 | |
d6c61aab | 1535 | ppc_4xx_eth_setup_bridge(0, bis); |
a06752e3 WD |
1536 | #endif |
1537 | ||
1e25f957 | 1538 | for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { |
ba56f625 WD |
1539 | |
1540 | /* See if we can actually bring up the interface, otherwise, skip it */ | |
1541 | switch (eth_num) { | |
e2ffd59b | 1542 | default: /* fall through */ |
ba56f625 | 1543 | case 0: |
3c74e32a WD |
1544 | if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { |
1545 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1546 | continue; |
3c74e32a | 1547 | } |
ba56f625 | 1548 | break; |
e2ffd59b | 1549 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 | 1550 | case 1: |
3c74e32a WD |
1551 | if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { |
1552 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1553 | continue; |
3c74e32a | 1554 | } |
ba56f625 | 1555 | break; |
e2ffd59b WD |
1556 | #endif |
1557 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 | 1558 | case 2: |
3c74e32a WD |
1559 | if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { |
1560 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1561 | continue; |
3c74e32a | 1562 | } |
ba56f625 | 1563 | break; |
e2ffd59b WD |
1564 | #endif |
1565 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 | 1566 | case 3: |
3c74e32a WD |
1567 | if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { |
1568 | bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; | |
ba56f625 | 1569 | continue; |
3c74e32a | 1570 | } |
ba56f625 | 1571 | break; |
e2ffd59b | 1572 | #endif |
ba56f625 WD |
1573 | } |
1574 | ||
1575 | /* Allocate device structure */ | |
1576 | dev = (struct eth_device *) malloc (sizeof (*dev)); | |
1577 | if (dev == NULL) { | |
d6c61aab | 1578 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 1579 | "Cannot allocate eth_device %d\n", eth_num); |
ba56f625 WD |
1580 | return (-1); |
1581 | } | |
b2532eff | 1582 | memset(dev, 0, sizeof(*dev)); |
ba56f625 WD |
1583 | |
1584 | /* Allocate our private use data */ | |
d6c61aab | 1585 | hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); |
ba56f625 | 1586 | if (hw == NULL) { |
d6c61aab | 1587 | printf ("ppc_4xx_eth_initialize: " |
3f85ce27 | 1588 | "Cannot allocate private hw data for eth_device %d", |
ba56f625 WD |
1589 | eth_num); |
1590 | free (dev); | |
1591 | return (-1); | |
1592 | } | |
b2532eff | 1593 | memset(hw, 0, sizeof(*hw)); |
ba56f625 WD |
1594 | |
1595 | switch (eth_num) { | |
e2ffd59b | 1596 | default: /* fall through */ |
ba56f625 WD |
1597 | case 0: |
1598 | hw->hw_addr = 0; | |
1599 | memcpy (dev->enetaddr, bis->bi_enetaddr, 6); | |
1600 | break; | |
e2ffd59b | 1601 | #ifdef CONFIG_HAS_ETH1 |
ba56f625 WD |
1602 | case 1: |
1603 | hw->hw_addr = 0x100; | |
1604 | memcpy (dev->enetaddr, bis->bi_enet1addr, 6); | |
1605 | break; | |
e2ffd59b WD |
1606 | #endif |
1607 | #ifdef CONFIG_HAS_ETH2 | |
ba56f625 WD |
1608 | case 2: |
1609 | hw->hw_addr = 0x400; | |
1610 | memcpy (dev->enetaddr, bis->bi_enet2addr, 6); | |
1611 | break; | |
e2ffd59b WD |
1612 | #endif |
1613 | #ifdef CONFIG_HAS_ETH3 | |
ba56f625 WD |
1614 | case 3: |
1615 | hw->hw_addr = 0x600; | |
1616 | memcpy (dev->enetaddr, bis->bi_enet3addr, 6); | |
1617 | break; | |
e2ffd59b | 1618 | #endif |
ba56f625 WD |
1619 | } |
1620 | ||
1621 | hw->devnum = eth_num; | |
c157d8e2 | 1622 | hw->print_speed = 1; |
ba56f625 | 1623 | |
d6c61aab | 1624 | sprintf (dev->name, "ppc_4xx_eth%d", eth_num); |
ba56f625 | 1625 | dev->priv = (void *) hw; |
d6c61aab SR |
1626 | dev->init = ppc_4xx_eth_init; |
1627 | dev->halt = ppc_4xx_eth_halt; | |
1628 | dev->send = ppc_4xx_eth_send; | |
1629 | dev->recv = ppc_4xx_eth_rx; | |
ba56f625 WD |
1630 | |
1631 | if (0 == virgin) { | |
1632 | /* set the MAL IER ??? names may change with new spec ??? */ | |
887e2ec9 | 1633 | #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
6c5879f3 MB |
1634 | mal_ier = |
1635 | MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | | |
1636 | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; | |
1637 | #else | |
ba56f625 WD |
1638 | mal_ier = |
1639 | MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | | |
1640 | MAL_IER_OPBE | MAL_IER_PLBE; | |
6c5879f3 | 1641 | #endif |
ba56f625 WD |
1642 | mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ |
1643 | mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ | |
1644 | mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ | |
1645 | mtdcr (malier, mal_ier); | |
1646 | ||
1647 | /* install MAL interrupt handler */ | |
1648 | irq_install_handler (VECNUM_MS, | |
1649 | (interrupt_handler_t *) enetInt, | |
1650 | dev); | |
1651 | irq_install_handler (VECNUM_MTE, | |
1652 | (interrupt_handler_t *) enetInt, | |
1653 | dev); | |
1654 | irq_install_handler (VECNUM_MRE, | |
1655 | (interrupt_handler_t *) enetInt, | |
1656 | dev); | |
1657 | irq_install_handler (VECNUM_TXDE, | |
1658 | (interrupt_handler_t *) enetInt, | |
1659 | dev); | |
1660 | irq_install_handler (VECNUM_RXDE, | |
1661 | (interrupt_handler_t *) enetInt, | |
1662 | dev); | |
1663 | virgin = 1; | |
1664 | } | |
1665 | ||
d6c61aab | 1666 | #if defined(CONFIG_NET_MULTI) |
ba56f625 | 1667 | eth_register (dev); |
d6c61aab SR |
1668 | #else |
1669 | emac0_dev = dev; | |
1670 | #endif | |
6c5879f3 MB |
1671 | |
1672 | #if defined(CONFIG_NET_MULTI) | |
63ff004c MB |
1673 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) |
1674 | miiphy_register (dev->name, | |
6e7fb6ea | 1675 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c | 1676 | #endif |
6c5879f3 | 1677 | #endif |
ba56f625 WD |
1678 | } /* end for each supported device */ |
1679 | return (1); | |
1680 | } | |
d6c61aab SR |
1681 | |
1682 | ||
1683 | #if !defined(CONFIG_NET_MULTI) | |
1684 | void eth_halt (void) { | |
1685 | if (emac0_dev) { | |
1686 | ppc_4xx_eth_halt(emac0_dev); | |
1687 | free(emac0_dev); | |
1688 | emac0_dev = NULL; | |
1689 | } | |
1690 | } | |
1691 | ||
1692 | int eth_init (bd_t *bis) | |
1693 | { | |
1694 | ppc_4xx_eth_initialize(bis); | |
4f92ac36 SR |
1695 | if (emac0_dev) { |
1696 | return ppc_4xx_eth_init(emac0_dev, bis); | |
1697 | } else { | |
1698 | printf("ERROR: ethaddr not set!\n"); | |
1699 | return -1; | |
1700 | } | |
d6c61aab SR |
1701 | } |
1702 | ||
1703 | int eth_send(volatile void *packet, int length) | |
1704 | { | |
d6c61aab SR |
1705 | return (ppc_4xx_eth_send(emac0_dev, packet, length)); |
1706 | } | |
1707 | ||
1708 | int eth_rx(void) | |
1709 | { | |
1710 | return (ppc_4xx_eth_rx(emac0_dev)); | |
1711 | } | |
63ff004c MB |
1712 | |
1713 | int emac4xx_miiphy_initialize (bd_t * bis) | |
1714 | { | |
1715 | #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) | |
1716 | miiphy_register ("ppc_4xx_eth0", | |
6e7fb6ea | 1717 | emac4xx_miiphy_read, emac4xx_miiphy_write); |
63ff004c MB |
1718 | #endif |
1719 | ||
1720 | return 0; | |
1721 | } | |
d6c61aab SR |
1722 | #endif /* !defined(CONFIG_NET_MULTI) */ |
1723 | ||
1724 | #endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ |