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ppc4xx: Consolidate PPC4xx UIC defines
[people/ms/u-boot.git] / cpu / ppc4xx / 4xx_enet.c
CommitLineData
ba56f625
WD		 1/*-----------------------------------------------------------------------------+
2 *
265817c7
WD		 3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
ba56f625 9 *
265817c7
WD		 10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
ba56f625 13 *
265817c7
WD		 14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
ba56f625 17 *
265817c7
WD		 18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
ba56f625
WD		 20 *-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 *
265817c7 23 * File Name: enetemac.c
ba56f625 24 *
265817c7 25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
ba56f625 26 *
265817c7 27 * Author: Mark Wisner
ba56f625
WD		 28 *
29 * Change Activity-
30 *
265817c7
WD		 31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
ba56f625 70 *-----------------------------------------------------------------------------*
265817c7
WD		 71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
ba56f625
WD		 78 *-----------------------------------------------------------------------------*/
79
80#include <config.h>
ba56f625
WD		 81#include <common.h>
82#include <net.h>
83#include <asm/processor.h>
2d83476a 84#include <asm/io.h>
ff768cb1
SR		 85#include <asm/cache.h>
86#include <asm/mmu.h>
ba56f625 87#include <commproc.h>
d6c61aab
SR		 88#include <ppc4xx.h>
89#include <ppc4xx_enet.h>
ba56f625
WD		 90#include <405_mal.h>
91#include <miiphy.h>
92#include <malloc.h>
ba56f625 93
d6c61aab 94/*
0c8721a4 95 * Only compile for platform with AMCC EMAC ethernet controller and
d6c61aab
SR		 96 * network support enabled.
97 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
98 */
3a1ed1e1 99#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
d6c61aab 100
3a1ed1e1 101#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
d6c61aab
SR		 102#error "CONFIG_MII has to be defined!"
103#endif
ba56f625 104
1e25f957
SR		 105#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
106#error "CONFIG_NET_MULTI has to be defined for NetConsole"
107#endif
108
265817c7 109#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
1338e6a8 110#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
ba56f625 111
ba56f625
WD		 112/* Ethernet Transmit and Receive Buffers */
113/* AS.HARNOIS
114 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
115 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
116 */
265817c7 117#define ENET_MAX_MTU PKTSIZE
ba56f625
WD		 118#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
119
ba56f625
WD		 120/*-----------------------------------------------------------------------------+
121 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
122 * Interrupt Controller).
123 *-----------------------------------------------------------------------------*/
d1631fe1
SR		 124#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
125
126#if defined(CONFIG_HAS_ETH3)
127#if !defined(CONFIG_440GX)
128#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
129 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
130#else
131/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
132#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
133#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
134#endif /* !defined(CONFIG_440GX) */
135#elif defined(CONFIG_HAS_ETH2)
136#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
137 UIC_MASK(ETH_IRQ_NUM(2)))
138#elif defined(CONFIG_HAS_ETH1)
139#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
140#else
141#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
142#endif
143
144/*
145 * Define a default version for UIC_ETHxB for non 440GX so that we can
146 * use common code for all 4xx variants
147 */
148#if !defined(UIC_ETHxB)
149#define UIC_ETHxB 0
150#endif
151
152#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
153#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
154#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
155#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
156#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
157
158#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
159#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
160
161/*
162 * We have 3 different interrupt types:
163 * - MAL interrupts indicating successful transfer
164 * - MAL error interrupts indicating MAL related errors
165 * - EMAC interrupts indicating EMAC related errors
166 *
167 * All those interrupts can be on different UIC's, but since
168 * now at least all interrupts from one type are on the same
169 * UIC. Only exception is 440GX where the EMAC interrupts are
170 * spread over two UIC's!
171 */
172#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
173#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
174#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
175#if defined(CONFIG_440GX)
176#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(2)) * 0x10))
177#else
178#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
179#endif
ba56f625 180
d6c61aab 181#undef INFO_4XX_ENET
ba56f625 182
265817c7
WD		 183#define BI_PHYMODE_NONE 0
184#define BI_PHYMODE_ZMII 1
3c74e32a 185#define BI_PHYMODE_RGMII 2
887e2ec9
SR		 186#define BI_PHYMODE_GMII 3
187#define BI_PHYMODE_RTBI 4
188#define BI_PHYMODE_TBI 5
dbbd1257 189#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
8ac41e3e 190 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 191 defined(CONFIG_405EX)
887e2ec9
SR		 192#define BI_PHYMODE_SMII 6
193#define BI_PHYMODE_MII 7
8ac41e3e
SR		 194#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
195#define BI_PHYMODE_RMII 8
196#endif
887e2ec9 197#endif
3c74e32a 198
1941cce7 199#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
dbbd1257 200 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
8ac41e3e 201 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 202 defined(CONFIG_405EX)
887e2ec9
SR		 203#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
204#endif
d6c61aab 205
8ac41e3e
SR		 206#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
207#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
208#endif
209
210#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
211#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
212#else
213#define MAL_RX_CHAN_MUL 1
214#endif
215
ba56f625
WD		 216/*-----------------------------------------------------------------------------+
217 * Global variables. TX and RX descriptors and buffers.
218 *-----------------------------------------------------------------------------*/
d6c61aab 219#if !defined(CONFIG_NET_MULTI)
4f92ac36 220struct eth_device *emac0_dev = NULL;
d6c61aab
SR		 221#endif
222
1e25f957
SR		 223/*
224 * Get count of EMAC devices (doesn't have to be the max. possible number
225 * supported by the cpu)
353f2688
SR		 226 *
227 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
228 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
229 * 405EX/405EXr eval board, using the same binary.
1e25f957 230 */
353f2688
SR		 231#if defined(CONFIG_BOARD_EMAC_COUNT)
232#define LAST_EMAC_NUM board_emac_count()
233#else /* CONFIG_BOARD_EMAC_COUNT */
1e25f957
SR		 234#if defined(CONFIG_HAS_ETH3)
235#define LAST_EMAC_NUM 4
236#elif defined(CONFIG_HAS_ETH2)
237#define LAST_EMAC_NUM 3
238#elif defined(CONFIG_HAS_ETH1)
239#define LAST_EMAC_NUM 2
240#else
241#define LAST_EMAC_NUM 1
242#endif
353f2688 243#endif /* CONFIG_BOARD_EMAC_COUNT */
d6c61aab 244
5fb692ca
SR		 245/* normal boards start with EMAC0 */
246#if !defined(CONFIG_EMAC_NR_START)
247#define CONFIG_EMAC_NR_START 0
248#endif
249
ff768cb1
SR		 250#define MAL_RX_DESC_SIZE 2048
251#define MAL_TX_DESC_SIZE 2048
252#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
253
ba56f625
WD		 254/*-----------------------------------------------------------------------------+
255 * Prototypes and externals.
256 *-----------------------------------------------------------------------------*/
257static void enet_rcv (struct eth_device *dev, unsigned long malisr);
258
259int enetInt (struct eth_device *dev);
260static void mal_err (struct eth_device *dev, unsigned long isr,
261 unsigned long uic, unsigned long maldef,
262 unsigned long mal_errr);
263static void emac_err (struct eth_device *dev, unsigned long isr);
264
63ff004c
MB		 265extern int phy_setup_aneg (char *devname, unsigned char addr);
266extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
267 unsigned char reg, unsigned short *value);
268extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
269 unsigned char reg, unsigned short value);
d6c61aab 270
353f2688
SR		 271int board_emac_count(void);
272
8ac41e3e
SR		 273static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
274{
275#if defined(CONFIG_440SPE) || \
276 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
277 defined(CONFIG_405EX)
278 u32 val;
279
280 mfsdr(sdr_mfr, val);
281 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
282 mtsdr(sdr_mfr, val);
283#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
284 u32 val;
285
286 mfsdr(SDR0_ETH_CFG, val);
287 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
288 mtsdr(SDR0_ETH_CFG, val);
289#endif
290}
291
292static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
293{
294#if defined(CONFIG_440SPE) || \
295 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
296 defined(CONFIG_405EX)
297 u32 val;
298
299 mfsdr(sdr_mfr, val);
300 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
301 mtsdr(sdr_mfr, val);
302#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
303 u32 val;
304
305 mfsdr(SDR0_ETH_CFG, val);
306 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
307 mtsdr(SDR0_ETH_CFG, val);
308#endif
309}
310
ba56f625 311/*-----------------------------------------------------------------------------+
d6c61aab 312| ppc_4xx_eth_halt
ba56f625 313| Disable MAL channel, and EMACn
ba56f625 314+-----------------------------------------------------------------------------*/
d6c61aab 315static void ppc_4xx_eth_halt (struct eth_device *dev)
ba56f625 316{
d6c61aab 317 EMAC_4XX_HW_PST hw_p = dev->priv;
9ad31989 318 u32 val = 10000;
ba56f625 319
2d83476a 320 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
ba56f625
WD		 321
322 /* 1st reset MAL channel */
323 /* Note: writing a 0 to a channel has no effect */
d6c61aab
SR		 324#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
325 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
326#else
ba56f625 327 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
d6c61aab 328#endif
ba56f625
WD		 329 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
330
331 /* wait for reset */
d6c61aab 332 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
ba56f625 333 udelay (1000); /* Delay 1 MS so as not to hammer the register */
9ad31989
SR		 334 val--;
335 if (val == 0)
ba56f625 336 break;
ba56f625
WD		 337 }
338
6c5879f3 339 /* provide clocks for EMAC internal loopback */
8ac41e3e 340 emac_loopback_enable(hw_p);
6c5879f3 341
8ac41e3e 342 /* EMAC RESET */
2d83476a 343 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
ba56f625 344
6c5879f3 345 /* remove clocks for EMAC internal loopback */
8ac41e3e 346 emac_loopback_disable(hw_p);
6c5879f3 347
a93316c5 348#ifndef CONFIG_NETCONSOLE
c157d8e2 349 hw_p->print_speed = 1; /* print speed message again next time */
a93316c5 350#endif
c157d8e2 351
4c9e8557
SR		 352#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
353 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
9ad31989
SR		 354 mfsdr(SDR0_ETH_CFG, val);
355 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
356 mtsdr(SDR0_ETH_CFG, val);
4c9e8557
SR		 357#endif
358
ba56f625
WD		 359 return;
360}
361
846b0dd2 362#if defined (CONFIG_440GX)
d6c61aab 363int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
855a496f
WD		 364{
365 unsigned long pfc1;
366 unsigned long zmiifer;
367 unsigned long rmiifer;
368
369 mfsdr(sdr_pfc1, pfc1);
370 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
371
372 zmiifer = 0;
373 rmiifer = 0;
374
375 switch (pfc1) {
376 case 1:
377 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
378 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
379 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
380 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
381 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
382 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
383 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
384 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
385 break;
386 case 2:
f6e495f5
SR		 387 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
388 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
389 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
390 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
855a496f
WD		 391 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
392 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
393 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
394 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
395 break;
396 case 3:
397 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
398 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
399 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
400 bis->bi_phymode[1] = BI_PHYMODE_NONE;
401 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
402 bis->bi_phymode[3] = BI_PHYMODE_NONE;
403 break;
404 case 4:
405 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
406 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
407 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
408 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
409 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
410 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
411 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
412 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
413 break;
414 case 5:
415 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
416 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
417 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
418 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
419 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
420 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
421 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
422 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
423 break;
424 case 6:
425 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
426 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
427 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
855a496f
WD		 428 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
429 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
430 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
855a496f
WD		 431 break;
432 case 0:
433 default:
434 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
435 rmiifer = 0x0;
436 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
437 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
438 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
439 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
440 break;
441 }
442
443 /* Ensure we setup mdio for this devnum and ONLY this devnum */
444 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
445
ff768cb1
SR		 446 out_be32((void *)ZMII_FER, zmiifer);
447 out_be32((void *)RGMII_FER, rmiifer);
855a496f
WD		 448
449 return ((int)pfc1);
855a496f 450}
6c5879f3 451#endif /* CONFIG_440_GX */
855a496f 452
887e2ec9
SR		 453#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
454int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
455{
456 unsigned long zmiifer=0x0;
37ed6cdd 457 unsigned long pfc1;
887e2ec9 458
37ed6cdd
MF		 459 mfsdr(sdr_pfc1, pfc1);
460 pfc1 &= SDR0_PFC1_SELECT_MASK;
461
2f15278c 462 switch (pfc1) {
37ed6cdd 463 case SDR0_PFC1_SELECT_CONFIG_2:
887e2ec9 464 /* 1 x GMII port */
2d83476a
SR		 465 out_be32((void *)ZMII_FER, 0x00);
466 out_be32((void *)RGMII_FER, 0x00000037);
887e2ec9
SR		 467 bis->bi_phymode[0] = BI_PHYMODE_GMII;
468 bis->bi_phymode[1] = BI_PHYMODE_NONE;
469 break;
37ed6cdd 470 case SDR0_PFC1_SELECT_CONFIG_4:
887e2ec9 471 /* 2 x RGMII ports */
2d83476a
SR		 472 out_be32((void *)ZMII_FER, 0x00);
473 out_be32((void *)RGMII_FER, 0x00000055);
887e2ec9
SR		 474 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
475 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
476 break;
37ed6cdd 477 case SDR0_PFC1_SELECT_CONFIG_6:
887e2ec9 478 /* 2 x SMII ports */
2d83476a
SR		 479 out_be32((void *)ZMII_FER,
480 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
481 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
482 out_be32((void *)RGMII_FER, 0x00000000);
37ed6cdd
MF		 483 bis->bi_phymode[0] = BI_PHYMODE_SMII;
484 bis->bi_phymode[1] = BI_PHYMODE_SMII;
485 break;
486 case SDR0_PFC1_SELECT_CONFIG_1_2:
487 /* only 1 x MII supported */
2d83476a
SR		 488 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
489 out_be32((void *)RGMII_FER, 0x00000000);
37ed6cdd
MF		 490 bis->bi_phymode[0] = BI_PHYMODE_MII;
491 bis->bi_phymode[1] = BI_PHYMODE_NONE;
887e2ec9
SR		 492 break;
493 default:
494 break;
495 }
496
497 /* Ensure we setup mdio for this devnum and ONLY this devnum */
2d83476a 498 zmiifer = in_be32((void *)ZMII_FER);
887e2ec9 499 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
2d83476a 500 out_be32((void *)ZMII_FER, zmiifer);
887e2ec9
SR		 501
502 return ((int)0x0);
503}
504#endif /* CONFIG_440EPX */
505
dbbd1257
SR		 506#if defined(CONFIG_405EX)
507int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
508{
1740c1bf 509 u32 rgmiifer = 0;
dbbd1257
SR		 510
511 /*
1740c1bf
GE		 512 * The 405EX(r)'s RGMII bridge can operate in one of several
513 * modes, only one of which (2 x RGMII) allows the
514 * simultaneous use of both EMACs on the 405EX.
dbbd1257 515 */
1740c1bf
GE		 516
517 switch (CONFIG_EMAC_PHY_MODE) {
518
519 case EMAC_PHY_MODE_NONE:
520 /* No ports */
521 rgmiifer |= RGMII_FER_DIS << 0;
522 rgmiifer |= RGMII_FER_DIS << 4;
523 out_be32((void *)RGMII_FER, rgmiifer);
524 bis->bi_phymode[0] = BI_PHYMODE_NONE;
525 bis->bi_phymode[1] = BI_PHYMODE_NONE;
526 break;
527 case EMAC_PHY_MODE_NONE_RGMII:
528 /* 1 x RGMII port on channel 0 */
529 rgmiifer |= RGMII_FER_RGMII << 0;
530 rgmiifer |= RGMII_FER_DIS << 4;
531 out_be32((void *)RGMII_FER, rgmiifer);
532 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
533 bis->bi_phymode[1] = BI_PHYMODE_NONE;
534 break;
535 case EMAC_PHY_MODE_RGMII_NONE:
536 /* 1 x RGMII port on channel 1 */
537 rgmiifer |= RGMII_FER_DIS << 0;
538 rgmiifer |= RGMII_FER_RGMII << 4;
539 out_be32((void *)RGMII_FER, rgmiifer);
540 bis->bi_phymode[0] = BI_PHYMODE_NONE;
541 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
542 break;
543 case EMAC_PHY_MODE_RGMII_RGMII:
dbbd1257 544 /* 2 x RGMII ports */
1740c1bf
GE		 545 rgmiifer |= RGMII_FER_RGMII << 0;
546 rgmiifer |= RGMII_FER_RGMII << 4;
547 out_be32((void *)RGMII_FER, rgmiifer);
dbbd1257
SR		 548 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
549 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
550 break;
1740c1bf
GE		 551 case EMAC_PHY_MODE_NONE_GMII:
552 /* 1 x GMII port on channel 0 */
553 rgmiifer |= RGMII_FER_GMII << 0;
554 rgmiifer |= RGMII_FER_DIS << 4;
555 out_be32((void *)RGMII_FER, rgmiifer);
556 bis->bi_phymode[0] = BI_PHYMODE_GMII;
557 bis->bi_phymode[1] = BI_PHYMODE_NONE;
558 break;
559 case EMAC_PHY_MODE_NONE_MII:
560 /* 1 x MII port on channel 0 */
561 rgmiifer |= RGMII_FER_MII << 0;
562 rgmiifer |= RGMII_FER_DIS << 4;
563 out_be32((void *)RGMII_FER, rgmiifer);
564 bis->bi_phymode[0] = BI_PHYMODE_MII;
565 bis->bi_phymode[1] = BI_PHYMODE_NONE;
566 break;
567 case EMAC_PHY_MODE_GMII_NONE:
568 /* 1 x GMII port on channel 1 */
569 rgmiifer |= RGMII_FER_DIS << 0;
570 rgmiifer |= RGMII_FER_GMII << 4;
571 out_be32((void *)RGMII_FER, rgmiifer);
572 bis->bi_phymode[0] = BI_PHYMODE_NONE;
573 bis->bi_phymode[1] = BI_PHYMODE_GMII;
574 break;
575 case EMAC_PHY_MODE_MII_NONE:
576 /* 1 x MII port on channel 1 */
577 rgmiifer |= RGMII_FER_DIS << 0;
578 rgmiifer |= RGMII_FER_MII << 4;
579 out_be32((void *)RGMII_FER, rgmiifer);
580 bis->bi_phymode[0] = BI_PHYMODE_NONE;
581 bis->bi_phymode[1] = BI_PHYMODE_MII;
dbbd1257
SR		 582 break;
583 default:
584 break;
585 }
586
587 /* Ensure we setup mdio for this devnum and ONLY this devnum */
1740c1bf
GE		 588 rgmiifer = in_be32((void *)RGMII_FER);
589 rgmiifer |= (1 << (19-devnum));
590 out_be32((void *)RGMII_FER, rgmiifer);
dbbd1257
SR		 591
592 return ((int)0x0);
593}
594#endif /* CONFIG_405EX */
595
8ac41e3e
SR		 596#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
597int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
598{
599 u32 eth_cfg;
600 u32 zmiifer; /* ZMII0_FER reg. */
601 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
602 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
4c9e8557 603 int mode;
8ac41e3e
SR		 604
605 zmiifer = 0;
606 rmiifer = 0;
607 rmiifer1 = 0;
608
4c9e8557
SR		 609#if defined(CONFIG_460EX)
610 mode = 9;
611#else
612 mode = 10;
613#endif
614
8ac41e3e
SR		 615 /* TODO:
616 * NOTE: 460GT has 2 RGMII bridge cores:
617 * emac0 ------ RGMII0_BASE
618 * |
619 * emac1 -----+
620 *
621 * emac2 ------ RGMII1_BASE
622 * |
623 * emac3 -----+
624 *
625 * 460EX has 1 RGMII bridge core:
626 * and RGMII1_BASE is disabled
627 * emac0 ------ RGMII0_BASE
628 * |
629 * emac1 -----+
630 */
631
632 /*
633 * Right now only 2*RGMII is supported. Please extend when needed.
634 * sr - 2008-02-19
635 */
4c9e8557 636 switch (mode) {
8ac41e3e
SR		 637 case 1:
638 /* 1 MII - 460EX */
639 /* GMC0 EMAC4_0, ZMII Bridge */
640 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
641 bis->bi_phymode[0] = BI_PHYMODE_MII;
642 bis->bi_phymode[1] = BI_PHYMODE_NONE;
643 bis->bi_phymode[2] = BI_PHYMODE_NONE;
644 bis->bi_phymode[3] = BI_PHYMODE_NONE;
645 break;
646 case 2:
647 /* 2 MII - 460GT */
648 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
649 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
650 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
651 bis->bi_phymode[0] = BI_PHYMODE_MII;
652 bis->bi_phymode[1] = BI_PHYMODE_NONE;
653 bis->bi_phymode[2] = BI_PHYMODE_MII;
654 bis->bi_phymode[3] = BI_PHYMODE_NONE;
655 break;
656 case 3:
657 /* 2 RMII - 460EX */
658 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
659 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
660 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
661 bis->bi_phymode[0] = BI_PHYMODE_RMII;
662 bis->bi_phymode[1] = BI_PHYMODE_RMII;
663 bis->bi_phymode[2] = BI_PHYMODE_NONE;
664 bis->bi_phymode[3] = BI_PHYMODE_NONE;
665 break;
666 case 4:
667 /* 4 RMII - 460GT */
668 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
669 /* ZMII Bridge */
670 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
671 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
672 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
673 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
674 bis->bi_phymode[0] = BI_PHYMODE_RMII;
675 bis->bi_phymode[1] = BI_PHYMODE_RMII;
676 bis->bi_phymode[2] = BI_PHYMODE_RMII;
677 bis->bi_phymode[3] = BI_PHYMODE_RMII;
678 break;
679 case 5:
680 /* 2 SMII - 460EX */
681 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
682 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
683 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
684 bis->bi_phymode[0] = BI_PHYMODE_SMII;
685 bis->bi_phymode[1] = BI_PHYMODE_SMII;
686 bis->bi_phymode[2] = BI_PHYMODE_NONE;
687 bis->bi_phymode[3] = BI_PHYMODE_NONE;
688 break;
689 case 6:
690 /* 4 SMII - 460GT */
691 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
692 /* ZMII Bridge */
693 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
694 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
695 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
696 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
697 bis->bi_phymode[0] = BI_PHYMODE_SMII;
698 bis->bi_phymode[1] = BI_PHYMODE_SMII;
699 bis->bi_phymode[2] = BI_PHYMODE_SMII;
700 bis->bi_phymode[3] = BI_PHYMODE_SMII;
701 break;
702 case 7:
703 /* This is the default mode that we want for board bringup - Maple */
704 /* 1 GMII - 460EX */
705 /* GMC0 EMAC4_0, RGMII Bridge 0 */
706 rmiifer |= RGMII_FER_MDIO(0);
707
708 if (devnum == 0) {
709 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
710 bis->bi_phymode[0] = BI_PHYMODE_GMII;
711 bis->bi_phymode[1] = BI_PHYMODE_NONE;
712 bis->bi_phymode[2] = BI_PHYMODE_NONE;
713 bis->bi_phymode[3] = BI_PHYMODE_NONE;
714 } else {
715 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
716 bis->bi_phymode[0] = BI_PHYMODE_NONE;
717 bis->bi_phymode[1] = BI_PHYMODE_GMII;
718 bis->bi_phymode[2] = BI_PHYMODE_NONE;
719 bis->bi_phymode[3] = BI_PHYMODE_NONE;
720 }
721 break;
722 case 8:
723 /* 2 GMII - 460GT */
724 /* GMC0 EMAC4_0, RGMII Bridge 0 */
725 /* GMC1 EMAC4_2, RGMII Bridge 1 */
726 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
727 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
728 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
729 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
730
731 bis->bi_phymode[0] = BI_PHYMODE_GMII;
732 bis->bi_phymode[1] = BI_PHYMODE_NONE;
733 bis->bi_phymode[2] = BI_PHYMODE_GMII;
734 bis->bi_phymode[3] = BI_PHYMODE_NONE;
735 break;
736 case 9:
737 /* 2 RGMII - 460EX */
738 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
739 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
740 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
741 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
742
743 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
744 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
745 bis->bi_phymode[2] = BI_PHYMODE_NONE;
746 bis->bi_phymode[3] = BI_PHYMODE_NONE;
747 break;
748 case 10:
749 /* 4 RGMII - 460GT */
750 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
751 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
752 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
753 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
754 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
755 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
756 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
757 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
758 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
759 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
760 break;
761 default:
762 break;
763 }
764
765 /* Set EMAC for MDIO */
766 mfsdr(SDR0_ETH_CFG, eth_cfg);
767 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
768 mtsdr(SDR0_ETH_CFG, eth_cfg);
769
770 out_be32((void *)RGMII_FER, rmiifer);
771#if defined(CONFIG_460GT)
772 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
773#endif
774
775 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
776 mfsdr(SDR0_ETH_CFG, eth_cfg);
777 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
778 mtsdr(SDR0_ETH_CFG, eth_cfg);
779
780 return 0;
781}
782#endif /* CONFIG_460EX || CONFIG_460GT */
783
ff768cb1
SR		 784static inline void *malloc_aligned(u32 size, u32 align)
785{
786 return (void *)(((u32)malloc(size + align) + align - 1) &
787 ~(align - 1));
788}
789
d6c61aab 790static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
ba56f625 791{
ff768cb1 792 int i;
d6c61aab 793 unsigned long reg = 0;
ba56f625
WD		 794 unsigned long msr;
795 unsigned long speed;
796 unsigned long duplex;
797 unsigned long failsafe;
798 unsigned mode_reg;
799 unsigned short devnum;
800 unsigned short reg_short;
887e2ec9
SR		 801#if defined(CONFIG_440GX) || \
802 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
dbbd1257 803 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
8ac41e3e 804 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 805 defined(CONFIG_405EX)
d6c61aab 806 sys_info_t sysinfo;
887e2ec9 807#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
dbbd1257 808 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
8ac41e3e 809 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 810 defined(CONFIG_405EX)
6e7fb6ea
SR		 811 int ethgroup = -1;
812#endif
6c5879f3 813#endif
ff768cb1
SR		 814 u32 bd_cached;
815 u32 bd_uncached = 0;
4fae35a5
AG		 816#ifdef CONFIG_4xx_DCACHE
817 static u32 last_used_ea = 0;
818#endif
e54ec0f0
SR		 819#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
820 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
821 defined(CONFIG_405EX)
822 int rgmii_channel;
823#endif
6c5879f3 824
d6c61aab 825 EMAC_4XX_HW_PST hw_p = dev->priv;
ba56f625
WD		 826
827 /* before doing anything, figure out if we have a MAC address */
828 /* if not, bail */
4f92ac36
SR		 829 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
830 printf("ERROR: ethaddr not set!\n");
ba56f625 831 return -1;
4f92ac36 832 }
ba56f625 833
887e2ec9
SR		 834#if defined(CONFIG_440GX) || \
835 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
dbbd1257 836 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
8ac41e3e 837 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 838 defined(CONFIG_405EX)
ba56f625
WD		 839 /* Need to get the OPB frequency so we can access the PHY */
840 get_sys_info (&sysinfo);
d6c61aab 841#endif
ba56f625 842
ba56f625
WD		 843 msr = mfmsr ();
844 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
845
846 devnum = hw_p->devnum;
847
d6c61aab 848#ifdef INFO_4XX_ENET
ba56f625
WD		 849 /* AS.HARNOIS
850 * We should have :
265817c7 851 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
ba56f625
WD		 852 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
853 * is possible that new packets (without relationship with
854 * current transfer) have got the time to arrived before
855 * netloop calls eth_halt
856 */
857 printf ("About preceeding transfer (eth%d):\n"
858 "- Sent packet number %d\n"
859 "- Received packet number %d\n"
860 "- Handled packet number %d\n",
861 hw_p->devnum,
862 hw_p->stats.pkts_tx,
863 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
864
865 hw_p->stats.pkts_tx = 0;
866 hw_p->stats.pkts_rx = 0;
867 hw_p->stats.pkts_handled = 0;
6c5879f3 868 hw_p->print_speed = 1; /* print speed message again next time */
ba56f625
WD		 869#endif
870
265817c7
WD		 871 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
872 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
ba56f625
WD		 873
874 hw_p->rx_slot = 0; /* MAL Receive Slot */
875 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
876 hw_p->rx_u_index = 0; /* Receive User Queue Index */
877
878 hw_p->tx_slot = 0; /* MAL Transmit Slot */
879 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
880 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
881
6c5879f3 882#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
ba56f625
WD		 883 /* set RMII mode */
884 /* NOTE: 440GX spec states that mode is mutually exclusive */
885 /* NOTE: Therefore, disable all other EMACS, since we handle */
886 /* NOTE: only one emac at a time */
887 reg = 0;
2d83476a 888 out_be32((void *)ZMII_FER, 0);
ba56f625 889 udelay (100);
ba56f625 890
8ac41e3e 891#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
2d83476a 892 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
8ac41e3e
SR		 893#elif defined(CONFIG_440GX) || \
894 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
895 defined(CONFIG_460EX) || defined(CONFIG_460GT)
d6c61aab 896 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
0e6d798c 897#endif
c57c7980 898
2d83476a 899 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
6e7fb6ea 900#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
dbbd1257
SR		 901#if defined(CONFIG_405EX)
902 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
903#endif
d6c61aab 904
8ac41e3e 905 sync();
0e6d798c 906
6c5879f3 907 /* provide clocks for EMAC internal loopback */
8ac41e3e 908 emac_loopback_enable(hw_p);
0e6d798c 909
8ac41e3e 910 /* EMAC RESET */
2d83476a 911 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
ba56f625 912
8ac41e3e
SR		 913 /* remove clocks for EMAC internal loopback */
914 emac_loopback_disable(hw_p);
915
ba56f625 916 failsafe = 1000;
2d83476a 917 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
ba56f625
WD		 918 udelay (1000);
919 failsafe--;
920 }
887e2ec9
SR		 921 if (failsafe <= 0)
922 printf("\nProblem resetting EMAC!\n");
ba56f625 923
887e2ec9
SR		 924#if defined(CONFIG_440GX) || \
925 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
dbbd1257 926 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
8ac41e3e 927 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 928 defined(CONFIG_405EX)
ba56f625
WD		 929 /* Whack the M1 register */
930 mode_reg = 0x0;
931 mode_reg &= ~0x00000038;
932 if (sysinfo.freqOPB <= 50000000);
933 else if (sysinfo.freqOPB <= 66666667)
934 mode_reg |= EMAC_M1_OBCI_66;
935 else if (sysinfo.freqOPB <= 83333333)
936 mode_reg |= EMAC_M1_OBCI_83;
937 else if (sysinfo.freqOPB <= 100000000)
938 mode_reg |= EMAC_M1_OBCI_100;
939 else
940 mode_reg |= EMAC_M1_OBCI_GT100;
941
2d83476a 942 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
6e7fb6ea 943#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
ba56f625
WD		 944
945 /* wait for PHY to complete auto negotiation */
946 reg_short = 0;
947#ifndef CONFIG_CS8952_PHY
948 switch (devnum) {
949 case 0:
950 reg = CONFIG_PHY_ADDR;
951 break;
d6c61aab 952#if defined (CONFIG_PHY1_ADDR)
ba56f625
WD		 953 case 1:
954 reg = CONFIG_PHY1_ADDR;
955 break;
d6c61aab 956#endif
4c9e8557 957#if defined (CONFIG_PHY2_ADDR)
ba56f625
WD		 958 case 2:
959 reg = CONFIG_PHY2_ADDR;
960 break;
4c9e8557
SR		 961#endif
962#if defined (CONFIG_PHY3_ADDR)
ba56f625
WD		 963 case 3:
964 reg = CONFIG_PHY3_ADDR;
965 break;
966#endif
967 default:
968 reg = CONFIG_PHY_ADDR;
969 break;
970 }
971
3c74e32a
WD		 972 bis->bi_phynum[devnum] = reg;
973
d6c61aab 974#if defined(CONFIG_PHY_RESET)
a06752e3
WD		 975 /*
976 * Reset the phy, only if its the first time through
977 * otherwise, just check the speeds & feeds
978 */
979 if (hw_p->first_init == 0) {
ec0c2ec7 980#if defined(CONFIG_M88E1111_PHY)
887e2ec9
SR		 981 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
982 miiphy_write (dev->name, reg, 0x18, 0x4101);
983 miiphy_write (dev->name, reg, 0x09, 0x0e00);
984 miiphy_write (dev->name, reg, 0x04, 0x01e1);
985#endif
63ff004c 986 miiphy_reset (dev->name, reg);
ba56f625 987
887e2ec9
SR		 988#if defined(CONFIG_440GX) || \
989 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
dbbd1257 990 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
8ac41e3e 991 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 992 defined(CONFIG_405EX)
887e2ec9 993
0e6d798c 994#if defined(CONFIG_CIS8201_PHY)
fc1cfcdb 995 /*
17f50f22
SR		 996 * Cicada 8201 PHY needs to have an extended register whacked
997 * for RGMII mode.
fc1cfcdb 998 */
887e2ec9 999 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
b79316f2 1000#if defined(CONFIG_CIS8201_SHORT_ETCH)
63ff004c 1001 miiphy_write (dev->name, reg, 23, 0x1300);
b79316f2 1002#else
63ff004c 1003 miiphy_write (dev->name, reg, 23, 0x1000);
b79316f2 1004#endif
17f50f22
SR		 1005 /*
1006 * Vitesse VSC8201/Cicada CIS8201 errata:
1007 * Interoperability problem with Intel 82547EI phys
1008 * This work around (provided by Vitesse) changes
1009 * the default timer convergence from 8ms to 12ms
1010 */
63ff004c
MB		 1011 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1012 miiphy_write (dev->name, reg, 0x08, 0x0200);
1013 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
1014 miiphy_write (dev->name, reg, 0x02, 0x0004);
1015 miiphy_write (dev->name, reg, 0x01, 0x0671);
1016 miiphy_write (dev->name, reg, 0x00, 0x8fae);
1017 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1018 miiphy_write (dev->name, reg, 0x08, 0x0000);
1019 miiphy_write (dev->name, reg, 0x1f, 0x0000);
17f50f22
SR		 1020 /* end Vitesse/Cicada errata */
1021 }
0e6d798c 1022#endif
5fb692ca
SR		 1023
1024#if defined(CONFIG_ET1011C_PHY)
1025 /*
1026 * Agere ET1011c PHY needs to have an extended register whacked
1027 * for RGMII mode.
1028 */
1029 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
1030 miiphy_read (dev->name, reg, 0x16, &reg_short);
1031 reg_short &= ~(0x7);
1032 reg_short |= 0x6; /* RGMII DLL Delay*/
1033 miiphy_write (dev->name, reg, 0x16, reg_short);
1034
1035 miiphy_read (dev->name, reg, 0x17, &reg_short);
1036 reg_short &= ~(0x40);
1037 miiphy_write (dev->name, reg, 0x17, reg_short);
1038
1039 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
1040 }
1041#endif
1042
855a496f 1043#endif
a06752e3 1044 /* Start/Restart autonegotiation */
63ff004c 1045 phy_setup_aneg (dev->name, reg);
a06752e3
WD		 1046 udelay (1000);
1047 }
d6c61aab 1048#endif /* defined(CONFIG_PHY_RESET) */
ba56f625 1049
63ff004c 1050 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
ba56f625
WD		 1051
1052 /*
0e6d798c 1053 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
ba56f625
WD		 1054 */
1055 if ((reg_short & PHY_BMSR_AUTN_ABLE)
1056 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
1057 puts ("Waiting for PHY auto negotiation to complete");
1058 i = 0;
1059 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
1060 /*
1061 * Timeout reached ?
1062 */
1063 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1064 puts (" TIMEOUT !\n");
1065 break;
1066 }
1067
1068 if ((i++ % 1000) == 0) {
1069 putc ('.');
1070 }
1071 udelay (1000); /* 1 ms */
63ff004c 1072 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
ba56f625
WD		 1073
1074 }
1075 puts (" done\n");
1076 udelay (500000); /* another 500 ms (results in faster booting) */
1077 }
d6c61aab
SR		 1078#endif /* #ifndef CONFIG_CS8952_PHY */
1079
63ff004c
MB		 1080 speed = miiphy_speed (dev->name, reg);
1081 duplex = miiphy_duplex (dev->name, reg);
ba56f625
WD		 1082
1083 if (hw_p->print_speed) {
1084 hw_p->print_speed = 0;
5fb692ca
SR		 1085 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1086 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
1087 hw_p->devnum);
ba56f625
WD		 1088 }
1089
8ac41e3e
SR		 1090#if defined(CONFIG_440) && \
1091 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1092 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1093 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
846b0dd2 1094#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
c157d8e2
SR		 1095 mfsdr(sdr_mfr, reg);
1096 if (speed == 100) {
1097 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
1098 } else {
1099 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1100 }
1101 mtsdr(sdr_mfr, reg);
1102#endif
c57c7980 1103
ba56f625 1104 /* Set ZMII/RGMII speed according to the phy link speed */
ff768cb1 1105 reg = in_be32((void *)ZMII_SSR);
855a496f 1106 if ( (speed == 100) || (speed == 1000) )
ff768cb1 1107 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
ba56f625 1108 else
ff768cb1 1109 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
ba56f625
WD		 1110
1111 if ((devnum == 2) || (devnum == 3)) {
1112 if (speed == 1000)
1113 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1114 else if (speed == 100)
1115 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
887e2ec9 1116 else if (speed == 10)
ba56f625 1117 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
887e2ec9
SR		 1118 else {
1119 printf("Error in RGMII Speed\n");
1120 return -1;
1121 }
ff768cb1 1122 out_be32((void *)RGMII_SSR, reg);
ba56f625 1123 }
6e7fb6ea 1124#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
ba56f625 1125
dbbd1257 1126#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
8ac41e3e 1127 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 1128 defined(CONFIG_405EX)
e54ec0f0
SR		 1129 if (devnum >= 2)
1130 rgmii_channel = devnum - 2;
1131 else
1132 rgmii_channel = devnum;
1133
887e2ec9 1134 if (speed == 1000)
e54ec0f0 1135 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
887e2ec9 1136 else if (speed == 100)
e54ec0f0 1137 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
887e2ec9 1138 else if (speed == 10)
e54ec0f0 1139 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
887e2ec9
SR		 1140 else {
1141 printf("Error in RGMII Speed\n");
1142 return -1;
1143 }
2d83476a 1144 out_be32((void *)RGMII_SSR, reg);
8ac41e3e
SR		 1145#if defined(CONFIG_460GT)
1146 if ((devnum == 2) || (devnum == 3))
1147 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1148#endif
887e2ec9
SR		 1149#endif
1150
ba56f625 1151 /* set the Mal configuration reg */
887e2ec9
SR		 1152#if defined(CONFIG_440GX) || \
1153 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
dbbd1257 1154 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
8ac41e3e 1155 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 1156 defined(CONFIG_405EX)
17f50f22
SR		 1157 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
1158 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1159#else
1160 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
ba56f625 1161 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
17f50f22
SR		 1162 if (get_pvr() == PVR_440GP_RB) {
1163 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
1164 }
1165#endif
ba56f625 1166
ba56f625
WD		 1167 /*
1168 * Malloc MAL buffer desciptors, make sure they are
1169 * aligned on cache line boundary size
1170 * (401/403/IOP480 = 16, 405 = 32)
1171 * and doesn't cross cache block boundaries.
1172 */
ff768cb1
SR		 1173 if (hw_p->first_init == 0) {
1174 debug("*** Allocating descriptor memory ***\n");
ba56f625 1175
ff768cb1
SR		 1176 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1177 if (!bd_cached) {
b002144e 1178 printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
ff768cb1
SR		 1179 return -1;
1180 }
b79316f2 1181
ff768cb1 1182#ifdef CONFIG_4xx_DCACHE
ba79fde5 1183 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
4fae35a5 1184 if (!last_used_ea)
5e3dca57
AG		 1185#if defined(CFG_MEM_TOP_HIDE)
1186 bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
1187#else
4fae35a5 1188 bd_uncached = bis->bi_memsize;
5e3dca57 1189#endif
4fae35a5
AG		 1190 else
1191 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1192
1193 last_used_ea = bd_uncached;
ff768cb1
SR		 1194 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1195 TLB_WORD2_I_ENABLE);
1196#else
1197 bd_uncached = bd_cached;
1198#endif
1199 hw_p->tx_phys = bd_cached;
1200 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1201 hw_p->tx = (mal_desc_t *)(bd_uncached);
1202 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
1203 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
ba56f625
WD		 1204 }
1205
1206 for (i = 0; i < NUM_TX_BUFF; i++) {
1207 hw_p->tx[i].ctrl = 0;
1208 hw_p->tx[i].data_len = 0;
ff768cb1
SR		 1209 if (hw_p->first_init == 0)
1210 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1211 L1_CACHE_BYTES);
ba56f625
WD		 1212 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1213 if ((NUM_TX_BUFF - 1) == i)
1214 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1215 hw_p->tx_run[i] = -1;
ff768cb1 1216 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
ba56f625
WD		 1217 }
1218
1219 for (i = 0; i < NUM_RX_BUFF; i++) {
1220 hw_p->rx[i].ctrl = 0;
1221 hw_p->rx[i].data_len = 0;
ff768cb1 1222 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
ba56f625
WD		 1223 if ((NUM_RX_BUFF - 1) == i)
1224 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1225 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1226 hw_p->rx_ready[i] = -1;
ff768cb1 1227 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
ba56f625
WD		 1228 }
1229
1230 reg = 0x00000000;
1231
1232 reg |= dev->enetaddr[0]; /* set high address */
1233 reg = reg << 8;
1234 reg |= dev->enetaddr[1];
1235
2d83476a 1236 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
ba56f625
WD		 1237
1238 reg = 0x00000000;
1239 reg |= dev->enetaddr[2]; /* set low address */
1240 reg = reg << 8;
1241 reg |= dev->enetaddr[3];
1242 reg = reg << 8;
1243 reg |= dev->enetaddr[4];
1244 reg = reg << 8;
1245 reg |= dev->enetaddr[5];
1246
2d83476a 1247 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
ba56f625
WD		 1248
1249 switch (devnum) {
1250 case 1:
1251 /* setup MAL tx & rx channel pointers */
d6c61aab 1252#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
ff768cb1 1253 mtdcr (maltxctp2r, hw_p->tx_phys);
c157d8e2 1254#else
ff768cb1 1255 mtdcr (maltxctp1r, hw_p->tx_phys);
c157d8e2 1256#endif
d6c61aab 1257#if defined(CONFIG_440)
c157d8e2 1258 mtdcr (maltxbattr, 0x0);
ba56f625 1259 mtdcr (malrxbattr, 0x0);
d6c61aab 1260#endif
8ac41e3e
SR		 1261
1262#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
4c9e8557 1263 mtdcr (malrxctp8r, hw_p->rx_phys);
8ac41e3e
SR		 1264 /* set RX buffer size */
1265 mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
1266#else
ff768cb1 1267 mtdcr (malrxctp1r, hw_p->rx_phys);
ba56f625
WD		 1268 /* set RX buffer size */
1269 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
8ac41e3e 1270#endif
ba56f625 1271 break;
846b0dd2 1272#if defined (CONFIG_440GX)
ba56f625
WD		 1273 case 2:
1274 /* setup MAL tx & rx channel pointers */
1275 mtdcr (maltxbattr, 0x0);
ba56f625 1276 mtdcr (malrxbattr, 0x0);
ff768cb1
SR		 1277 mtdcr (maltxctp2r, hw_p->tx_phys);
1278 mtdcr (malrxctp2r, hw_p->rx_phys);
ba56f625
WD		 1279 /* set RX buffer size */
1280 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
1281 break;
1282 case 3:
1283 /* setup MAL tx & rx channel pointers */
1284 mtdcr (maltxbattr, 0x0);
ff768cb1 1285 mtdcr (maltxctp3r, hw_p->tx_phys);
ba56f625 1286 mtdcr (malrxbattr, 0x0);
ff768cb1 1287 mtdcr (malrxctp3r, hw_p->rx_phys);
ba56f625
WD		 1288 /* set RX buffer size */
1289 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
1290 break;
c57c7980 1291#endif /* CONFIG_440GX */
4c9e8557
SR		 1292#if defined (CONFIG_460GT)
1293 case 2:
1294 /* setup MAL tx & rx channel pointers */
1295 mtdcr (maltxbattr, 0x0);
1296 mtdcr (malrxbattr, 0x0);
1297 mtdcr (maltxctp2r, hw_p->tx_phys);
1298 mtdcr (malrxctp16r, hw_p->rx_phys);
1299 /* set RX buffer size */
1300 mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
1301 break;
1302 case 3:
1303 /* setup MAL tx & rx channel pointers */
1304 mtdcr (maltxbattr, 0x0);
1305 mtdcr (malrxbattr, 0x0);
1306 mtdcr (maltxctp3r, hw_p->tx_phys);
1307 mtdcr (malrxctp24r, hw_p->rx_phys);
1308 /* set RX buffer size */
1309 mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
1310 break;
1311#endif /* CONFIG_460GT */
ba56f625
WD		 1312 case 0:
1313 default:
1314 /* setup MAL tx & rx channel pointers */
d6c61aab 1315#if defined(CONFIG_440)
ba56f625 1316 mtdcr (maltxbattr, 0x0);
ba56f625 1317 mtdcr (malrxbattr, 0x0);
d6c61aab 1318#endif
ff768cb1
SR		 1319 mtdcr (maltxctp0r, hw_p->tx_phys);
1320 mtdcr (malrxctp0r, hw_p->rx_phys);
ba56f625
WD		 1321 /* set RX buffer size */
1322 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
1323 break;
1324 }
1325
1326 /* Enable MAL transmit and receive channels */
d6c61aab 1327#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
c157d8e2
SR		 1328 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
1329#else
ba56f625 1330 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
c157d8e2 1331#endif
ba56f625
WD		 1332 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1333
1334 /* set transmit enable & receive enable */
2d83476a 1335 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
ba56f625 1336
2d83476a 1337 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
76957cb3
SR		 1338
1339 /* set rx-/tx-fifo size */
1340 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
ba56f625
WD		 1341
1342 /* set speed */
6e7fb6ea 1343 if (speed == _1000BASET) {
738815c0
SR		 1344#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1345 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
6e7fb6ea 1346 unsigned long pfc1;
887e2ec9 1347
6e7fb6ea
SR		 1348 mfsdr (sdr_pfc1, pfc1);
1349 pfc1 |= SDR0_PFC1_EM_1000;
1350 mtsdr (sdr_pfc1, pfc1);
1351#endif
855a496f 1352 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
6e7fb6ea 1353 } else if (speed == _100BASET)
ba56f625
WD		 1354 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
1355 else
1356 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1357 if (duplex == FULL)
1358 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1359
2d83476a 1360 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
ba56f625
WD		 1361
1362 /* Enable broadcast and indvidual address */
1363 /* TBS: enabling runts as some misbehaved nics will send runts */
2d83476a 1364 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
ba56f625
WD		 1365
1366 /* we probably need to set the tx mode1 reg? maybe at tx time */
1367
1368 /* set transmit request threshold register */
2d83476a 1369 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
ba56f625 1370
265817c7 1371 /* set receive low/high water mark register */
d6c61aab 1372#if defined(CONFIG_440)
6c5879f3 1373 /* 440s has a 64 byte burst length */
2d83476a 1374 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
d6c61aab
SR		 1375#else
1376 /* 405s have a 16 byte burst length */
2d83476a 1377 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
d6c61aab 1378#endif /* defined(CONFIG_440) */
2d83476a 1379 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
ba56f625
WD		 1380
1381 /* Set fifo limit entry in tx mode 0 */
2d83476a 1382 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
ba56f625 1383 /* Frame gap set */
2d83476a 1384 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
ba56f625
WD		 1385
1386 /* Set EMAC IER */
d6c61aab 1387 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
ba56f625
WD		 1388 if (speed == _100BASET)
1389 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1390
2d83476a
SR		 1391 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1392 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
ba56f625
WD		 1393
1394 if (hw_p->first_init == 0) {
1395 /*
1396 * Connect interrupt service routines
1397 */
dbbd1257
SR		 1398 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1399 (interrupt_handler_t *) enetInt, dev);
ba56f625 1400 }
ba56f625
WD		 1401
1402 mtmsr (msr); /* enable interrupts again */
1403
1404 hw_p->bis = bis;
1405 hw_p->first_init = 1;
1406
802b769b 1407 return 0;
ba56f625
WD		 1408}
1409
1410
d6c61aab 1411static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
ba56f625
WD		 1412 int len)
1413{
1414 struct enet_frame *ef_ptr;
1415 ulong time_start, time_now;
1416 unsigned long temp_txm0;
d6c61aab 1417 EMAC_4XX_HW_PST hw_p = dev->priv;
ba56f625
WD		 1418
1419 ef_ptr = (struct enet_frame *) ptr;
1420
1421 /*-----------------------------------------------------------------------+
1422 * Copy in our address into the frame.
1423 *-----------------------------------------------------------------------*/
1424 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1425
1426 /*-----------------------------------------------------------------------+
1427 * If frame is too long or too short, modify length.
1428 *-----------------------------------------------------------------------*/
1429 /* TBS: where does the fragment go???? */
1430 if (len > ENET_MAX_MTU)
1431 len = ENET_MAX_MTU;
1432
1433 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1434 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
ba79fde5 1435 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
ba56f625
WD		 1436
1437 /*-----------------------------------------------------------------------+
1438 * set TX Buffer busy, and send it
1439 *-----------------------------------------------------------------------*/
1440 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1441 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1442 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1443 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1444 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1445
1446 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1447 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1448
8ac41e3e 1449 sync();
ba56f625 1450
2d83476a
SR		 1451 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1452 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
d6c61aab 1453#ifdef INFO_4XX_ENET
ba56f625
WD		 1454 hw_p->stats.pkts_tx++;
1455#endif
1456
1457 /*-----------------------------------------------------------------------+
1458 * poll unitl the packet is sent and then make sure it is OK
1459 *-----------------------------------------------------------------------*/
1460 time_start = get_timer (0);
1461 while (1) {
2d83476a 1462 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
ba56f625
WD		 1463 /* loop until either TINT turns on or 3 seconds elapse */
1464 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1465 /* transmit is done, so now check for errors
1466 * If there is an error, an interrupt should
1467 * happen when we return
1468 */
1469 time_now = get_timer (0);
1470 if ((time_now - time_start) > 3000) {
1471 return (-1);
1472 }
1473 } else {
1474 return (len);
1475 }
1476 }
1477}
1478
ba56f625
WD		 1479int enetInt (struct eth_device *dev)
1480{
1481 int serviced;
1482 int rc = -1; /* default to not us */
d1631fe1
SR		 1483 u32 mal_isr;
1484 u32 emac_isr = 0;
1485 u32 mal_eob;
1486 u32 uic_mal;
1487 u32 uic_mal_err;
1488 u32 uic_emac;
1489 u32 uic_emac_b;
d6c61aab 1490 EMAC_4XX_HW_PST hw_p;
ba56f625
WD		 1491
1492 /*
1493 * Because the mal is generic, we need to get the current
1494 * eth device
1495 */
d6c61aab
SR		 1496#if defined(CONFIG_NET_MULTI)
1497 dev = eth_get_dev();
1498#else
1499 dev = emac0_dev;
1500#endif
ba56f625
WD		 1501
1502 hw_p = dev->priv;
1503
ba56f625
WD		 1504 /* enter loop that stays in interrupt code until nothing to service */
1505 do {
1506 serviced = 0;
1507
d1631fe1
SR		 1508 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
1509 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
1510 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
1511 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
887e2ec9 1512
d1631fe1
SR		 1513 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
1514 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
1515 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
ba56f625
WD		 1516 /* not for us */
1517 return (rc);
1518 }
d1631fe1 1519
ba56f625 1520 /* get and clear controller status interrupts */
d1631fe1
SR		 1521 /* look at MAL and EMAC error interrupts */
1522 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
1523 /* we have a MAL error interrupt */
1524 mal_isr = mfdcr(malesr);
1525 mal_err(dev, mal_isr, uic_mal_err,
1526 MAL_UIC_DEF, MAL_UIC_ERR);
ba56f625 1527
d1631fe1
SR		 1528 /* clear MAL error interrupt status bits */
1529 mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
1530 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
ba56f625 1531
d1631fe1 1532 return -1;
ba56f625
WD		 1533 }
1534
d1631fe1
SR		 1535 /* look for EMAC errors */
1536 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
1537 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1538 emac_err(dev, emac_isr);
6e7fb6ea 1539
d1631fe1
SR		 1540 /* clear EMAC error interrupt status bits */
1541 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
1542 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
6e7fb6ea 1543
d1631fe1 1544 return -1;
ba56f625 1545 }
d6c61aab 1546
d1631fe1
SR		 1547 /* handle MAX TX EOB interrupt from a tx */
1548 if (uic_mal & UIC_MAL_TXEOB) {
1549 /* clear MAL interrupt status bits */
1550 mal_eob = mfdcr(maltxeobisr);
1551 mtdcr(maltxeobisr, mal_eob);
1552 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
1553
1554 /* indicate that we serviced an interrupt */
1555 serviced = 1;
1556 rc = 0;
d6c61aab
SR		 1557 }
1558
d1631fe1
SR		 1559 /* handle MAL RX EOB interupt from a receive */
1560 /* check for EOB on valid channels */
1561 if (uic_mal & UIC_MAL_RXEOB) {
1562 mal_eob = mfdcr(malrxeobisr);
1563 if (mal_eob &
1564 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
1565 /* push packet to upper layer */
1566 enet_rcv(dev, emac_isr);
d6c61aab 1567
d1631fe1
SR		 1568 /* clear MAL interrupt status bits */
1569 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
d6c61aab 1570
d6c61aab
SR		 1571 /* indicate that we serviced an interrupt */
1572 serviced = 1;
1573 rc = 0;
1574 }
1575 }
d1631fe1 1576 } while (serviced);
d6c61aab
SR		 1577
1578 return (rc);
1579}
1580
ba56f625
WD		 1581/*-----------------------------------------------------------------------------+
1582 * MAL Error Routine
1583 *-----------------------------------------------------------------------------*/
1584static void mal_err (struct eth_device *dev, unsigned long isr,
1585 unsigned long uic, unsigned long maldef,
1586 unsigned long mal_errr)
1587{
d6c61aab 1588 EMAC_4XX_HW_PST hw_p = dev->priv;
ba56f625
WD		 1589
1590 mtdcr (malesr, isr); /* clear interrupt */
1591
1592 /* clear DE interrupt */
1593 mtdcr (maltxdeir, 0xC0000000);
1594 mtdcr (malrxdeir, 0x80000000);
1595
d6c61aab 1596#ifdef INFO_4XX_ENET
265817c7 1597 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
ba56f625
WD		 1598#endif
1599
1600 eth_init (hw_p->bis); /* start again... */
1601}
1602
1603/*-----------------------------------------------------------------------------+
1604 * EMAC Error Routine
1605 *-----------------------------------------------------------------------------*/
1606static void emac_err (struct eth_device *dev, unsigned long isr)
1607{
d6c61aab 1608 EMAC_4XX_HW_PST hw_p = dev->priv;
ba56f625
WD		 1609
1610 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
2d83476a 1611 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
ba56f625
WD		 1612}
1613
1614/*-----------------------------------------------------------------------------+
1615 * enet_rcv() handles the ethernet receive data
1616 *-----------------------------------------------------------------------------*/
1617static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1618{
1619 struct enet_frame *ef_ptr;
1620 unsigned long data_len;
1621 unsigned long rx_eob_isr;
d6c61aab 1622 EMAC_4XX_HW_PST hw_p = dev->priv;
ba56f625
WD		 1623
1624 int handled = 0;
1625 int i;
1626 int loop_count = 0;
1627
1628 rx_eob_isr = mfdcr (malrxeobisr);
8ac41e3e 1629 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
ba56f625
WD		 1630 /* clear EOB */
1631 mtdcr (malrxeobisr, rx_eob_isr);
1632
1633 /* EMAC RX done */
1634 while (1) { /* do all */
1635 i = hw_p->rx_slot;
1636
1637 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1638 || (loop_count >= NUM_RX_BUFF))
1639 break;
a2e1c709 1640
ba56f625 1641 loop_count++;
ba56f625 1642 handled++;
8ac41e3e 1643 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
ba56f625
WD		 1644 if (data_len) {
1645 if (data_len > ENET_MAX_MTU) /* Check len */
1646 data_len = 0;
1647 else {
1648 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1649 data_len = 0;
1650 hw_p->stats.rx_err_log[hw_p->
1651 rx_err_index]
1652 = hw_p->rx[i].ctrl;
1653 hw_p->rx_err_index++;
1654 if (hw_p->rx_err_index ==
1655 MAX_ERR_LOG)
1656 hw_p->rx_err_index =
1657 0;
fc1cfcdb 1658 } /* emac_erros */
ba56f625 1659 } /* data_len < max mtu */
fc1cfcdb 1660 } /* if data_len */
ba56f625
WD		 1661 if (!data_len) { /* no data */
1662 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1663
1664 hw_p->stats.data_len_err++; /* Error at Rx */
1665 }
1666
1667 /* !data_len */
1668 /* AS.HARNOIS */
1669 /* Check if user has already eaten buffer */
1670 /* if not => ERROR */
1671 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1672 if (hw_p->is_receiving)
1673 printf ("ERROR : Receive buffers are full!\n");
1674 break;
1675 } else {
1676 hw_p->stats.rx_frames++;
1677 hw_p->stats.rx += data_len;
1678 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1679 data_ptr;
d6c61aab 1680#ifdef INFO_4XX_ENET
ba56f625
WD		 1681 hw_p->stats.pkts_rx++;
1682#endif
1683 /* AS.HARNOIS
1684 * use ring buffer
1685 */
1686 hw_p->rx_ready[hw_p->rx_i_index] = i;
1687 hw_p->rx_i_index++;
1688 if (NUM_RX_BUFF == hw_p->rx_i_index)
1689 hw_p->rx_i_index = 0;
1690
a2e1c709
SR		 1691 hw_p->rx_slot++;
1692 if (NUM_RX_BUFF == hw_p->rx_slot)
1693 hw_p->rx_slot = 0;
1694
ba56f625
WD		 1695 /* AS.HARNOIS
1696 * free receive buffer only when
1697 * buffer has been handled (eth_rx)
1698 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1699 */
1700 } /* if data_len */
1701 } /* while */
1702 } /* if EMACK_RXCHL */
1703}
1704
1705
d6c61aab 1706static int ppc_4xx_eth_rx (struct eth_device *dev)
ba56f625
WD		 1707{
1708 int length;
1709 int user_index;
1710 unsigned long msr;
d6c61aab 1711 EMAC_4XX_HW_PST hw_p = dev->priv;
ba56f625 1712
265817c7 1713 hw_p->is_receiving = 1; /* tell driver */
ba56f625
WD		 1714
1715 for (;;) {
1716 /* AS.HARNOIS
1717 * use ring buffer and
1718 * get index from rx buffer desciptor queue
1719 */
1720 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1721 if (user_index == -1) {
1722 length = -1;
1723 break; /* nothing received - leave for() loop */
1724 }
1725
1726 msr = mfmsr ();
1727 mtmsr (msr & ~(MSR_EE));
1728
8ac41e3e 1729 length = hw_p->rx[user_index].data_len & 0x0fff;
ba56f625
WD		 1730
1731 /* Pass the packet up to the protocol layers. */
265817c7
WD		 1732 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1733 /* NetReceive(NetRxPackets[i], length); */
ff768cb1
SR		 1734 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1735 (u32)hw_p->rx[user_index].data_ptr +
ba79fde5 1736 length - 4);
ba56f625
WD		 1737 NetReceive (NetRxPackets[user_index], length - 4);
1738 /* Free Recv Buffer */
1739 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1740 /* Free rx buffer descriptor queue */
1741 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1742 hw_p->rx_u_index++;
1743 if (NUM_RX_BUFF == hw_p->rx_u_index)
1744 hw_p->rx_u_index = 0;
1745
d6c61aab 1746#ifdef INFO_4XX_ENET
ba56f625
WD		 1747 hw_p->stats.pkts_handled++;
1748#endif
1749
1750 mtmsr (msr); /* Enable IRQ's */
1751 }
1752
265817c7 1753 hw_p->is_receiving = 0; /* tell driver */
ba56f625
WD		 1754
1755 return length;
1756}
1757
d6c61aab 1758int ppc_4xx_eth_initialize (bd_t * bis)
ba56f625
WD		 1759{
1760 static int virgin = 0;
ba56f625
WD		 1761 struct eth_device *dev;
1762 int eth_num = 0;
d6c61aab 1763 EMAC_4XX_HW_PST hw = NULL;
5fb692ca
SR		 1764 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1765 u32 hw_addr[4];
d1631fe1 1766 u32 mal_ier;
ba56f625 1767
846b0dd2 1768#if defined(CONFIG_440GX)
c157d8e2
SR		 1769 unsigned long pfc1;
1770
ba56f625
WD		 1771 mfsdr (sdr_pfc1, pfc1);
1772 pfc1 &= ~(0x01e00000);
1773 pfc1 |= 0x01200000;
1774 mtsdr (sdr_pfc1, pfc1);
c157d8e2 1775#endif
6c5879f3 1776
5fb692ca
SR		 1777 /* first clear all mac-addresses */
1778 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1779 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
a06752e3 1780
1e25f957 1781 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
ba56f625 1782 switch (eth_num) {
e2ffd59b 1783 default: /* fall through */
ba56f625 1784 case 0:
5fb692ca
SR		 1785 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1786 bis->bi_enetaddr, 6);
1787 hw_addr[eth_num] = 0x0;
ba56f625 1788 break;
e2ffd59b 1789#ifdef CONFIG_HAS_ETH1
ba56f625 1790 case 1:
5fb692ca
SR		 1791 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1792 bis->bi_enet1addr, 6);
1793 hw_addr[eth_num] = 0x100;
ba56f625 1794 break;
e2ffd59b
WD		 1795#endif
1796#ifdef CONFIG_HAS_ETH2
ba56f625 1797 case 2:
5fb692ca
SR		 1798 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1799 bis->bi_enet2addr, 6);
4c9e8557
SR		 1800#if defined(CONFIG_460GT)
1801 hw_addr[eth_num] = 0x300;
1802#else
5fb692ca 1803 hw_addr[eth_num] = 0x400;
4c9e8557 1804#endif
ba56f625 1805 break;
e2ffd59b
WD		 1806#endif
1807#ifdef CONFIG_HAS_ETH3
ba56f625 1808 case 3:
5fb692ca
SR		 1809 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1810 bis->bi_enet3addr, 6);
4c9e8557
SR		 1811#if defined(CONFIG_460GT)
1812 hw_addr[eth_num] = 0x400;
1813#else
5fb692ca 1814 hw_addr[eth_num] = 0x600;
4c9e8557 1815#endif
ba56f625 1816 break;
e2ffd59b 1817#endif
ba56f625 1818 }
5fb692ca
SR		 1819 }
1820
1821 /* set phy num and mode */
1822 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1823 bis->bi_phymode[0] = 0;
1824
1825#if defined(CONFIG_PHY1_ADDR)
1826 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1827 bis->bi_phymode[1] = 0;
1828#endif
1829#if defined(CONFIG_440GX)
1830 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1831 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1832 bis->bi_phymode[2] = 2;
1833 bis->bi_phymode[3] = 2;
dbbd1257 1834#endif
5fb692ca 1835
dbbd1257
SR		 1836#if defined(CONFIG_440GX) || \
1837 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1838 defined(CONFIG_405EX)
5fb692ca
SR		 1839 ppc_4xx_eth_setup_bridge(0, bis);
1840#endif
1841
1842 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1843 /*
1844 * See if we can actually bring up the interface,
1845 * otherwise, skip it
1846 */
1847 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1848 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1849 continue;
1850 }
ba56f625
WD		 1851
1852 /* Allocate device structure */
1853 dev = (struct eth_device *) malloc (sizeof (*dev));
1854 if (dev == NULL) {
d6c61aab 1855 printf ("ppc_4xx_eth_initialize: "
3f85ce27 1856 "Cannot allocate eth_device %d\n", eth_num);
ba56f625
WD		 1857 return (-1);
1858 }
b2532eff 1859 memset(dev, 0, sizeof(*dev));
ba56f625
WD		 1860
1861 /* Allocate our private use data */
d6c61aab 1862 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
ba56f625 1863 if (hw == NULL) {
d6c61aab 1864 printf ("ppc_4xx_eth_initialize: "
3f85ce27 1865 "Cannot allocate private hw data for eth_device %d",
ba56f625
WD		 1866 eth_num);
1867 free (dev);
1868 return (-1);
1869 }
b2532eff 1870 memset(hw, 0, sizeof(*hw));
ba56f625 1871
5fb692ca
SR		 1872 hw->hw_addr = hw_addr[eth_num];
1873 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
ba56f625 1874 hw->devnum = eth_num;
c157d8e2 1875 hw->print_speed = 1;
ba56f625 1876
5fb692ca 1877 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
ba56f625 1878 dev->priv = (void *) hw;
d6c61aab
SR		 1879 dev->init = ppc_4xx_eth_init;
1880 dev->halt = ppc_4xx_eth_halt;
1881 dev->send = ppc_4xx_eth_send;
1882 dev->recv = ppc_4xx_eth_rx;
ba56f625
WD		 1883
1884 if (0 == virgin) {
1885 /* set the MAL IER ??? names may change with new spec ??? */
dbbd1257
SR		 1886#if defined(CONFIG_440SPE) || \
1887 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
8ac41e3e 1888 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
dbbd1257 1889 defined(CONFIG_405EX)
6c5879f3
MB		 1890 mal_ier =
1891 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1892 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1893#else
ba56f625
WD		 1894 mal_ier =
1895 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1896 MAL_IER_OPBE | MAL_IER_PLBE;
6c5879f3 1897#endif
ba56f625
WD		 1898 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1899 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1900 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1901 mtdcr (malier, mal_ier);
1902
1903 /* install MAL interrupt handler */
d1631fe1 1904 irq_install_handler (VECNUM_MAL_SERR,
ba56f625
WD		 1905 (interrupt_handler_t *) enetInt,
1906 dev);
d1631fe1 1907 irq_install_handler (VECNUM_MAL_TXEOB,
ba56f625
WD		 1908 (interrupt_handler_t *) enetInt,
1909 dev);
d1631fe1 1910 irq_install_handler (VECNUM_MAL_RXEOB,
ba56f625
WD		 1911 (interrupt_handler_t *) enetInt,
1912 dev);
d1631fe1 1913 irq_install_handler (VECNUM_MAL_TXDE,
ba56f625
WD		 1914 (interrupt_handler_t *) enetInt,
1915 dev);
d1631fe1 1916 irq_install_handler (VECNUM_MAL_RXDE,
ba56f625
WD		 1917 (interrupt_handler_t *) enetInt,
1918 dev);
1919 virgin = 1;
1920 }
1921
d6c61aab 1922#if defined(CONFIG_NET_MULTI)
ba56f625 1923 eth_register (dev);
d6c61aab
SR		 1924#else
1925 emac0_dev = dev;
1926#endif
6c5879f3
MB		 1927
1928#if defined(CONFIG_NET_MULTI)
3a1ed1e1 1929#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
63ff004c 1930 miiphy_register (dev->name,
6e7fb6ea 1931 emac4xx_miiphy_read, emac4xx_miiphy_write);
63ff004c 1932#endif
6c5879f3 1933#endif
ba56f625 1934 } /* end for each supported device */
802b769b
SR		 1935
1936 return 0;
ba56f625 1937}
d6c61aab 1938
d6c61aab
SR		 1939#if !defined(CONFIG_NET_MULTI)
1940void eth_halt (void) {
1941 if (emac0_dev) {
1942 ppc_4xx_eth_halt(emac0_dev);
1943 free(emac0_dev);
1944 emac0_dev = NULL;
1945 }
1946}
1947
1948int eth_init (bd_t *bis)
1949{
1950 ppc_4xx_eth_initialize(bis);
4f92ac36
SR		 1951 if (emac0_dev) {
1952 return ppc_4xx_eth_init(emac0_dev, bis);
1953 } else {
1954 printf("ERROR: ethaddr not set!\n");
1955 return -1;
1956 }
d6c61aab
SR		 1957}
1958
1959int eth_send(volatile void *packet, int length)
1960{
d6c61aab
SR		 1961 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1962}
1963
1964int eth_rx(void)
1965{
1966 return (ppc_4xx_eth_rx(emac0_dev));
1967}
63ff004c
MB		 1968
1969int emac4xx_miiphy_initialize (bd_t * bis)
1970{
3a1ed1e1 1971#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
63ff004c 1972 miiphy_register ("ppc_4xx_eth0",
6e7fb6ea 1973 emac4xx_miiphy_read, emac4xx_miiphy_write);
63ff004c
MB		 1974#endif
1975
1976 return 0;
1977}
d6c61aab
SR		 1978#endif /* !defined(CONFIG_NET_MULTI) */
1979
3a1ed1e1 1980#endif
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