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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
b940ca64 2/*
a6f2a6ea 3 * Copyright 2014 Freescale Semiconductor, Inc.
669884ea 4 * Copyright 2017-2018, 2020-2021 NXP
b940ca64 5 */
d678a59d 6#include <common.h>
288b29e4 7#include <command.h>
1eb69ae4 8#include <cpu_func.h>
7b51b576 9#include <env.h>
b940ca64 10#include <errno.h>
4d72caa5 11#include <image.h>
f7ae49fc 12#include <log.h>
336d4615 13#include <malloc.h>
ed06772a 14#include <mapmem.h>
401d1c4f 15#include <asm/global_data.h>
84b8bf6d 16#include <linux/bug.h>
b940ca64 17#include <asm/io.h>
c05ed00a 18#include <linux/delay.h>
b08c8c48 19#include <linux/libfdt.h>
5707dfb0 20#include <net.h>
21c69870 21#include <fdt_support.h>
7b3bd9a7
GR
22#include <fsl-mc/fsl_mc.h>
23#include <fsl-mc/fsl_mc_sys.h>
a2a55e51 24#include <fsl-mc/fsl_mc_private.h>
7b3bd9a7 25#include <fsl-mc/fsl_dpmng.h>
a2a55e51
PK
26#include <fsl-mc/fsl_dprc.h>
27#include <fsl-mc/fsl_dpio.h>
fb4a87a7 28#include <fsl-mc/fsl_dpni.h>
1990cc7d 29#include <fsl-mc/fsl_dpsparser.h>
a2a55e51 30#include <fsl-mc/fsl_qbman_portal.h>
fb4a87a7 31#include <fsl-mc/ldpaa_wriop.h>
8491a7e4 32#include <net/ldpaa_eth.h>
1dd7b566
LT
33#include <asm/arch/cpu.h>
34#include <asm/arch-fsl-layerscape/fsl_icid.h>
b940ca64 35
125e2bc1
GR
36#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
37#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK (~(MC_RAM_BASE_ADDR_ALIGNMENT - 1))
38#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
39
40#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
41#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
33a8991a 42#define MC_BOOT_ENV_VAR "mcinitcmd"
43ad41e6 43#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
125e2bc1 44
ed06772a
CFA
45#define MC_BUFFER_SIZE (1024 * 1024 * 16)
46#define MAGIC_MC 0x4d430100
47#define MC_FW_ADDR_MASK_LOW 0xE0000000
48#define MC_FW_ADDR_MASK_HIGH 0X1FFFF
49#define MC_STRUCT_BUFFER_OFFSET 0x01000000
50#define MC_OFFSET_DELTA MC_STRUCT_BUFFER_OFFSET
51
52#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x80000000
53#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND))
54
b940ca64 55DECLARE_GLOBAL_DATA_PTR;
87519a9e 56static int mc_memset_resv_ram;
1990cc7d 57static struct mc_version mc_ver_info;
fb4a87a7
PK
58static int mc_boot_status = -1;
59static int mc_dpl_applied = -1;
65cc0e2a 60#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
fb4a87a7
PK
61static int mc_aiop_applied = -1;
62#endif
1730a17d
PK
63struct fsl_mc_io *root_mc_io = NULL;
64struct fsl_mc_io *dflt_mc_io = NULL; /* child container */
65uint16_t root_dprc_handle = 0;
a2a55e51 66uint16_t dflt_dprc_handle = 0;
1730a17d 67int child_dprc_id;
a2a55e51
PK
68struct fsl_dpbp_obj *dflt_dpbp = NULL;
69struct fsl_dpio_obj *dflt_dpio = NULL;
1730a17d 70struct fsl_dpni_obj *dflt_dpni = NULL;
b7b8410a 71static u64 mc_lazy_dpl_addr;
1990cc7d
FI
72static u32 dpsparser_obj_id;
73static u16 dpsparser_handle;
74static char *mc_err_msg_apply_spb[] = MC_ERROR_MSG_APPLY_SPB;
125e2bc1
GR
75
76#ifdef DEBUG
77void dump_ram_words(const char *title, void *addr)
78{
79 int i;
80 uint32_t *words = addr;
81
82 printf("Dumping beginning of %s (%p):\n", title, addr);
83 for (i = 0; i < 16; i++)
84 printf("%#x ", words[i]);
85
86 printf("\n");
87}
b940ca64 88
125e2bc1
GR
89void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs)
90{
91 printf("MC CCSR registers:\n"
92 "reg_gcr1 %#x\n"
93 "reg_gsr %#x\n"
94 "reg_sicbalr %#x\n"
95 "reg_sicbahr %#x\n"
96 "reg_sicapr %#x\n"
97 "reg_mcfbalr %#x\n"
98 "reg_mcfbahr %#x\n"
99 "reg_mcfapr %#x\n"
100 "reg_psr %#x\n",
101 mc_ccsr_regs->reg_gcr1,
102 mc_ccsr_regs->reg_gsr,
103 mc_ccsr_regs->reg_sicbalr,
104 mc_ccsr_regs->reg_sicbahr,
105 mc_ccsr_regs->reg_sicapr,
106 mc_ccsr_regs->reg_mcfbalr,
107 mc_ccsr_regs->reg_mcfbahr,
108 mc_ccsr_regs->reg_mcfapr,
109 mc_ccsr_regs->reg_psr);
110}
111#else
112
113#define dump_ram_words(title, addr)
114#define dump_mc_ccsr_regs(mc_ccsr_regs)
115
116#endif /* DEBUG */
117
b940ca64
GR
118/**
119 * Copying MC firmware or DPL image to DDR
120 */
121static int mc_copy_image(const char *title,
7b3bd9a7 122 u64 image_addr, u32 image_size, u64 mc_ram_addr)
b940ca64
GR
123{
124 debug("%s copied to address %p\n", title, (void *)mc_ram_addr);
125 memcpy((void *)mc_ram_addr, (void *)image_addr, image_size);
125e2bc1 126 flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size);
b940ca64
GR
127 return 0;
128}
129
1990cc7d 130#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
b940ca64
GR
131/**
132 * MC firmware FIT image parser checks if the image is in FIT
133 * format, verifies integrity of the image and calculates
134 * raw image address and size values.
7b3bd9a7 135 * Returns 0 on success and a negative errno on error.
b940ca64
GR
136 * task fail.
137 **/
fb4a87a7
PK
138int parse_mc_firmware_fit_image(u64 mc_fw_addr,
139 const void **raw_image_addr,
b940ca64
GR
140 size_t *raw_image_size)
141{
142 int format;
f1061c57 143 void *fit_hdr = (void *)mc_fw_addr;
b940ca64
GR
144
145 /* Check if Image is in FIT format */
146 format = genimg_get_format(fit_hdr);
147
148 if (format != IMAGE_FORMAT_FIT) {
fb4a87a7 149 printf("fsl-mc: ERR: Bad firmware image (not a FIT image)\n");
7b3bd9a7 150 return -EINVAL;
b940ca64
GR
151 }
152
c5819701 153 if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
fb4a87a7 154 printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
7b3bd9a7 155 return -EINVAL;
b940ca64
GR
156 }
157
f1061c57
SA
158 return fit_get_data_node(fit_hdr, "firmware", raw_image_addr,
159 raw_image_size);
b940ca64 160}
125e2bc1
GR
161#endif
162
1161dbcc
BP
163#define MC_DT_INCREASE_SIZE 64
164
165enum mc_fixup_type {
166 MC_FIXUP_DPL,
167 MC_FIXUP_DPC
168};
169
170static int mc_fixup_mac_addr(void *blob, int nodeoffset,
988e33f8 171 const char *propname, struct udevice *eth_dev,
1161dbcc 172 enum mc_fixup_type type)
5707dfb0 173{
c69cda25 174 struct eth_pdata *plat = dev_get_plat(eth_dev);
988e33f8 175 unsigned char *enetaddr = plat->enetaddr;
8b85dfc6 176 int eth_index = dev_seq(eth_dev);
1161dbcc
BP
177 int err = 0, len = 0, size, i;
178 unsigned char env_enetaddr[ARP_HLEN];
179 unsigned int enetaddr_32[ARP_HLEN];
180 void *val = NULL;
181
182 switch (type) {
183 case MC_FIXUP_DPL:
988e33f8
IC
184 /* DPL likes its addresses on 32 * ARP_HLEN bits */
185 for (i = 0; i < ARP_HLEN; i++)
186 enetaddr_32[i] = cpu_to_fdt32(enetaddr[i]);
187 val = enetaddr_32;
188 len = sizeof(enetaddr_32);
189 break;
1161dbcc 190 case MC_FIXUP_DPC:
988e33f8
IC
191 val = enetaddr;
192 len = ARP_HLEN;
193 break;
1161dbcc
BP
194 }
195
196 /* MAC address property present */
197 if (fdt_get_property(blob, nodeoffset, propname, NULL)) {
198 /* u-boot MAC addr randomly assigned - leave the present one */
988e33f8 199 if (!eth_env_get_enetaddr_by_index("eth", eth_index,
35affd7a 200 env_enetaddr))
1161dbcc
BP
201 return err;
202 } else {
203 size = MC_DT_INCREASE_SIZE + strlen(propname) + len;
204 /* make room for mac address property */
205 err = fdt_increase_size(blob, size);
206 if (err) {
207 printf("fdt_increase_size: err=%s\n",
208 fdt_strerror(err));
209 return err;
210 }
211 }
212
213 err = fdt_setprop(blob, nodeoffset, propname, val, len);
214 if (err) {
215 printf("fdt_setprop: err=%s\n", fdt_strerror(err));
216 return err;
217 }
218
219 return err;
220}
221
222#define is_dpni(s) (s != NULL ? !strncmp(s, "dpni@", 5) : 0)
223
224const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
225{
226 int connoffset = fdt_path_offset(blob, "/connections"), off;
227 const char *s1, *s2;
228
229 for (off = fdt_first_subnode(blob, connoffset);
230 off >= 0;
231 off = fdt_next_subnode(blob, off)) {
232 s1 = fdt_stringlist_get(blob, off, "endpoint1", 0, NULL);
233 s2 = fdt_stringlist_get(blob, off, "endpoint2", 0, NULL);
234
235 if (!s1 || !s2)
236 continue;
237
238 if (strcmp(endpoint, s1) == 0)
239 return s2;
240
241 if (strcmp(endpoint, s2) == 0)
242 return s1;
243 }
244
245 return NULL;
246}
247
248static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
988e33f8 249 struct udevice *eth_dev)
1161dbcc
BP
250{
251 int objoff = fdt_path_offset(blob, "/objects");
252 int dpmacoff = -1, dpnioff = -1;
253 const char *endpoint;
254 char mac_name[10];
255 int err;
256
257 sprintf(mac_name, "dpmac@%d", dpmac_id);
258 dpmacoff = fdt_subnode_offset(blob, objoff, mac_name);
259 if (dpmacoff < 0)
260 /* dpmac not defined in DPL, so skip it. */
261 return 0;
262
263 err = mc_fixup_mac_addr(blob, dpmacoff, "mac_addr", eth_dev,
264 MC_FIXUP_DPL);
265 if (err) {
266 printf("Error fixing up dpmac mac_addr in DPL\n");
267 return err;
268 }
269
270 /* now we need to figure out if there is any
271 * DPNI connected to this MAC, so we walk the
272 * connection list
273 */
274 endpoint = dpl_get_connection_endpoint(blob, mac_name);
275 if (!is_dpni(endpoint))
276 return 0;
277
278 /* let's see if we can fixup the DPNI as well */
279 dpnioff = fdt_subnode_offset(blob, objoff, endpoint);
280 if (dpnioff < 0)
281 /* DPNI not defined in DPL in the objects area */
282 return 0;
283
284 return mc_fixup_mac_addr(blob, dpnioff, "mac_addr", eth_dev,
285 MC_FIXUP_DPL);
286}
287
cf0bbbd1
MA
288void fdt_fixup_mc_ddr(u64 *base, u64 *size)
289{
290 u64 mc_size = mc_get_dram_block_size();
291
292 if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
293 *base = mc_get_dram_addr() + mc_size;
294 *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
295 }
296}
297
a78df40c
NG
298void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
299{
300 u32 *prop;
21a00d13 301 u32 iommu_map[4], phandle;
a78df40c
NG
302 int offset;
303 int lenp;
304
305 /* find fsl-mc node */
306 offset = fdt_path_offset(blob, "/soc/fsl-mc");
307 if (offset < 0)
308 offset = fdt_path_offset(blob, "/fsl-mc");
309 if (offset < 0) {
310 printf("%s: fsl-mc: ERR: fsl-mc node not found in DT, err %d\n",
311 __func__, offset);
312 return;
313 }
314
315 prop = fdt_getprop_w(blob, offset, "iommu-map", &lenp);
316 if (!prop) {
317 debug("%s: fsl-mc: ERR: missing iommu-map in fsl-mc bus node\n",
318 __func__);
319 return;
320 }
321
322 iommu_map[0] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
323 iommu_map[1] = *++prop;
324 iommu_map[2] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_START);
325 iommu_map[3] = cpu_to_fdt32(FSL_DPAA2_STREAM_ID_END -
326 FSL_DPAA2_STREAM_ID_START + 1);
327
328 fdt_setprop_inplace(blob, offset, "iommu-map",
329 iommu_map, sizeof(iommu_map));
21a00d13
LT
330
331 /* get phandle to MSI controller */
332 prop = (u32 *)fdt_getprop(blob, offset, "msi-parent", 0);
333 if (!prop) {
334 debug("\n%s: ERROR: missing msi-parent\n", __func__);
335 return;
336 }
337 phandle = fdt32_to_cpu(*prop);
338
339 /* also set msi-map property */
340 fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
341 fdt_appendprop_u32(blob, offset, "msi-map", phandle);
342 fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START);
343 fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_END -
344 FSL_DPAA2_STREAM_ID_START + 1);
a78df40c
NG
345}
346
1161dbcc 347static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
988e33f8 348 struct udevice *eth_dev)
1161dbcc
BP
349{
350 int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
351 int err = 0;
5707dfb0 352 char mac_name[10];
1161dbcc 353 const char link_type_mode[] = "MAC_LINK_TYPE_FIXED";
5707dfb0
BP
354
355 sprintf(mac_name, "mac@%d", dpmac_id);
356
357 /* node not found - create it */
1161dbcc
BP
358 noff = fdt_subnode_offset(blob, nodeoffset, (const char *)mac_name);
359 if (noff < 0) {
5707dfb0
BP
360 err = fdt_increase_size(blob, 200);
361 if (err) {
f45ed0b5 362 printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
5707dfb0
BP
363 return err;
364 }
365
1161dbcc
BP
366 noff = fdt_add_subnode(blob, nodeoffset, mac_name);
367 if (noff < 0) {
368 printf("fdt_add_subnode: err=%s\n",
369 fdt_strerror(err));
370 return err;
371 }
5707dfb0
BP
372
373 /* add default property of fixed link */
1161dbcc 374 err = fdt_appendprop_string(blob, noff,
5707dfb0
BP
375 "link_type", link_type_mode);
376 if (err) {
377 printf("fdt_appendprop_string: err=%s\n",
f45ed0b5 378 fdt_strerror(err));
5707dfb0
BP
379 return err;
380 }
381 }
382
1161dbcc
BP
383 return mc_fixup_mac_addr(blob, noff, "port_mac_address", eth_dev,
384 MC_FIXUP_DPC);
385}
5707dfb0 386
1161dbcc
BP
387static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
388{
988e33f8 389 struct udevice *eth_dev;
8491a7e4
IC
390 int err = 0, ret = 0;
391 struct uclass *uc;
392 uint32_t dpmac_id;
393
394 uclass_get(UCLASS_ETH, &uc);
395 uclass_foreach_dev(eth_dev, uc) {
396 if (!eth_dev->driver || !eth_dev->driver->name ||
397 strcmp(eth_dev->driver->name, LDPAA_ETH_DRIVER_NAME))
1161dbcc
BP
398 continue;
399
8491a7e4 400 dpmac_id = ldpaa_eth_get_dpmac_id(eth_dev);
1161dbcc
BP
401 switch (type) {
402 case MC_FIXUP_DPL:
8491a7e4 403 err = mc_fixup_dpl_mac_addr(blob, dpmac_id, eth_dev);
1161dbcc
BP
404 break;
405 case MC_FIXUP_DPC:
8491a7e4 406 err = mc_fixup_dpc_mac_addr(blob, dpmac_id, eth_dev);
1161dbcc
BP
407 break;
408 default:
409 break;
410 }
411
412 if (err)
8491a7e4 413 printf("fsl-mc: ERROR fixing mac address for %s\n", eth_dev->name);
1161dbcc 414 ret |= err;
5707dfb0
BP
415 }
416
1161dbcc 417 return ret;
5707dfb0
BP
418}
419
21c69870
SY
420static int mc_fixup_dpc(u64 dpc_addr)
421{
422 void *blob = (void *)dpc_addr;
5707dfb0 423 int nodeoffset, err = 0;
21c69870
SY
424
425 /* delete any existing ICID pools */
426 nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
427 if (fdt_del_node(blob, nodeoffset) < 0)
428 printf("\nfsl-mc: WARNING: could not delete ICID pool\n");
429
430 /* add a new pool */
431 nodeoffset = fdt_path_offset(blob, "/resources");
432 if (nodeoffset < 0) {
433 printf("\nfsl-mc: ERROR: DPC is missing /resources\n");
434 return -EINVAL;
435 }
436 nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pools");
437 nodeoffset = fdt_add_subnode(blob, nodeoffset, "icid_pool@0");
438 do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
439 "base_icid", FSL_DPAA2_STREAM_ID_START, 1);
440 do_fixup_by_path_u32(blob, "/resources/icid_pools/icid_pool@0",
441 "num",
442 FSL_DPAA2_STREAM_ID_END -
443 FSL_DPAA2_STREAM_ID_START + 1, 1);
444
5707dfb0
BP
445 /* fixup MAC addresses for dpmac ports */
446 nodeoffset = fdt_path_offset(blob, "/board_info/ports");
d5b0af04
RIC
447 if (nodeoffset < 0) {
448 err = fdt_increase_size(blob, 512);
449 if (err) {
450 printf("fdt_increase_size: err=%s\n",
451 fdt_strerror(err));
452 goto out;
453 }
454 nodeoffset = fdt_path_offset(blob, "/board_info");
455 if (nodeoffset < 0)
456 nodeoffset = fdt_add_subnode(blob, 0, "board_info");
457
458 nodeoffset = fdt_add_subnode(blob, nodeoffset, "ports");
459 }
5707dfb0 460
1161dbcc 461 err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
2e9f1bf5
ICR
462
463out:
21c69870
SY
464 flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
465
5707dfb0 466 return err;
21c69870
SY
467}
468
fb4a87a7 469static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)
125e2bc1
GR
470{
471 u64 mc_dpc_offset;
472#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
473 int error;
474 void *dpc_fdt_hdr;
475 int dpc_size;
476#endif
477
65cc0e2a
TR
478#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET
479 BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 ||
480 CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff);
125e2bc1 481
65cc0e2a 482 mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET;
125e2bc1 483#else
65cc0e2a 484#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined"
125e2bc1
GR
485#endif
486
487 /*
488 * Load the MC DPC blob in the MC private DRAM block:
489 */
490#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
491 printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset);
492#else
493 /*
494 * Get address and size of the DPC blob stored in flash:
495 */
fb4a87a7 496 dpc_fdt_hdr = (void *)mc_dpc_addr;
125e2bc1
GR
497
498 error = fdt_check_header(dpc_fdt_hdr);
499 if (error != 0) {
500 /*
501 * Don't return with error here, since the MC firmware can
502 * still boot without a DPC
503 */
cc088c3a 504 printf("\nfsl-mc: WARNING: No DPC image found");
125e2bc1
GR
505 return 0;
506 }
507
508 dpc_size = fdt_totalsize(dpc_fdt_hdr);
65cc0e2a 509 if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) {
cc088c3a 510 printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n",
125e2bc1
GR
511 dpc_size);
512 return -EINVAL;
513 }
514
515 mc_copy_image("MC DPC blob",
516 (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset);
517#endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */
518
21c69870
SY
519 if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset))
520 return -EINVAL;
521
125e2bc1
GR
522 dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset));
523 return 0;
524}
525
1161dbcc
BP
526static int mc_fixup_dpl(u64 dpl_addr)
527{
528 void *blob = (void *)dpl_addr;
529 u32 ver = fdt_getprop_u32_default(blob, "/", "dpl-version", 0);
530 int err = 0;
531
532 /* The DPL fixup for mac addresses is only relevant
533 * for old-style DPLs
534 */
535 if (ver >= 10)
536 return 0;
537
538 err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPL);
539 flush_dcache_range(dpl_addr, dpl_addr + fdt_totalsize(blob));
540
541 return err;
542}
543
fb4a87a7 544static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr)
125e2bc1
GR
545{
546 u64 mc_dpl_offset;
547#ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR
548 int error;
549 void *dpl_fdt_hdr;
550 int dpl_size;
551#endif
552
65cc0e2a
TR
553#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET
554 BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 ||
555 CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff);
125e2bc1 556
65cc0e2a 557 mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET;
125e2bc1 558#else
65cc0e2a 559#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined"
125e2bc1
GR
560#endif
561
562 /*
563 * Load the MC DPL blob in the MC private DRAM block:
564 */
565#ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR
566 printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset);
567#else
568 /*
569 * Get address and size of the DPL blob stored in flash:
570 */
fb4a87a7 571 dpl_fdt_hdr = (void *)mc_dpl_addr;
125e2bc1
GR
572
573 error = fdt_check_header(dpl_fdt_hdr);
574 if (error != 0) {
cc088c3a 575 printf("\nfsl-mc: ERROR: Bad DPL image (bad header)\n");
125e2bc1
GR
576 return error;
577 }
578
579 dpl_size = fdt_totalsize(dpl_fdt_hdr);
65cc0e2a 580 if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) {
cc088c3a 581 printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n",
125e2bc1
GR
582 dpl_size);
583 return -EINVAL;
584 }
585
586 mc_copy_image("MC DPL blob",
587 (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset);
588#endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */
589
1161dbcc
BP
590 if (mc_fixup_dpl(mc_ram_addr + mc_dpl_offset))
591 return -EINVAL;
125e2bc1
GR
592 dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset));
593 return 0;
594}
595
596/**
597 * Return the MC boot timeout value in milliseconds
598 */
599static unsigned long get_mc_boot_timeout_ms(void)
600{
65cc0e2a 601 unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
125e2bc1 602
00caae6d 603 char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR);
125e2bc1
GR
604
605 if (timeout_ms_env_var) {
0b1284eb 606 timeout_ms = dectoul(timeout_ms_env_var, NULL);
125e2bc1
GR
607 if (timeout_ms == 0) {
608 printf("fsl-mc: WARNING: Invalid value for \'"
609 MC_BOOT_TIMEOUT_ENV_VAR
610 "\' environment variable: %lu\n",
611 timeout_ms);
612
65cc0e2a 613 timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS;
125e2bc1
GR
614 }
615 }
616
617 return timeout_ms;
618}
619
65cc0e2a 620#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
3c1d218a
YS
621
622__weak bool soc_has_aiop(void)
623{
624 return false;
625}
626
fb4a87a7 627static int load_mc_aiop_img(u64 aiop_fw_addr)
c1000c12 628{
fb4a87a7
PK
629 u64 mc_ram_addr = mc_get_dram_addr();
630#ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR
c1000c12 631 void *aiop_img;
fb4a87a7 632#endif
c1000c12 633
3c1d218a
YS
634 /* Check if AIOP is available */
635 if (!soc_has_aiop())
636 return -ENODEV;
c1000c12
GR
637 /*
638 * Load the MC AIOP image in the MC private DRAM block:
639 */
640
fb4a87a7
PK
641#ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR
642 printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr +
65cc0e2a 643 CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
fb4a87a7
PK
644#else
645 aiop_img = (void *)aiop_fw_addr;
c1000c12 646 mc_copy_image("MC AIOP image",
65cc0e2a
TR
647 (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH,
648 mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET);
fb4a87a7
PK
649#endif
650 mc_aiop_applied = 0;
c1000c12
GR
651
652 return 0;
653}
654#endif
fb4a87a7 655
125e2bc1
GR
656static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr)
657{
658 u32 reg_gsr;
659 u32 mc_fw_boot_status;
660 unsigned long timeout_ms = get_mc_boot_timeout_ms();
661 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
662
663 dmb();
125e2bc1
GR
664 assert(timeout_ms > 0);
665 for (;;) {
666 udelay(1000); /* throttle polling */
667 reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr);
668 mc_fw_boot_status = (reg_gsr & GSR_FS_MASK);
669 if (mc_fw_boot_status & 0x1)
670 break;
671
672 timeout_ms--;
673 if (timeout_ms == 0)
674 break;
675 }
676
677 if (timeout_ms == 0) {
cc088c3a 678 printf("ERROR: timeout\n");
125e2bc1
GR
679
680 /* TODO: Get an error status from an MC CCSR register */
681 return -ETIMEDOUT;
682 }
683
684 if (mc_fw_boot_status != 0x1) {
685 /*
686 * TODO: Identify critical errors from the GSR register's FS
687 * field and for those errors, set error to -ENODEV or other
688 * appropriate errno, so that the status property is set to
689 * failure in the fsl,dprc device tree node.
690 */
cc088c3a
GR
691 printf("WARNING: Firmware returned an error (GSR: %#x)\n",
692 reg_gsr);
693 } else {
694 printf("SUCCESS\n");
125e2bc1
GR
695 }
696
697 *final_reg_gsr = reg_gsr;
698 return 0;
699}
b940ca64 700
fb4a87a7 701int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
b940ca64
GR
702{
703 int error = 0;
a2a55e51 704 int portal_id = 0;
b940ca64 705 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
fb4a87a7 706 u64 mc_ram_addr = mc_get_dram_addr();
b940ca64 707 u32 reg_gsr;
125e2bc1
GR
708 u32 reg_mcfbalr;
709#ifndef CONFIG_SYS_LS_MC_FW_IN_DDR
b940ca64
GR
710 const void *raw_image_addr;
711 size_t raw_image_size = 0;
125e2bc1 712#endif
125e2bc1
GR
713 u8 mc_ram_num_256mb_blocks;
714 size_t mc_ram_size = mc_get_dram_block_size();
b940ca64 715
437858b6 716 mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
43ad41e6
MA
717
718 if (mc_ram_num_256mb_blocks >= 0xff) {
437858b6
YS
719 error = -EINVAL;
720 printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
721 mc_ram_size);
125e2bc1 722 goto out;
437858b6 723 }
125e2bc1 724
43ad41e6
MA
725 /*
726 * To support 128 MB DDR Size for MC
727 */
728 if (mc_ram_num_256mb_blocks == 0)
729 mc_ram_num_256mb_blocks = 0xFF;
730
b940ca64
GR
731 /*
732 * Management Complex cores should be held at reset out of POR.
a187559e 733 * U-Boot should be the first software to touch MC. To be safe,
b940ca64
GR
734 * we reset all cores again by setting GCR1 to 0. It doesn't do
735 * anything if they are held at reset. After we setup the firmware
736 * we kick off MC by deasserting the reset bit for core 0, and
737 * deasserting the reset bits for Command Portal Managers.
738 * The stop bits are not touched here. They are used to stop the
739 * cores when they are active. Setting stop bits doesn't stop the
740 * cores from fetching instructions when they are released from
741 * reset.
742 */
743 out_le32(&mc_ccsr_regs->reg_gcr1, 0);
744 dmb();
745
125e2bc1
GR
746#ifdef CONFIG_SYS_LS_MC_FW_IN_DDR
747 printf("MC firmware is preloaded to %#llx\n", mc_ram_addr);
748#else
fb4a87a7
PK
749 error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr,
750 &raw_image_size);
b940ca64
GR
751 if (error != 0)
752 goto out;
753 /*
754 * Load the MC FW at the beginning of the MC private DRAM block:
755 */
7b3bd9a7
GR
756 mc_copy_image("MC Firmware",
757 (u64)raw_image_addr, raw_image_size, mc_ram_addr);
7b3bd9a7 758#endif
125e2bc1 759 dump_ram_words("firmware", (void *)mc_ram_addr);
7b3bd9a7 760
fb4a87a7 761 error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr);
125e2bc1 762 if (error != 0)
b940ca64 763 goto out;
b940ca64
GR
764
765 debug("mc_ccsr_regs %p\n", mc_ccsr_regs);
125e2bc1 766 dump_mc_ccsr_regs(mc_ccsr_regs);
b940ca64
GR
767
768 /*
125e2bc1 769 * Tell MC what is the address range of the DRAM block assigned to it:
b940ca64 770 */
43ad41e6
MA
771 if (mc_ram_num_256mb_blocks < 0xFF) {
772 reg_mcfbalr = (u32)mc_ram_addr |
773 (mc_ram_num_256mb_blocks - 1);
774 } else {
775 reg_mcfbalr = (u32)mc_ram_addr |
776 (mc_ram_num_256mb_blocks);
777 }
778
125e2bc1
GR
779 out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
780 out_le32(&mc_ccsr_regs->reg_mcfbahr,
437858b6 781 (u32)(mc_ram_addr >> 32));
39da644e 782 out_le32(&mc_ccsr_regs->reg_mcfapr, FSL_BYPASS_AMQ);
b940ca64
GR
783
784 /*
125e2bc1 785 * Tell the MC that we want delayed DPL deployment.
b940ca64 786 */
125e2bc1 787 out_le32(&mc_ccsr_regs->reg_gsr, 0xDD00);
b940ca64 788
cc088c3a 789 printf("\nfsl-mc: Booting Management Complex ... ");
7b3bd9a7 790
b940ca64
GR
791 /*
792 * Deassert reset and release MC core 0 to run
793 */
794 out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST);
125e2bc1
GR
795 error = wait_for_mc(true, &reg_gsr);
796 if (error != 0)
b940ca64 797 goto out;
b940ca64 798
7b3bd9a7
GR
799 /*
800 * TODO: need to obtain the portal_id for the root container from the
801 * DPL
802 */
803 portal_id = 0;
804
805 /*
a2a55e51
PK
806 * Initialize the global default MC portal
807 * And check that the MC firmware is responding portal commands:
7b3bd9a7 808 */
6dcf5e44 809 root_mc_io = calloc(sizeof(struct fsl_mc_io), 1);
1730a17d 810 if (!root_mc_io) {
a572fb6b 811 printf(" No memory: calloc() failed\n");
a2a55e51
PK
812 return -ENOMEM;
813 }
814
1730a17d 815 root_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(portal_id);
7b3bd9a7 816 debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n",
1730a17d 817 portal_id, root_mc_io->mmio_regs);
7b3bd9a7 818
1730a17d 819 error = mc_get_version(root_mc_io, MC_CMD_NO_FLAGS, &mc_ver_info);
7b3bd9a7
GR
820 if (error != 0) {
821 printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n",
822 error);
823 goto out;
824 }
825
7b3bd9a7
GR
826 printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n",
827 mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision,
125e2bc1
GR
828 reg_gsr & GSR_FS_MASK);
829
fb4a87a7
PK
830out:
831 if (error != 0)
832 mc_boot_status = error;
833 else
834 mc_boot_status = 0;
835
836 return error;
837}
838
839int mc_apply_dpl(u64 mc_dpl_addr)
840{
841 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
842 int error = 0;
843 u32 reg_gsr;
844 u64 mc_ram_addr = mc_get_dram_addr();
845 size_t mc_ram_size = mc_get_dram_block_size();
846
b7b8410a
AG
847 if (!mc_dpl_addr)
848 return -1;
849
fb4a87a7
PK
850 error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr);
851 if (error != 0)
852 return error;
853
125e2bc1
GR
854 /*
855 * Tell the MC to deploy the DPL:
856 */
857 out_le32(&mc_ccsr_regs->reg_gsr, 0x0);
cc088c3a 858 printf("fsl-mc: Deploying data path layout ... ");
125e2bc1 859 error = wait_for_mc(false, &reg_gsr);
cc088c3a 860
fb4a87a7
PK
861 if (!error)
862 mc_dpl_applied = 0;
b940ca64
GR
863
864 return error;
865}
866
867int get_mc_boot_status(void)
868{
869 return mc_boot_status;
870}
871
65cc0e2a 872#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
fb4a87a7
PK
873int get_aiop_apply_status(void)
874{
875 return mc_aiop_applied;
876}
877#endif
878
879int get_dpl_apply_status(void)
880{
881 return mc_dpl_applied;
882}
883
7e968049
MYK
884int is_lazy_dpl_addr_valid(void)
885{
886 return !!mc_lazy_dpl_addr;
887}
888
033c538e 889/*
fb4a87a7 890 * Return the MC address of private DRAM block.
033c538e
PJ
891 * As per MC design document, MC initial base address
892 * should be least significant 512MB address of MC private
893 * memory, i.e. address should point to end address masked
894 * with 512MB offset in private DRAM block.
fb4a87a7
PK
895 */
896u64 mc_get_dram_addr(void)
897{
033c538e
PJ
898 size_t mc_ram_size = mc_get_dram_block_size();
899
87519a9e
PK
900 if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) {
901 mc_memset_resv_ram = 1;
902 memset((void *)gd->arch.resv_ram, 0, mc_ram_size);
903 }
904
033c538e
PJ
905 return (gd->arch.resv_ram + mc_ram_size - 1) &
906 MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
fb4a87a7
PK
907}
908
b940ca64
GR
909/**
910 * Return the actual size of the MC private DRAM block.
b940ca64
GR
911 */
912unsigned long mc_get_dram_block_size(void)
913{
65cc0e2a 914 unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
125e2bc1 915
00caae6d 916 char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR);
125e2bc1
GR
917
918 if (dram_block_size_env_var) {
7e5f460e 919 dram_block_size = hextoul(dram_block_size_env_var, NULL);
125e2bc1 920
65cc0e2a 921 if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) {
125e2bc1
GR
922 printf("fsl-mc: WARNING: Invalid value for \'"
923 MC_MEM_SIZE_ENV_VAR
924 "\' environment variable: %lu\n",
925 dram_block_size);
926
43ad41e6 927 dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
125e2bc1
GR
928 }
929 }
930
931 return dram_block_size;
b940ca64 932}
a2a55e51 933
1dd7b566
LT
934/**
935 * Populate the device tree with MC reserved memory ranges.
936 */
937void fdt_reserve_mc_mem(void *blob, u32 mc_icid)
938{
939 u32 phandle, mc_ph;
940 int noff, ret, i;
941 char mem_name[16];
942 struct fdt_memory mc_mem_ranges[] = {
943 {
944 .start = 0,
945 .end = 0
946 },
947 {
948 .start = CFG_SYS_FSL_MC_BASE,
949 .end = CFG_SYS_FSL_MC_BASE + CFG_SYS_FSL_MC_SIZE - 1
950 },
951 {
952 .start = CFG_SYS_FSL_NI_BASE,
953 .end = CFG_SYS_FSL_NI_BASE + CFG_SYS_FSL_NI_SIZE - 1
954 },
955 {
956 .start = CFG_SYS_FSL_QBMAN_BASE,
957 .end = CFG_SYS_FSL_QBMAN_BASE +
958 CFG_SYS_FSL_QBMAN_SIZE - 1
959 },
960 {
961 .start = CFG_SYS_FSL_PEBUF_BASE,
962 .end = CFG_SYS_FSL_PEBUF_BASE +
963 CFG_SYS_FSL_PEBUF_SIZE - 1
964 },
965 {
966 .start = CFG_SYS_FSL_CCSR_BASE,
967 .end = CFG_SYS_FSL_CCSR_BASE + CFG_SYS_FSL_CCSR_SIZE - 1
968 }
969 };
970
971 mc_mem_ranges[0].start = gd->arch.resv_ram;
972 mc_mem_ranges[0].end = mc_mem_ranges[0].start +
973 mc_get_dram_block_size() - 1;
974
975 for (i = 0; i < ARRAY_SIZE(mc_mem_ranges); i++) {
976 noff = fdt_node_offset_by_compatible(blob, -1, "fsl,qoriq-mc");
977 if (noff < 0) {
978 printf("WARN: failed to get MC node: %d\n", noff);
979 return;
980 }
981 mc_ph = fdt_get_phandle(blob, noff);
982 if (!mc_ph) {
983 mc_ph = fdt_create_phandle(blob, noff);
984 if (!mc_ph) {
985 printf("WARN: failed to get MC node phandle\n");
986 return;
987 }
988 }
989
990 sprintf(mem_name, "mc-mem%d", i);
991 ret = fdtdec_add_reserved_memory(blob, mem_name,
992 &mc_mem_ranges[i], NULL, 0,
993 &phandle, 0);
994 if (ret < 0) {
995 printf("ERROR: failed to reserve MC memory: %d\n", ret);
996 return;
997 }
998
999 noff = fdt_node_offset_by_phandle(blob, phandle);
1000 if (noff < 0) {
1001 printf("ERROR: failed get resvmem node offset: %d\n",
1002 noff);
1003 return;
1004 }
1005 ret = fdt_setprop_u32(blob, noff, "iommu-addresses", mc_ph);
1006 if (ret < 0) {
1007 printf("ERROR: failed to set 'iommu-addresses': %d\n",
1008 ret);
1009 return;
1010 }
1011 ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
1012 mc_mem_ranges[i].start);
1013 if (ret < 0) {
1014 printf("ERROR: failed to set 'iommu-addresses': %d\n",
1015 ret);
1016 return;
1017 }
1018 ret = fdt_appendprop_u64(blob, noff, "iommu-addresses",
1019 mc_mem_ranges[i].end -
1020 mc_mem_ranges[i].start + 1);
1021 if (ret < 0) {
1022 printf("ERROR: failed to set 'iommu-addresses': %d\n",
1023 ret);
1024 return;
1025 }
1026
1027 noff = fdt_node_offset_by_phandle(blob, mc_ph);
1028 if (noff < 0) {
1029 printf("ERROR: failed get MC node offset: %d\n", noff);
1030 return;
1031 }
1032 ret = fdt_appendprop_u32(blob, noff, "memory-region", phandle);
1033 if (ret < 0) {
1034 printf("ERROR: failed to set 'memory-region': %d\n",
1035 ret);
1036 }
1037 }
1038
1039 fdt_set_iommu_prop(blob, noff, fdt_get_smmu_phandle(blob), &mc_icid, 1);
1040}
1041
b75d8dc5 1042int fsl_mc_ldpaa_init(struct bd_info *bis)
1730a17d 1043{
c919ab9e
PK
1044 int i;
1045
1046 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++)
1ed19a14 1047 if (wriop_is_enabled_dpmac(i) == 1)
c919ab9e 1048 ldpaa_eth_init(i, wriop_get_enet_if(i));
1730a17d
PK
1049 return 0;
1050}
1051
9a696f56
PK
1052static int dprc_version_check(struct fsl_mc_io *mc_io, uint16_t handle)
1053{
9a696f56 1054 int error;
2557c5a9 1055 uint16_t major_ver, minor_ver;
9a696f56 1056
2557c5a9
YG
1057 error = dprc_get_api_version(mc_io, 0,
1058 &major_ver,
1059 &minor_ver);
1060 if (error < 0) {
1061 printf("dprc_get_api_version() failed: %d\n", error);
1062 return error;
1063 }
1064
1065 if (major_ver < DPRC_VER_MAJOR || (major_ver == DPRC_VER_MAJOR &&
1066 minor_ver < DPRC_VER_MINOR)) {
1067 printf("DPRC version mismatch found %u.%u,",
1068 major_ver, minor_ver);
1069 printf("supported version is %u.%u\n",
1070 DPRC_VER_MAJOR, DPRC_VER_MINOR);
9a696f56 1071 }
2557c5a9 1072
9a696f56
PK
1073 return error;
1074}
1075
1730a17d 1076static int dpio_init(void)
a2a55e51
PK
1077{
1078 struct qbman_swp_desc p_des;
1079 struct dpio_attr attr;
1730a17d 1080 struct dpio_cfg dpio_cfg;
a2a55e51 1081 int err = 0;
2557c5a9 1082 uint16_t major_ver, minor_ver;
a2a55e51 1083
6dcf5e44 1084 dflt_dpio = calloc(sizeof(struct fsl_dpio_obj), 1);
a2a55e51 1085 if (!dflt_dpio) {
a572fb6b 1086 printf("No memory: calloc() failed\n");
1730a17d 1087 err = -ENOMEM;
a572fb6b 1088 goto err_calloc;
a2a55e51 1089 }
1730a17d
PK
1090 dpio_cfg.channel_mode = DPIO_LOCAL_CHANNEL;
1091 dpio_cfg.num_priorities = 8;
a2a55e51 1092
2557c5a9
YG
1093 err = dpio_create(dflt_mc_io,
1094 dflt_dprc_handle,
1095 MC_CMD_NO_FLAGS,
1096 &dpio_cfg,
1097 &dflt_dpio->dpio_id);
1730a17d
PK
1098 if (err < 0) {
1099 printf("dpio_create() failed: %d\n", err);
1100 err = -ENODEV;
1101 goto err_create;
a2a55e51
PK
1102 }
1103
2557c5a9
YG
1104 err = dpio_get_api_version(dflt_mc_io, 0,
1105 &major_ver,
1106 &minor_ver);
1107 if (err < 0) {
1108 printf("dpio_get_api_version() failed: %d\n", err);
1109 goto err_get_api_ver;
1110 }
1111
1112 if (major_ver < DPIO_VER_MAJOR || (major_ver == DPIO_VER_MAJOR &&
1113 minor_ver < DPIO_VER_MINOR)) {
1114 printf("DPRC version mismatch found %u.%u,",
1115 major_ver,
1116 minor_ver);
1117 }
1118
1119 err = dpio_open(dflt_mc_io,
1120 MC_CMD_NO_FLAGS,
1121 dflt_dpio->dpio_id,
1122 &dflt_dpio->dpio_handle);
1123 if (err) {
1124 printf("dpio_open() failed\n");
1125 goto err_open;
1126 }
1127
1730a17d 1128 memset(&attr, 0, sizeof(struct dpio_attr));
87457d11 1129 err = dpio_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
1730a17d
PK
1130 dflt_dpio->dpio_handle, &attr);
1131 if (err < 0) {
1132 printf("dpio_get_attributes() failed: %d\n", err);
a2a55e51
PK
1133 goto err_get_attr;
1134 }
1135
2557c5a9
YG
1136 if (dflt_dpio->dpio_id != attr.id) {
1137 printf("dnpi object id and attribute id are not same\n");
1138 goto err_attr_not_same;
9a696f56
PK
1139 }
1140
1730a17d 1141#ifdef DEBUG
8ecf1ca0 1142 printf("Init: DPIO.%d\n", dflt_dpio->dpio_id);
1730a17d 1143#endif
1730a17d
PK
1144 err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
1145 if (err < 0) {
a2a55e51
PK
1146 printf("dpio_enable() failed %d\n", err);
1147 goto err_get_enable;
1148 }
1f1c25c7
PK
1149 debug("ce_offset=0x%llx, ci_offset=0x%llx, portalid=%d, prios=%d\n",
1150 attr.qbman_portal_ce_offset,
1151 attr.qbman_portal_ci_offset,
a2a55e51
PK
1152 attr.qbman_portal_id,
1153 attr.num_priorities);
1154
1f1c25c7
PK
1155 p_des.cena_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
1156 + attr.qbman_portal_ce_offset);
1157 p_des.cinh_bar = (void *)(SOC_QBMAN_PORTALS_BASE_ADDR
1158 + attr.qbman_portal_ci_offset);
a2a55e51
PK
1159
1160 dflt_dpio->sw_portal = qbman_swp_init(&p_des);
1161 if (dflt_dpio->sw_portal == NULL) {
1162 printf("qbman_swp_init() failed\n");
1163 goto err_get_swp_init;
1164 }
1165 return 0;
1166
1167err_get_swp_init:
1730a17d 1168 dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
a2a55e51 1169err_get_enable:
1730a17d 1170err_get_attr:
2557c5a9 1171err_attr_not_same:
1730a17d 1172 dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
2557c5a9
YG
1173err_open:
1174err_get_api_ver:
1175 dpio_destroy(dflt_mc_io,
1176 dflt_dprc_handle,
1177 MC_CMD_NO_FLAGS,
1178 dflt_dpio->dpio_id);
1730a17d 1179err_create:
cd7b3fbc 1180 free(dflt_dpio);
a572fb6b 1181err_calloc:
1730a17d
PK
1182 return err;
1183}
1184
1185static int dpio_exit(void)
1186{
1187 int err;
1188
1189 err = dpio_disable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
1190 if (err < 0) {
1191 printf("dpio_disable() failed: %d\n", err);
1192 goto err;
1193 }
1194
669884ea 1195 err = dpio_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle);
2557c5a9
YG
1196 if (err < 0) {
1197 printf("dpio_close() failed: %d\n", err);
1198 goto err;
1199 }
1200
1201 err = dpio_destroy(dflt_mc_io,
1202 dflt_dprc_handle,
1203 MC_CMD_NO_FLAGS,
1204 dflt_dpio->dpio_id);
1730a17d
PK
1205 if (err < 0) {
1206 printf("dpio_destroy() failed: %d\n", err);
1207 goto err;
1208 }
1209
1210#ifdef DEBUG
8ecf1ca0 1211 printf("Exit: DPIO.%d\n", dflt_dpio->dpio_id);
1730a17d
PK
1212#endif
1213
1214 if (dflt_dpio)
1215 free(dflt_dpio);
1216
1217 return 0;
1218err:
1219 return err;
1220}
1221
1222static int dprc_init(void)
1223{
1224 int err, child_portal_id, container_id;
1225 struct dprc_cfg cfg;
1226 uint64_t mc_portal_offset;
1227
1228 /* Open root container */
1229 err = dprc_get_container_id(root_mc_io, MC_CMD_NO_FLAGS, &container_id);
1230 if (err < 0) {
1231 printf("dprc_get_container_id(): Root failed: %d\n", err);
1232 goto err_root_container_id;
1233 }
1234
1235#ifdef DEBUG
1236 printf("Root container id = %d\n", container_id);
1237#endif
1238 err = dprc_open(root_mc_io, MC_CMD_NO_FLAGS, container_id,
1239 &root_dprc_handle);
1240 if (err < 0) {
1241 printf("dprc_open(): Root Container failed: %d\n", err);
1242 goto err_root_open;
1243 }
1244
1245 if (!root_dprc_handle) {
1246 printf("dprc_open(): Root Container Handle is not valid\n");
1247 goto err_root_open;
1248 }
1249
9a696f56
PK
1250 err = dprc_version_check(root_mc_io, root_dprc_handle);
1251 if (err < 0) {
1252 printf("dprc_version_check() failed: %d\n", err);
1253 goto err_root_open;
1254 }
1255
5373b204 1256 memset(&cfg, 0, sizeof(struct dprc_cfg));
1730a17d
PK
1257 cfg.options = DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED |
1258 DPRC_CFG_OPT_OBJ_CREATE_ALLOWED |
1259 DPRC_CFG_OPT_ALLOC_ALLOWED;
1260 cfg.icid = DPRC_GET_ICID_FROM_POOL;
335b1936 1261 cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL;
1730a17d 1262 err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS,
f45ed0b5
IC
1263 root_dprc_handle, &cfg,
1264 &child_dprc_id,
1265 &mc_portal_offset);
1730a17d
PK
1266 if (err < 0) {
1267 printf("dprc_create_container() failed: %d\n", err);
1268 goto err_create;
1269 }
1270
6dcf5e44 1271 dflt_mc_io = calloc(sizeof(struct fsl_mc_io), 1);
1730a17d
PK
1272 if (!dflt_mc_io) {
1273 err = -ENOMEM;
a572fb6b
PK
1274 printf(" No memory: calloc() failed\n");
1275 goto err_calloc;
1730a17d
PK
1276 }
1277
1278 child_portal_id = MC_PORTAL_OFFSET_TO_PORTAL_ID(mc_portal_offset);
1279 dflt_mc_io->mmio_regs = SOC_MC_PORTAL_ADDR(child_portal_id);
2557c5a9 1280
1730a17d
PK
1281#ifdef DEBUG
1282 printf("MC portal of child DPRC container: %d, physical addr %p)\n",
1283 child_dprc_id, dflt_mc_io->mmio_regs);
1284#endif
1285
1286 err = dprc_open(dflt_mc_io, MC_CMD_NO_FLAGS, child_dprc_id,
1287 &dflt_dprc_handle);
1288 if (err < 0) {
1289 printf("dprc_open(): Child container failed: %d\n", err);
1290 goto err_child_open;
1291 }
1292
1293 if (!dflt_dprc_handle) {
1294 printf("dprc_open(): Child container Handle is not valid\n");
1295 goto err_child_open;
1296 }
1297
1298 return 0;
1299err_child_open:
1300 free(dflt_mc_io);
a572fb6b 1301err_calloc:
1730a17d
PK
1302 dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
1303 root_dprc_handle, child_dprc_id);
1304err_create:
1305 dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
1306err_root_open:
1307err_root_container_id:
1308 return err;
1309}
1310
1311static int dprc_exit(void)
1312{
1313 int err;
1314
1315 err = dprc_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle);
1316 if (err < 0) {
1317 printf("dprc_close(): Child failed: %d\n", err);
1318 goto err;
1319 }
1320
1321 err = dprc_destroy_container(root_mc_io, MC_CMD_NO_FLAGS,
1322 root_dprc_handle, child_dprc_id);
1323 if (err < 0) {
1324 printf("dprc_destroy_container() failed: %d\n", err);
1325 goto err;
1326 }
1327
1328 err = dprc_close(root_mc_io, MC_CMD_NO_FLAGS, root_dprc_handle);
1329 if (err < 0) {
1330 printf("dprc_close(): Root failed: %d\n", err);
1331 goto err;
1332 }
1333
1334 if (dflt_mc_io)
1335 free(dflt_mc_io);
1336
1337 if (root_mc_io)
1338 free(root_mc_io);
1339
1340 return 0;
1341
1342err:
a2a55e51
PK
1343 return err;
1344}
1345
1730a17d 1346static int dpbp_init(void)
a2a55e51 1347{
1730a17d
PK
1348 int err;
1349 struct dpbp_attr dpbp_attr;
1350 struct dpbp_cfg dpbp_cfg;
2557c5a9 1351 uint16_t major_ver, minor_ver;
1730a17d 1352
6dcf5e44 1353 dflt_dpbp = calloc(sizeof(struct fsl_dpbp_obj), 1);
a2a55e51 1354 if (!dflt_dpbp) {
a572fb6b 1355 printf("No memory: calloc() failed\n");
1730a17d 1356 err = -ENOMEM;
a572fb6b 1357 goto err_calloc;
1730a17d
PK
1358 }
1359
1360 dpbp_cfg.options = 512;
1361
2557c5a9
YG
1362 err = dpbp_create(dflt_mc_io,
1363 dflt_dprc_handle,
1364 MC_CMD_NO_FLAGS,
1365 &dpbp_cfg,
1366 &dflt_dpbp->dpbp_id);
1730a17d
PK
1367
1368 if (err < 0) {
1369 err = -ENODEV;
1370 printf("dpbp_create() failed: %d\n", err);
1371 goto err_create;
1372 }
1373
2557c5a9
YG
1374 err = dpbp_get_api_version(dflt_mc_io, 0,
1375 &major_ver,
1376 &minor_ver);
1377 if (err < 0) {
1378 printf("dpbp_get_api_version() failed: %d\n", err);
1379 goto err_get_api_ver;
1380 }
1381
1382 if (major_ver < DPBP_VER_MAJOR || (major_ver == DPBP_VER_MAJOR &&
1383 minor_ver < DPBP_VER_MINOR)) {
1384 printf("DPBP version mismatch found %u.%u,",
1385 major_ver, minor_ver);
1386 printf("supported version is %u.%u\n",
1387 DPBP_VER_MAJOR, DPBP_VER_MINOR);
1388 }
1389
1390 err = dpbp_open(dflt_mc_io,
1391 MC_CMD_NO_FLAGS,
1392 dflt_dpbp->dpbp_id,
1393 &dflt_dpbp->dpbp_handle);
1394 if (err) {
1395 printf("dpbp_open() failed\n");
1396 goto err_open;
1397 }
1398
1730a17d
PK
1399 memset(&dpbp_attr, 0, sizeof(struct dpbp_attr));
1400 err = dpbp_get_attributes(dflt_mc_io, MC_CMD_NO_FLAGS,
1401 dflt_dpbp->dpbp_handle,
1402 &dpbp_attr);
1403 if (err < 0) {
1404 printf("dpbp_get_attributes() failed: %d\n", err);
1405 goto err_get_attr;
1406 }
1407
2557c5a9
YG
1408 if (dflt_dpbp->dpbp_id != dpbp_attr.id) {
1409 printf("dpbp object id and attribute id are not same\n");
1410 goto err_attr_not_same;
9a696f56
PK
1411 }
1412
1730a17d 1413#ifdef DEBUG
8ecf1ca0 1414 printf("Init: DPBP.%d\n", dflt_dpbp->dpbp_attr.id);
1730a17d
PK
1415#endif
1416
1417 err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
1418 if (err < 0) {
1419 printf("dpbp_close() failed: %d\n", err);
1420 goto err_close;
a2a55e51 1421 }
a2a55e51
PK
1422
1423 return 0;
1730a17d 1424
1730a17d 1425err_get_attr:
2557c5a9 1426err_attr_not_same:
1730a17d 1427 dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle);
2557c5a9
YG
1428 dpbp_destroy(dflt_mc_io,
1429 dflt_dprc_handle,
1430 MC_CMD_NO_FLAGS,
1431 dflt_dpbp->dpbp_id);
1432err_get_api_ver:
1433err_close:
1434err_open:
1730a17d 1435err_create:
2557c5a9 1436 free(dflt_dpbp);
a572fb6b 1437err_calloc:
1730a17d 1438 return err;
a2a55e51
PK
1439}
1440
1730a17d
PK
1441static int dpbp_exit(void)
1442{
1443 int err;
1444
2557c5a9
YG
1445 err = dpbp_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
1446 dflt_dpbp->dpbp_id);
1730a17d
PK
1447 if (err < 0) {
1448 printf("dpbp_destroy() failed: %d\n", err);
1449 goto err;
1450 }
1451
1452#ifdef DEBUG
8ecf1ca0 1453 printf("Exit: DPBP.%d\n", dflt_dpbp->dpbp_attr.id);
1730a17d
PK
1454#endif
1455
1456 if (dflt_dpbp)
1457 free(dflt_dpbp);
1458 return 0;
1459
1460err:
1461 return err;
1462}
1463
1464static int dpni_init(void)
1465{
207c8157 1466 struct dpni_cfg dpni_cfg = {0};
2557c5a9 1467 uint16_t major_ver, minor_ver;
207c8157 1468 int err;
1730a17d 1469
6dcf5e44 1470 dflt_dpni = calloc(sizeof(struct fsl_dpni_obj), 1);
1730a17d 1471 if (!dflt_dpni) {
a572fb6b 1472 printf("No memory: calloc() failed\n");
1730a17d 1473 err = -ENOMEM;
a572fb6b 1474 goto err_calloc;
1730a17d
PK
1475 }
1476
2557c5a9
YG
1477 err = dpni_create(dflt_mc_io,
1478 dflt_dprc_handle,
1479 MC_CMD_NO_FLAGS,
1480 &dpni_cfg,
1481 &dflt_dpni->dpni_id);
1730a17d
PK
1482 if (err < 0) {
1483 err = -ENODEV;
2557c5a9 1484 printf("dpni create() failed: %d\n", err);
1730a17d
PK
1485 goto err_create;
1486 }
1487
2557c5a9
YG
1488 err = dpni_get_api_version(dflt_mc_io, 0,
1489 &major_ver,
1490 &minor_ver);
1730a17d 1491 if (err < 0) {
2557c5a9
YG
1492 printf("dpni_get_api_version() failed: %d\n", err);
1493 goto err_get_version;
1730a17d
PK
1494 }
1495
2557c5a9
YG
1496 if (major_ver < DPNI_VER_MAJOR || (major_ver == DPNI_VER_MAJOR &&
1497 minor_ver < DPNI_VER_MINOR)) {
9a696f56 1498 printf("DPNI version mismatch found %u.%u,",
2557c5a9 1499 major_ver, minor_ver);
9a696f56
PK
1500 printf("supported version is %u.%u\n",
1501 DPNI_VER_MAJOR, DPNI_VER_MINOR);
1502 }
1503
2557c5a9
YG
1504 err = dpni_open(dflt_mc_io,
1505 MC_CMD_NO_FLAGS,
1506 dflt_dpni->dpni_id,
1507 &dflt_dpni->dpni_handle);
1508 if (err) {
1509 printf("dpni_open() failed\n");
1510 goto err_open;
1511 }
1512
1730a17d 1513#ifdef DEBUG
8ecf1ca0 1514 printf("Init: DPNI.%d\n", dflt_dpni->dpni_id);
1730a17d 1515#endif
1730a17d
PK
1516 err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
1517 if (err < 0) {
1518 printf("dpni_close() failed: %d\n", err);
1519 goto err_close;
1520 }
1521
1522 return 0;
1523
1524err_close:
1730a17d 1525 dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle);
2557c5a9
YG
1526err_open:
1527err_get_version:
1528 dpni_destroy(dflt_mc_io,
1529 dflt_dprc_handle,
1530 MC_CMD_NO_FLAGS,
1531 dflt_dpni->dpni_id);
1730a17d 1532err_create:
879a59ac 1533 free(dflt_dpni);
a572fb6b 1534err_calloc:
1730a17d
PK
1535 return err;
1536}
1537
1538static int dpni_exit(void)
1539{
1540 int err;
1541
2557c5a9
YG
1542 err = dpni_destroy(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS,
1543 dflt_dpni->dpni_id);
1730a17d
PK
1544 if (err < 0) {
1545 printf("dpni_destroy() failed: %d\n", err);
1546 goto err;
1547 }
1548
1549#ifdef DEBUG
8ecf1ca0 1550 printf("Exit: DPNI.%d\n", dflt_dpni->dpni_id);
1730a17d
PK
1551#endif
1552
1553 if (dflt_dpni)
1554 free(dflt_dpni);
1555 return 0;
1556
1557err:
1558 return err;
1559}
1560
1990cc7d
FI
1561static bool is_dpsparser_supported(void)
1562{
1563 /* dpsparser support was first introduced in MC version: 10.12.0 */
1564 if (mc_ver_info.major < 10)
1565 return false;
1566 if (mc_ver_info.major == 10)
1567 return (mc_ver_info.minor >= 12);
1568 return true;
1569}
1570
1571static int dpsparser_version_check(struct fsl_mc_io *mc_io)
1572{
1573 int error;
1574 u16 major_ver, minor_ver;
1575
1576 if (!is_dpsparser_supported())
1577 return 0;
1578
1579 error = dpsparser_get_api_version(mc_io, 0,
1580 &major_ver,
1581 &minor_ver);
1582 if (error < 0) {
1583 printf("dpsparser_get_api_version() failed: %d\n", error);
1584 return error;
1585 }
1586
1587 if (major_ver < DPSPARSER_VER_MAJOR || (major_ver ==
1588 DPSPARSER_VER_MAJOR && minor_ver < DPSPARSER_VER_MINOR)) {
1589 printf("DPSPARSER version mismatch found %u.%u,",
1590 major_ver, minor_ver);
1591 printf("supported version is %u.%u\n",
1592 DPSPARSER_VER_MAJOR, DPSPARSER_VER_MINOR);
1593 }
1594
1595 return error;
1596}
1597
1598static int dpsparser_init(void)
1599{
1600 int err = 0;
1601
1602 if (!is_dpsparser_supported())
1603 return 0;
1604
1605 err = dpsparser_create(dflt_mc_io,
1606 dflt_dprc_handle,
1607 MC_CMD_NO_FLAGS,
1608 &dpsparser_obj_id);
1609 if (err)
1610 printf("dpsparser_create() failed\n");
1611
1612 err = dpsparser_version_check(dflt_mc_io);
1613 if (err < 0) {
1614 printf("dpsparser_version_check() failed: %d\n", err);
1615 goto err_version_check;
1616 }
1617
1618 err = dpsparser_open(dflt_mc_io,
1619 MC_CMD_NO_FLAGS,
1620 &dpsparser_handle);
1621 if (err < 0) {
1622 printf("dpsparser_open() failed: %d\n", err);
1623 goto err_open;
1624 }
1625
1626 return err;
1627
1628err_open:
1629err_version_check:
1630 dpsparser_destroy(dflt_mc_io,
1631 dflt_dprc_handle,
1632 MC_CMD_NO_FLAGS, dpsparser_obj_id);
1633
1634 return err;
1635}
1636
1637#ifdef DPSPARSER_DESTROY
1638/* TODO: refactoring needed in the future to allow DPSPARSER object destroy
1639 * Workaround: DO NOT destroy DPSPARSER object because it needs to be available
1640 * on Apply DPL
1641 */
1642static int dpsparser_exit(void)
1643{
1644 int err;
1645
1646 if (!is_dpsparser_supported())
1647 return 0;
1648
1649 dpsparser_close(dflt_mc_io, MC_CMD_NO_FLAGS, dpsparser_handle);
1650 if (err < 0) {
1651 printf("dpsparser_close() failed: %d\n", err);
1652 goto err;
1653 }
1654
1655 err = dpsparser_destroy(dflt_mc_io, dflt_dprc_handle,
1656 MC_CMD_NO_FLAGS, dpsparser_obj_id);
1657 if (err < 0) {
1658 printf("dpsparser_destroy() failed: %d\n", err);
1659 goto err;
1660 }
1661 return 0;
1662
1663err:
1664 return err;
1665}
1666#endif
1667
1668int mc_apply_spb(u64 mc_spb_addr)
1669{
1670 int err = 0;
1671 u16 error, err_arr_size;
1672 u64 mc_spb_offset;
1673 u32 spb_size;
1674 struct sp_blob_header *sp_blob;
1675 u64 mc_ram_addr = mc_get_dram_addr();
1676
1677 if (!is_dpsparser_supported())
1678 return 0;
1679
1680 if (!mc_spb_addr) {
1681 printf("fsl-mc: Invalid Blob address\n");
1682 return -1;
1683 }
1684
1685#ifdef CONFIG_MC_DRAM_SPB_OFFSET
1686 mc_spb_offset = CONFIG_MC_DRAM_SPB_OFFSET;
1687#else
1688#error "CONFIG_MC_DRAM_SPB_OFFSET not defined"
1689#endif
1690
1691 // Read blob header and get size of SPB blob
1692 sp_blob = (struct sp_blob_header *)mc_spb_addr;
1693 spb_size = le32_to_cpu(sp_blob->length);
1694 if (spb_size > CONFIG_MC_SPB_MAX_SIZE) {
1695 printf("\nfsl-mc: ERROR: Bad SPB image (too large: %d)\n",
1696 spb_size);
1697 return -EINVAL;
1698 }
1699
1700 mc_copy_image("MC SP Blob", mc_spb_addr, spb_size,
1701 mc_ram_addr + mc_spb_offset);
1702
1703 //Invoke MC command to apply SPB blob
1704 printf("fsl-mc: Applying soft parser blob... ");
1705 err = dpsparser_apply_spb(dflt_mc_io, MC_CMD_NO_FLAGS, dpsparser_handle,
1706 mc_spb_offset, &error);
1707 if (err)
1708 return err;
1709
1710 if (error == 0) {
1711 printf("SUCCESS\n");
1712 } else {
1713 printf("FAILED with error code = %d:\n", error);
1714 err_arr_size = (u16)ARRAY_SIZE(mc_err_msg_apply_spb);
1715
1716 if (error > 0 && error < err_arr_size)
1717 printf(mc_err_msg_apply_spb[error]);
1718 else
1719 printf(MC_ERROR_MSG_SPB_UNKNOWN);
1720 }
1721
1722 return err;
1723}
1724
1730a17d 1725static int mc_init_object(void)
a2a55e51 1726{
1730a17d
PK
1727 int err = 0;
1728
1729 err = dprc_init();
1730 if (err < 0) {
1731 printf("dprc_init() failed: %d\n", err);
1732 goto err;
1733 }
1734
1735 err = dpbp_init();
1736 if (err < 0) {
1737 printf("dpbp_init() failed: %d\n", err);
1738 goto err;
1739 }
1740
1741 err = dpio_init();
1742 if (err < 0) {
1743 printf("dpio_init() failed: %d\n", err);
1744 goto err;
1745 }
1746
1747 err = dpni_init();
1748 if (err < 0) {
1749 printf("dpni_init() failed: %d\n", err);
1750 goto err;
1751 }
a2a55e51 1752
1990cc7d
FI
1753 err = dpsparser_init();
1754 if (err < 0) {
1755 printf("dpsparser_init() failed: %d\n", err);
1756 goto err;
1757 }
1758
fb4a87a7 1759 return 0;
1730a17d
PK
1760err:
1761 return err;
a2a55e51
PK
1762}
1763
b75d8dc5 1764int fsl_mc_ldpaa_exit(struct bd_info *bd)
a2a55e51 1765{
1730a17d 1766 int err = 0;
42e81790 1767 bool is_dpl_apply_status = false;
06651b94 1768 bool mc_boot_status = false;
1730a17d 1769
b7b8410a 1770 if (bd && mc_lazy_dpl_addr && !fsl_mc_ldpaa_exit(NULL)) {
f9747a5a
YG
1771 err = mc_apply_dpl(mc_lazy_dpl_addr);
1772 if (!err)
1773 fdt_fixup_board_enet(working_fdt);
b7b8410a
AG
1774 mc_lazy_dpl_addr = 0;
1775 }
1776
06651b94
SK
1777 if (!get_mc_boot_status())
1778 mc_boot_status = true;
1779
6dedcedd 1780 /* MC is not loaded intentionally, So return success. */
06651b94 1781 if (bd && !mc_boot_status)
1730a17d
PK
1782 return 0;
1783
42e81790
YG
1784 /* If DPL is deployed, set is_dpl_apply_status as TRUE. */
1785 if (!get_dpl_apply_status())
1786 is_dpl_apply_status = true;
1730a17d 1787
42e81790
YG
1788 /*
1789 * For case MC is loaded but DPL is not deployed, return success and
1790 * print message on console. Else FDT fix-up code execution hanged.
1791 */
06651b94 1792 if (bd && mc_boot_status && !is_dpl_apply_status) {
42e81790 1793 printf("fsl-mc: DPL not deployed, DPAA2 ethernet not work\n");
73fa206a 1794 goto mc_obj_cleanup;
42e81790 1795 }
1730a17d 1796
06651b94
SK
1797 if (bd && mc_boot_status && is_dpl_apply_status)
1798 return 0;
1799
73fa206a 1800mc_obj_cleanup:
1730a17d
PK
1801 err = dpbp_exit();
1802 if (err < 0) {
a2a4dc56 1803 printf("dpbp_exit() failed: %d\n", err);
1730a17d
PK
1804 goto err;
1805 }
1806
1807 err = dpio_exit();
1808 if (err < 0) {
1809 printf("dpio_exit() failed: %d\n", err);
1810 goto err;
1811 }
1812
1813 err = dpni_exit();
1814 if (err < 0) {
1815 printf("dpni_exit() failed: %d\n", err);
1816 goto err;
1817 }
1818
1819 err = dprc_exit();
1820 if (err < 0) {
1821 printf("dprc_exit() failed: %d\n", err);
1822 goto err;
1823 }
1824
1825 return 0;
1826err:
1827 return err;
a2a55e51
PK
1828}
1829
ed06772a
CFA
1830static void print_k_bytes(const void *buf, ssize_t *size)
1831{
1832 while (*size > 0) {
1833 int count = printf("%s", (char *)buf);
1834
1835 buf += count;
1836 *size -= count;
1837 }
1838}
1839
1840static void mc_dump_log(void)
1841{
1842 struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR;
1843 u64 high = in_le64(&mc_ccsr_regs->reg_mcfbahr) & MC_FW_ADDR_MASK_HIGH;
1844 u64 low = in_le64(&mc_ccsr_regs->reg_mcfbalr) & MC_FW_ADDR_MASK_LOW;
1845 u32 buf_len, wrapped, last_byte, magic, buf_start;
1846 u64 mc_addr = (high << 32) | low;
1847 struct log_header *header;
1848 ssize_t size, bytes_end;
1849 const void *end_of_data;
1850 const void *map_addr;
1851 const void *end_addr;
1852 const void *cur_ptr;
1853 const void *buf;
1854
1855 map_addr = map_sysmem(mc_addr + MC_STRUCT_BUFFER_OFFSET,
1856 MC_BUFFER_SIZE);
1857 header = (struct log_header *)map_addr;
1858 last_byte = in_le32(&header->last_byte);
1859 buf_len = in_le32(&header->buf_length);
1860 magic = in_le32(&header->magic_word);
1861 buf_start = in_le32(&header->buf_start);
1862 buf = map_addr + buf_start - MC_OFFSET_DELTA;
1863 end_addr = buf + buf_len;
1864 wrapped = last_byte & LOG_HEADER_FLAG_BUFFER_WRAPAROUND;
1865 end_of_data = buf + LAST_BYTE(last_byte);
1866
1867 if (magic != MAGIC_MC) {
1868 puts("Magic number is not valid\n");
1869 printf("expected = %08x, received = %08x\n", MAGIC_MC, magic);
1870 goto err_magic;
1871 }
1872
1873 if (wrapped && end_of_data != end_addr)
1874 cur_ptr = end_of_data + 1;
1875 else
1876 cur_ptr = buf;
1877
1878 if (cur_ptr <= end_of_data)
1879 size = end_of_data - cur_ptr;
1880 else
1881 size = (end_addr - cur_ptr) + (end_of_data - buf);
1882
1883 bytes_end = end_addr - cur_ptr;
1884 if (size > bytes_end) {
1885 print_k_bytes(cur_ptr, &bytes_end);
1886
ed06772a
CFA
1887 size -= bytes_end;
1888 }
1889
1890 print_k_bytes(buf, &size);
1891
1892err_magic:
1893 unmap_sysmem(map_addr);
1894}
1895
09140113
SG
1896static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc,
1897 char *const argv[])
a2a55e51 1898{
fb4a87a7 1899 int err = 0;
ed06772a 1900 if (argc < 2)
fb4a87a7
PK
1901 goto usage;
1902
1903 switch (argv[1][0]) {
1904 case 's': {
1905 char sub_cmd;
44937214 1906 u64 mc_fw_addr, mc_dpc_addr;
65cc0e2a 1907#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
44937214
PK
1908 u64 aiop_fw_addr;
1909#endif
ed06772a
CFA
1910 if (argc < 3)
1911 goto usage;
fb4a87a7
PK
1912
1913 sub_cmd = argv[2][0];
2557c5a9 1914
fb4a87a7
PK
1915 switch (sub_cmd) {
1916 case 'm':
1917 if (argc < 5)
1918 goto usage;
1919
1920 if (get_mc_boot_status() == 0) {
1921 printf("fsl-mc: MC is already booted");
1922 printf("\n");
1923 return err;
1924 }
1925 mc_fw_addr = simple_strtoull(argv[3], NULL, 16);
1926 mc_dpc_addr = simple_strtoull(argv[4], NULL,
1927 16);
1730a17d
PK
1928
1929 if (!mc_init(mc_fw_addr, mc_dpc_addr))
1930 err = mc_init_object();
fb4a87a7
PK
1931 break;
1932
65cc0e2a 1933#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
fb4a87a7
PK
1934 case 'a':
1935 if (argc < 4)
1936 goto usage;
1937 if (get_aiop_apply_status() == 0) {
1938 printf("fsl-mc: AIOP FW is already");
1939 printf(" applied\n");
1940 return err;
1941 }
1942
1943 aiop_fw_addr = simple_strtoull(argv[3], NULL,
1944 16);
1945
3c1d218a 1946 /* if SoC doesn't have AIOP, err = -ENODEV */
fb4a87a7
PK
1947 err = load_mc_aiop_img(aiop_fw_addr);
1948 if (!err)
1949 printf("fsl-mc: AIOP FW applied\n");
1950 break;
1951#endif
1952 default:
1953 printf("Invalid option: %s\n", argv[2]);
1954 goto usage;
a2a55e51 1955
fb4a87a7
PK
1956 break;
1957 }
125e2bc1 1958 }
fb4a87a7
PK
1959 break;
1960
1990cc7d
FI
1961 case 'l': {
1962 /* lazyapply */
1963 u64 mc_dpl_addr;
1964
1965 if (argc < 4)
1966 goto usage;
1967
1968 if (get_dpl_apply_status() == 0) {
1969 printf("fsl-mc: DPL already applied\n");
1970 return err;
1971 }
1972
1973 mc_dpl_addr = simple_strtoull(argv[3], NULL, 16);
1974
1975 if (get_mc_boot_status() != 0) {
1976 printf("fsl-mc: Deploying data path layout ..");
1977 printf("ERROR (MC is not booted)\n");
1978 return -ENODEV;
1979 }
1980
1981 /*
1982 * We will do the actual dpaa exit and dpl apply
1983 * later from announce_and_cleanup().
1984 */
1985 mc_lazy_dpl_addr = mc_dpl_addr;
1986 break;
1987 }
1988
fb4a87a7 1989 case 'a': {
1990cc7d
FI
1990 /* apply */
1991 char sub_cmd;
1992 u64 mc_apply_addr;
fb4a87a7 1993
1990cc7d
FI
1994 if (argc < 4)
1995 goto usage;
1996
1997 sub_cmd = argv[2][0];
fb4a87a7 1998
1990cc7d
FI
1999 switch (sub_cmd) {
2000 case 'd':
2001 case 'D':
fb4a87a7
PK
2002 if (get_dpl_apply_status() == 0) {
2003 printf("fsl-mc: DPL already applied\n");
2004 return err;
2005 }
fb4a87a7
PK
2006 if (get_mc_boot_status() != 0) {
2007 printf("fsl-mc: Deploying data path layout ..");
2008 printf("ERROR (MC is not booted)\n");
2009 return -ENODEV;
2010 }
1730a17d 2011
1990cc7d
FI
2012 mc_apply_addr = simple_strtoull(argv[3], NULL, 16);
2013
2014 /* The user wants DPL applied now */
2015 if (!fsl_mc_ldpaa_exit(NULL))
2016 err = mc_apply_dpl(mc_apply_addr);
2017 break;
2018
2019 case 's':
2020 if (!is_dpsparser_supported()) {
2021 printf("fsl-mc: apply spb command .. ");
2022 printf("ERROR: requires at least MC 10.12.0\n");
2023 return err;
b7b8410a 2024 }
1990cc7d
FI
2025 if (get_mc_boot_status() != 0) {
2026 printf("fsl-mc: Deploying Soft Parser Blob...");
2027 printf("ERROR (MC is not booted)\n");
2028 return err;
2029 }
2030
2031 mc_apply_addr = simple_strtoull(argv[3], NULL, 16);
2032
2033 /* Apply spb (Soft Parser Blob) */
2034 err = mc_apply_spb(mc_apply_addr);
fb4a87a7 2035 break;
1990cc7d
FI
2036
2037 default:
2038 printf("Invalid option: %s\n", argv[2]);
2039 goto usage;
2040 }
2041 break;
125e2bc1 2042 }
ed06772a
CFA
2043 case 'd':
2044 if (argc > 2)
2045 goto usage;
2046
2047 mc_dump_log();
2048 break;
fb4a87a7
PK
2049 default:
2050 printf("Invalid option: %s\n", argv[1]);
2051 goto usage;
a2a55e51 2052 }
fb4a87a7
PK
2053 return err;
2054 usage:
2055 return CMD_RET_USAGE;
a2a55e51 2056}
fb4a87a7
PK
2057
2058U_BOOT_CMD(
2059 fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc,
2060 "DPAA2 command to manage Management Complex (MC)",
2061 "start mc [FW_addr] [DPC_addr] - Start Management Complex\n"
2062 "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n"
b7b8410a 2063 "fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n"
1990cc7d 2064 "fsl_mc apply spb [spb_addr] - Apply SPB Soft Parser Blob\n"
fb4a87a7 2065 "fsl_mc start aiop [FW_addr] - Start AIOP\n"
ed06772a 2066 "fsl_mc dump_log - Dump MC Log\n"
fb4a87a7 2067);
33a8991a
BP
2068
2069void mc_env_boot(void)
2070{
2071#if defined(CONFIG_FSL_MC_ENET)
2072 char *mc_boot_env_var;
2073 /* The MC may only be initialized in the reset PHY function
2074 * because otherwise U-Boot has not yet set up all the MAC
2075 * address info properly. Without MAC addresses, the MC code
2076 * can not properly initialize the DPC.
2077 */
00caae6d 2078 mc_boot_env_var = env_get(MC_BOOT_ENV_VAR);
33a8991a
BP
2079 if (mc_boot_env_var)
2080 run_command_list(mc_boot_env_var, -1, 0);
2081#endif /* CONFIG_FSL_MC_ENET */
2082}