[people/ms/u-boot.git] / drivers / net / sh_eth.c

/*
 * sh_eth.c - Driver for Renesas ethernet controler.
 *
 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
 * Copyright (C) 2013  Renesas Electronics Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/errno.h>
#include <asm/io.h>

#include "sh_eth.h"

#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#endif
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif

#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len)    \
		flush_dcache_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif

#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
#define invalidate_cache(addr, len)		\
	{	\
		u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;	\
		u32 start, end;	\
		\
		start = (u32)addr;	\
		end = start + len;	\
		start &= ~(line_size - 1);	\
		end = ((end + line_size - 1) & ~(line_size - 1));	\
		\
		invalidate_dcache_range(start, end);	\
	}
#else
#define invalidate_cache(...)
#endif

#define TIMEOUT_CNT 1000

int sh_eth_send(struct eth_device *dev, void *packet, int len)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, ret = 0, timeout;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (!packet || len > 0xffff) {
		printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
		ret = -EINVAL;
		goto err;
	}

	/* packet must be a 4 byte boundary */
	if ((int)packet & 3) {
		printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
		ret = -EFAULT;
		goto err;
	}

	/* Update tx descriptor */
	flush_cache_wback(packet, len);
	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	port_info->tx_desc_cur->td1 = len << 16;
	/* Must preserve the end of descriptor list indication */
	if (port_info->tx_desc_cur->td0 & TD_TDLE)
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
	else
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;

	/* Restart the transmitter if disabled */
	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
		sh_eth_write(eth, EDTRR_TRNS, EDTRR);

	/* Wait until packet is transmitted */
	timeout = TIMEOUT_CNT;
	do {
		invalidate_cache(port_info->tx_desc_cur,
				 sizeof(struct tx_desc_s));
		udelay(100);
	} while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);

	if (timeout < 0) {
		printf(SHETHER_NAME ": transmit timeout\n");
		ret = -ETIMEDOUT;
		goto err;
	}

	port_info->tx_desc_cur++;
	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
		port_info->tx_desc_cur = port_info->tx_desc_base;

err:
	return ret;
}

int sh_eth_recv(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, len = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	uchar *packet;

	/* Check if the rx descriptor is ready */
	invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
		/* Check for errors */
		if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
			len = port_info->rx_desc_cur->rd1 & 0xffff;
			packet = (uchar *)
				ADDR_TO_P2(port_info->rx_desc_cur->rd2);
			invalidate_cache(packet, len);
			NetReceive(packet, len);
		}

		/* Make current descriptor available again */
		if (port_info->rx_desc_cur->rd0 & RD_RDLE)
			port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
		else
			port_info->rx_desc_cur->rd0 = RD_RACT;
		/* Point to the next descriptor */
		port_info->rx_desc_cur++;
		if (port_info->rx_desc_cur >=
		    port_info->rx_desc_base + NUM_RX_DESC)
			port_info->rx_desc_cur = port_info->rx_desc_base;
	}

	/* Restart the receiver if disabled */
	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
		sh_eth_write(eth, EDRRR_R, EDRRR);

	return len;
}

static int sh_eth_reset(struct sh_eth_dev *eth)
{
#if defined(SH_ETH_TYPE_GETHER)
	int ret = 0, i;

	/* Start e-dmac transmitter and receiver */
	sh_eth_write(eth, EDSR_ENALL, EDSR);

	/* Perform a software reset and wait for it to complete */
	sh_eth_write(eth, EDMR_SRST, EDMR);
	for (i = 0; i < TIMEOUT_CNT ; i++) {
		if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
			break;
		udelay(1000);
	}

	if (i == TIMEOUT_CNT) {
		printf(SHETHER_NAME  ": Software reset timeout\n");
		ret = -EIO;
	}

	return ret;
#else
	sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
	udelay(3000);
	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);

	return 0;
#endif
}

static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i, ret = 0;
	u32 tmp_addr;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct tx_desc_s *cur_tx_desc;

	/*
	 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	 */
	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
						 sizeof(struct tx_desc_s) +
						 TX_DESC_SIZE - 1);
	if (!port_info->tx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
			  ~(TX_DESC_SIZE - 1));
	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
	port_info->tx_desc_cur = port_info->tx_desc_base;

	/* Initialize all descriptors */
	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	     cur_tx_desc++, i++) {
		cur_tx_desc->td0 = 0x00;
		cur_tx_desc->td1 = 0x00;
		cur_tx_desc->td2 = 0x00;
	}

	/* Mark the end of the descriptors */
	cur_tx_desc--;
	cur_tx_desc->td0 |= TD_TDLE;

	/* Point the controller to the tx descriptor list. Must use physical
	   addresses */
	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
#endif

err:
	return ret;
}

static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i , ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct rx_desc_s *cur_rx_desc;
	u32 tmp_addr;
	u8 *rx_buf;

	/*
	 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	 */
	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
						 sizeof(struct rx_desc_s) +
						 RX_DESC_SIZE - 1);
	if (!port_info->rx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
			  ~(RX_DESC_SIZE - 1));
	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);

	port_info->rx_desc_cur = port_info->rx_desc_base;

	/*
	 * Allocate rx data buffers. They must be 32 bytes aligned  and in
	 * P2 area
	 */
	port_info->rx_buf_malloc = malloc(
		NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
	if (!port_info->rx_buf_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err_buf_malloc;
	}

	tmp_addr = (u32)(((int)port_info->rx_buf_malloc
			  + (RX_BUF_ALIGNE_SIZE - 1)) &
			  ~(RX_BUF_ALIGNE_SIZE - 1));
	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);

	/* Initialize all descriptors */
	for (cur_rx_desc = port_info->rx_desc_base,
	     rx_buf = port_info->rx_buf_base, i = 0;
	     i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
		cur_rx_desc->rd0 = RD_RACT;
		cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
		cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	}

	/* Mark the end of the descriptors */
	cur_rx_desc--;
	cur_rx_desc->rd0 |= RD_RDLE;

	/* Point the controller to the rx descriptor list */
	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
#endif

	return ret;

err_buf_malloc:
	free(port_info->rx_desc_malloc);
	port_info->rx_desc_malloc = NULL;

err:
	return ret;
}

static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->tx_desc_malloc) {
		free(port_info->tx_desc_malloc);
		port_info->tx_desc_malloc = NULL;
	}
}

static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->rx_desc_malloc) {
		free(port_info->rx_desc_malloc);
		port_info->rx_desc_malloc = NULL;
	}

	if (port_info->rx_buf_malloc) {
		free(port_info->rx_buf_malloc);
		port_info->rx_buf_malloc = NULL;
	}
}

static int sh_eth_desc_init(struct sh_eth_dev *eth)
{
	int ret = 0;

	ret = sh_eth_tx_desc_init(eth);
	if (ret)
		goto err_tx_init;

	ret = sh_eth_rx_desc_init(eth);
	if (ret)
		goto err_rx_init;

	return ret;
err_rx_init:
	sh_eth_tx_desc_free(eth);

err_tx_init:
	return ret;
}

static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
	int port = eth->port, ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct eth_device *dev = port_info->dev;
	struct phy_device *phydev;

	phydev = phy_connect(
			miiphy_get_dev_by_name(dev->name),
			port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
	port_info->phydev = phydev;
	phy_config(phydev);

	return ret;
}

static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
	int port = eth->port, ret = 0;
	u32 val;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct eth_device *dev = port_info->dev;
	struct phy_device *phy;

	/* Configure e-dmac registers */
	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
			(EMDR_DESC | EDMR_EL), EDMR);

	sh_eth_write(eth, 0, EESIPR);
	sh_eth_write(eth, 0, TRSCER);
	sh_eth_write(eth, 0, TFTR);
	sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
	sh_eth_write(eth, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, 0, RPADIR);
#endif
	sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);

	/* Configure e-mac registers */
	sh_eth_write(eth, 0, ECSIPR);

	/* Set Mac address */
	val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
	    dev->enetaddr[2] << 8 | dev->enetaddr[3];
	sh_eth_write(eth, val, MAHR);

	val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
	sh_eth_write(eth, val, MALR);

	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, 0, PIPR);
	sh_eth_write(eth, APR_AP, APR);
	sh_eth_write(eth, MPR_MP, MPR);
	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
#endif

#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
	sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
	/* Configure phy */
	ret = sh_eth_phy_config(eth);
	if (ret) {
		printf(SHETHER_NAME ": phy config timeout\n");
		goto err_phy_cfg;
	}
	phy = port_info->phydev;
	ret = phy_startup(phy);
	if (ret) {
		printf(SHETHER_NAME ": phy startup failure\n");
		return ret;
	}

	val = 0;

	/* Set the transfer speed */
	if (phy->speed == 100) {
		printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
		sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
		sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
		defined(CONFIG_R8A7791)
		val = ECMR_RTM;
#endif
	} else if (phy->speed == 10) {
		printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
		sh_eth_write(eth, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
		sh_eth_write(eth, 0, RTRATE);
#endif
	}
#if defined(SH_ETH_TYPE_GETHER)
	else if (phy->speed == 1000) {
		printf(SHETHER_NAME ": 1000Base/");
		sh_eth_write(eth, GECMR_1000B, GECMR);
	}
#endif

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex) {
		printf("Full\n");
		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
			     ECMR);
	} else {
		printf("Half\n");
		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
	}

	return ret;

err_phy_cfg:
	return ret;
}

static void sh_eth_start(struct sh_eth_dev *eth)
{
	/*
	 * Enable the e-dmac receiver only. The transmitter will be enabled when
	 * we have something to transmit
	 */
	sh_eth_write(eth, EDRRR_R, EDRRR);
}

static void sh_eth_stop(struct sh_eth_dev *eth)
{
	sh_eth_write(eth, ~EDRRR_R, EDRRR);
}

int sh_eth_init(struct eth_device *dev, bd_t *bd)
{
	int ret = 0;
	struct sh_eth_dev *eth = dev->priv;

	ret = sh_eth_reset(eth);
	if (ret)
		goto err;

	ret = sh_eth_desc_init(eth);
	if (ret)
		goto err;

	ret = sh_eth_config(eth, bd);
	if (ret)
		goto err_config;

	sh_eth_start(eth);

	return ret;

err_config:
	sh_eth_tx_desc_free(eth);
	sh_eth_rx_desc_free(eth);

err:
	return ret;
}

void sh_eth_halt(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	sh_eth_stop(eth);
}

int sh_eth_initialize(bd_t *bd)
{
    int ret = 0;
	struct sh_eth_dev *eth = NULL;
    struct eth_device *dev = NULL;

    eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	if (!eth) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}

    dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	if (!dev) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}
    memset(dev, 0, sizeof(struct eth_device));
    memset(eth, 0, sizeof(struct sh_eth_dev));

	eth->port = CONFIG_SH_ETHER_USE_PORT;
	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;

    dev->priv = (void *)eth;
    dev->iobase = 0;
    dev->init = sh_eth_init;
    dev->halt = sh_eth_halt;
    dev->send = sh_eth_send;
    dev->recv = sh_eth_recv;
    eth->port_info[eth->port].dev = dev;

	sprintf(dev->name, SHETHER_NAME);

    /* Register Device to EtherNet subsystem  */
    eth_register(dev);

	bb_miiphy_buses[0].priv = eth;
	miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);

	if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
		puts("Please set MAC address\n");

	return ret;

err:
	if (dev)
		free(dev);

	if (eth)
		free(eth);

	printf(SHETHER_NAME ": Failed\n");
	return ret;
}

/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct sh_eth_dev *eth = bus->priv;

	sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);

	return 0;
}

static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct sh_eth_dev *eth = bus->priv;

	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);

	return 0;
}

static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct sh_eth_dev *eth = bus->priv;

	if (v)
		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
	else
		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);

	return 0;
}

static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct sh_eth_dev *eth = bus->priv;

	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;

	return 0;
}

static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct sh_eth_dev *eth = bus->priv;

	if (v)
		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
	else
		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);

	return 0;
}

static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "sh_eth",
		.init		= sh_eth_bb_init,
		.mdio_active	= sh_eth_bb_mdio_active,
		.mdio_tristate	= sh_eth_bb_mdio_tristate,
		.set_mdio	= sh_eth_bb_set_mdio,
		.get_mdio	= sh_eth_bb_get_mdio,
		.set_mdc	= sh_eth_bb_set_mdc,
		.delay		= sh_eth_bb_delay,
	}
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
Commit	Line	Data
9751ee09	1	/*
26235093	2	* sh_eth.c - Driver for Renesas ethernet controler.
9751ee09	3	*
3bb4cc31 NI	4	* Copyright (C) 2008, 2011 Renesas Solutions Corp.
3bb4cc31 NI	5	* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
9751ee09	6	* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8707678c	7	* Copyright (C) 2013 Renesas Electronics Corporation
9751ee09	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
9751ee09 NI	10	*/
	11
	12	#include <config.h>
	13	#include <common.h>
	14	#include <malloc.h>
	15	#include <net.h>
bd3980cc	16	#include <netdev.h>
bd1024b0	17	#include <miiphy.h>
9751ee09 NI	18	#include <asm/errno.h>
	19	#include <asm/io.h>
	20
	21	#include "sh_eth.h"
	22
	23	#ifndef CONFIG_SH_ETHER_USE_PORT
	24	# error "Please define CONFIG_SH_ETHER_USE_PORT"
	25	#endif
	26	#ifndef CONFIG_SH_ETHER_PHY_ADDR
	27	# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
	28	#endif
870cc23f	29
92f07134 NI	30	#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
	31	#define flush_cache_wback(addr, len) \
	32	flush_dcache_range((u32)addr, (u32)(addr + len - 1))
68260aab YS	33	#else
	34	#define flush_cache_wback(...)
	35	#endif
9751ee09	36
92f07134 NI	37	#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
	38	#define invalidate_cache(addr, len) \
	39	{ \
	40	u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
	41	u32 start, end; \
	42	\
	43	start = (u32)addr; \
	44	end = start + len; \
	45	start &= ~(line_size - 1); \
	46	end = ((end + line_size - 1) & ~(line_size - 1)); \
	47	\
	48	invalidate_dcache_range(start, end); \
	49	}
	50	#else
	51	#define invalidate_cache(...)
	52	#endif
	53
4ba62c72 NI	54	#define TIMEOUT_CNT 1000
4ba62c72 NI	55
10cbe3b6	56	int sh_eth_send(struct eth_device dev, void packet, int len)
9751ee09	57	{
bd3980cc NI	58	struct sh_eth_dev *eth = dev->priv;
	59	int port = eth->port, ret = 0, timeout;
	60	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	61
9751ee09 NI	62	if (!packet \|\| len > 0xffff) {
bd3980cc NI	63	printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
	64	ret = -EINVAL;
	65	goto err;
9751ee09 NI	66	}
	67
	68	/* packet must be a 4 byte boundary */
ee6ec5d4	69	if ((int)packet & 3) {
bd3980cc NI	70	printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
	71	ret = -EFAULT;
	72	goto err;
9751ee09 NI	73	}
	74
	75	/* Update tx descriptor */
68260aab	76	flush_cache_wback(packet, len);
9751ee09 NI	77	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	78	port_info->tx_desc_cur->td1 = len << 16;
	79	/* Must preserve the end of descriptor list indication */
	80	if (port_info->tx_desc_cur->td0 & TD_TDLE)
	81	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP \| TD_TDLE;
	82	else
	83	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP;
	84
	85	/* Restart the transmitter if disabled */
49afb8ca YS	86	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
49afb8ca YS	87	sh_eth_write(eth, EDTRR_TRNS, EDTRR);
9751ee09 NI	88
9751ee09 NI	89	/* Wait until packet is transmitted */
4ba62c72	90	timeout = TIMEOUT_CNT;
92f07134 NI	91	do {
	92	invalidate_cache(port_info->tx_desc_cur,
	93	sizeof(struct tx_desc_s));
9751ee09	94	udelay(100);
92f07134	95	} while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
9751ee09 NI	96
9751ee09 NI	97	if (timeout < 0) {
bd3980cc NI	98	printf(SHETHER_NAME ": transmit timeout\n");
bd3980cc NI	99	ret = -ETIMEDOUT;
9751ee09 NI	100	goto err;
	101	}
	102
9751ee09 NI	103	port_info->tx_desc_cur++;
	104	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
	105	port_info->tx_desc_cur = port_info->tx_desc_base;
	106
bd3980cc NI	107	err:
bd3980cc NI	108	return ret;
9751ee09 NI	109	}
9751ee09 NI	110
bd3980cc	111	int sh_eth_recv(struct eth_device *dev)
9751ee09	112	{
bd3980cc NI	113	struct sh_eth_dev *eth = dev->priv;
	114	int port = eth->port, len = 0;
	115	struct sh_eth_info *port_info = &eth->port_info[port];
10cbe3b6	116	uchar *packet;
9751ee09 NI	117
9751ee09 NI	118	/* Check if the rx descriptor is ready */
92f07134	119	invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
9751ee09 NI	120	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
	121	/* Check for errors */
	122	if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
	123	len = port_info->rx_desc_cur->rd1 & 0xffff;
10cbe3b6 JH	124	packet = (uchar *)
10cbe3b6 JH	125	ADDR_TO_P2(port_info->rx_desc_cur->rd2);
92f07134	126	invalidate_cache(packet, len);
9751ee09 NI	127	NetReceive(packet, len);
	128	}
	129
	130	/* Make current descriptor available again */
	131	if (port_info->rx_desc_cur->rd0 & RD_RDLE)
	132	port_info->rx_desc_cur->rd0 = RD_RACT \| RD_RDLE;
	133	else
	134	port_info->rx_desc_cur->rd0 = RD_RACT;
9751ee09 NI	135	/* Point to the next descriptor */
	136	port_info->rx_desc_cur++;
	137	if (port_info->rx_desc_cur >=
	138	port_info->rx_desc_base + NUM_RX_DESC)
	139	port_info->rx_desc_cur = port_info->rx_desc_base;
	140	}
	141
	142	/* Restart the receiver if disabled */
49afb8ca YS	143	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
49afb8ca YS	144	sh_eth_write(eth, EDRRR_R, EDRRR);
9751ee09 NI	145
	146	return len;
	147	}
	148
bd3980cc	149	static int sh_eth_reset(struct sh_eth_dev *eth)
9751ee09	150	{
26235093	151	#if defined(SH_ETH_TYPE_GETHER)
bd3980cc	152	int ret = 0, i;
9751ee09 NI	153
9751ee09 NI	154	/* Start e-dmac transmitter and receiver */
49afb8ca	155	sh_eth_write(eth, EDSR_ENALL, EDSR);
9751ee09 NI	156
9751ee09 NI	157	/* Perform a software reset and wait for it to complete */
49afb8ca	158	sh_eth_write(eth, EDMR_SRST, EDMR);
4ba62c72	159	for (i = 0; i < TIMEOUT_CNT ; i++) {
49afb8ca	160	if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
9751ee09 NI	161	break;
	162	udelay(1000);
	163	}
	164
4ba62c72	165	if (i == TIMEOUT_CNT) {
bd3980cc NI	166	printf(SHETHER_NAME ": Software reset timeout\n");
bd3980cc NI	167	ret = -EIO;
9751ee09	168	}
bd3980cc NI	169
bd3980cc NI	170	return ret;
903de461	171	#else
49afb8ca	172	sh_eth_write(eth, sh_eth_read(eth, EDMR) \| EDMR_SRST, EDMR);
903de461	173	udelay(3000);
49afb8ca	174	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
903de461 YS	175
	176	return 0;
	177	#endif
9751ee09 NI	178	}
9751ee09 NI	179
bd3980cc	180	static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
9751ee09	181	{
bd3980cc	182	int port = eth->port, i, ret = 0;
9751ee09	183	u32 tmp_addr;
bd3980cc	184	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	185	struct tx_desc_s *cur_tx_desc;
9751ee09	186
bd3980cc NI	187	/*
	188	* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	189	*/
	190	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
9751ee09	191	sizeof(struct tx_desc_s) +
bd3980cc NI	192	TX_DESC_SIZE - 1);
	193	if (!port_info->tx_desc_malloc) {
	194	printf(SHETHER_NAME ": malloc failed\n");
	195	ret = -ENOMEM;
	196	goto err;
9751ee09	197	}
bd3980cc	198
9751ee09 NI	199	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
9751ee09 NI	200	~(TX_DESC_SIZE - 1));
68260aab	201	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
9751ee09 NI	202	/* Make sure we use a P2 address (non-cacheable) */
9751ee09 NI	203	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
9751ee09 NI	204	port_info->tx_desc_cur = port_info->tx_desc_base;
	205
	206	/* Initialize all descriptors */
	207	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	208	cur_tx_desc++, i++) {
	209	cur_tx_desc->td0 = 0x00;
	210	cur_tx_desc->td1 = 0x00;
	211	cur_tx_desc->td2 = 0x00;
	212	}
	213
	214	/* Mark the end of the descriptors */
	215	cur_tx_desc--;
	216	cur_tx_desc->td0 \|= TD_TDLE;
	217
	218	/* Point the controller to the tx descriptor list. Must use physical
	219	addresses */
49afb8ca	220	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
26235093	221	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	222	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
	223	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
	224	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
903de461	225	#endif
9751ee09	226
bd3980cc NI	227	err:
bd3980cc NI	228	return ret;
9751ee09 NI	229	}
9751ee09 NI	230
bd3980cc	231	static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
9751ee09	232	{
bd3980cc NI	233	int port = eth->port, i , ret = 0;
bd3980cc NI	234	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	235	struct rx_desc_s *cur_rx_desc;
bd3980cc	236	u32 tmp_addr;
9751ee09	237	u8 *rx_buf;
9751ee09	238
bd3980cc NI	239	/*
	240	* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	241	*/
	242	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
9751ee09	243	sizeof(struct rx_desc_s) +
bd3980cc NI	244	RX_DESC_SIZE - 1);
	245	if (!port_info->rx_desc_malloc) {
	246	printf(SHETHER_NAME ": malloc failed\n");
	247	ret = -ENOMEM;
	248	goto err;
9751ee09	249	}
bd3980cc	250
9751ee09 NI	251	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
9751ee09 NI	252	~(RX_DESC_SIZE - 1));
68260aab	253	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
9751ee09 NI	254	/* Make sure we use a P2 address (non-cacheable) */
	255	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
	256
	257	port_info->rx_desc_cur = port_info->rx_desc_base;
	258
bd3980cc NI	259	/*
	260	* Allocate rx data buffers. They must be 32 bytes aligned and in
	261	* P2 area
	262	*/
f8b7507d NI	263	port_info->rx_buf_malloc = malloc(
f8b7507d NI	264	NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
bd3980cc NI	265	if (!port_info->rx_buf_malloc) {
	266	printf(SHETHER_NAME ": malloc failed\n");
	267	ret = -ENOMEM;
	268	goto err_buf_malloc;
9751ee09	269	}
bd3980cc	270
f8b7507d NI	271	tmp_addr = (u32)(((int)port_info->rx_buf_malloc
	272	+ (RX_BUF_ALIGNE_SIZE - 1)) &
	273	~(RX_BUF_ALIGNE_SIZE - 1));
9751ee09 NI	274	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
	275
	276	/* Initialize all descriptors */
	277	for (cur_rx_desc = port_info->rx_desc_base,
	278	rx_buf = port_info->rx_buf_base, i = 0;
	279	i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
	280	cur_rx_desc->rd0 = RD_RACT;
	281	cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
	282	cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	283	}
	284
	285	/* Mark the end of the descriptors */
	286	cur_rx_desc--;
	287	cur_rx_desc->rd0 \|= RD_RDLE;
	288
	289	/* Point the controller to the rx descriptor list */
49afb8ca	290	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
26235093	291	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	292	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
	293	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
	294	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
903de461	295	#endif
9751ee09	296
bd3980cc NI	297	return ret;
	298
	299	err_buf_malloc:
	300	free(port_info->rx_desc_malloc);
	301	port_info->rx_desc_malloc = NULL;
	302
	303	err:
	304	return ret;
9751ee09 NI	305	}
9751ee09 NI	306
bd3980cc	307	static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
9751ee09	308	{
bd3980cc NI	309	int port = eth->port;
bd3980cc NI	310	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	311
	312	if (port_info->tx_desc_malloc) {
	313	free(port_info->tx_desc_malloc);
	314	port_info->tx_desc_malloc = NULL;
	315	}
bd3980cc NI	316	}
	317
	318	static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
	319	{
	320	int port = eth->port;
	321	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	322
	323	if (port_info->rx_desc_malloc) {
	324	free(port_info->rx_desc_malloc);
	325	port_info->rx_desc_malloc = NULL;
	326	}
	327
	328	if (port_info->rx_buf_malloc) {
	329	free(port_info->rx_buf_malloc);
	330	port_info->rx_buf_malloc = NULL;
	331	}
	332	}
	333
bd3980cc	334	static int sh_eth_desc_init(struct sh_eth_dev *eth)
9751ee09	335	{
bd3980cc	336	int ret = 0;
9751ee09	337
bd3980cc NI	338	ret = sh_eth_tx_desc_init(eth);
	339	if (ret)
	340	goto err_tx_init;
9751ee09	341
bd3980cc NI	342	ret = sh_eth_rx_desc_init(eth);
	343	if (ret)
	344	goto err_rx_init;
	345
	346	return ret;
	347	err_rx_init:
	348	sh_eth_tx_desc_free(eth);
	349
	350	err_tx_init:
	351	return ret;
9751ee09 NI	352	}
9751ee09 NI	353
bd3980cc	354	static int sh_eth_phy_config(struct sh_eth_dev *eth)
9751ee09	355	{
bd1024b0	356	int port = eth->port, ret = 0;
bd3980cc	357	struct sh_eth_info *port_info = &eth->port_info[port];
bd1024b0 YS	358	struct eth_device *dev = port_info->dev;
bd1024b0 YS	359	struct phy_device *phydev;
9751ee09	360
ee6ec5d4 NI	361	phydev = phy_connect(
ee6ec5d4 NI	362	miiphy_get_dev_by_name(dev->name),
4398d559	363	port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
bd1024b0 YS	364	port_info->phydev = phydev;
bd1024b0 YS	365	phy_config(phydev);
bd3980cc	366
bd3980cc	367	return ret;
9751ee09 NI	368	}
9751ee09 NI	369
bd3980cc	370	static int sh_eth_config(struct sh_eth_dev eth, bd_t bd)
9751ee09	371	{
bd3980cc	372	int port = eth->port, ret = 0;
bd1024b0	373	u32 val;
bd3980cc	374	struct sh_eth_info *port_info = &eth->port_info[port];
c527ce92	375	struct eth_device *dev = port_info->dev;
bd1024b0	376	struct phy_device *phy;
9751ee09 NI	377
9751ee09 NI	378	/* Configure e-dmac registers */
f8b7507d NI	379	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) \|
	380	(EMDR_DESC \| EDMR_EL), EDMR);
	381
49afb8ca YS	382	sh_eth_write(eth, 0, EESIPR);
	383	sh_eth_write(eth, 0, TRSCER);
	384	sh_eth_write(eth, 0, TFTR);
	385	sh_eth_write(eth, (FIFO_SIZE_T \| FIFO_SIZE_R), FDR);
	386	sh_eth_write(eth, RMCR_RST, RMCR);
26235093	387	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	388	sh_eth_write(eth, 0, RPADIR);
903de461	389	#endif
49afb8ca	390	sh_eth_write(eth, (FIFO_F_D_RFF \| FIFO_F_D_RFD), FCFTR);
9751ee09 NI	391
9751ee09 NI	392	/* Configure e-mac registers */
49afb8ca	393	sh_eth_write(eth, 0, ECSIPR);
9751ee09 NI	394
9751ee09 NI	395	/* Set Mac address */
c527ce92 MF	396	val = dev->enetaddr[0] << 24 \| dev->enetaddr[1] << 16 \|
c527ce92 MF	397	dev->enetaddr[2] << 8 \| dev->enetaddr[3];
49afb8ca	398	sh_eth_write(eth, val, MAHR);
9751ee09	399
c527ce92	400	val = dev->enetaddr[4] << 8 \| dev->enetaddr[5];
49afb8ca	401	sh_eth_write(eth, val, MALR);
9751ee09	402
49afb8ca	403	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
26235093	404	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	405	sh_eth_write(eth, 0, PIPR);
	406	sh_eth_write(eth, APR_AP, APR);
	407	sh_eth_write(eth, MPR_MP, MPR);
	408	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
903de461	409	#endif
3bb4cc31	410
dcd5a593	411	#if defined(CONFIG_CPU_SH7734) \|\| defined(CONFIG_R8A7740)
49afb8ca	412	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
47ce8890	413	#elif defined(CONFIG_R8A7790) \|\| defined(CONFIG_R8A7791)
8707678c	414	sh_eth_write(eth, sh_eth_read(eth, RMIIMR) \| 0x1, RMIIMR);
4398d559	415	#endif
9751ee09	416	/* Configure phy */
bd3980cc NI	417	ret = sh_eth_phy_config(eth);
bd3980cc NI	418	if (ret) {
88a4c2e7	419	printf(SHETHER_NAME ": phy config timeout\n");
bd3980cc NI	420	goto err_phy_cfg;
bd3980cc NI	421	}
bd1024b0	422	phy = port_info->phydev;
11af8d65 TT	423	ret = phy_startup(phy);
	424	if (ret) {
	425	printf(SHETHER_NAME ": phy startup failure\n");
	426	return ret;
	427	}
9751ee09	428
3bb4cc31 NI	429	val = 0;
3bb4cc31 NI	430
9751ee09	431	/* Set the transfer speed */
bd1024b0	432	if (phy->speed == 100) {
bd3980cc	433	printf(SHETHER_NAME ": 100Base/");
26235093	434	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	435	sh_eth_write(eth, GECMR_100B, GECMR);
e3bb3254	436	#elif defined(CONFIG_CPU_SH7757) \|\| defined(CONFIG_CPU_SH7752)
49afb8ca	437	sh_eth_write(eth, 1, RTRATE);
47ce8890 NI	438	#elif defined(CONFIG_CPU_SH7724) \|\| defined(CONFIG_R8A7790) \|\| \
47ce8890 NI	439	defined(CONFIG_R8A7791)
3bb4cc31 NI	440	val = ECMR_RTM;
3bb4cc31 NI	441	#endif
bd1024b0	442	} else if (phy->speed == 10) {
bd3980cc	443	printf(SHETHER_NAME ": 10Base/");
26235093	444	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	445	sh_eth_write(eth, GECMR_10B, GECMR);
e3bb3254	446	#elif defined(CONFIG_CPU_SH7757) \|\| defined(CONFIG_CPU_SH7752)
49afb8ca	447	sh_eth_write(eth, 0, RTRATE);
903de461	448	#endif
3bb4cc31	449	}
26235093	450	#if defined(SH_ETH_TYPE_GETHER)
4398d559 NI	451	else if (phy->speed == 1000) {
4398d559 NI	452	printf(SHETHER_NAME ": 1000Base/");
49afb8ca	453	sh_eth_write(eth, GECMR_1000B, GECMR);
4398d559 NI	454	}
4398d559 NI	455	#endif
9751ee09 NI	456
9751ee09 NI	457	/* Check if full duplex mode is supported by the phy */
bd1024b0	458	if (phy->duplex) {
9751ee09	459	printf("Full\n");
49afb8ca YS	460	sh_eth_write(eth, val \| (ECMR_CHG_DM\|ECMR_RE\|ECMR_TE\|ECMR_DM),
49afb8ca YS	461	ECMR);
9751ee09 NI	462	} else {
9751ee09 NI	463	printf("Half\n");
49afb8ca	464	sh_eth_write(eth, val \| (ECMR_CHG_DM\|ECMR_RE\|ECMR_TE), ECMR);
9751ee09	465	}
bd3980cc NI	466
	467	return ret;
	468
	469	err_phy_cfg:
	470	return ret;
9751ee09 NI	471	}
9751ee09 NI	472
bd3980cc	473	static void sh_eth_start(struct sh_eth_dev *eth)
9751ee09 NI	474	{
	475	/*
	476	* Enable the e-dmac receiver only. The transmitter will be enabled when
	477	* we have something to transmit
	478	*/
49afb8ca	479	sh_eth_write(eth, EDRRR_R, EDRRR);
bd3980cc	480	}
9751ee09	481
bd3980cc NI	482	static void sh_eth_stop(struct sh_eth_dev *eth)
bd3980cc NI	483	{
49afb8ca	484	sh_eth_write(eth, ~EDRRR_R, EDRRR);
9751ee09 NI	485	}
9751ee09 NI	486
bd3980cc	487	int sh_eth_init(struct eth_device dev, bd_t bd)
9751ee09	488	{
bd3980cc NI	489	int ret = 0;
bd3980cc NI	490	struct sh_eth_dev *eth = dev->priv;
9751ee09	491
bd3980cc NI	492	ret = sh_eth_reset(eth);
	493	if (ret)
	494	goto err;
9751ee09	495
bd3980cc NI	496	ret = sh_eth_desc_init(eth);
	497	if (ret)
	498	goto err;
9751ee09	499
bd3980cc NI	500	ret = sh_eth_config(eth, bd);
	501	if (ret)
	502	goto err_config;
	503
	504	sh_eth_start(eth);
	505
	506	return ret;
9751ee09	507
bd3980cc NI	508	err_config:
	509	sh_eth_tx_desc_free(eth);
	510	sh_eth_rx_desc_free(eth);
	511
	512	err:
	513	return ret;
	514	}
	515
	516	void sh_eth_halt(struct eth_device *dev)
	517	{
	518	struct sh_eth_dev *eth = dev->priv;
bd3980cc NI	519	sh_eth_stop(eth);
	520	}
	521
	522	int sh_eth_initialize(bd_t *bd)
	523	{
	524	int ret = 0;
	525	struct sh_eth_dev *eth = NULL;
	526	struct eth_device *dev = NULL;
	527
	528	eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	529	if (!eth) {
	530	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	531	ret = -ENOMEM;
9751ee09	532	goto err;
bd3980cc	533	}
9751ee09	534
bd3980cc NI	535	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	536	if (!dev) {
	537	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	538	ret = -ENOMEM;
	539	goto err;
	540	}
	541	memset(dev, 0, sizeof(struct eth_device));
	542	memset(eth, 0, sizeof(struct sh_eth_dev));
9751ee09	543
bd3980cc NI	544	eth->port = CONFIG_SH_ETHER_USE_PORT;
	545	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
	546
	547	dev->priv = (void *)eth;
	548	dev->iobase = 0;
	549	dev->init = sh_eth_init;
	550	dev->halt = sh_eth_halt;
	551	dev->send = sh_eth_send;
	552	dev->recv = sh_eth_recv;
	553	eth->port_info[eth->port].dev = dev;
	554
	555	sprintf(dev->name, SHETHER_NAME);
	556
	557	/* Register Device to EtherNet subsystem */
	558	eth_register(dev);
	559
bd1024b0 YS	560	bb_miiphy_buses[0].priv = eth;
	561	miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
	562
c527ce92 MF	563	if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
c527ce92 MF	564	puts("Please set MAC address\n");
bd3980cc NI	565
bd3980cc NI	566	return ret;
9751ee09	567
9751ee09	568	err:
bd3980cc NI	569	if (dev)
	570	free(dev);
	571
	572	if (eth)
	573	free(eth);
	574
	575	printf(SHETHER_NAME ": Failed\n");
	576	return ret;
9751ee09	577	}
bd1024b0 YS	578
	579	/***** for bb_miiphy *****/
	580	static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
	581	{
	582	return 0;
	583	}
	584
	585	static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
	586	{
	587	struct sh_eth_dev *eth = bus->priv;
bd1024b0	588
49afb8ca	589	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MMD, PIR);
bd1024b0 YS	590
	591	return 0;
	592	}
	593
	594	static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	595	{
	596	struct sh_eth_dev *eth = bus->priv;
bd1024b0	597
49afb8ca	598	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
bd1024b0 YS	599
	600	return 0;
	601	}
	602
	603	static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	604	{
	605	struct sh_eth_dev *eth = bus->priv;
bd1024b0 YS	606
bd1024b0 YS	607	if (v)
49afb8ca	608	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MDO, PIR);
bd1024b0	609	else
49afb8ca	610	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
bd1024b0 YS	611
	612	return 0;
	613	}
	614
	615	static int sh_eth_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	616	{
	617	struct sh_eth_dev *eth = bus->priv;
bd1024b0	618
49afb8ca	619	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
bd1024b0 YS	620
	621	return 0;
	622	}
	623
	624	static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	625	{
	626	struct sh_eth_dev *eth = bus->priv;
bd1024b0 YS	627
bd1024b0 YS	628	if (v)
49afb8ca	629	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MDC, PIR);
bd1024b0	630	else
49afb8ca	631	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
bd1024b0 YS	632
	633	return 0;
	634	}
	635
	636	static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
	637	{
	638	udelay(10);
	639
	640	return 0;
	641	}
	642
	643	struct bb_miiphy_bus bb_miiphy_buses[] = {
	644	{
	645	.name = "sh_eth",
	646	.init = sh_eth_bb_init,
	647	.mdio_active = sh_eth_bb_mdio_active,
	648	.mdio_tristate = sh_eth_bb_mdio_tristate,
	649	.set_mdio = sh_eth_bb_set_mdio,
	650	.get_mdio = sh_eth_bb_get_mdio,
	651	.set_mdc = sh_eth_bb_set_mdc,
	652	.delay = sh_eth_bb_delay,
	653	}
	654	};
	655	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);