[people/ms/u-boot.git] / drivers / net / sh_eth.c

/*
 * sh_eth.c - Driver for Renesas ethernet controler.
 *
 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/errno.h>
#include <asm/io.h>

#include "sh_eth.h"

#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#endif
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif

#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
#define flush_cache_wback(addr, len)	\
			flush_dcache_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif

#define TIMEOUT_CNT 1000

int sh_eth_send(struct eth_device *dev, void *packet, int len)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, ret = 0, timeout;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (!packet || len > 0xffff) {
		printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
		ret = -EINVAL;
		goto err;
	}

	/* packet must be a 4 byte boundary */
	if ((int)packet & 3) {
		printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
		ret = -EFAULT;
		goto err;
	}

	/* Update tx descriptor */
	flush_cache_wback(packet, len);
	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	port_info->tx_desc_cur->td1 = len << 16;
	/* Must preserve the end of descriptor list indication */
	if (port_info->tx_desc_cur->td0 & TD_TDLE)
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
	else
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;

	/* Restart the transmitter if disabled */
	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
		sh_eth_write(eth, EDTRR_TRNS, EDTRR);

	/* Wait until packet is transmitted */
	timeout = TIMEOUT_CNT;
	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
		udelay(100);

	if (timeout < 0) {
		printf(SHETHER_NAME ": transmit timeout\n");
		ret = -ETIMEDOUT;
		goto err;
	}

	port_info->tx_desc_cur++;
	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
		port_info->tx_desc_cur = port_info->tx_desc_base;

err:
	return ret;
}

int sh_eth_recv(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, len = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	uchar *packet;

	/* Check if the rx descriptor is ready */
	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
		/* Check for errors */
		if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
			len = port_info->rx_desc_cur->rd1 & 0xffff;
			packet = (uchar *)
				ADDR_TO_P2(port_info->rx_desc_cur->rd2);
			NetReceive(packet, len);
		}

		/* Make current descriptor available again */
		if (port_info->rx_desc_cur->rd0 & RD_RDLE)
			port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
		else
			port_info->rx_desc_cur->rd0 = RD_RACT;

		/* Point to the next descriptor */
		port_info->rx_desc_cur++;
		if (port_info->rx_desc_cur >=
		    port_info->rx_desc_base + NUM_RX_DESC)
			port_info->rx_desc_cur = port_info->rx_desc_base;
	}

	/* Restart the receiver if disabled */
	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
		sh_eth_write(eth, EDRRR_R, EDRRR);

	return len;
}

static int sh_eth_reset(struct sh_eth_dev *eth)
{
#if defined(SH_ETH_TYPE_GETHER)
	int ret = 0, i;

	/* Start e-dmac transmitter and receiver */
	sh_eth_write(eth, EDSR_ENALL, EDSR);

	/* Perform a software reset and wait for it to complete */
	sh_eth_write(eth, EDMR_SRST, EDMR);
	for (i = 0; i < TIMEOUT_CNT ; i++) {
		if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
			break;
		udelay(1000);
	}

	if (i == TIMEOUT_CNT) {
		printf(SHETHER_NAME  ": Software reset timeout\n");
		ret = -EIO;
	}

	return ret;
#else
	sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
	udelay(3000);
	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);

	return 0;
#endif
}

static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i, ret = 0;
	u32 tmp_addr;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct tx_desc_s *cur_tx_desc;

	/*
	 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	 */
	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
						 sizeof(struct tx_desc_s) +
						 TX_DESC_SIZE - 1);
	if (!port_info->tx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
			  ~(TX_DESC_SIZE - 1));
	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
	port_info->tx_desc_cur = port_info->tx_desc_base;

	/* Initialize all descriptors */
	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	     cur_tx_desc++, i++) {
		cur_tx_desc->td0 = 0x00;
		cur_tx_desc->td1 = 0x00;
		cur_tx_desc->td2 = 0x00;
	}

	/* Mark the end of the descriptors */
	cur_tx_desc--;
	cur_tx_desc->td0 |= TD_TDLE;

	/* Point the controller to the tx descriptor list. Must use physical
	   addresses */
	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
#endif

err:
	return ret;
}

static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i , ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct rx_desc_s *cur_rx_desc;
	u32 tmp_addr;
	u8 *rx_buf;

	/*
	 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	 */
	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
						 sizeof(struct rx_desc_s) +
						 RX_DESC_SIZE - 1);
	if (!port_info->rx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
			  ~(RX_DESC_SIZE - 1));
	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);

	port_info->rx_desc_cur = port_info->rx_desc_base;

	/*
	 * Allocate rx data buffers. They must be 32 bytes aligned  and in
	 * P2 area
	 */
	port_info->rx_buf_malloc = malloc(
		NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
	if (!port_info->rx_buf_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err_buf_malloc;
	}

	tmp_addr = (u32)(((int)port_info->rx_buf_malloc
			  + (RX_BUF_ALIGNE_SIZE - 1)) &
			  ~(RX_BUF_ALIGNE_SIZE - 1));
	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);

	/* Initialize all descriptors */
	for (cur_rx_desc = port_info->rx_desc_base,
	     rx_buf = port_info->rx_buf_base, i = 0;
	     i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
		cur_rx_desc->rd0 = RD_RACT;
		cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
		cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	}

	/* Mark the end of the descriptors */
	cur_rx_desc--;
	cur_rx_desc->rd0 |= RD_RDLE;

	/* Point the controller to the rx descriptor list */
	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
#endif

	return ret;

err_buf_malloc:
	free(port_info->rx_desc_malloc);
	port_info->rx_desc_malloc = NULL;

err:
	return ret;
}

static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->tx_desc_malloc) {
		free(port_info->tx_desc_malloc);
		port_info->tx_desc_malloc = NULL;
	}
}

static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->rx_desc_malloc) {
		free(port_info->rx_desc_malloc);
		port_info->rx_desc_malloc = NULL;
	}

	if (port_info->rx_buf_malloc) {
		free(port_info->rx_buf_malloc);
		port_info->rx_buf_malloc = NULL;
	}
}

static int sh_eth_desc_init(struct sh_eth_dev *eth)
{
	int ret = 0;

	ret = sh_eth_tx_desc_init(eth);
	if (ret)
		goto err_tx_init;

	ret = sh_eth_rx_desc_init(eth);
	if (ret)
		goto err_rx_init;

	return ret;
err_rx_init:
	sh_eth_tx_desc_free(eth);

err_tx_init:
	return ret;
}

static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
	int port = eth->port, ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct eth_device *dev = port_info->dev;
	struct phy_device *phydev;

	phydev = phy_connect(
			miiphy_get_dev_by_name(dev->name),
			port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
	port_info->phydev = phydev;
	phy_config(phydev);

	return ret;
}

static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
	int port = eth->port, ret = 0;
	u32 val;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct eth_device *dev = port_info->dev;
	struct phy_device *phy;

	/* Configure e-dmac registers */
	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
			(EMDR_DESC | EDMR_EL), EDMR);

	sh_eth_write(eth, 0, EESIPR);
	sh_eth_write(eth, 0, TRSCER);
	sh_eth_write(eth, 0, TFTR);
	sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
	sh_eth_write(eth, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, 0, RPADIR);
#endif
	sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);

	/* Configure e-mac registers */
	sh_eth_write(eth, 0, ECSIPR);

	/* Set Mac address */
	val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
	    dev->enetaddr[2] << 8 | dev->enetaddr[3];
	sh_eth_write(eth, val, MAHR);

	val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
	sh_eth_write(eth, val, MALR);

	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
	sh_eth_write(eth, 0, PIPR);
	sh_eth_write(eth, APR_AP, APR);
	sh_eth_write(eth, MPR_MP, MPR);
	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
#endif

#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#endif
	/* Configure phy */
	ret = sh_eth_phy_config(eth);
	if (ret) {
		printf(SHETHER_NAME ": phy config timeout\n");
		goto err_phy_cfg;
	}
	phy = port_info->phydev;
	ret = phy_startup(phy);
	if (ret) {
		printf(SHETHER_NAME ": phy startup failure\n");
		return ret;
	}

	val = 0;

	/* Set the transfer speed */
	if (phy->speed == 100) {
		printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
		sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
		sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724)
		val = ECMR_RTM;
#endif
	} else if (phy->speed == 10) {
		printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
		sh_eth_write(eth, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
		sh_eth_write(eth, 0, RTRATE);
#endif
	}
#if defined(SH_ETH_TYPE_GETHER)
	else if (phy->speed == 1000) {
		printf(SHETHER_NAME ": 1000Base/");
		sh_eth_write(eth, GECMR_1000B, GECMR);
	}
#endif

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex) {
		printf("Full\n");
		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
			     ECMR);
	} else {
		printf("Half\n");
		sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
	}

	return ret;

err_phy_cfg:
	return ret;
}

static void sh_eth_start(struct sh_eth_dev *eth)
{
	/*
	 * Enable the e-dmac receiver only. The transmitter will be enabled when
	 * we have something to transmit
	 */
	sh_eth_write(eth, EDRRR_R, EDRRR);
}

static void sh_eth_stop(struct sh_eth_dev *eth)
{
	sh_eth_write(eth, ~EDRRR_R, EDRRR);
}

int sh_eth_init(struct eth_device *dev, bd_t *bd)
{
	int ret = 0;
	struct sh_eth_dev *eth = dev->priv;

	ret = sh_eth_reset(eth);
	if (ret)
		goto err;

	ret = sh_eth_desc_init(eth);
	if (ret)
		goto err;

	ret = sh_eth_config(eth, bd);
	if (ret)
		goto err_config;

	sh_eth_start(eth);

	return ret;

err_config:
	sh_eth_tx_desc_free(eth);
	sh_eth_rx_desc_free(eth);

err:
	return ret;
}

void sh_eth_halt(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	sh_eth_stop(eth);
}

int sh_eth_initialize(bd_t *bd)
{
    int ret = 0;
	struct sh_eth_dev *eth = NULL;
    struct eth_device *dev = NULL;

    eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	if (!eth) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}

    dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	if (!dev) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}
    memset(dev, 0, sizeof(struct eth_device));
    memset(eth, 0, sizeof(struct sh_eth_dev));

	eth->port = CONFIG_SH_ETHER_USE_PORT;
	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;

    dev->priv = (void *)eth;
    dev->iobase = 0;
    dev->init = sh_eth_init;
    dev->halt = sh_eth_halt;
    dev->send = sh_eth_send;
    dev->recv = sh_eth_recv;
    eth->port_info[eth->port].dev = dev;

	sprintf(dev->name, SHETHER_NAME);

    /* Register Device to EtherNet subsystem  */
    eth_register(dev);

	bb_miiphy_buses[0].priv = eth;
	miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);

	if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
		puts("Please set MAC address\n");

	return ret;

err:
	if (dev)
		free(dev);

	if (eth)
		free(eth);

	printf(SHETHER_NAME ": Failed\n");
	return ret;
}

/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct sh_eth_dev *eth = bus->priv;

	sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);

	return 0;
}

static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct sh_eth_dev *eth = bus->priv;

	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);

	return 0;
}

static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct sh_eth_dev *eth = bus->priv;

	if (v)
		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
	else
		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);

	return 0;
}

static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct sh_eth_dev *eth = bus->priv;

	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;

	return 0;
}

static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct sh_eth_dev *eth = bus->priv;

	if (v)
		sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
	else
		sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);

	return 0;
}

static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "sh_eth",
		.init		= sh_eth_bb_init,
		.mdio_active	= sh_eth_bb_mdio_active,
		.mdio_tristate	= sh_eth_bb_mdio_tristate,
		.set_mdio	= sh_eth_bb_set_mdio,
		.get_mdio	= sh_eth_bb_get_mdio,
		.set_mdc	= sh_eth_bb_set_mdc,
		.delay		= sh_eth_bb_delay,
	}
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
Commit	Line	Data
9751ee09	1	/*
26235093	2	* sh_eth.c - Driver for Renesas ethernet controler.
9751ee09	3	*
3bb4cc31 NI	4	* Copyright (C) 2008, 2011 Renesas Solutions Corp.
3bb4cc31 NI	5	* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
9751ee09 NI	6	* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
9751ee09 NI	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
9751ee09 NI	9	*/
	10
	11	#include <config.h>
	12	#include <common.h>
	13	#include <malloc.h>
	14	#include <net.h>
bd3980cc	15	#include <netdev.h>
bd1024b0	16	#include <miiphy.h>
9751ee09 NI	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19
	20	#include "sh_eth.h"
	21
	22	#ifndef CONFIG_SH_ETHER_USE_PORT
	23	# error "Please define CONFIG_SH_ETHER_USE_PORT"
	24	#endif
	25	#ifndef CONFIG_SH_ETHER_PHY_ADDR
	26	# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
	27	#endif
870cc23f	28
68260aab YS	29	#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
68260aab YS	30	#define flush_cache_wback(addr, len) \
870cc23f	31	flush_dcache_range((u32)addr, (u32)(addr + len - 1))
68260aab YS	32	#else
	33	#define flush_cache_wback(...)
	34	#endif
9751ee09	35
4ba62c72 NI	36	#define TIMEOUT_CNT 1000
4ba62c72 NI	37
10cbe3b6	38	int sh_eth_send(struct eth_device dev, void packet, int len)
9751ee09	39	{
bd3980cc NI	40	struct sh_eth_dev *eth = dev->priv;
	41	int port = eth->port, ret = 0, timeout;
	42	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	43
9751ee09 NI	44	if (!packet \|\| len > 0xffff) {
bd3980cc NI	45	printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
	46	ret = -EINVAL;
	47	goto err;
9751ee09 NI	48	}
	49
	50	/* packet must be a 4 byte boundary */
ee6ec5d4	51	if ((int)packet & 3) {
bd3980cc NI	52	printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
	53	ret = -EFAULT;
	54	goto err;
9751ee09 NI	55	}
	56
	57	/* Update tx descriptor */
68260aab	58	flush_cache_wback(packet, len);
9751ee09 NI	59	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	60	port_info->tx_desc_cur->td1 = len << 16;
	61	/* Must preserve the end of descriptor list indication */
	62	if (port_info->tx_desc_cur->td0 & TD_TDLE)
	63	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP \| TD_TDLE;
	64	else
	65	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP;
	66
	67	/* Restart the transmitter if disabled */
49afb8ca YS	68	if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
49afb8ca YS	69	sh_eth_write(eth, EDTRR_TRNS, EDTRR);
9751ee09 NI	70
9751ee09 NI	71	/* Wait until packet is transmitted */
4ba62c72	72	timeout = TIMEOUT_CNT;
9751ee09 NI	73	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
	74	udelay(100);
	75
	76	if (timeout < 0) {
bd3980cc NI	77	printf(SHETHER_NAME ": transmit timeout\n");
bd3980cc NI	78	ret = -ETIMEDOUT;
9751ee09 NI	79	goto err;
	80	}
	81
9751ee09 NI	82	port_info->tx_desc_cur++;
	83	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
	84	port_info->tx_desc_cur = port_info->tx_desc_base;
	85
bd3980cc NI	86	err:
bd3980cc NI	87	return ret;
9751ee09 NI	88	}
9751ee09 NI	89
bd3980cc	90	int sh_eth_recv(struct eth_device *dev)
9751ee09	91	{
bd3980cc NI	92	struct sh_eth_dev *eth = dev->priv;
	93	int port = eth->port, len = 0;
	94	struct sh_eth_info *port_info = &eth->port_info[port];
10cbe3b6	95	uchar *packet;
9751ee09 NI	96
	97	/* Check if the rx descriptor is ready */
	98	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
	99	/* Check for errors */
	100	if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
	101	len = port_info->rx_desc_cur->rd1 & 0xffff;
10cbe3b6 JH	102	packet = (uchar *)
10cbe3b6 JH	103	ADDR_TO_P2(port_info->rx_desc_cur->rd2);
9751ee09 NI	104	NetReceive(packet, len);
	105	}
	106
	107	/* Make current descriptor available again */
	108	if (port_info->rx_desc_cur->rd0 & RD_RDLE)
	109	port_info->rx_desc_cur->rd0 = RD_RACT \| RD_RDLE;
	110	else
	111	port_info->rx_desc_cur->rd0 = RD_RACT;
	112
	113	/* Point to the next descriptor */
	114	port_info->rx_desc_cur++;
	115	if (port_info->rx_desc_cur >=
	116	port_info->rx_desc_base + NUM_RX_DESC)
	117	port_info->rx_desc_cur = port_info->rx_desc_base;
	118	}
	119
	120	/* Restart the receiver if disabled */
49afb8ca YS	121	if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
49afb8ca YS	122	sh_eth_write(eth, EDRRR_R, EDRRR);
9751ee09 NI	123
	124	return len;
	125	}
	126
bd3980cc	127	static int sh_eth_reset(struct sh_eth_dev *eth)
9751ee09	128	{
26235093	129	#if defined(SH_ETH_TYPE_GETHER)
bd3980cc	130	int ret = 0, i;
9751ee09 NI	131
9751ee09 NI	132	/* Start e-dmac transmitter and receiver */
49afb8ca	133	sh_eth_write(eth, EDSR_ENALL, EDSR);
9751ee09 NI	134
9751ee09 NI	135	/* Perform a software reset and wait for it to complete */
49afb8ca	136	sh_eth_write(eth, EDMR_SRST, EDMR);
4ba62c72	137	for (i = 0; i < TIMEOUT_CNT ; i++) {
49afb8ca	138	if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
9751ee09 NI	139	break;
	140	udelay(1000);
	141	}
	142
4ba62c72	143	if (i == TIMEOUT_CNT) {
bd3980cc NI	144	printf(SHETHER_NAME ": Software reset timeout\n");
bd3980cc NI	145	ret = -EIO;
9751ee09	146	}
bd3980cc NI	147
bd3980cc NI	148	return ret;
903de461	149	#else
49afb8ca	150	sh_eth_write(eth, sh_eth_read(eth, EDMR) \| EDMR_SRST, EDMR);
903de461	151	udelay(3000);
49afb8ca	152	sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
903de461 YS	153
	154	return 0;
	155	#endif
9751ee09 NI	156	}
9751ee09 NI	157
bd3980cc	158	static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
9751ee09	159	{
bd3980cc	160	int port = eth->port, i, ret = 0;
9751ee09	161	u32 tmp_addr;
bd3980cc	162	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	163	struct tx_desc_s *cur_tx_desc;
9751ee09	164
bd3980cc NI	165	/*
	166	* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	167	*/
	168	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
9751ee09	169	sizeof(struct tx_desc_s) +
bd3980cc NI	170	TX_DESC_SIZE - 1);
	171	if (!port_info->tx_desc_malloc) {
	172	printf(SHETHER_NAME ": malloc failed\n");
	173	ret = -ENOMEM;
	174	goto err;
9751ee09	175	}
bd3980cc	176
9751ee09 NI	177	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
9751ee09 NI	178	~(TX_DESC_SIZE - 1));
68260aab	179	flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
9751ee09 NI	180	/* Make sure we use a P2 address (non-cacheable) */
9751ee09 NI	181	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
9751ee09 NI	182	port_info->tx_desc_cur = port_info->tx_desc_base;
	183
	184	/* Initialize all descriptors */
	185	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	186	cur_tx_desc++, i++) {
	187	cur_tx_desc->td0 = 0x00;
	188	cur_tx_desc->td1 = 0x00;
	189	cur_tx_desc->td2 = 0x00;
	190	}
	191
	192	/* Mark the end of the descriptors */
	193	cur_tx_desc--;
	194	cur_tx_desc->td0 \|= TD_TDLE;
	195
	196	/* Point the controller to the tx descriptor list. Must use physical
	197	addresses */
49afb8ca	198	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
26235093	199	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	200	sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
	201	sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
	202	sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
903de461	203	#endif
9751ee09	204
bd3980cc NI	205	err:
bd3980cc NI	206	return ret;
9751ee09 NI	207	}
9751ee09 NI	208
bd3980cc	209	static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
9751ee09	210	{
bd3980cc NI	211	int port = eth->port, i , ret = 0;
bd3980cc NI	212	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	213	struct rx_desc_s *cur_rx_desc;
bd3980cc	214	u32 tmp_addr;
9751ee09	215	u8 *rx_buf;
9751ee09	216
bd3980cc NI	217	/*
	218	* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	219	*/
	220	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
9751ee09	221	sizeof(struct rx_desc_s) +
bd3980cc NI	222	RX_DESC_SIZE - 1);
	223	if (!port_info->rx_desc_malloc) {
	224	printf(SHETHER_NAME ": malloc failed\n");
	225	ret = -ENOMEM;
	226	goto err;
9751ee09	227	}
bd3980cc	228
9751ee09 NI	229	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
9751ee09 NI	230	~(RX_DESC_SIZE - 1));
68260aab	231	flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
9751ee09 NI	232	/* Make sure we use a P2 address (non-cacheable) */
	233	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
	234
	235	port_info->rx_desc_cur = port_info->rx_desc_base;
	236
bd3980cc NI	237	/*
	238	* Allocate rx data buffers. They must be 32 bytes aligned and in
	239	* P2 area
	240	*/
f8b7507d NI	241	port_info->rx_buf_malloc = malloc(
f8b7507d NI	242	NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
bd3980cc NI	243	if (!port_info->rx_buf_malloc) {
	244	printf(SHETHER_NAME ": malloc failed\n");
	245	ret = -ENOMEM;
	246	goto err_buf_malloc;
9751ee09	247	}
bd3980cc	248
f8b7507d NI	249	tmp_addr = (u32)(((int)port_info->rx_buf_malloc
	250	+ (RX_BUF_ALIGNE_SIZE - 1)) &
	251	~(RX_BUF_ALIGNE_SIZE - 1));
9751ee09 NI	252	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
	253
	254	/* Initialize all descriptors */
	255	for (cur_rx_desc = port_info->rx_desc_base,
	256	rx_buf = port_info->rx_buf_base, i = 0;
	257	i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
	258	cur_rx_desc->rd0 = RD_RACT;
	259	cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
	260	cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	261	}
	262
	263	/* Mark the end of the descriptors */
	264	cur_rx_desc--;
	265	cur_rx_desc->rd0 \|= RD_RDLE;
	266
	267	/* Point the controller to the rx descriptor list */
49afb8ca	268	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
26235093	269	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	270	sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
	271	sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
	272	sh_eth_write(eth, RDFFR_RDLF, RDFFR);
903de461	273	#endif
9751ee09	274
bd3980cc NI	275	return ret;
	276
	277	err_buf_malloc:
	278	free(port_info->rx_desc_malloc);
	279	port_info->rx_desc_malloc = NULL;
	280
	281	err:
	282	return ret;
9751ee09 NI	283	}
9751ee09 NI	284
bd3980cc	285	static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
9751ee09	286	{
bd3980cc NI	287	int port = eth->port;
bd3980cc NI	288	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	289
	290	if (port_info->tx_desc_malloc) {
	291	free(port_info->tx_desc_malloc);
	292	port_info->tx_desc_malloc = NULL;
	293	}
bd3980cc NI	294	}
	295
	296	static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
	297	{
	298	int port = eth->port;
	299	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	300
	301	if (port_info->rx_desc_malloc) {
	302	free(port_info->rx_desc_malloc);
	303	port_info->rx_desc_malloc = NULL;
	304	}
	305
	306	if (port_info->rx_buf_malloc) {
	307	free(port_info->rx_buf_malloc);
	308	port_info->rx_buf_malloc = NULL;
	309	}
	310	}
	311
bd3980cc	312	static int sh_eth_desc_init(struct sh_eth_dev *eth)
9751ee09	313	{
bd3980cc	314	int ret = 0;
9751ee09	315
bd3980cc NI	316	ret = sh_eth_tx_desc_init(eth);
	317	if (ret)
	318	goto err_tx_init;
9751ee09	319
bd3980cc NI	320	ret = sh_eth_rx_desc_init(eth);
	321	if (ret)
	322	goto err_rx_init;
	323
	324	return ret;
	325	err_rx_init:
	326	sh_eth_tx_desc_free(eth);
	327
	328	err_tx_init:
	329	return ret;
9751ee09 NI	330	}
9751ee09 NI	331
bd3980cc	332	static int sh_eth_phy_config(struct sh_eth_dev *eth)
9751ee09	333	{
bd1024b0	334	int port = eth->port, ret = 0;
bd3980cc	335	struct sh_eth_info *port_info = &eth->port_info[port];
bd1024b0 YS	336	struct eth_device *dev = port_info->dev;
bd1024b0 YS	337	struct phy_device *phydev;
9751ee09	338
ee6ec5d4 NI	339	phydev = phy_connect(
ee6ec5d4 NI	340	miiphy_get_dev_by_name(dev->name),
4398d559	341	port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
bd1024b0 YS	342	port_info->phydev = phydev;
bd1024b0 YS	343	phy_config(phydev);
bd3980cc	344
bd3980cc	345	return ret;
9751ee09 NI	346	}
9751ee09 NI	347
bd3980cc	348	static int sh_eth_config(struct sh_eth_dev eth, bd_t bd)
9751ee09	349	{
bd3980cc	350	int port = eth->port, ret = 0;
bd1024b0	351	u32 val;
bd3980cc	352	struct sh_eth_info *port_info = &eth->port_info[port];
c527ce92	353	struct eth_device *dev = port_info->dev;
bd1024b0	354	struct phy_device *phy;
9751ee09 NI	355
9751ee09 NI	356	/* Configure e-dmac registers */
f8b7507d NI	357	sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) \|
	358	(EMDR_DESC \| EDMR_EL), EDMR);
	359
49afb8ca YS	360	sh_eth_write(eth, 0, EESIPR);
	361	sh_eth_write(eth, 0, TRSCER);
	362	sh_eth_write(eth, 0, TFTR);
	363	sh_eth_write(eth, (FIFO_SIZE_T \| FIFO_SIZE_R), FDR);
	364	sh_eth_write(eth, RMCR_RST, RMCR);
26235093	365	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	366	sh_eth_write(eth, 0, RPADIR);
903de461	367	#endif
49afb8ca	368	sh_eth_write(eth, (FIFO_F_D_RFF \| FIFO_F_D_RFD), FCFTR);
9751ee09 NI	369
9751ee09 NI	370	/* Configure e-mac registers */
49afb8ca	371	sh_eth_write(eth, 0, ECSIPR);
9751ee09 NI	372
9751ee09 NI	373	/* Set Mac address */
c527ce92 MF	374	val = dev->enetaddr[0] << 24 \| dev->enetaddr[1] << 16 \|
c527ce92 MF	375	dev->enetaddr[2] << 8 \| dev->enetaddr[3];
49afb8ca	376	sh_eth_write(eth, val, MAHR);
9751ee09	377
c527ce92	378	val = dev->enetaddr[4] << 8 \| dev->enetaddr[5];
49afb8ca	379	sh_eth_write(eth, val, MALR);
9751ee09	380
49afb8ca	381	sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
26235093	382	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca YS	383	sh_eth_write(eth, 0, PIPR);
	384	sh_eth_write(eth, APR_AP, APR);
	385	sh_eth_write(eth, MPR_MP, MPR);
	386	sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
903de461	387	#endif
3bb4cc31	388
dcd5a593	389	#if defined(CONFIG_CPU_SH7734) \|\| defined(CONFIG_R8A7740)
49afb8ca	390	sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
4398d559	391	#endif
9751ee09	392	/* Configure phy */
bd3980cc NI	393	ret = sh_eth_phy_config(eth);
bd3980cc NI	394	if (ret) {
88a4c2e7	395	printf(SHETHER_NAME ": phy config timeout\n");
bd3980cc NI	396	goto err_phy_cfg;
bd3980cc NI	397	}
bd1024b0	398	phy = port_info->phydev;
11af8d65 TT	399	ret = phy_startup(phy);
	400	if (ret) {
	401	printf(SHETHER_NAME ": phy startup failure\n");
	402	return ret;
	403	}
9751ee09	404
3bb4cc31 NI	405	val = 0;
3bb4cc31 NI	406
9751ee09	407	/* Set the transfer speed */
bd1024b0	408	if (phy->speed == 100) {
bd3980cc	409	printf(SHETHER_NAME ": 100Base/");
26235093	410	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	411	sh_eth_write(eth, GECMR_100B, GECMR);
e3bb3254	412	#elif defined(CONFIG_CPU_SH7757) \|\| defined(CONFIG_CPU_SH7752)
49afb8ca	413	sh_eth_write(eth, 1, RTRATE);
3bb4cc31 NI	414	#elif defined(CONFIG_CPU_SH7724)
	415	val = ECMR_RTM;
	416	#endif
bd1024b0	417	} else if (phy->speed == 10) {
bd3980cc	418	printf(SHETHER_NAME ": 10Base/");
26235093	419	#if defined(SH_ETH_TYPE_GETHER)
49afb8ca	420	sh_eth_write(eth, GECMR_10B, GECMR);
e3bb3254	421	#elif defined(CONFIG_CPU_SH7757) \|\| defined(CONFIG_CPU_SH7752)
49afb8ca	422	sh_eth_write(eth, 0, RTRATE);
903de461	423	#endif
3bb4cc31	424	}
26235093	425	#if defined(SH_ETH_TYPE_GETHER)
4398d559 NI	426	else if (phy->speed == 1000) {
4398d559 NI	427	printf(SHETHER_NAME ": 1000Base/");
49afb8ca	428	sh_eth_write(eth, GECMR_1000B, GECMR);
4398d559 NI	429	}
4398d559 NI	430	#endif
9751ee09 NI	431
9751ee09 NI	432	/* Check if full duplex mode is supported by the phy */
bd1024b0	433	if (phy->duplex) {
9751ee09	434	printf("Full\n");
49afb8ca YS	435	sh_eth_write(eth, val \| (ECMR_CHG_DM\|ECMR_RE\|ECMR_TE\|ECMR_DM),
49afb8ca YS	436	ECMR);
9751ee09 NI	437	} else {
9751ee09 NI	438	printf("Half\n");
49afb8ca	439	sh_eth_write(eth, val \| (ECMR_CHG_DM\|ECMR_RE\|ECMR_TE), ECMR);
9751ee09	440	}
bd3980cc NI	441
	442	return ret;
	443
	444	err_phy_cfg:
	445	return ret;
9751ee09 NI	446	}
9751ee09 NI	447
bd3980cc	448	static void sh_eth_start(struct sh_eth_dev *eth)
9751ee09 NI	449	{
	450	/*
	451	* Enable the e-dmac receiver only. The transmitter will be enabled when
	452	* we have something to transmit
	453	*/
49afb8ca	454	sh_eth_write(eth, EDRRR_R, EDRRR);
bd3980cc	455	}
9751ee09	456
bd3980cc NI	457	static void sh_eth_stop(struct sh_eth_dev *eth)
bd3980cc NI	458	{
49afb8ca	459	sh_eth_write(eth, ~EDRRR_R, EDRRR);
9751ee09 NI	460	}
9751ee09 NI	461
bd3980cc	462	int sh_eth_init(struct eth_device dev, bd_t bd)
9751ee09	463	{
bd3980cc NI	464	int ret = 0;
bd3980cc NI	465	struct sh_eth_dev *eth = dev->priv;
9751ee09	466
bd3980cc NI	467	ret = sh_eth_reset(eth);
	468	if (ret)
	469	goto err;
9751ee09	470
bd3980cc NI	471	ret = sh_eth_desc_init(eth);
	472	if (ret)
	473	goto err;
9751ee09	474
bd3980cc NI	475	ret = sh_eth_config(eth, bd);
	476	if (ret)
	477	goto err_config;
	478
	479	sh_eth_start(eth);
	480
	481	return ret;
9751ee09	482
bd3980cc NI	483	err_config:
	484	sh_eth_tx_desc_free(eth);
	485	sh_eth_rx_desc_free(eth);
	486
	487	err:
	488	return ret;
	489	}
	490
	491	void sh_eth_halt(struct eth_device *dev)
	492	{
	493	struct sh_eth_dev *eth = dev->priv;
bd3980cc NI	494	sh_eth_stop(eth);
	495	}
	496
	497	int sh_eth_initialize(bd_t *bd)
	498	{
	499	int ret = 0;
	500	struct sh_eth_dev *eth = NULL;
	501	struct eth_device *dev = NULL;
	502
	503	eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	504	if (!eth) {
	505	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	506	ret = -ENOMEM;
9751ee09	507	goto err;
bd3980cc	508	}
9751ee09	509
bd3980cc NI	510	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	511	if (!dev) {
	512	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	513	ret = -ENOMEM;
	514	goto err;
	515	}
	516	memset(dev, 0, sizeof(struct eth_device));
	517	memset(eth, 0, sizeof(struct sh_eth_dev));
9751ee09	518
bd3980cc NI	519	eth->port = CONFIG_SH_ETHER_USE_PORT;
	520	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
	521
	522	dev->priv = (void *)eth;
	523	dev->iobase = 0;
	524	dev->init = sh_eth_init;
	525	dev->halt = sh_eth_halt;
	526	dev->send = sh_eth_send;
	527	dev->recv = sh_eth_recv;
	528	eth->port_info[eth->port].dev = dev;
	529
	530	sprintf(dev->name, SHETHER_NAME);
	531
	532	/* Register Device to EtherNet subsystem */
	533	eth_register(dev);
	534
bd1024b0 YS	535	bb_miiphy_buses[0].priv = eth;
	536	miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
	537
c527ce92 MF	538	if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
c527ce92 MF	539	puts("Please set MAC address\n");
bd3980cc NI	540
bd3980cc NI	541	return ret;
9751ee09	542
9751ee09	543	err:
bd3980cc NI	544	if (dev)
	545	free(dev);
	546
	547	if (eth)
	548	free(eth);
	549
	550	printf(SHETHER_NAME ": Failed\n");
	551	return ret;
9751ee09	552	}
bd1024b0 YS	553
	554	/***** for bb_miiphy *****/
	555	static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
	556	{
	557	return 0;
	558	}
	559
	560	static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
	561	{
	562	struct sh_eth_dev *eth = bus->priv;
bd1024b0	563
49afb8ca	564	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MMD, PIR);
bd1024b0 YS	565
	566	return 0;
	567	}
	568
	569	static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	570	{
	571	struct sh_eth_dev *eth = bus->priv;
bd1024b0	572
49afb8ca	573	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
bd1024b0 YS	574
	575	return 0;
	576	}
	577
	578	static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	579	{
	580	struct sh_eth_dev *eth = bus->priv;
bd1024b0 YS	581
bd1024b0 YS	582	if (v)
49afb8ca	583	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MDO, PIR);
bd1024b0	584	else
49afb8ca	585	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
bd1024b0 YS	586
	587	return 0;
	588	}
	589
	590	static int sh_eth_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	591	{
	592	struct sh_eth_dev *eth = bus->priv;
bd1024b0	593
49afb8ca	594	*v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
bd1024b0 YS	595
	596	return 0;
	597	}
	598
	599	static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	600	{
	601	struct sh_eth_dev *eth = bus->priv;
bd1024b0 YS	602
bd1024b0 YS	603	if (v)
49afb8ca	604	sh_eth_write(eth, sh_eth_read(eth, PIR) \| PIR_MDC, PIR);
bd1024b0	605	else
49afb8ca	606	sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
bd1024b0 YS	607
	608	return 0;
	609	}
	610
	611	static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
	612	{
	613	udelay(10);
	614
	615	return 0;
	616	}
	617
	618	struct bb_miiphy_bus bb_miiphy_buses[] = {
	619	{
	620	.name = "sh_eth",
	621	.init = sh_eth_bb_init,
	622	.mdio_active = sh_eth_bb_mdio_active,
	623	.mdio_tristate = sh_eth_bb_mdio_tristate,
	624	.set_mdio = sh_eth_bb_set_mdio,
	625	.get_mdio = sh_eth_bb_get_mdio,
	626	.set_mdc = sh_eth_bb_set_mdc,
	627	.delay = sh_eth_bb_delay,
	628	}
	629	};
	630	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);