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9b56f4f0 SH |
1 | /* |
2 | * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <common.h> | |
4ec3d2a7 | 21 | #include <watchdog.h> |
47d19da4 | 22 | #ifdef CONFIG_MX31 |
9b56f4f0 | 23 | #include <asm/arch/mx31.h> |
47d19da4 IY |
24 | #else |
25 | #include <asm/arch/imx-regs.h> | |
26 | #include <asm/arch/clock.h> | |
27 | #endif | |
9b56f4f0 SH |
28 | |
29 | #define __REG(x) (*((volatile u32 *)(x))) | |
30 | ||
552ff8f1 | 31 | #if defined(CONFIG_SYS_MX31_UART1) || defined(CONFIG_SYS_MX25_UART1) |
9b56f4f0 | 32 | #define UART_PHYS 0x43f90000 |
552ff8f1 | 33 | #elif defined(CONFIG_SYS_MX31_UART2) || defined(CONFIG_SYS_MX25_UART2) |
9b56f4f0 | 34 | #define UART_PHYS 0x43f94000 |
552ff8f1 | 35 | #elif defined(CONFIG_SYS_MX31_UART3) || defined(CONFIG_SYS_MX25_UART3) |
9b56f4f0 | 36 | #define UART_PHYS 0x5000c000 |
552ff8f1 | 37 | #elif defined(CONFIG_SYS_MX31_UART4) || defined(CONFIG_SYS_MX25_UART4) |
9b56f4f0 | 38 | #define UART_PHYS 0x43fb0000 |
552ff8f1 | 39 | #elif defined(CONFIG_SYS_MX31_UART5) || defined(CONFIG_SYS_MX25_UART5) |
9b56f4f0 | 40 | #define UART_PHYS 0x43fb4000 |
47d19da4 IY |
41 | #elif defined(CONFIG_SYS_MX27_UART1) |
42 | #define UART_PHYS 0x1000a000 | |
43 | #elif defined(CONFIG_SYS_MX27_UART2) | |
44 | #define UART_PHYS 0x1000b000 | |
45 | #elif defined(CONFIG_SYS_MX27_UART3) | |
46 | #define UART_PHYS 0x1000c000 | |
47 | #elif defined(CONFIG_SYS_MX27_UART4) | |
48 | #define UART_PHYS 0x1000d000 | |
49 | #elif defined(CONFIG_SYS_MX27_UART5) | |
50 | #define UART_PHYS 0x1001b000 | |
51 | #elif defined(CONFIG_SYS_MX27_UART6) | |
52 | #define UART_PHYS 0x1001c000 | |
1b22b0d3 SB |
53 | #elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \ |
54 | defined(CONFIG_SYS_MX53_UART1) | |
71d64c0e | 55 | #define UART_PHYS UART1_BASE_ADDR |
1b22b0d3 SB |
56 | #elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \ |
57 | defined(CONFIG_SYS_MX53_UART2) | |
71d64c0e | 58 | #define UART_PHYS UART2_BASE_ADDR |
1b22b0d3 SB |
59 | #elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \ |
60 | defined(CONFIG_SYS_MX53_UART3) | |
0c466ad0 | 61 | #define UART_PHYS UART3_BASE_ADDR |
9b56f4f0 | 62 | #else |
71d64c0e SB |
63 | #error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" |
64 | #endif | |
65 | ||
66 | #ifdef CONFIG_SERIAL_MULTI | |
67 | #warning "MXC driver does not support MULTI serials." | |
9b56f4f0 SH |
68 | #endif |
69 | ||
70 | /* Register definitions */ | |
71 | #define URXD 0x0 /* Receiver Register */ | |
72 | #define UTXD 0x40 /* Transmitter Register */ | |
73 | #define UCR1 0x80 /* Control Register 1 */ | |
74 | #define UCR2 0x84 /* Control Register 2 */ | |
75 | #define UCR3 0x88 /* Control Register 3 */ | |
76 | #define UCR4 0x8c /* Control Register 4 */ | |
77 | #define UFCR 0x90 /* FIFO Control Register */ | |
78 | #define USR1 0x94 /* Status Register 1 */ | |
79 | #define USR2 0x98 /* Status Register 2 */ | |
80 | #define UESC 0x9c /* Escape Character Register */ | |
81 | #define UTIM 0xa0 /* Escape Timer Register */ | |
82 | #define UBIR 0xa4 /* BRM Incremental Register */ | |
83 | #define UBMR 0xa8 /* BRM Modulator Register */ | |
84 | #define UBRC 0xac /* Baud Rate Count Register */ | |
85 | #define UTS 0xb4 /* UART Test Register (mx31) */ | |
86 | ||
87 | /* UART Control Register Bit Fields.*/ | |
88 | #define URXD_CHARRDY (1<<15) | |
89 | #define URXD_ERR (1<<14) | |
90 | #define URXD_OVRRUN (1<<13) | |
91 | #define URXD_FRMERR (1<<12) | |
92 | #define URXD_BRK (1<<11) | |
93 | #define URXD_PRERR (1<<10) | |
d92ea21b | 94 | #define URXD_RX_DATA (0xFF) |
9b56f4f0 SH |
95 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ |
96 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | |
97 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | |
98 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | |
99 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | |
100 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | |
101 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | |
102 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | |
103 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | |
104 | #define UCR1_SNDBRK (1<<4) /* Send break */ | |
105 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | |
106 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | |
107 | #define UCR1_DOZE (1<<1) /* Doze */ | |
108 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | |
53677ef1 WD |
109 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
110 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | |
111 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | |
9b56f4f0 SH |
112 | #define UCR2_CTS (1<<12) /* Clear to send */ |
113 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | |
114 | #define UCR2_PREN (1<<8) /* Parity enable */ | |
115 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | |
116 | #define UCR2_STPB (1<<6) /* Stop */ | |
117 | #define UCR2_WS (1<<5) /* Word size */ | |
118 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
119 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
120 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
53677ef1 WD |
121 | #define UCR2_SRST (1<<0) /* SW reset */ |
122 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | |
9b56f4f0 SH |
123 | #define UCR3_PARERREN (1<<12) /* Parity enable */ |
124 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | |
125 | #define UCR3_DSR (1<<10) /* Data set ready */ | |
126 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | |
127 | #define UCR3_RI (1<<8) /* Ring indicator */ | |
128 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | |
129 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | |
130 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | |
131 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | |
53677ef1 WD |
132 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ |
133 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ | |
134 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | |
135 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | |
9b56f4f0 | 136 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ |
53677ef1 WD |
137 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ |
138 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | |
139 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | |
140 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | |
141 | #define UCR4_IRSC (1<<5) /* IR special case */ | |
142 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | |
143 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | |
144 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | |
145 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | |
9b56f4f0 SH |
146 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ |
147 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | |
148 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ | |
149 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | |
53677ef1 WD |
150 | #define USR1_RTSS (1<<14) /* RTS pin status */ |
151 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | |
152 | #define USR1_RTSD (1<<12) /* RTS delta */ | |
153 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | |
9b56f4f0 SH |
154 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ |
155 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | |
156 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | |
53677ef1 | 157 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ |
9b56f4f0 | 158 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ |
53677ef1 WD |
159 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ |
160 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | |
161 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | |
162 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | |
163 | #define USR2_IDLE (1<<12) /* Idle condition */ | |
164 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | |
165 | #define USR2_WAKE (1<<7) /* Wake */ | |
166 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | |
167 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | |
168 | #define USR2_BRCD (1<<2) /* Break condition */ | |
9b56f4f0 SH |
169 | #define USR2_ORE (1<<1) /* Overrun error */ |
170 | #define USR2_RDR (1<<0) /* Recv data ready */ | |
171 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | |
172 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | |
173 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | |
174 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | |
53677ef1 WD |
175 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ |
176 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | |
9b56f4f0 SH |
177 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
178 | ||
179 | DECLARE_GLOBAL_DATA_PTR; | |
180 | ||
181 | void serial_setbrg (void) | |
182 | { | |
71d64c0e | 183 | u32 clk = imx_get_uartclk(); |
9b56f4f0 SH |
184 | |
185 | if (!gd->baudrate) | |
186 | gd->baudrate = CONFIG_BAUDRATE; | |
187 | ||
188 | __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ | |
189 | __REG(UART_PHYS + UBIR) = 0xf; | |
190 | __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); | |
191 | ||
192 | } | |
193 | ||
194 | int serial_getc (void) | |
195 | { | |
4ec3d2a7 SB |
196 | while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) |
197 | WATCHDOG_RESET(); | |
d92ea21b | 198 | return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ |
9b56f4f0 SH |
199 | } |
200 | ||
201 | void serial_putc (const char c) | |
202 | { | |
203 | __REG(UART_PHYS + UTXD) = c; | |
204 | ||
205 | /* wait for transmitter to be ready */ | |
4ec3d2a7 SB |
206 | while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) |
207 | WATCHDOG_RESET(); | |
9b56f4f0 SH |
208 | |
209 | /* If \n, also do \r */ | |
210 | if (c == '\n') | |
211 | serial_putc ('\r'); | |
212 | } | |
213 | ||
214 | /* | |
215 | * Test whether a character is in the RX buffer | |
216 | */ | |
217 | int serial_tstc (void) | |
218 | { | |
219 | /* If receive fifo is empty, return false */ | |
220 | if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) | |
221 | return 0; | |
222 | return 1; | |
223 | } | |
224 | ||
225 | void | |
226 | serial_puts (const char *s) | |
227 | { | |
228 | while (*s) { | |
229 | serial_putc (*s++); | |
230 | } | |
231 | } | |
232 | ||
233 | /* | |
234 | * Initialise the serial port with the given baudrate. The settings | |
235 | * are always 8 data bits, no parity, 1 stop bit, no start bits. | |
236 | * | |
237 | */ | |
238 | int serial_init (void) | |
239 | { | |
240 | __REG(UART_PHYS + UCR1) = 0x0; | |
241 | __REG(UART_PHYS + UCR2) = 0x0; | |
242 | ||
243 | while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); | |
244 | ||
245 | __REG(UART_PHYS + UCR3) = 0x0704; | |
246 | __REG(UART_PHYS + UCR4) = 0x8000; | |
247 | __REG(UART_PHYS + UESC) = 0x002b; | |
248 | __REG(UART_PHYS + UTIM) = 0x0; | |
249 | ||
250 | __REG(UART_PHYS + UTS) = 0x0; | |
251 | ||
252 | serial_setbrg(); | |
253 | ||
254 | __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; | |
255 | ||
256 | __REG(UART_PHYS + UCR1) = UCR1_UARTEN; | |
257 | ||
258 | return 0; | |
259 | } |