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Commit | Line | Data |
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adde6300 AM |
1 | /* tc-avr.c -- Assembler code for the ATMEL AVR |
2 | ||
b90efa5b | 3 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
adde6300 AM |
4 | Contributed by Denis Chertykov <denisc@overta.ru> |
5 | ||
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
adde6300 AM |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
20 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
adde6300 | 22 | |
adde6300 | 23 | #include "as.h" |
3882b010 | 24 | #include "safe-ctype.h" |
adde6300 | 25 | #include "subsegs.h" |
fb5b7503 | 26 | #include "dwarf2dbg.h" |
af3ecb4a | 27 | #include "dw2gencfi.h" |
eac7440d | 28 | #include "elf/avr.h" |
adde6300 | 29 | |
1188e082 DC |
30 | struct avr_opcodes_s |
31 | { | |
dc191a8f NC |
32 | char * name; |
33 | char * constraints; | |
8cc66334 | 34 | char * opcode; |
dc191a8f NC |
35 | int insn_size; /* In words. */ |
36 | int isa; | |
37 | unsigned int bin_opcode; | |
1188e082 DC |
38 | }; |
39 | ||
40 | #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ | |
8cc66334 | 41 | {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN}, |
1188e082 DC |
42 | |
43 | struct avr_opcodes_s avr_opcodes[] = | |
44 | { | |
45 | #include "opcode/avr.h" | |
8cc66334 | 46 | {NULL, NULL, NULL, 0, 0, 0} |
1188e082 DC |
47 | }; |
48 | ||
adde6300 AM |
49 | const char comment_chars[] = ";"; |
50 | const char line_comment_chars[] = "#"; | |
51 | const char line_separator_chars[] = "$"; | |
52 | ||
adde6300 AM |
53 | const char *md_shortopts = "m:"; |
54 | struct mcu_type_s | |
55 | { | |
56 | char *name; | |
57 | int isa; | |
58 | int mach; | |
59 | }; | |
60 | ||
1f8ae5e6 | 61 | /* XXX - devices that don't seem to exist (renamed, replaced with larger |
7b21ac3f | 62 | ones, or planned but never produced), left here for compatibility. */ |
1f8ae5e6 | 63 | |
adde6300 AM |
64 | static struct mcu_type_s mcu_types[] = |
65 | { | |
7b21ac3f EW |
66 | {"avr1", AVR_ISA_AVR1, bfd_mach_avr1}, |
67 | /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2, | |
99700d6f NC |
68 | but set to AVR_ISA_AVR25 for some following version |
69 | of GCC (from 4.3) for backward compatibility. */ | |
7b21ac3f EW |
70 | {"avr2", AVR_ISA_AVR25, bfd_mach_avr2}, |
71 | {"avr25", AVR_ISA_AVR25, bfd_mach_avr25}, | |
99700d6f NC |
72 | /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3, |
73 | but set to AVR_ISA_AVR3_ALL for some following version | |
7b21ac3f EW |
74 | of GCC (from 4.3) for backward compatibility. */ |
75 | {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3}, | |
76 | {"avr31", AVR_ISA_AVR31, bfd_mach_avr31}, | |
77 | {"avr35", AVR_ISA_AVR35, bfd_mach_avr35}, | |
78 | {"avr4", AVR_ISA_AVR4, bfd_mach_avr4}, | |
99700d6f NC |
79 | /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5, |
80 | but set to AVR_ISA_AVR51 for some following version | |
7b21ac3f EW |
81 | of GCC (from 4.3) for backward compatibility. */ |
82 | {"avr5", AVR_ISA_AVR51, bfd_mach_avr5}, | |
83 | {"avr51", AVR_ISA_AVR51, bfd_mach_avr51}, | |
84 | {"avr6", AVR_ISA_AVR6, bfd_mach_avr6}, | |
8cc66334 EW |
85 | {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1}, |
86 | {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, | |
87 | {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3}, | |
88 | {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, | |
89 | {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, | |
90 | {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, | |
91 | {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7}, | |
f36e8886 | 92 | {"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, |
28c9d252 | 93 | {"at90s1200", AVR_ISA_1200, bfd_mach_avr1}, |
7b21ac3f EW |
94 | {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1}, |
95 | {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1}, | |
96 | {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1}, | |
97 | {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1}, | |
98 | {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2}, | |
99 | {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2}, | |
100 | {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */ | |
101 | {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2}, | |
102 | {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */ | |
d669d37f | 103 | {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2}, |
7b21ac3f EW |
104 | {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */ |
105 | {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2}, | |
106 | {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */ | |
107 | {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2}, | |
108 | {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2}, | |
109 | {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2}, | |
255d9eec | 110 | {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f EW |
111 | {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25}, |
112 | {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25}, | |
113 | {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25}, | |
8453da2e | 114 | {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f | 115 | {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25}, |
8453da2e EW |
116 | {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25}, |
117 | {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25}, | |
7b21ac3f | 118 | {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25}, |
8453da2e | 119 | {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f | 120 | {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25}, |
e760a81b | 121 | {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f EW |
122 | {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25}, |
123 | {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25}, | |
124 | {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25}, | |
125 | {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25}, | |
8453da2e | 126 | {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f | 127 | {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25}, |
e760a81b | 128 | {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f | 129 | {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25}, |
8453da2e | 130 | {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25}, |
2b02f87c | 131 | {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f EW |
132 | {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25}, |
133 | {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25}, | |
134 | {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25}, | |
255d9eec | 135 | {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25}, |
7b21ac3f EW |
136 | {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25}, |
137 | {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3}, | |
138 | {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3}, | |
139 | {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31}, | |
140 | {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31}, | |
141 | {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35}, | |
142 | {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35}, | |
143 | {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35}, | |
255d9eec | 144 | {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35}, |
11908008 EW |
145 | {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35}, |
146 | {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35}, | |
147 | {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35}, | |
255d9eec | 148 | {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35}, |
28c9d252 | 149 | {"atmega8", AVR_ISA_M8, bfd_mach_avr4}, |
8be59acb | 150 | {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4}, |
255d9eec DC |
151 | {"atmega8a", AVR_ISA_M8, bfd_mach_avr4}, |
152 | {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4}, | |
153 | {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4}, | |
7b21ac3f | 154 | {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4}, |
e760a81b | 155 | {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4}, |
255d9eec | 156 | {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4}, |
7b21ac3f EW |
157 | {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4}, |
158 | {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4}, | |
e760a81b | 159 | {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4}, |
7b21ac3f | 160 | {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4}, |
e760a81b | 161 | {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4}, |
28c9d252 NC |
162 | {"atmega8515", AVR_ISA_M8, bfd_mach_avr4}, |
163 | {"atmega8535", AVR_ISA_M8, bfd_mach_avr4}, | |
7b21ac3f EW |
164 | {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4}, |
165 | {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4}, | |
166 | {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4}, | |
167 | {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4}, | |
168 | {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4}, | |
169 | {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4}, | |
2b02f87c | 170 | {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4}, |
255d9eec DC |
171 | {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5}, |
172 | {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5}, | |
173 | {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 174 | {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 175 | {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5}, |
28c9d252 | 176 | {"atmega161", AVR_ISA_M161, bfd_mach_avr5}, |
7b21ac3f | 177 | {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5}, |
28c9d252 | 178 | {"atmega163", AVR_ISA_M161, bfd_mach_avr5}, |
e760a81b | 179 | {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 180 | {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec | 181 | {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 182 | {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 183 | {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 184 | {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec | 185 | {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 186 | {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 187 | {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 188 | {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec | 189 | {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 190 | {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 191 | {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 192 | {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 193 | {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 194 | {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec | 195 | {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 196 | {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 197 | {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 198 | {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 199 | {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 200 | {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 201 | {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 202 | {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5}, |
b8c610a7 | 203 | {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 204 | {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 205 | {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 206 | {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5}, |
b8c610a7 | 207 | {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 208 | {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f EW |
209 | {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5}, |
210 | {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5}, | |
e760a81b | 211 | {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 212 | {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 213 | {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 214 | {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b | 215 | {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 216 | {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5}, |
b8c610a7 | 217 | {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 218 | {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec DC |
219 | {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5}, |
220 | {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 221 | {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec | 222 | {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f EW |
223 | {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5}, |
224 | {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5}, | |
e760a81b | 225 | {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 226 | {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5}, |
8453da2e | 227 | {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 228 | {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b EW |
229 | {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5}, |
230 | {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 231 | {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b EW |
232 | {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5}, |
233 | {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 234 | {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b EW |
235 | {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5}, |
236 | {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 237 | {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5}, |
e760a81b EW |
238 | {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5}, |
239 | {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5}, | |
4d13caa0 NC |
240 | {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, |
241 | {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 242 | {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5}, |
255d9eec | 243 | {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5}, |
2b02f87c | 244 | {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5}, |
b8c610a7 | 245 | {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5}, |
2b02f87c | 246 | {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5}, |
b8c610a7 | 247 | {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5}, |
e760a81b | 248 | {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f EW |
249 | {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5}, |
250 | {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5}, | |
b8c610a7 | 251 | {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f EW |
252 | {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5}, |
253 | {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5}, | |
254 | {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5}, | |
2b02f87c NC |
255 | {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5}, |
256 | {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 257 | {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5}, |
2b02f87c NC |
258 | {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5}, |
259 | {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5}, | |
7b21ac3f | 260 | {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5}, |
2b02f87c | 261 | {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f EW |
262 | {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5}, |
263 | {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5}, | |
2b02f87c | 264 | {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5}, |
28c9d252 | 265 | {"at94k", AVR_ISA_94K, bfd_mach_avr5}, |
e760a81b | 266 | {"m3000", AVR_ISA_AVR5, bfd_mach_avr5}, |
7b21ac3f | 267 | {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51}, |
255d9eec | 268 | {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51}, |
7b21ac3f EW |
269 | {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51}, |
270 | {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51}, | |
255d9eec | 271 | {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51}, |
7b21ac3f | 272 | {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51}, |
17f4880d | 273 | {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51}, |
4d13caa0 NC |
274 | {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51}, |
275 | {"atmega1284rfr2",AVR_ISA_AVR51, bfd_mach_avr51}, | |
7b21ac3f EW |
276 | {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51}, |
277 | {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51}, | |
278 | {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51}, | |
279 | {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6}, | |
280 | {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6}, | |
4d13caa0 NC |
281 | {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, |
282 | {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, | |
8cc66334 | 283 | {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, |
255d9eec DC |
284 | {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, |
285 | {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, | |
8cc66334 EW |
286 | {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, |
287 | {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, | |
255d9eec DC |
288 | {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, |
289 | {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, | |
8cc66334 | 290 | {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, |
255d9eec DC |
291 | {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, |
292 | {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, | |
293 | {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, | |
6f8a4444 | 294 | {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, |
8cc66334 | 295 | {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, |
255d9eec DC |
296 | {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, |
297 | {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, | |
298 | {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, | |
299 | {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, | |
300 | {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, | |
8cc66334 | 301 | {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, |
255d9eec | 302 | {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, |
8cc66334 | 303 | {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, |
7bab7634 | 304 | {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5}, |
8cc66334 | 305 | {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
255d9eec | 306 | {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, |
7bab7634 | 307 | {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, |
255d9eec DC |
308 | {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, |
309 | {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, | |
8cc66334 | 310 | {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
255d9eec | 311 | {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
8cc66334 | 312 | {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
255d9eec DC |
313 | {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, |
314 | {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, | |
8cc66334 EW |
315 | {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
316 | {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, | |
255d9eec | 317 | {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, |
8cc66334 | 318 | {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
7bab7634 | 319 | {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, |
255d9eec | 320 | {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, |
8cc66334 | 321 | {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, |
255d9eec DC |
322 | {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, |
323 | {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, | |
8cc66334 | 324 | {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7}, |
7bab7634 | 325 | {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7}, |
255d9eec | 326 | {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7}, |
f36e8886 BS |
327 | {"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, |
328 | {"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, | |
329 | {"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, | |
330 | {"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, | |
331 | {"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, | |
332 | {"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny}, | |
adde6300 AM |
333 | {NULL, 0, 0} |
334 | }; | |
335 | ||
af910977 | 336 | |
adde6300 | 337 | /* Current MCU type. */ |
7b21ac3f | 338 | static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2}; |
af910977 | 339 | static struct mcu_type_s specified_mcu; |
dc191a8f | 340 | static struct mcu_type_s * avr_mcu = & default_mcu; |
adde6300 | 341 | |
00d2865b NC |
342 | /* AVR target-specific switches. */ |
343 | struct avr_opt_s | |
344 | { | |
dc191a8f NC |
345 | int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */ |
346 | int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */ | |
347 | int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */ | |
edc9e9a6 AB |
348 | int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not) |
349 | relocations for linker relaxation. */ | |
00d2865b NC |
350 | }; |
351 | ||
e4ef1b6c | 352 | static struct avr_opt_s avr_opt = { 0, 0, 0, 0 }; |
00d2865b | 353 | |
adde6300 AM |
354 | const char EXP_CHARS[] = "eE"; |
355 | const char FLT_CHARS[] = "dD"; | |
dc191a8f NC |
356 | |
357 | static void avr_set_arch (int); | |
adde6300 AM |
358 | |
359 | /* The target specific pseudo-ops which we support. */ | |
360 | const pseudo_typeS md_pseudo_table[] = | |
361 | { | |
362 | {"arch", avr_set_arch, 0}, | |
363 | { NULL, NULL, 0} | |
364 | }; | |
365 | ||
366 | #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00)) | |
adde6300 | 367 | |
dc191a8f NC |
368 | #define EXP_MOD_NAME(i) exp_mod[i].name |
369 | #define EXP_MOD_RELOC(i) exp_mod[i].reloc | |
370 | #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc | |
371 | #define HAVE_PM_P(i) exp_mod[i].have_pm | |
adde6300 AM |
372 | |
373 | struct exp_mod_s | |
374 | { | |
dc191a8f NC |
375 | char * name; |
376 | bfd_reloc_code_real_type reloc; | |
377 | bfd_reloc_code_real_type neg_reloc; | |
378 | int have_pm; | |
adde6300 AM |
379 | }; |
380 | ||
c6a7ab1f NC |
381 | static struct exp_mod_s exp_mod[] = |
382 | { | |
adde6300 AM |
383 | {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1}, |
384 | {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0}, | |
385 | {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1}, | |
386 | {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0}, | |
387 | {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1}, | |
388 | {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0}, | |
df406460 | 389 | {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0}, |
e4efb665 | 390 | {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0}, |
adde6300 AM |
391 | }; |
392 | ||
8ad7c533 NC |
393 | /* A union used to store indicies into the exp_mod[] array |
394 | in a hash table which expects void * data types. */ | |
395 | typedef union | |
396 | { | |
397 | void * ptr; | |
398 | int index; | |
399 | } mod_index; | |
400 | ||
adde6300 AM |
401 | /* Opcode hash table. */ |
402 | static struct hash_control *avr_hash; | |
403 | ||
404 | /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */ | |
405 | static struct hash_control *avr_mod_hash; | |
406 | ||
00d2865b | 407 | #define OPTION_MMCU 'm' |
dc191a8f NC |
408 | enum options |
409 | { | |
410 | OPTION_ALL_OPCODES = OPTION_MD_BASE + 1, | |
411 | OPTION_NO_SKIP_BUG, | |
af910977 | 412 | OPTION_NO_WRAP, |
e4ef1b6c | 413 | OPTION_ISA_RMW, |
edc9e9a6 AB |
414 | OPTION_LINK_RELAX, |
415 | OPTION_NO_LINK_RELAX | |
dc191a8f | 416 | }; |
adde6300 | 417 | |
c6a7ab1f NC |
418 | struct option md_longopts[] = |
419 | { | |
00d2865b NC |
420 | { "mmcu", required_argument, NULL, OPTION_MMCU }, |
421 | { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES }, | |
422 | { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG }, | |
423 | { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP }, | |
af910977 | 424 | { "mrmw", no_argument, NULL, OPTION_ISA_RMW }, |
e4ef1b6c | 425 | { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX }, |
edc9e9a6 | 426 | { "mno-link-relax", no_argument, NULL, OPTION_NO_LINK_RELAX }, |
00d2865b | 427 | { NULL, no_argument, NULL, 0 } |
adde6300 | 428 | }; |
adde6300 | 429 | |
c6a7ab1f | 430 | size_t md_longopts_size = sizeof (md_longopts); |
00d2865b NC |
431 | |
432 | /* Display nicely formatted list of known MCU names. */ | |
c6a7ab1f | 433 | |
00d2865b | 434 | static void |
dc191a8f | 435 | show_mcu_list (FILE *stream) |
00d2865b NC |
436 | { |
437 | int i, x; | |
438 | ||
439 | fprintf (stream, _("Known MCU names:")); | |
440 | x = 1000; | |
1dab94dd | 441 | |
00d2865b NC |
442 | for (i = 0; mcu_types[i].name; i++) |
443 | { | |
444 | int len = strlen (mcu_types[i].name); | |
1dab94dd | 445 | |
00d2865b | 446 | x += len + 1; |
1dab94dd | 447 | |
00d2865b | 448 | if (x < 75) |
c6a7ab1f | 449 | fprintf (stream, " %s", mcu_types[i].name); |
00d2865b NC |
450 | else |
451 | { | |
452 | fprintf (stream, "\n %s", mcu_types[i].name); | |
453 | x = len + 2; | |
454 | } | |
455 | } | |
1dab94dd | 456 | |
c6a7ab1f | 457 | fprintf (stream, "\n"); |
00d2865b NC |
458 | } |
459 | ||
adde6300 | 460 | static inline char * |
dc191a8f | 461 | skip_space (char *s) |
adde6300 AM |
462 | { |
463 | while (*s == ' ' || *s == '\t') | |
464 | ++s; | |
465 | return s; | |
466 | } | |
467 | ||
468 | /* Extract one word from FROM and copy it to TO. */ | |
c6a7ab1f | 469 | |
adde6300 AM |
470 | static char * |
471 | extract_word (char *from, char *to, int limit) | |
472 | { | |
adde6300 AM |
473 | char *op_end; |
474 | int size = 0; | |
475 | ||
476 | /* Drop leading whitespace. */ | |
477 | from = skip_space (from); | |
478 | *to = 0; | |
c6a7ab1f | 479 | |
adde6300 | 480 | /* Find the op code end. */ |
87975d2a | 481 | for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);) |
adde6300 AM |
482 | { |
483 | to[size++] = *op_end++; | |
484 | if (size + 1 >= limit) | |
485 | break; | |
486 | } | |
1dab94dd | 487 | |
adde6300 AM |
488 | to[size] = 0; |
489 | return op_end; | |
490 | } | |
491 | ||
492 | int | |
dc191a8f NC |
493 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
494 | asection *seg ATTRIBUTE_UNUSED) | |
adde6300 AM |
495 | { |
496 | abort (); | |
497 | return 0; | |
498 | } | |
499 | ||
500 | void | |
dc191a8f | 501 | md_show_usage (FILE *stream) |
adde6300 | 502 | { |
00d2865b | 503 | fprintf (stream, |
4fb8d1c6 | 504 | _("AVR Assembler options:\n" |
adde6300 AM |
505 | " -mmcu=[avr-name] select microcontroller variant\n" |
506 | " [avr-name] can be:\n" | |
7b21ac3f EW |
507 | " avr1 - classic AVR core without data RAM\n" |
508 | " avr2 - classic AVR core with up to 8K program memory\n" | |
509 | " avr25 - classic AVR core with up to 8K program memory\n" | |
510 | " plus the MOVW instruction\n" | |
511 | " avr3 - classic AVR core with up to 64K program memory\n" | |
512 | " avr31 - classic AVR core with up to 128K program memory\n" | |
513 | " avr35 - classic AVR core with up to 64K program memory\n" | |
514 | " plus the MOVW instruction\n" | |
515 | " avr4 - enhanced AVR core with up to 8K program memory\n" | |
516 | " avr5 - enhanced AVR core with up to 64K program memory\n" | |
517 | " avr51 - enhanced AVR core with up to 128K program memory\n" | |
518 | " avr6 - enhanced AVR core with up to 256K program memory\n" | |
8c997c27 | 519 | " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n" |
8cc66334 EW |
520 | " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n" |
521 | " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n" | |
522 | " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n" | |
523 | " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n" | |
524 | " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n" | |
f36e8886 | 525 | " avrtiny - AVR Tiny core with 16 gp registers\n")); |
00d2865b NC |
526 | fprintf (stream, |
527 | _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n" | |
528 | " -mno-skip-bug disable warnings for skipping two-word instructions\n" | |
529 | " (default for avr4, avr5)\n" | |
530 | " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n" | |
af910977 DC |
531 | " (default for avr3, avr5)\n" |
532 | " -mrmw accept Read-Modify-Write instructions\n" | |
edc9e9a6 AB |
533 | " -mlink-relax generate relocations for linker relaxation (default)\n" |
534 | " -mno-link-relax don't generate relocations for linker relaxation.\n" | |
535 | )); | |
00d2865b | 536 | show_mcu_list (stream); |
adde6300 AM |
537 | } |
538 | ||
539 | static void | |
dc191a8f | 540 | avr_set_arch (int dummy ATTRIBUTE_UNUSED) |
adde6300 | 541 | { |
dc191a8f | 542 | char str[20]; |
1dab94dd | 543 | |
adde6300 | 544 | input_line_pointer = extract_word (input_line_pointer, str, 20); |
00d2865b | 545 | md_parse_option (OPTION_MMCU, str); |
adde6300 AM |
546 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach); |
547 | } | |
548 | ||
549 | int | |
dc191a8f | 550 | md_parse_option (int c, char *arg) |
adde6300 | 551 | { |
00d2865b | 552 | switch (c) |
adde6300 | 553 | { |
00d2865b NC |
554 | case OPTION_MMCU: |
555 | { | |
556 | int i; | |
557 | char *s = alloca (strlen (arg) + 1); | |
adde6300 | 558 | |
00d2865b NC |
559 | { |
560 | char *t = s; | |
561 | char *arg1 = arg; | |
562 | ||
563 | do | |
3882b010 | 564 | *t = TOLOWER (*arg1++); |
00d2865b NC |
565 | while (*t++); |
566 | } | |
567 | ||
568 | for (i = 0; mcu_types[i].name; ++i) | |
569 | if (strcmp (mcu_types[i].name, s) == 0) | |
570 | break; | |
adde6300 | 571 | |
00d2865b NC |
572 | if (!mcu_types[i].name) |
573 | { | |
574 | show_mcu_list (stderr); | |
575 | as_fatal (_("unknown MCU: %s\n"), arg); | |
576 | } | |
65aa24b6 | 577 | |
00d2865b NC |
578 | /* It is OK to redefine mcu type within the same avr[1-5] bfd machine |
579 | type - this for allows passing -mmcu=... via gcc ASM_SPEC as well | |
580 | as .arch ... in the asm output at the same time. */ | |
00d2865b | 581 | if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach) |
af910977 DC |
582 | { |
583 | specified_mcu.name = mcu_types[i].name; | |
584 | specified_mcu.isa |= mcu_types[i].isa; | |
585 | specified_mcu.mach = mcu_types[i].mach; | |
586 | avr_mcu = &specified_mcu; | |
587 | } | |
00d2865b NC |
588 | else |
589 | as_fatal (_("redefinition of mcu type `%s' to `%s'"), | |
590 | avr_mcu->name, mcu_types[i].name); | |
591 | return 1; | |
592 | } | |
593 | case OPTION_ALL_OPCODES: | |
594 | avr_opt.all_opcodes = 1; | |
595 | return 1; | |
596 | case OPTION_NO_SKIP_BUG: | |
597 | avr_opt.no_skip_bug = 1; | |
598 | return 1; | |
599 | case OPTION_NO_WRAP: | |
600 | avr_opt.no_wrap = 1; | |
adde6300 | 601 | return 1; |
af910977 DC |
602 | case OPTION_ISA_RMW: |
603 | specified_mcu.isa |= AVR_ISA_RMW; | |
604 | return 1; | |
e4ef1b6c | 605 | case OPTION_LINK_RELAX: |
edc9e9a6 AB |
606 | avr_opt.no_link_relax = 0; |
607 | return 1; | |
608 | case OPTION_NO_LINK_RELAX: | |
609 | avr_opt.no_link_relax = 1; | |
e4ef1b6c | 610 | return 1; |
adde6300 | 611 | } |
1dab94dd | 612 | |
adde6300 AM |
613 | return 0; |
614 | } | |
615 | ||
616 | symbolS * | |
dc191a8f | 617 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
adde6300 | 618 | { |
dc191a8f | 619 | return NULL; |
adde6300 AM |
620 | } |
621 | ||
adde6300 | 622 | char * |
dc191a8f | 623 | md_atof (int type, char *litP, int *sizeP) |
adde6300 | 624 | { |
499ac353 | 625 | return ieee_md_atof (type, litP, sizeP, FALSE); |
adde6300 AM |
626 | } |
627 | ||
628 | void | |
dc191a8f NC |
629 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
630 | asection *sec ATTRIBUTE_UNUSED, | |
631 | fragS *fragP ATTRIBUTE_UNUSED) | |
adde6300 AM |
632 | { |
633 | abort (); | |
634 | } | |
635 | ||
adde6300 | 636 | void |
dc191a8f | 637 | md_begin (void) |
adde6300 | 638 | { |
df136245 | 639 | unsigned int i; |
adde6300 | 640 | struct avr_opcodes_s *opcode; |
dc191a8f | 641 | |
c6a7ab1f | 642 | avr_hash = hash_new (); |
adde6300 AM |
643 | |
644 | /* Insert unique names into hash table. This hash table then provides a | |
645 | quick index to the first opcode with a particular name in the opcode | |
646 | table. */ | |
adde6300 AM |
647 | for (opcode = avr_opcodes; opcode->name; opcode++) |
648 | hash_insert (avr_hash, opcode->name, (char *) opcode); | |
649 | ||
650 | avr_mod_hash = hash_new (); | |
651 | ||
dc191a8f | 652 | for (i = 0; i < ARRAY_SIZE (exp_mod); ++i) |
8ad7c533 NC |
653 | { |
654 | mod_index m; | |
655 | ||
656 | m.index = i + 10; | |
657 | hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr); | |
658 | } | |
c6a7ab1f | 659 | |
adde6300 | 660 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach); |
edc9e9a6 | 661 | linkrelax = !avr_opt.no_link_relax; |
adde6300 AM |
662 | } |
663 | ||
df136245 | 664 | /* Resolve STR as a constant expression and return the result. |
c6a7ab1f | 665 | If result greater than MAX then error. */ |
df136245 DC |
666 | |
667 | static unsigned int | |
dc191a8f | 668 | avr_get_constant (char *str, int max) |
df136245 DC |
669 | { |
670 | expressionS ex; | |
dc191a8f | 671 | |
df136245 DC |
672 | str = skip_space (str); |
673 | input_line_pointer = str; | |
dc191a8f | 674 | expression (& ex); |
df136245 DC |
675 | |
676 | if (ex.X_op != O_constant) | |
677 | as_bad (_("constant value required")); | |
678 | ||
679 | if (ex.X_add_number > max || ex.X_add_number < 0) | |
73f4d86e | 680 | as_bad (_("number must be positive and less than %d"), max + 1); |
1dab94dd | 681 | |
df136245 DC |
682 | return ex.X_add_number; |
683 | } | |
684 | ||
dc191a8f | 685 | /* Parse for ldd/std offset. */ |
df136245 | 686 | |
dc191a8f NC |
687 | static void |
688 | avr_offset_expression (expressionS *exp) | |
adde6300 | 689 | { |
dc191a8f NC |
690 | char *str = input_line_pointer; |
691 | char *tmp; | |
692 | char op[8]; | |
adde6300 | 693 | |
dc191a8f NC |
694 | tmp = str; |
695 | str = extract_word (str, op, sizeof (op)); | |
696 | ||
697 | input_line_pointer = tmp; | |
698 | expression (exp); | |
699 | ||
700 | /* Warn about expressions that fail to use lo8 (). */ | |
701 | if (exp->X_op == O_constant) | |
adde6300 | 702 | { |
dc191a8f | 703 | int x = exp->X_add_number; |
28c9d252 | 704 | |
dc191a8f NC |
705 | if (x < -255 || x > 255) |
706 | as_warn (_("constant out of 8-bit range: %d"), x); | |
707 | } | |
708 | } | |
adde6300 | 709 | |
dc191a8f | 710 | /* Parse ordinary expression. */ |
adde6300 | 711 | |
dc191a8f NC |
712 | static char * |
713 | parse_exp (char *s, expressionS *op) | |
714 | { | |
715 | input_line_pointer = s; | |
716 | expression (op); | |
717 | if (op->X_op == O_absent) | |
718 | as_bad (_("missing operand")); | |
719 | return input_line_pointer; | |
720 | } | |
1dab94dd | 721 | |
dc191a8f NC |
722 | /* Parse special expressions (needed for LDI command): |
723 | xx8 (address) | |
724 | xx8 (-address) | |
725 | pm_xx8 (address) | |
726 | pm_xx8 (-address) | |
727 | where xx is: hh, hi, lo. */ | |
adde6300 | 728 | |
dc191a8f NC |
729 | static bfd_reloc_code_real_type |
730 | avr_ldi_expression (expressionS *exp) | |
731 | { | |
732 | char *str = input_line_pointer; | |
733 | char *tmp; | |
734 | char op[8]; | |
735 | int mod; | |
28c9d252 NC |
736 | int linker_stubs_should_be_generated = 0; |
737 | ||
dc191a8f | 738 | tmp = str; |
adde6300 | 739 | |
dc191a8f | 740 | str = extract_word (str, op, sizeof (op)); |
adde6300 | 741 | |
dc191a8f NC |
742 | if (op[0]) |
743 | { | |
8ad7c533 | 744 | mod_index m; |
28c9d252 | 745 | |
8ad7c533 NC |
746 | m.ptr = hash_find (avr_mod_hash, op); |
747 | mod = m.index; | |
1dab94dd | 748 | |
dc191a8f NC |
749 | if (mod) |
750 | { | |
751 | int closes = 0; | |
b170af93 | 752 | |
dc191a8f NC |
753 | mod -= 10; |
754 | str = skip_space (str); | |
00d2865b | 755 | |
dc191a8f NC |
756 | if (*str == '(') |
757 | { | |
28c9d252 | 758 | bfd_reloc_code_real_type reloc_to_return; |
dc191a8f | 759 | int neg_p = 0; |
00d2865b | 760 | |
dc191a8f | 761 | ++str; |
00d2865b | 762 | |
dc191a8f | 763 | if (strncmp ("pm(", str, 3) == 0 |
28c9d252 NC |
764 | || strncmp ("gs(",str,3) == 0 |
765 | || strncmp ("-(gs(",str,5) == 0 | |
dc191a8f NC |
766 | || strncmp ("-(pm(", str, 5) == 0) |
767 | { | |
768 | if (HAVE_PM_P (mod)) | |
769 | { | |
770 | ++mod; | |
771 | ++closes; | |
772 | } | |
773 | else | |
774 | as_bad (_("illegal expression")); | |
b170af93 | 775 | |
28c9d252 NC |
776 | if (str[0] == 'g' || str[2] == 'g') |
777 | linker_stubs_should_be_generated = 1; | |
778 | ||
dc191a8f NC |
779 | if (*str == '-') |
780 | { | |
781 | neg_p = 1; | |
782 | ++closes; | |
783 | str += 5; | |
784 | } | |
785 | else | |
786 | str += 3; | |
787 | } | |
adde6300 | 788 | |
dc191a8f NC |
789 | if (*str == '-' && *(str + 1) == '(') |
790 | { | |
791 | neg_p ^= 1; | |
792 | ++closes; | |
793 | str += 2; | |
794 | } | |
750bce0e | 795 | |
dc191a8f NC |
796 | input_line_pointer = str; |
797 | expression (exp); | |
750bce0e | 798 | |
dc191a8f NC |
799 | do |
800 | { | |
801 | if (*input_line_pointer != ')') | |
802 | { | |
803 | as_bad (_("`)' required")); | |
804 | break; | |
805 | } | |
806 | input_line_pointer++; | |
807 | } | |
808 | while (closes--); | |
809 | ||
28c9d252 NC |
810 | reloc_to_return = |
811 | neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod); | |
812 | if (linker_stubs_should_be_generated) | |
813 | { | |
814 | switch (reloc_to_return) | |
815 | { | |
816 | case BFD_RELOC_AVR_LO8_LDI_PM: | |
817 | reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS; | |
818 | break; | |
819 | case BFD_RELOC_AVR_HI8_LDI_PM: | |
820 | reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS; | |
821 | break; | |
822 | ||
823 | default: | |
0a903bab NC |
824 | /* PR 5523: Do not generate a warning here, |
825 | legitimate code can trigger this case. */ | |
826 | break; | |
28c9d252 NC |
827 | } |
828 | } | |
829 | return reloc_to_return; | |
dc191a8f NC |
830 | } |
831 | } | |
832 | } | |
750bce0e NC |
833 | |
834 | input_line_pointer = tmp; | |
835 | expression (exp); | |
836 | ||
837 | /* Warn about expressions that fail to use lo8 (). */ | |
838 | if (exp->X_op == O_constant) | |
839 | { | |
840 | int x = exp->X_add_number; | |
dc191a8f | 841 | |
750bce0e NC |
842 | if (x < -255 || x > 255) |
843 | as_warn (_("constant out of 8-bit range: %d"), x); | |
844 | } | |
dc191a8f NC |
845 | |
846 | return BFD_RELOC_AVR_LDI; | |
750bce0e NC |
847 | } |
848 | ||
df136245 | 849 | /* Parse one instruction operand. |
c6a7ab1f NC |
850 | Return operand bitmask. Also fixups can be generated. */ |
851 | ||
adde6300 | 852 | static unsigned int |
dc191a8f NC |
853 | avr_operand (struct avr_opcodes_s *opcode, |
854 | int where, | |
855 | char *op, | |
856 | char **line) | |
adde6300 | 857 | { |
adde6300 | 858 | expressionS op_expr; |
df136245 DC |
859 | unsigned int op_mask = 0; |
860 | char *str = skip_space (*line); | |
adde6300 | 861 | |
adde6300 AM |
862 | switch (*op) |
863 | { | |
864 | /* Any register operand. */ | |
865 | case 'w': | |
866 | case 'd': | |
867 | case 'r': | |
b170af93 DC |
868 | case 'a': |
869 | case 'v': | |
75f58085 BS |
870 | { |
871 | char * old_str = str; | |
872 | char *lower; | |
873 | char r_name[20]; | |
1dab94dd | 874 | |
75f58085 BS |
875 | str = extract_word (str, r_name, sizeof (r_name)); |
876 | for (lower = r_name; *lower; ++lower) | |
877 | { | |
878 | if (*lower >= 'A' && *lower <= 'Z') | |
879 | *lower += 'a' - 'A'; | |
880 | } | |
881 | ||
882 | if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0) | |
883 | /* Single-digit register number, ie r0-r9. */ | |
884 | op_mask = r_name[1] - '0'; | |
885 | else if (r_name[0] == 'r' && ISDIGIT (r_name[1]) | |
886 | && ISDIGIT (r_name[2]) && r_name[3] == 0) | |
887 | /* Double-digit register number, ie r10 - r32. */ | |
888 | op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0'; | |
889 | else if (r_name[0] >= 'x' && r_name[0] <= 'z' | |
890 | && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0) | |
891 | /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */ | |
892 | op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26; | |
893 | else if ((*op == 'v' || *op == 'w') | |
894 | && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0) | |
895 | /* For the movw and addiw instructions, refer to registers x, y and z by name. */ | |
896 | op_mask = (r_name[0] - 'x') * 2 + 26; | |
897 | else | |
898 | { | |
899 | /* Numeric or symbolic constant register number. */ | |
900 | op_mask = avr_get_constant (old_str, 31); | |
901 | str = input_line_pointer; | |
902 | } | |
903 | } | |
f36e8886 BS |
904 | |
905 | if (avr_mcu->mach == bfd_mach_avrtiny) | |
906 | { | |
907 | if (op_mask < 16 || op_mask > 31) | |
908 | { | |
909 | as_bad (_("register name or number from 16 to 31 required")); | |
910 | break; | |
911 | } | |
912 | } | |
913 | else if (op_mask > 31) | |
914 | { | |
915 | as_bad (_("register name or number from 0 to 31 required")); | |
916 | break; | |
917 | } | |
1dab94dd | 918 | |
c6a7ab1f NC |
919 | switch (*op) |
920 | { | |
921 | case 'a': | |
922 | if (op_mask < 16 || op_mask > 23) | |
923 | as_bad (_("register r16-r23 required")); | |
924 | op_mask -= 16; | |
925 | break; | |
1dab94dd | 926 | |
c6a7ab1f NC |
927 | case 'd': |
928 | if (op_mask < 16) | |
929 | as_bad (_("register number above 15 required")); | |
930 | op_mask -= 16; | |
931 | break; | |
1dab94dd | 932 | |
c6a7ab1f NC |
933 | case 'v': |
934 | if (op_mask & 1) | |
935 | as_bad (_("even register number required")); | |
936 | op_mask >>= 1; | |
937 | break; | |
1dab94dd | 938 | |
c6a7ab1f | 939 | case 'w': |
65b1d096 | 940 | if ((op_mask & 1) || op_mask < 24) |
c6a7ab1f | 941 | as_bad (_("register r24, r26, r28 or r30 required")); |
65b1d096 | 942 | op_mask = (op_mask - 24) >> 1; |
c6a7ab1f NC |
943 | break; |
944 | } | |
945 | break; | |
adde6300 AM |
946 | |
947 | case 'e': | |
948 | { | |
949 | char c; | |
1dab94dd | 950 | |
adde6300 AM |
951 | if (*str == '-') |
952 | { | |
c6a7ab1f | 953 | str = skip_space (str + 1); |
adde6300 AM |
954 | op_mask = 0x1002; |
955 | } | |
3882b010 | 956 | c = TOLOWER (*str); |
adde6300 AM |
957 | if (c == 'x') |
958 | op_mask |= 0x100c; | |
959 | else if (c == 'y') | |
960 | op_mask |= 0x8; | |
961 | else if (c != 'z') | |
00d2865b | 962 | as_bad (_("pointer register (X, Y or Z) required")); |
adde6300 | 963 | |
c6a7ab1f | 964 | str = skip_space (str + 1); |
adde6300 AM |
965 | if (*str == '+') |
966 | { | |
967 | ++str; | |
968 | if (op_mask & 2) | |
00d2865b | 969 | as_bad (_("cannot both predecrement and postincrement")); |
adde6300 AM |
970 | op_mask |= 0x1001; |
971 | } | |
e38c9cc2 | 972 | |
1188e082 | 973 | /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer |
e38c9cc2 | 974 | registers, no predecrement, no postincrement. */ |
00d2865b NC |
975 | if (!avr_opt.all_opcodes && (op_mask & 0x100F) |
976 | && !(avr_mcu->isa & AVR_ISA_SRAM)) | |
977 | as_bad (_("addressing mode not supported")); | |
adde6300 AM |
978 | } |
979 | break; | |
980 | ||
b170af93 | 981 | case 'z': |
c6a7ab1f NC |
982 | if (*str == '-') |
983 | as_bad (_("can't predecrement")); | |
1dab94dd | 984 | |
c6a7ab1f NC |
985 | if (! (*str == 'z' || *str == 'Z')) |
986 | as_bad (_("pointer register Z required")); | |
1dab94dd | 987 | |
c6a7ab1f NC |
988 | str = skip_space (str + 1); |
989 | ||
990 | if (*str == '+') | |
991 | { | |
992 | ++str; | |
8cc66334 EW |
993 | char *s; |
994 | for (s = opcode->opcode; *s; ++s) | |
995 | { | |
996 | if (*s == '+') | |
997 | op_mask |= (1 << (15 - (s - opcode->opcode))); | |
998 | } | |
c6a7ab1f | 999 | } |
d669d37f NC |
1000 | |
1001 | /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */ | |
1002 | if (!avr_opt.all_opcodes | |
1003 | && (op_mask & 0x0001) | |
1004 | && !(avr_mcu->isa & AVR_ISA_MOVW)) | |
1005 | as_bad (_("postincrement not supported")); | |
b170af93 DC |
1006 | break; |
1007 | ||
adde6300 AM |
1008 | case 'b': |
1009 | { | |
3882b010 | 1010 | char c = TOLOWER (*str++); |
1dab94dd | 1011 | |
adde6300 AM |
1012 | if (c == 'y') |
1013 | op_mask |= 0x8; | |
1014 | else if (c != 'z') | |
00d2865b | 1015 | as_bad (_("pointer register (Y or Z) required")); |
adde6300 AM |
1016 | str = skip_space (str); |
1017 | if (*str++ == '+') | |
1018 | { | |
750bce0e NC |
1019 | input_line_pointer = str; |
1020 | avr_offset_expression (& op_expr); | |
adde6300 | 1021 | str = input_line_pointer; |
750bce0e NC |
1022 | fix_new_exp (frag_now, where, 3, |
1023 | &op_expr, FALSE, BFD_RELOC_AVR_6); | |
adde6300 AM |
1024 | } |
1025 | } | |
1026 | break; | |
1027 | ||
1028 | case 'h': | |
c6a7ab1f NC |
1029 | str = parse_exp (str, &op_expr); |
1030 | fix_new_exp (frag_now, where, opcode->insn_size * 2, | |
b34976b6 | 1031 | &op_expr, FALSE, BFD_RELOC_AVR_CALL); |
adde6300 AM |
1032 | break; |
1033 | ||
1034 | case 'L': | |
c6a7ab1f NC |
1035 | str = parse_exp (str, &op_expr); |
1036 | fix_new_exp (frag_now, where, opcode->insn_size * 2, | |
b34976b6 | 1037 | &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL); |
adde6300 AM |
1038 | break; |
1039 | ||
1040 | case 'l': | |
c6a7ab1f NC |
1041 | str = parse_exp (str, &op_expr); |
1042 | fix_new_exp (frag_now, where, opcode->insn_size * 2, | |
b34976b6 | 1043 | &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL); |
adde6300 AM |
1044 | break; |
1045 | ||
1046 | case 'i': | |
c6a7ab1f NC |
1047 | str = parse_exp (str, &op_expr); |
1048 | fix_new_exp (frag_now, where + 2, opcode->insn_size * 2, | |
b34976b6 | 1049 | &op_expr, FALSE, BFD_RELOC_16); |
adde6300 AM |
1050 | break; |
1051 | ||
f36e8886 BS |
1052 | case 'j': |
1053 | str = parse_exp (str, &op_expr); | |
1054 | fix_new_exp (frag_now, where, opcode->insn_size * 2, | |
1055 | &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16); | |
1056 | break; | |
1057 | ||
adde6300 AM |
1058 | case 'M': |
1059 | { | |
1060 | bfd_reloc_code_real_type r_type; | |
1dab94dd | 1061 | |
c6a7ab1f NC |
1062 | input_line_pointer = str; |
1063 | r_type = avr_ldi_expression (&op_expr); | |
1064 | str = input_line_pointer; | |
adde6300 | 1065 | fix_new_exp (frag_now, where, 3, |
b34976b6 | 1066 | &op_expr, FALSE, r_type); |
adde6300 AM |
1067 | } |
1068 | break; | |
1069 | ||
1070 | case 'n': | |
1071 | { | |
1072 | unsigned int x; | |
1dab94dd | 1073 | |
adde6300 AM |
1074 | x = ~avr_get_constant (str, 255); |
1075 | str = input_line_pointer; | |
1076 | op_mask |= (x & 0xf) | ((x << 4) & 0xf00); | |
1077 | } | |
1078 | break; | |
1079 | ||
1080 | case 'K': | |
750bce0e NC |
1081 | input_line_pointer = str; |
1082 | avr_offset_expression (& op_expr); | |
1083 | str = input_line_pointer; | |
1084 | fix_new_exp (frag_now, where, 3, | |
1085 | & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW); | |
adde6300 AM |
1086 | break; |
1087 | ||
1088 | case 'S': | |
1089 | case 's': | |
1090 | { | |
1091 | unsigned int x; | |
1dab94dd | 1092 | |
adde6300 AM |
1093 | x = avr_get_constant (str, 7); |
1094 | str = input_line_pointer; | |
1095 | if (*op == 'S') | |
1096 | x <<= 4; | |
1097 | op_mask |= x; | |
1098 | } | |
1099 | break; | |
1100 | ||
1101 | case 'P': | |
75f58085 BS |
1102 | str = parse_exp (str, &op_expr); |
1103 | fix_new_exp (frag_now, where, opcode->insn_size * 2, | |
1104 | &op_expr, FALSE, BFD_RELOC_AVR_PORT6); | |
adde6300 AM |
1105 | break; |
1106 | ||
1107 | case 'p': | |
75f58085 BS |
1108 | str = parse_exp (str, &op_expr); |
1109 | fix_new_exp (frag_now, where, opcode->insn_size * 2, | |
1110 | &op_expr, FALSE, BFD_RELOC_AVR_PORT5); | |
adde6300 | 1111 | break; |
1dab94dd | 1112 | |
8cc66334 EW |
1113 | case 'E': |
1114 | { | |
1115 | unsigned int x; | |
1116 | ||
1117 | x = avr_get_constant (str, 15); | |
1118 | str = input_line_pointer; | |
1119 | op_mask |= (x << 4); | |
1120 | } | |
1121 | break; | |
99700d6f | 1122 | |
1188e082 DC |
1123 | case '?': |
1124 | break; | |
1dab94dd | 1125 | |
adde6300 | 1126 | default: |
00d2865b | 1127 | as_bad (_("unknown constraint `%c'"), *op); |
adde6300 | 1128 | } |
1dab94dd | 1129 | |
adde6300 AM |
1130 | *line = str; |
1131 | return op_mask; | |
1132 | } | |
1133 | ||
dc191a8f NC |
1134 | /* Parse instruction operands. |
1135 | Return binary opcode. */ | |
1136 | ||
1137 | static unsigned int | |
1138 | avr_operands (struct avr_opcodes_s *opcode, char **line) | |
1139 | { | |
1140 | char *op = opcode->constraints; | |
1141 | unsigned int bin = opcode->bin_opcode; | |
1142 | char *frag = frag_more (opcode->insn_size * 2); | |
1143 | char *str = *line; | |
1144 | int where = frag - frag_now->fr_literal; | |
1145 | static unsigned int prev = 0; /* Previous opcode. */ | |
1146 | ||
1147 | /* Opcode have operands. */ | |
1148 | if (*op) | |
1149 | { | |
1150 | unsigned int reg1 = 0; | |
1151 | unsigned int reg2 = 0; | |
1152 | int reg1_present = 0; | |
1153 | int reg2_present = 0; | |
1154 | ||
1155 | /* Parse first operand. */ | |
1156 | if (REGISTER_P (*op)) | |
1157 | reg1_present = 1; | |
1158 | reg1 = avr_operand (opcode, where, op, &str); | |
1159 | ++op; | |
1160 | ||
1161 | /* Parse second operand. */ | |
1162 | if (*op) | |
1163 | { | |
1164 | if (*op == ',') | |
1165 | ++op; | |
1166 | ||
1167 | if (*op == '=') | |
1168 | { | |
1169 | reg2 = reg1; | |
1170 | reg2_present = 1; | |
1171 | } | |
1172 | else | |
1173 | { | |
1174 | if (REGISTER_P (*op)) | |
1175 | reg2_present = 1; | |
1176 | ||
1177 | str = skip_space (str); | |
1178 | if (*str++ != ',') | |
1179 | as_bad (_("`,' required")); | |
1180 | str = skip_space (str); | |
1181 | ||
1182 | reg2 = avr_operand (opcode, where, op, &str); | |
1183 | } | |
1184 | ||
1185 | if (reg1_present && reg2_present) | |
1186 | reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200); | |
1187 | else if (reg2_present) | |
1188 | reg2 <<= 4; | |
1189 | } | |
1190 | if (reg1_present) | |
1191 | reg1 <<= 4; | |
1192 | bin |= reg1 | reg2; | |
1193 | } | |
1194 | ||
1195 | /* Detect undefined combinations (like ld r31,Z+). */ | |
1196 | if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin)) | |
1197 | as_warn (_("undefined combination of operands")); | |
1198 | ||
1199 | if (opcode->insn_size == 2) | |
1200 | { | |
1201 | /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs | |
1202 | (AVR core bug, fixed in the newer devices). */ | |
1203 | if (!(avr_opt.no_skip_bug || | |
1204 | (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW))) | |
1205 | && AVR_SKIP_P (prev)) | |
1206 | as_warn (_("skipping two-word instruction")); | |
1207 | ||
1208 | bfd_putl32 ((bfd_vma) bin, frag); | |
1209 | } | |
1210 | else | |
1211 | bfd_putl16 ((bfd_vma) bin, frag); | |
1212 | ||
1213 | prev = bin; | |
1214 | *line = str; | |
1215 | return bin; | |
1216 | } | |
1217 | ||
adde6300 AM |
1218 | /* GAS will call this function for each section at the end of the assembly, |
1219 | to permit the CPU backend to adjust the alignment of a section. */ | |
c6a7ab1f | 1220 | |
adde6300 | 1221 | valueT |
dc191a8f | 1222 | md_section_align (asection *seg, valueT addr) |
adde6300 AM |
1223 | { |
1224 | int align = bfd_get_section_alignment (stdoutput, seg); | |
1225 | return ((addr + (1 << align) - 1) & (-1 << align)); | |
1226 | } | |
1227 | ||
1228 | /* If you define this macro, it should return the offset between the | |
1229 | address of a PC relative fixup and the position from which the PC | |
1230 | relative adjustment should be made. On many processors, the base | |
1231 | of a PC relative instruction is the next instruction, so this | |
1232 | macro would return the length of an instruction. */ | |
c6a7ab1f | 1233 | |
adde6300 | 1234 | long |
dc191a8f | 1235 | md_pcrel_from_section (fixS *fixp, segT sec) |
adde6300 | 1236 | { |
c6a7ab1f | 1237 | if (fixp->fx_addsy != (symbolS *) NULL |
adde6300 AM |
1238 | && (!S_IS_DEFINED (fixp->fx_addsy) |
1239 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) | |
1240 | return 0; | |
1dab94dd | 1241 | |
adde6300 AM |
1242 | return fixp->fx_frag->fr_address + fixp->fx_where; |
1243 | } | |
1244 | ||
e4ef1b6c DC |
1245 | static bfd_boolean |
1246 | relaxable_section (asection *sec) | |
1247 | { | |
edc9e9a6 AB |
1248 | return ((sec->flags & SEC_DEBUGGING) == 0 |
1249 | && (sec->flags & SEC_CODE) != 0 | |
1250 | && (sec->flags & SEC_ALLOC) != 0); | |
e4ef1b6c DC |
1251 | } |
1252 | ||
75f58085 | 1253 | /* Does whatever the xtensa port does. */ |
e4ef1b6c DC |
1254 | int |
1255 | avr_validate_fix_sub (fixS *fix) | |
1256 | { | |
1257 | segT add_symbol_segment, sub_symbol_segment; | |
1258 | ||
1259 | /* The difference of two symbols should be resolved by the assembler when | |
1260 | linkrelax is not set. If the linker may relax the section containing | |
1261 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
1262 | the linker knows to adjust the difference value. */ | |
1263 | if (!linkrelax || fix->fx_addsy == NULL) | |
1264 | return 0; | |
1265 | ||
1266 | /* Make sure both symbols are in the same segment, and that segment is | |
1267 | "normal" and relaxable. If the segment is not "normal", then the | |
1268 | fix is not valid. If the segment is not "relaxable", then the fix | |
1269 | should have been handled earlier. */ | |
1270 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
1271 | if (! SEG_NORMAL (add_symbol_segment) || | |
1272 | ! relaxable_section (add_symbol_segment)) | |
1273 | return 0; | |
1274 | ||
1275 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
1276 | return (sub_symbol_segment == add_symbol_segment); | |
1277 | } | |
1278 | ||
1279 | /* TC_FORCE_RELOCATION hook */ | |
1280 | ||
1281 | /* If linkrelax is turned on, and the symbol to relocate | |
1282 | against is in a relaxable segment, don't compute the value - | |
75f58085 | 1283 | generate a relocation instead. */ |
e4ef1b6c DC |
1284 | int |
1285 | avr_force_relocation (fixS *fix) | |
1286 | { | |
1287 | if (linkrelax && fix->fx_addsy | |
1288 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
1289 | return 1; | |
1290 | ||
1291 | return generic_force_reloc (fix); | |
1292 | } | |
1293 | ||
adde6300 | 1294 | /* GAS will call this for each fixup. It should store the correct |
c6a7ab1f NC |
1295 | value in the object file. */ |
1296 | ||
94f592af | 1297 | void |
dc191a8f | 1298 | md_apply_fix (fixS *fixP, valueT * valP, segT seg) |
adde6300 AM |
1299 | { |
1300 | unsigned char *where; | |
1301 | unsigned long insn; | |
a161fe53 | 1302 | long value = *valP; |
adde6300 | 1303 | |
94f592af NC |
1304 | if (fixP->fx_addsy == (symbolS *) NULL) |
1305 | fixP->fx_done = 1; | |
1306 | ||
87733541 AM |
1307 | else if (fixP->fx_pcrel) |
1308 | { | |
1309 | segT s = S_GET_SEGMENT (fixP->fx_addsy); | |
1310 | ||
1311 | if (s == seg || s == absolute_section) | |
1312 | { | |
1313 | value += S_GET_VALUE (fixP->fx_addsy); | |
1314 | fixP->fx_done = 1; | |
1315 | } | |
1316 | } | |
e4ef1b6c DC |
1317 | else if (linkrelax && fixP->fx_subsy) |
1318 | { | |
1319 | /* For a subtraction relocation expression, generate one | |
1320 | of the DIFF relocs, with the value being the difference. | |
1321 | Note that a sym1 - sym2 expression is adjusted into a | |
1322 | section_start_sym + sym4_offset_from_section_start - sym1 | |
1323 | expression. fixP->fx_addsy holds the section start symbol, | |
1324 | fixP->fx_offset holds sym2's offset, and fixP->fx_subsy | |
1325 | holds sym1. Calculate the current difference and write value, | |
75f58085 BS |
1326 | but leave fx_offset as is - during relaxation, |
1327 | fx_offset - value gives sym1's value. */ | |
e4ef1b6c DC |
1328 | |
1329 | switch (fixP->fx_r_type) | |
1330 | { | |
1331 | case BFD_RELOC_8: | |
1332 | fixP->fx_r_type = BFD_RELOC_AVR_DIFF8; | |
1333 | break; | |
1334 | case BFD_RELOC_16: | |
1335 | fixP->fx_r_type = BFD_RELOC_AVR_DIFF16; | |
1336 | break; | |
1337 | case BFD_RELOC_32: | |
1338 | fixP->fx_r_type = BFD_RELOC_AVR_DIFF32; | |
1339 | break; | |
1340 | default: | |
1341 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
1342 | break; | |
1343 | } | |
1344 | ||
1345 | value = S_GET_VALUE (fixP->fx_addsy) + | |
1346 | fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy); | |
491793b5 | 1347 | *valP = value; |
e4ef1b6c DC |
1348 | |
1349 | fixP->fx_subsy = NULL; | |
1350 | } | |
a161fe53 AM |
1351 | /* We don't actually support subtracting a symbol. */ |
1352 | if (fixP->fx_subsy != (symbolS *) NULL) | |
1353 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
1dab94dd | 1354 | |
e4ef1b6c DC |
1355 | /* For the DIFF relocs, write the value into the object file while still |
1356 | keeping fx_done FALSE, as both the difference (recorded in the object file) | |
75f58085 | 1357 | and the sym offset (part of fixP) are needed at link relax time. */ |
e4ef1b6c | 1358 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
94f592af | 1359 | switch (fixP->fx_r_type) |
adde6300 AM |
1360 | { |
1361 | default: | |
94f592af | 1362 | fixP->fx_no_overflow = 1; |
adde6300 AM |
1363 | break; |
1364 | case BFD_RELOC_AVR_7_PCREL: | |
1365 | case BFD_RELOC_AVR_13_PCREL: | |
1366 | case BFD_RELOC_32: | |
1367 | case BFD_RELOC_16: | |
e4ef1b6c DC |
1368 | break; |
1369 | case BFD_RELOC_AVR_DIFF8: | |
1370 | *where = value; | |
1371 | break; | |
1372 | case BFD_RELOC_AVR_DIFF16: | |
1373 | bfd_putl16 ((bfd_vma) value, where); | |
1374 | break; | |
1375 | case BFD_RELOC_AVR_DIFF32: | |
1376 | bfd_putl32 ((bfd_vma) value, where); | |
1377 | break; | |
adde6300 AM |
1378 | case BFD_RELOC_AVR_CALL: |
1379 | break; | |
1380 | } | |
1381 | ||
94f592af | 1382 | if (fixP->fx_done) |
adde6300 AM |
1383 | { |
1384 | /* Fetch the instruction, insert the fully resolved operand | |
1385 | value, and stuff the instruction back again. */ | |
2132e3a3 | 1386 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
adde6300 AM |
1387 | insn = bfd_getl16 (where); |
1388 | ||
94f592af | 1389 | switch (fixP->fx_r_type) |
adde6300 AM |
1390 | { |
1391 | case BFD_RELOC_AVR_7_PCREL: | |
1392 | if (value & 1) | |
94f592af | 1393 | as_bad_where (fixP->fx_file, fixP->fx_line, |
adde6300 | 1394 | _("odd address operand: %ld"), value); |
1dab94dd | 1395 | |
adde6300 AM |
1396 | /* Instruction addresses are always right-shifted by 1. */ |
1397 | value >>= 1; | |
1398 | --value; /* Correct PC. */ | |
1dab94dd | 1399 | |
adde6300 | 1400 | if (value < -64 || value > 63) |
94f592af | 1401 | as_bad_where (fixP->fx_file, fixP->fx_line, |
adde6300 AM |
1402 | _("operand out of range: %ld"), value); |
1403 | value = (value << 3) & 0x3f8; | |
1404 | bfd_putl16 ((bfd_vma) (value | insn), where); | |
1405 | break; | |
1406 | ||
1407 | case BFD_RELOC_AVR_13_PCREL: | |
1408 | if (value & 1) | |
94f592af | 1409 | as_bad_where (fixP->fx_file, fixP->fx_line, |
adde6300 | 1410 | _("odd address operand: %ld"), value); |
1dab94dd | 1411 | |
adde6300 AM |
1412 | /* Instruction addresses are always right-shifted by 1. */ |
1413 | value >>= 1; | |
1414 | --value; /* Correct PC. */ | |
adde6300 AM |
1415 | |
1416 | if (value < -2048 || value > 2047) | |
1417 | { | |
65aa24b6 | 1418 | /* No wrap for devices with >8K of program memory. */ |
00d2865b | 1419 | if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap) |
94f592af | 1420 | as_bad_where (fixP->fx_file, fixP->fx_line, |
adde6300 AM |
1421 | _("operand out of range: %ld"), value); |
1422 | } | |
1423 | ||
1424 | value &= 0xfff; | |
1425 | bfd_putl16 ((bfd_vma) (value | insn), where); | |
1426 | break; | |
1427 | ||
1428 | case BFD_RELOC_32: | |
0b649256 | 1429 | bfd_putl32 ((bfd_vma) value, where); |
adde6300 AM |
1430 | break; |
1431 | ||
1432 | case BFD_RELOC_16: | |
1433 | bfd_putl16 ((bfd_vma) value, where); | |
1434 | break; | |
1435 | ||
17e57237 NC |
1436 | case BFD_RELOC_8: |
1437 | if (value > 255 || value < -128) | |
1438 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
1439 | _("operand out of range: %ld"), value); | |
1440 | *where = value; | |
1441 | break; | |
1442 | ||
adde6300 | 1443 | case BFD_RELOC_AVR_16_PM: |
c6a7ab1f | 1444 | bfd_putl16 ((bfd_vma) (value >> 1), where); |
adde6300 AM |
1445 | break; |
1446 | ||
750bce0e NC |
1447 | case BFD_RELOC_AVR_LDI: |
1448 | if (value > 255) | |
1449 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1450 | _("operand out of range: %ld"), value); | |
1451 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where); | |
1452 | break; | |
1453 | ||
f36e8886 BS |
1454 | case BFD_RELOC_AVR_LDS_STS_16: |
1455 | if ((value < 0x40) || (value > 0xBF)) | |
1456 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
1457 | _("operand out of range: 0x%lx"), | |
1458 | (unsigned long)value); | |
1459 | insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2)); | |
1460 | bfd_putl16 ((bfd_vma) insn, where); | |
1461 | break; | |
1462 | ||
750bce0e NC |
1463 | case BFD_RELOC_AVR_6: |
1464 | if ((value > 63) || (value < 0)) | |
1465 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1466 | _("operand out of range: %ld"), value); | |
f36e8886 BS |
1467 | bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) |
1468 | | ((value & (1 << 5)) << 8)), where); | |
750bce0e NC |
1469 | break; |
1470 | ||
1471 | case BFD_RELOC_AVR_6_ADIW: | |
1472 | if ((value > 63) || (value < 0)) | |
1473 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1474 | _("operand out of range: %ld"), value); | |
1475 | bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where); | |
1476 | break; | |
1477 | ||
adde6300 AM |
1478 | case BFD_RELOC_AVR_LO8_LDI: |
1479 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where); | |
1480 | break; | |
1481 | ||
adde6300 AM |
1482 | case BFD_RELOC_AVR_HI8_LDI: |
1483 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where); | |
1484 | break; | |
1485 | ||
df406460 | 1486 | case BFD_RELOC_AVR_MS8_LDI: |
adde6300 AM |
1487 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where); |
1488 | break; | |
1489 | ||
1490 | case BFD_RELOC_AVR_HH8_LDI: | |
1491 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where); | |
1492 | break; | |
1493 | ||
1494 | case BFD_RELOC_AVR_LO8_LDI_NEG: | |
1495 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where); | |
1496 | break; | |
1497 | ||
adde6300 AM |
1498 | case BFD_RELOC_AVR_HI8_LDI_NEG: |
1499 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where); | |
1500 | break; | |
1501 | ||
df406460 | 1502 | case BFD_RELOC_AVR_MS8_LDI_NEG: |
adde6300 AM |
1503 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where); |
1504 | break; | |
1505 | ||
1506 | case BFD_RELOC_AVR_HH8_LDI_NEG: | |
1507 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where); | |
1508 | break; | |
1509 | ||
1510 | case BFD_RELOC_AVR_LO8_LDI_PM: | |
1511 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where); | |
1512 | break; | |
1513 | ||
1514 | case BFD_RELOC_AVR_HI8_LDI_PM: | |
1515 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where); | |
1516 | break; | |
1517 | ||
1518 | case BFD_RELOC_AVR_HH8_LDI_PM: | |
1519 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where); | |
1520 | break; | |
1521 | ||
1522 | case BFD_RELOC_AVR_LO8_LDI_PM_NEG: | |
1523 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where); | |
1524 | break; | |
1525 | ||
1526 | case BFD_RELOC_AVR_HI8_LDI_PM_NEG: | |
1527 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where); | |
1528 | break; | |
1529 | ||
1530 | case BFD_RELOC_AVR_HH8_LDI_PM_NEG: | |
1531 | bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where); | |
1532 | break; | |
1533 | ||
1534 | case BFD_RELOC_AVR_CALL: | |
1535 | { | |
1536 | unsigned long x; | |
1dab94dd | 1537 | |
adde6300 AM |
1538 | x = bfd_getl16 (where); |
1539 | if (value & 1) | |
94f592af | 1540 | as_bad_where (fixP->fx_file, fixP->fx_line, |
adde6300 AM |
1541 | _("odd address operand: %ld"), value); |
1542 | value >>= 1; | |
1543 | x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16; | |
1544 | bfd_putl16 ((bfd_vma) x, where); | |
c6a7ab1f | 1545 | bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); |
adde6300 AM |
1546 | } |
1547 | break; | |
1548 | ||
99700d6f NC |
1549 | case BFD_RELOC_AVR_8_LO: |
1550 | *where = 0xff & value; | |
1551 | break; | |
1552 | ||
1553 | case BFD_RELOC_AVR_8_HI: | |
1554 | *where = 0xff & (value >> 8); | |
1555 | break; | |
1556 | ||
40551fb8 | 1557 | case BFD_RELOC_AVR_8_HLO: |
99700d6f NC |
1558 | *where = 0xff & (value >> 16); |
1559 | break; | |
1560 | ||
1561 | default: | |
c6a7ab1f | 1562 | as_fatal (_("line %d: unknown relocation type: 0x%x"), |
94f592af | 1563 | fixP->fx_line, fixP->fx_r_type); |
adde6300 | 1564 | break; |
75f58085 BS |
1565 | |
1566 | case BFD_RELOC_AVR_PORT6: | |
1567 | if (value > 63) | |
1568 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1569 | _("operand out of range: %ld"), value); | |
1570 | bfd_putl16 ((bfd_vma) insn | ((value & 0x30) << 5) | (value & 0x0f), where); | |
1571 | break; | |
1572 | ||
1573 | case BFD_RELOC_AVR_PORT5: | |
1574 | if (value > 31) | |
1575 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
1576 | _("operand out of range: %ld"), value); | |
1577 | bfd_putl16 ((bfd_vma) insn | ((value & 0x1f) << 3), where); | |
1578 | break; | |
adde6300 AM |
1579 | } |
1580 | } | |
1581 | else | |
1582 | { | |
a61a9fbc | 1583 | switch ((int) fixP->fx_r_type) |
adde6300 AM |
1584 | { |
1585 | case -BFD_RELOC_AVR_HI8_LDI_NEG: | |
1586 | case -BFD_RELOC_AVR_HI8_LDI: | |
1587 | case -BFD_RELOC_AVR_LO8_LDI_NEG: | |
1588 | case -BFD_RELOC_AVR_LO8_LDI: | |
94f592af | 1589 | as_bad_where (fixP->fx_file, fixP->fx_line, |
adde6300 | 1590 | _("only constant expression allowed")); |
94f592af | 1591 | fixP->fx_done = 1; |
adde6300 AM |
1592 | break; |
1593 | default: | |
1594 | break; | |
1595 | } | |
adde6300 | 1596 | } |
adde6300 AM |
1597 | } |
1598 | ||
7be1c489 AM |
1599 | /* GAS will call this to generate a reloc, passing the resulting reloc |
1600 | to `bfd_install_relocation'. This currently works poorly, as | |
1601 | `bfd_install_relocation' often does the wrong thing, and instances of | |
1602 | `tc_gen_reloc' have been written to work around the problems, which | |
1603 | in turns makes it difficult to fix `bfd_install_relocation'. */ | |
adde6300 AM |
1604 | |
1605 | /* If while processing a fixup, a reloc really needs to be created | |
1606 | then it is done here. */ | |
1607 | ||
1608 | arelent * | |
dc191a8f NC |
1609 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, |
1610 | fixS *fixp) | |
adde6300 AM |
1611 | { |
1612 | arelent *reloc; | |
1613 | ||
94d4433a | 1614 | if (fixp->fx_subsy != NULL) |
df406460 | 1615 | { |
94d4433a | 1616 | as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex")); |
df406460 NC |
1617 | return NULL; |
1618 | } | |
1619 | ||
dc191a8f | 1620 | reloc = xmalloc (sizeof (arelent)); |
adde6300 | 1621 | |
dc191a8f | 1622 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
adde6300 AM |
1623 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
1624 | ||
1625 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
1626 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
1627 | if (reloc->howto == (reloc_howto_type *) NULL) | |
1628 | { | |
1629 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
c6a7ab1f NC |
1630 | _("reloc %d not supported by object file format"), |
1631 | (int) fixp->fx_r_type); | |
adde6300 AM |
1632 | return NULL; |
1633 | } | |
1634 | ||
1635 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1636 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1637 | reloc->address = fixp->fx_offset; | |
1638 | ||
1639 | reloc->addend = fixp->fx_offset; | |
1640 | ||
1641 | return reloc; | |
1642 | } | |
1643 | ||
adde6300 | 1644 | void |
dc191a8f | 1645 | md_assemble (char *str) |
adde6300 | 1646 | { |
c6a7ab1f | 1647 | struct avr_opcodes_s *opcode; |
adde6300 AM |
1648 | char op[11]; |
1649 | ||
c6a7ab1f | 1650 | str = skip_space (extract_word (str, op, sizeof (op))); |
adde6300 AM |
1651 | |
1652 | if (!op[0]) | |
00d2865b | 1653 | as_bad (_("can't find opcode ")); |
adde6300 AM |
1654 | |
1655 | opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op); | |
1656 | ||
f36e8886 BS |
1657 | if (opcode && !avr_opt.all_opcodes) |
1658 | { | |
75f58085 | 1659 | /* Check if the instruction's ISA bit is ON in the ISA bits of the part |
f36e8886 | 1660 | specified by the user. If not look for other instructions |
75f58085 | 1661 | specifications with same mnemonic who's ISA bits matches. |
f36e8886 BS |
1662 | |
1663 | This requires include/opcode/avr.h to have the instructions with | |
1664 | same mnenomic to be specified in sequence. */ | |
1665 | ||
1666 | while ((opcode->isa & avr_mcu->isa) != opcode->isa) | |
1667 | { | |
1668 | opcode++; | |
75f58085 | 1669 | |
f36e8886 BS |
1670 | if (opcode->name && strcmp(op, opcode->name)) |
1671 | { | |
75f58085 | 1672 | as_bad (_("illegal opcode %s for mcu %s"), |
f36e8886 BS |
1673 | opcode->name, avr_mcu->name); |
1674 | return; | |
1675 | } | |
1676 | } | |
75f58085 | 1677 | } |
f36e8886 | 1678 | |
adde6300 AM |
1679 | if (opcode == NULL) |
1680 | { | |
00d2865b | 1681 | as_bad (_("unknown opcode `%s'"), op); |
adde6300 AM |
1682 | return; |
1683 | } | |
1684 | ||
b170af93 | 1685 | /* Special case for opcodes with optional operands (lpm, elpm) - |
1188e082 | 1686 | version with operands exists in avr_opcodes[] in the next entry. */ |
c6a7ab1f | 1687 | |
1188e082 DC |
1688 | if (*str && *opcode->constraints == '?') |
1689 | ++opcode; | |
b170af93 | 1690 | |
d4f4f3fb AM |
1691 | dwarf2_emit_insn (0); |
1692 | ||
adde6300 AM |
1693 | /* We used to set input_line_pointer to the result of get_operands, |
1694 | but that is wrong. Our caller assumes we don't change it. */ | |
1695 | { | |
1696 | char *t = input_line_pointer; | |
dc191a8f | 1697 | |
adde6300 | 1698 | avr_operands (opcode, &str); |
b170af93 | 1699 | if (*skip_space (str)) |
00d2865b | 1700 | as_bad (_("garbage at end of line")); |
adde6300 AM |
1701 | input_line_pointer = t; |
1702 | } | |
1703 | } | |
1704 | ||
62ebcb5c | 1705 | const exp_mod_data_t exp_mod_data[] = |
99700d6f NC |
1706 | { |
1707 | /* Default, must be first. */ | |
1708 | { "", 0, BFD_RELOC_16, "" }, | |
1709 | /* Divides by 2 to get word address. Generate Stub. */ | |
1710 | { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " }, | |
1711 | { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " }, | |
1712 | /* The following are used together with avr-gcc's __memx address space | |
1713 | in order to initialize a 24-bit pointer variable with a 24-bit address. | |
40551fb8 NC |
1714 | For address in flash, hlo8 will contain the flash segment if the |
1715 | symbol is located in flash. If the symbol is located in RAM; hlo8 | |
99700d6f NC |
1716 | will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash |
1717 | addresses linearize address space. */ | |
1718 | { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " }, | |
1719 | { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " }, | |
40551fb8 NC |
1720 | { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " }, |
1721 | { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " }, | |
99700d6f NC |
1722 | /* End of list. */ |
1723 | { NULL, 0, 0, NULL } | |
1724 | }; | |
1725 | ||
99700d6f NC |
1726 | /* Parse special CONS expression: pm (expression) or alternatively |
1727 | gs (expression). These are used for addressing program memory. Moreover, | |
40551fb8 | 1728 | define lo8 (expression), hi8 (expression) and hlo8 (expression). */ |
c6a7ab1f | 1729 | |
62ebcb5c | 1730 | const exp_mod_data_t * |
dc191a8f | 1731 | avr_parse_cons_expression (expressionS *exp, int nbytes) |
adde6300 | 1732 | { |
99700d6f | 1733 | const exp_mod_data_t *pexp = &exp_mod_data[0]; |
c6a7ab1f | 1734 | char *tmp; |
adde6300 | 1735 | |
adde6300 AM |
1736 | tmp = input_line_pointer = skip_space (input_line_pointer); |
1737 | ||
99700d6f NC |
1738 | /* The first entry of exp_mod_data[] contains an entry if no |
1739 | expression modifier is present. Skip it. */ | |
1740 | ||
1741 | for (pexp++; pexp->name; pexp++) | |
adde6300 | 1742 | { |
99700d6f | 1743 | int len = strlen (pexp->name); |
1dab94dd | 1744 | |
99700d6f NC |
1745 | if (nbytes == pexp->nbytes |
1746 | && strncasecmp (input_line_pointer, pexp->name, len) == 0) | |
adde6300 AM |
1747 | { |
1748 | input_line_pointer = skip_space (input_line_pointer + len); | |
1dab94dd | 1749 | |
adde6300 AM |
1750 | if (*input_line_pointer == '(') |
1751 | { | |
1752 | input_line_pointer = skip_space (input_line_pointer + 1); | |
adde6300 | 1753 | expression (exp); |
1dab94dd | 1754 | |
adde6300 | 1755 | if (*input_line_pointer == ')') |
62ebcb5c AM |
1756 | { |
1757 | ++input_line_pointer; | |
1758 | return pexp; | |
1759 | } | |
adde6300 AM |
1760 | else |
1761 | { | |
00d2865b | 1762 | as_bad (_("`)' required")); |
62ebcb5c | 1763 | return &exp_mod_data[0]; |
adde6300 | 1764 | } |
adde6300 | 1765 | } |
1dab94dd | 1766 | |
adde6300 | 1767 | input_line_pointer = tmp; |
99700d6f NC |
1768 | |
1769 | break; | |
adde6300 AM |
1770 | } |
1771 | } | |
1dab94dd | 1772 | |
adde6300 | 1773 | expression (exp); |
62ebcb5c | 1774 | return &exp_mod_data[0]; |
adde6300 AM |
1775 | } |
1776 | ||
1777 | void | |
dc191a8f NC |
1778 | avr_cons_fix_new (fragS *frag, |
1779 | int where, | |
1780 | int nbytes, | |
62ebcb5c AM |
1781 | expressionS *exp, |
1782 | const exp_mod_data_t *pexp_mod_data) | |
adde6300 | 1783 | { |
99700d6f NC |
1784 | int bad = 0; |
1785 | ||
1786 | switch (pexp_mod_data->reloc) | |
adde6300 | 1787 | { |
99700d6f | 1788 | default: |
17e57237 NC |
1789 | if (nbytes == 1) |
1790 | fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8); | |
1791 | else if (nbytes == 2) | |
b34976b6 | 1792 | fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16); |
adde6300 | 1793 | else if (nbytes == 4) |
b34976b6 | 1794 | fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32); |
adde6300 | 1795 | else |
99700d6f NC |
1796 | bad = 1; |
1797 | break; | |
1798 | ||
1799 | case BFD_RELOC_AVR_16_PM: | |
1800 | case BFD_RELOC_AVR_8_LO: | |
1801 | case BFD_RELOC_AVR_8_HI: | |
40551fb8 | 1802 | case BFD_RELOC_AVR_8_HLO: |
99700d6f NC |
1803 | if (nbytes == pexp_mod_data->nbytes) |
1804 | fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc); | |
adde6300 | 1805 | else |
99700d6f NC |
1806 | bad = 1; |
1807 | break; | |
adde6300 | 1808 | } |
99700d6f NC |
1809 | |
1810 | if (bad) | |
1811 | as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes); | |
adde6300 | 1812 | } |
af3ecb4a | 1813 | |
71863e73 NC |
1814 | static bfd_boolean |
1815 | mcu_has_3_byte_pc (void) | |
1816 | { | |
75f58085 | 1817 | int mach = avr_mcu->mach; |
71863e73 | 1818 | |
75f58085 BS |
1819 | return mach == bfd_mach_avr6 |
1820 | || mach == bfd_mach_avrxmega6 | |
71863e73 NC |
1821 | || mach == bfd_mach_avrxmega7; |
1822 | } | |
1823 | ||
af3ecb4a RH |
1824 | void |
1825 | tc_cfi_frame_initial_instructions (void) | |
1826 | { | |
1827 | /* AVR6 pushes 3 bytes for calls. */ | |
71863e73 | 1828 | int return_size = (mcu_has_3_byte_pc () ? 3 : 2); |
af3ecb4a RH |
1829 | |
1830 | /* The CFA is the caller's stack location before the call insn. */ | |
1831 | /* Note that the stack pointer is dwarf register number 32. */ | |
1832 | cfi_add_CFA_def_cfa (32, return_size); | |
1833 | ||
1834 | /* Note that AVR consistently uses post-decrement, which means that things | |
1835 | do not line up the same way as for targers that use pre-decrement. */ | |
1836 | cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size); | |
1837 | } | |
e4ef1b6c DC |
1838 | |
1839 | bfd_boolean | |
1840 | avr_allow_local_subtract (expressionS * left, | |
1841 | expressionS * right, | |
1842 | segT section) | |
1843 | { | |
75f58085 | 1844 | /* If we are not in relaxation mode, subtraction is OK. */ |
e4ef1b6c DC |
1845 | if (!linkrelax) |
1846 | return TRUE; | |
1847 | ||
1848 | /* If the symbols are not in a code section then they are OK. */ | |
1849 | if ((section->flags & SEC_CODE) == 0) | |
1850 | return TRUE; | |
1851 | ||
1852 | if (left->X_add_symbol == right->X_add_symbol) | |
1853 | return TRUE; | |
1854 | ||
1855 | /* We have to assume that there may be instructions between the | |
1856 | two symbols and that relaxation may increase the distance between | |
1857 | them. */ | |
1858 | return FALSE; | |
1859 | } | |
eac7440d AB |
1860 | |
1861 | void | |
1862 | avr_elf_final_processing (void) | |
1863 | { | |
1864 | if (linkrelax) | |
1865 | elf_elfheader (stdoutput)->e_flags |= EF_AVR_LINKRELAX_PREPARED; | |
1866 | } |