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c2dcd04e | 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
a2c58332 | 2 | Copyright (C) 1991-2022 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
bc0d738a | 21 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
252b5132 | 22 | |
252b5132 RH |
23 | #include "as.h" |
24 | #include "subsegs.h" | |
2c8714f2 | 25 | #include "dwarf2dbg.h" |
2c8714f2 | 26 | |
252b5132 RH |
27 | #define DEFINE_TABLE |
28 | #define h8_opcodes ops | |
29 | #include "opcode/h8300.h" | |
3882b010 | 30 | #include "safe-ctype.h" |
7e0de7bf | 31 | #include "elf/h8.h" |
7e0de7bf | 32 | |
63a0b638 | 33 | const char comment_chars[] = ";"; |
252b5132 | 34 | const char line_comment_chars[] = "#"; |
5518c738 YS |
35 | #ifdef TE_LINUX |
36 | const char line_separator_chars[] = "!"; | |
37 | #else | |
63a0b638 | 38 | const char line_separator_chars[] = ""; |
5518c738 | 39 | #endif |
252b5132 | 40 | |
600e9c99 KH |
41 | static void sbranch (int); |
42 | static void h8300hmode (int); | |
43 | static void h8300smode (int); | |
44 | static void h8300hnmode (int); | |
45 | static void h8300snmode (int); | |
46 | static void h8300sxmode (int); | |
47 | static void h8300sxnmode (int); | |
b54a3392 | 48 | static void pint (int); |
252b5132 | 49 | |
66faad26 KH |
50 | int Hmode; |
51 | int Smode; | |
52 | int Nmode; | |
53 | int SXmode; | |
3048287a | 54 | |
5518c738 YS |
55 | static int default_mach = bfd_mach_h8300; |
56 | ||
d4e2de6b | 57 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
3048287a | 58 | |
600e9c99 | 59 | static int bsize = L_8; /* Default branch displacement. */ |
252b5132 | 60 | |
a720f7bc KD |
61 | struct h8_instruction |
62 | { | |
63 | int length; | |
64 | int noperands; | |
65 | int idx; | |
66 | int size; | |
67 | const struct h8_opcode *opcode; | |
68 | }; | |
69 | ||
600e9c99 | 70 | static struct h8_instruction *h8_instructions; |
a720f7bc | 71 | |
600e9c99 | 72 | static void |
b54a3392 | 73 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
74 | { |
75 | Hmode = 1; | |
76 | Smode = 0; | |
83e20b45 JL |
77 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
78 | as_warn (_("could not set architecture and machine")); | |
252b5132 RH |
79 | } |
80 | ||
600e9c99 | 81 | static void |
b54a3392 | 82 | h8300smode (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
83 | { |
84 | Smode = 1; | |
85 | Hmode = 1; | |
83e20b45 JL |
86 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
87 | as_warn (_("could not set architecture and machine")); | |
252b5132 | 88 | } |
70d6ecf3 | 89 | |
600e9c99 | 90 | static void |
b54a3392 | 91 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
92 | { |
93 | Hmode = 1; | |
94 | Smode = 0; | |
95 | Nmode = 1; | |
8d9cd6b1 NC |
96 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
97 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
98 | } |
99 | ||
600e9c99 | 100 | static void |
b54a3392 | 101 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
8d9cd6b1 NC |
102 | { |
103 | Smode = 1; | |
104 | Hmode = 1; | |
105 | Nmode = 1; | |
8d9cd6b1 NC |
106 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
107 | as_warn (_("could not set architecture and machine")); | |
8d9cd6b1 NC |
108 | } |
109 | ||
600e9c99 | 110 | static void |
b54a3392 | 111 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
7ee7b84d MS |
112 | { |
113 | Smode = 1; | |
114 | Hmode = 1; | |
115 | SXmode = 1; | |
7ee7b84d MS |
116 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
117 | as_warn (_("could not set architecture and machine")); | |
7ee7b84d MS |
118 | } |
119 | ||
600e9c99 | 120 | static void |
b54a3392 | 121 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
f4984206 RS |
122 | { |
123 | Smode = 1; | |
124 | Hmode = 1; | |
125 | SXmode = 1; | |
126 | Nmode = 1; | |
f4984206 RS |
127 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
128 | as_warn (_("could not set architecture and machine")); | |
f4984206 RS |
129 | } |
130 | ||
600e9c99 | 131 | static void |
b54a3392 | 132 | sbranch (int size) |
252b5132 RH |
133 | { |
134 | bsize = size; | |
135 | } | |
136 | ||
70d6ecf3 | 137 | static void |
b54a3392 | 138 | pint (int arg ATTRIBUTE_UNUSED) |
252b5132 RH |
139 | { |
140 | cons (Hmode ? 4 : 2); | |
141 | } | |
142 | ||
52b010e4 NC |
143 | /* Like obj_elf_section, but issues a warning for new |
144 | sections which do not have an attribute specification. */ | |
145 | ||
146 | static void | |
147 | h8300_elf_section (int push) | |
148 | { | |
149 | static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; | |
9c8b3bfe | 150 | static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; |
52b010e4 | 151 | char * saved_ilp = input_line_pointer; |
b9bb4a93 | 152 | const char * name; |
52b010e4 NC |
153 | |
154 | name = obj_elf_section_name (); | |
155 | if (name == NULL) | |
156 | return; | |
157 | ||
158 | if (* input_line_pointer != ',' | |
159 | && bfd_get_section_by_name (stdoutput, name) == NULL) | |
160 | { | |
161 | signed int i; | |
162 | ||
163 | /* Ignore this warning for well known data sections. */ | |
164 | for (i = ARRAY_SIZE (known_data_sections); i--;) | |
165 | if (strcmp (name, known_data_sections[i]) == 0) | |
166 | break; | |
167 | ||
168 | if (i < 0) | |
169 | for (i = ARRAY_SIZE (known_data_prefixes); i--;) | |
d34049e8 | 170 | if (startswith (name, known_data_prefixes[i])) |
52b010e4 NC |
171 | break; |
172 | ||
173 | if (i < 0) | |
174 | as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); | |
175 | } | |
176 | ||
177 | /* FIXME: We ought to free the memory allocated by obj_elf_section_name() | |
178 | for 'name', but we do not know if it was taken from the obstack, via | |
179 | demand_copy_C_string(), or xmalloc()ed. */ | |
180 | input_line_pointer = saved_ilp; | |
181 | obj_elf_section (push); | |
182 | } | |
183 | ||
3048287a NC |
184 | /* This table describes all the machine specific pseudo-ops the assembler |
185 | has to support. The fields are: | |
186 | pseudo-op name without dot | |
187 | function to call to execute this pseudo-op | |
188 | Integer arg to pass to the function. */ | |
189 | ||
252b5132 RH |
190 | const pseudo_typeS md_pseudo_table[] = |
191 | { | |
7ee7b84d | 192 | {"h8300h", h8300hmode, 0}, |
8d9cd6b1 | 193 | {"h8300hn", h8300hnmode, 0}, |
7ee7b84d | 194 | {"h8300s", h8300smode, 0}, |
8d9cd6b1 | 195 | {"h8300sn", h8300snmode, 0}, |
7ee7b84d | 196 | {"h8300sx", h8300sxmode, 0}, |
f4984206 | 197 | {"h8300sxn", h8300sxnmode, 0}, |
252b5132 RH |
198 | {"sbranch", sbranch, L_8}, |
199 | {"lbranch", sbranch, L_16}, | |
200 | ||
201 | {"int", pint, 0}, | |
202 | {"data.b", cons, 1}, | |
203 | {"data.w", cons, 2}, | |
204 | {"data.l", cons, 4}, | |
205 | {"form", listing_psize, 0}, | |
206 | {"heading", listing_title, 0}, | |
7ee7b84d MS |
207 | {"import", s_ignore, 0}, |
208 | {"page", listing_eject, 0}, | |
252b5132 | 209 | {"program", s_ignore, 0}, |
52b010e4 | 210 | |
52b010e4 NC |
211 | {"section", h8300_elf_section, 0}, |
212 | {"section.s", h8300_elf_section, 0}, | |
213 | {"sect", h8300_elf_section, 0}, | |
214 | {"sect.s", h8300_elf_section, 0}, | |
52b010e4 | 215 | |
252b5132 RH |
216 | {0, 0, 0} |
217 | }; | |
218 | ||
252b5132 RH |
219 | const char EXP_CHARS[] = "eE"; |
220 | ||
3048287a NC |
221 | /* Chars that mean this number is a floating point constant |
222 | As in 0f12.456 | |
223 | or 0d1.2345e12. */ | |
252b5132 RH |
224 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
225 | ||
629310ab | 226 | static htab_t opcode_hash_control; /* Opcode mnemonics. */ |
252b5132 | 227 | |
70d6ecf3 AM |
228 | /* This function is called once, at assembler startup time. This |
229 | should set up all the tables, etc. that the MD part of the assembler | |
230 | needs. */ | |
3048287a | 231 | |
252b5132 | 232 | void |
b54a3392 | 233 | md_begin (void) |
252b5132 | 234 | { |
a720f7bc | 235 | unsigned int nopcodes; |
7ee7b84d | 236 | struct h8_opcode *p, *p1; |
a720f7bc | 237 | struct h8_instruction *pi; |
252b5132 RH |
238 | char prev_buffer[100]; |
239 | int idx = 0; | |
240 | ||
5518c738 | 241 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) |
83e20b45 | 242 | as_warn (_("could not set architecture and machine")); |
83e20b45 | 243 | |
629310ab | 244 | opcode_hash_control = str_htab_create (); |
252b5132 RH |
245 | prev_buffer[0] = 0; |
246 | ||
a720f7bc | 247 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
3739860c | 248 | |
add39d23 | 249 | h8_instructions = XNEWVEC (struct h8_instruction, nopcodes); |
a720f7bc | 250 | |
7ee7b84d MS |
251 | pi = h8_instructions; |
252 | p1 = h8_opcodes; | |
253 | /* We do a minimum amount of sorting on the opcode table; this is to | |
254 | make it easy to describe the mova instructions without unnecessary | |
255 | code duplication. | |
256 | Sorting only takes place inside blocks of instructions of the form | |
257 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ | |
258 | while (p1) | |
252b5132 | 259 | { |
7ee7b84d MS |
260 | struct h8_opcode *first_skipped = 0; |
261 | int len, cmplen = 0; | |
f86f5863 | 262 | const char *src = p1->name; |
7ee7b84d | 263 | char *dst, *buffer; |
252b5132 | 264 | |
7ee7b84d MS |
265 | if (p1->name == 0) |
266 | break; | |
267 | /* Strip off any . part when inserting the opcode and only enter | |
268 | unique codes into the hash table. */ | |
add39d23 | 269 | dst = buffer = XNEWVEC (char, strlen (src) + 1); |
252b5132 RH |
270 | while (*src) |
271 | { | |
272 | if (*src == '.') | |
273 | { | |
274 | src++; | |
252b5132 RH |
275 | break; |
276 | } | |
7ee7b84d MS |
277 | if (*src == '/') |
278 | cmplen = src - p1->name + 1; | |
252b5132 RH |
279 | *dst++ = *src++; |
280 | } | |
7ee7b84d MS |
281 | *dst = 0; |
282 | len = dst - buffer; | |
283 | if (cmplen == 0) | |
284 | cmplen = len; | |
fe0e921f | 285 | str_hash_insert (opcode_hash_control, buffer, pi, 0); |
7ee7b84d MS |
286 | strcpy (prev_buffer, buffer); |
287 | idx++; | |
288 | ||
289 | for (p = p1; p->name; p++) | |
252b5132 | 290 | { |
7ee7b84d MS |
291 | /* A negative TIME is used to indicate that we've added this opcode |
292 | already. */ | |
293 | if (p->time == -1) | |
294 | continue; | |
295 | if (strncmp (p->name, buffer, cmplen) != 0 | |
296 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' | |
297 | && p->name[cmplen - 1] != '/')) | |
298 | { | |
299 | if (first_skipped == 0) | |
300 | first_skipped = p; | |
301 | break; | |
302 | } | |
303 | if (strncmp (p->name, buffer, len) != 0) | |
304 | { | |
305 | if (first_skipped == 0) | |
306 | first_skipped = p; | |
307 | continue; | |
308 | } | |
309 | ||
310 | p->time = -1; | |
311 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; | |
312 | pi->idx = idx; | |
252b5132 | 313 | |
7ee7b84d MS |
314 | /* Find the number of operands. */ |
315 | pi->noperands = 0; | |
316 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) | |
317 | pi->noperands++; | |
70d6ecf3 | 318 | |
7ee7b84d MS |
319 | /* Find the length of the opcode in bytes. */ |
320 | pi->length = 0; | |
321 | while (p->data.nib[pi->length * 2] != (op_type) E) | |
322 | pi->length++; | |
a720f7bc | 323 | |
7ee7b84d MS |
324 | pi->opcode = p; |
325 | pi++; | |
326 | } | |
327 | p1 = first_skipped; | |
252b5132 RH |
328 | } |
329 | ||
a720f7bc KD |
330 | /* Add entry for the NULL vector terminator. */ |
331 | pi->length = 0; | |
332 | pi->noperands = 0; | |
333 | pi->idx = 0; | |
334 | pi->size = 0; | |
7ee7b84d | 335 | pi->opcode = 0; |
a720f7bc | 336 | |
252b5132 RH |
337 | linkrelax = 1; |
338 | } | |
339 | ||
252b5132 RH |
340 | struct h8_op |
341 | { | |
342 | op_type mode; | |
343 | unsigned reg; | |
344 | expressionS exp; | |
345 | }; | |
346 | ||
b54a3392 KH |
347 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
348 | static void fix_operand_size (struct h8_op *, int); | |
349 | static void build_bytes (const struct h8_instruction *, struct h8_op *); | |
bcb012d3 | 350 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
e0471c16 | 351 | static void check_operand (struct h8_op *, unsigned int, const char *); |
b54a3392 KH |
352 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; |
353 | static char *get_operands (unsigned, char *, struct h8_op *); | |
354 | static void get_operand (char **, struct h8_op *, int); | |
355 | static int parse_reg (char *, op_type *, unsigned *, int); | |
356 | static char *skip_colonthing (char *, int *); | |
357 | static char *parse_exp (char *, struct h8_op *); | |
358 | ||
b54a3392 | 359 | static int constant_fits_size_p (struct h8_op *, int, int); |
7ee7b84d | 360 | |
252b5132 RH |
361 | /* |
362 | parse operands | |
363 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp | |
364 | r0l,r0h,..r7l,r7h | |
365 | @WREG | |
366 | @WREG+ | |
367 | @-WREG | |
368 | #const | |
369 | ccr | |
370 | */ | |
371 | ||
bc0d738a NC |
372 | /* Try to parse a reg name. Return the number of chars consumed. */ |
373 | ||
40f09f82 | 374 | static int |
b54a3392 | 375 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
252b5132 RH |
376 | { |
377 | char *end; | |
378 | int len; | |
379 | ||
d02603dc | 380 | /* Cribbed from get_symbol_name. */ |
252b5132 RH |
381 | if (!is_name_beginner (*src) || *src == '\001') |
382 | return 0; | |
70d6ecf3 | 383 | end = src + 1; |
7ee7b84d | 384 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
252b5132 RH |
385 | end++; |
386 | len = end - src; | |
387 | ||
7ee7b84d | 388 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
389 | { |
390 | *mode = PSIZE | REG | direction; | |
391 | *reg = 7; | |
392 | return len; | |
393 | } | |
3739860c L |
394 | if (len == 3 && |
395 | TOLOWER (src[0]) == 'c' && | |
396 | TOLOWER (src[1]) == 'c' && | |
7ee7b84d | 397 | TOLOWER (src[2]) == 'r') |
252b5132 RH |
398 | { |
399 | *mode = CCR; | |
400 | *reg = 0; | |
401 | return len; | |
402 | } | |
3739860c L |
403 | if (len == 3 && |
404 | TOLOWER (src[0]) == 'e' && | |
405 | TOLOWER (src[1]) == 'x' && | |
7ee7b84d | 406 | TOLOWER (src[2]) == 'r') |
252b5132 RH |
407 | { |
408 | *mode = EXR; | |
7ee7b84d MS |
409 | *reg = 1; |
410 | return len; | |
411 | } | |
3739860c L |
412 | if (len == 3 && |
413 | TOLOWER (src[0]) == 'v' && | |
414 | TOLOWER (src[1]) == 'b' && | |
7ee7b84d MS |
415 | TOLOWER (src[2]) == 'r') |
416 | { | |
417 | *mode = VBR; | |
418 | *reg = 6; | |
419 | return len; | |
420 | } | |
3739860c L |
421 | if (len == 3 && |
422 | TOLOWER (src[0]) == 's' && | |
423 | TOLOWER (src[1]) == 'b' && | |
7ee7b84d MS |
424 | TOLOWER (src[2]) == 'r') |
425 | { | |
426 | *mode = SBR; | |
427 | *reg = 7; | |
252b5132 RH |
428 | return len; |
429 | } | |
7ee7b84d | 430 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
252b5132 RH |
431 | { |
432 | *mode = PSIZE | REG | direction; | |
433 | *reg = 6; | |
434 | return len; | |
435 | } | |
7ee7b84d MS |
436 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
437 | src[2] >= '0' && src[2] <= '7') | |
252b5132 RH |
438 | { |
439 | *mode = L_32 | REG | direction; | |
440 | *reg = src[2] - '0'; | |
441 | if (!Hmode) | |
442 | as_warn (_("Reg not valid for H8/300")); | |
443 | return len; | |
444 | } | |
7ee7b84d | 445 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
252b5132 RH |
446 | { |
447 | *mode = L_16 | REG | direction; | |
448 | *reg = src[1] - '0' + 8; | |
449 | if (!Hmode) | |
450 | as_warn (_("Reg not valid for H8/300")); | |
451 | return len; | |
452 | } | |
453 | ||
7ee7b84d | 454 | if (TOLOWER (src[0]) == 'r') |
252b5132 RH |
455 | { |
456 | if (src[1] >= '0' && src[1] <= '7') | |
457 | { | |
7ee7b84d | 458 | if (len == 3 && TOLOWER (src[2]) == 'l') |
252b5132 RH |
459 | { |
460 | *mode = L_8 | REG | direction; | |
461 | *reg = (src[1] - '0') + 8; | |
462 | return len; | |
463 | } | |
7ee7b84d | 464 | if (len == 3 && TOLOWER (src[2]) == 'h') |
252b5132 RH |
465 | { |
466 | *mode = L_8 | REG | direction; | |
467 | *reg = (src[1] - '0'); | |
468 | return len; | |
469 | } | |
470 | if (len == 2) | |
471 | { | |
472 | *mode = L_16 | REG | direction; | |
473 | *reg = (src[1] - '0'); | |
474 | return len; | |
475 | } | |
476 | } | |
477 | } | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
1b680e4f RS |
482 | |
483 | /* Parse an immediate or address-related constant and store it in OP. | |
484 | If the user also specifies the operand's size, store that size | |
485 | in OP->MODE, otherwise leave it for later code to decide. */ | |
486 | ||
40f09f82 | 487 | static char * |
b54a3392 | 488 | parse_exp (char *src, struct h8_op *op) |
252b5132 | 489 | { |
1b680e4f | 490 | char *save; |
252b5132 | 491 | |
1b680e4f RS |
492 | save = input_line_pointer; |
493 | input_line_pointer = src; | |
494 | expression (&op->exp); | |
495 | if (op->exp.X_op == O_absent) | |
252b5132 | 496 | as_bad (_("missing operand")); |
1b680e4f | 497 | src = input_line_pointer; |
252b5132 | 498 | input_line_pointer = save; |
1b680e4f RS |
499 | |
500 | return skip_colonthing (src, &op->mode); | |
252b5132 RH |
501 | } |
502 | ||
1b680e4f RS |
503 | |
504 | /* If SRC starts with an explicit operand size, skip it and store the size | |
505 | in *MODE. Leave *MODE unchanged otherwise. */ | |
506 | ||
252b5132 | 507 | static char * |
b54a3392 | 508 | skip_colonthing (char *src, int *mode) |
252b5132 | 509 | { |
1b680e4f | 510 | if (*src == ':') |
252b5132 | 511 | { |
1b680e4f | 512 | src++; |
252b5132 | 513 | *mode &= ~SIZE; |
1b680e4f | 514 | if (src[0] == '8' && !ISDIGIT (src[1])) |
7ee7b84d | 515 | *mode |= L_8; |
1b680e4f | 516 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
7ee7b84d | 517 | *mode |= L_2; |
1b680e4f | 518 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
7ee7b84d | 519 | *mode |= L_3; |
1b680e4f | 520 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
7ee7b84d | 521 | *mode |= L_4; |
1b680e4f | 522 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
7ee7b84d | 523 | *mode |= L_5; |
1b680e4f | 524 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
7ee7b84d | 525 | *mode |= L_24; |
1b680e4f | 526 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
7ee7b84d | 527 | *mode |= L_32; |
1b680e4f | 528 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
7ee7b84d | 529 | *mode |= L_16; |
252b5132 | 530 | else |
7ee7b84d MS |
531 | as_bad (_("invalid operand size requested")); |
532 | ||
1b680e4f RS |
533 | while (ISDIGIT (*src)) |
534 | src++; | |
252b5132 | 535 | } |
1b680e4f | 536 | return src; |
252b5132 RH |
537 | } |
538 | ||
539 | /* The many forms of operand: | |
540 | ||
541 | Rn Register direct | |
542 | @Rn Register indirect | |
543 | @(exp[:16], Rn) Register indirect with displacement | |
544 | @Rn+ | |
545 | @-Rn | |
70d6ecf3 AM |
546 | @aa:8 absolute 8 bit |
547 | @aa:16 absolute 16 bit | |
252b5132 RH |
548 | @aa absolute 16 bit |
549 | ||
550 | #xx[:size] immediate data | |
70d6ecf3 | 551 | @(exp:[8], pc) pc rel |
3048287a | 552 | @@aa[:8] memory indirect. */ |
252b5132 | 553 | |
7ee7b84d | 554 | static int |
df7b86aa | 555 | constant_fits_width_p (struct h8_op *operand, offsetT width) |
7ee7b84d | 556 | { |
35a35807 AM |
557 | offsetT num; |
558 | ||
559 | num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
560 | return (num & ~width) == 0 || (num | width) == ~0; | |
7ee7b84d MS |
561 | } |
562 | ||
563 | static int | |
b54a3392 | 564 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
7ee7b84d | 565 | { |
35a35807 AM |
566 | offsetT num; |
567 | ||
7ee7b84d MS |
568 | if (no_symbols |
569 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) | |
570 | return 0; | |
35a35807 | 571 | num = operand->exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
572 | switch (size) |
573 | { | |
574 | case L_2: | |
575 | return (num & ~3) == 0; | |
576 | case L_3: | |
577 | return (num & ~7) == 0; | |
578 | case L_3NZ: | |
579 | return num >= 1 && num < 8; | |
580 | case L_4: | |
581 | return (num & ~15) == 0; | |
582 | case L_5: | |
583 | return num >= 1 && num < 32; | |
584 | case L_8: | |
35a35807 AM |
585 | num = (num ^ 0x80000000) - 0x80000000; |
586 | return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; | |
7ee7b84d MS |
587 | case L_8U: |
588 | return (num & ~0xFF) == 0; | |
589 | case L_16: | |
35a35807 AM |
590 | num = (num ^ 0x80000000) - 0x80000000; |
591 | return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; | |
7ee7b84d MS |
592 | case L_16U: |
593 | return (num & ~0xFFFF) == 0; | |
594 | case L_32: | |
595 | return 1; | |
596 | default: | |
597 | abort (); | |
598 | } | |
599 | } | |
600 | ||
252b5132 | 601 | static void |
b54a3392 | 602 | get_operand (char **ptr, struct h8_op *op, int direction) |
252b5132 RH |
603 | { |
604 | char *src = *ptr; | |
605 | op_type mode; | |
606 | unsigned int num; | |
607 | unsigned int len; | |
608 | ||
7ee7b84d | 609 | op->mode = 0; |
252b5132 | 610 | |
3048287a NC |
611 | /* Check for '(' and ')' for instructions ldm and stm. */ |
612 | if (src[0] == '(' && src[8] == ')') | |
613 | ++ src; | |
614 | ||
252b5132 RH |
615 | /* Gross. Gross. ldm and stm have a format not easily handled |
616 | by get_operand. We deal with it explicitly here. */ | |
3739860c | 617 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
7ee7b84d MS |
618 | ISDIGIT (src[2]) && src[3] == '-' && |
619 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) | |
252b5132 RH |
620 | { |
621 | int low, high; | |
622 | ||
623 | low = src[2] - '0'; | |
624 | high = src[6] - '0'; | |
625 | ||
4892e510 NC |
626 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
627 | from Renesas for H8S and H8SX hardware manual. */ | |
628 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) | |
629 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) | |
630 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) | |
631 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) | |
632 | && !(low == 4 && (high == 5 || high == 6)) | |
b4f16abb | 633 | && !(low == 4 && high == 7 && SXmode) |
4892e510 NC |
634 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
635 | && !(low == 6 && high == 7 && SXmode)) | |
252b5132 RH |
636 | as_bad (_("Invalid register list for ldm/stm\n")); |
637 | ||
252b5132 RH |
638 | /* Even sicker. We encode two registers into op->reg. One |
639 | for the low register to save, the other for the high | |
640 | register to save; we also set the high bit in op->reg | |
641 | so we know this is "very special". */ | |
642 | op->reg = 0x80000000 | (high << 8) | low; | |
643 | op->mode = REG; | |
3048287a NC |
644 | if (src[7] == ')') |
645 | *ptr = src + 8; | |
646 | else | |
647 | *ptr = src + 7; | |
252b5132 RH |
648 | return; |
649 | } | |
650 | ||
651 | len = parse_reg (src, &op->mode, &op->reg, direction); | |
652 | if (len) | |
653 | { | |
7ee7b84d MS |
654 | src += len; |
655 | if (*src == '.') | |
656 | { | |
657 | int size = op->mode & SIZE; | |
658 | switch (src[1]) | |
659 | { | |
660 | case 'l': case 'L': | |
661 | if (size != L_32) | |
662 | as_warn (_("mismatch between register and suffix")); | |
663 | op->mode = (op->mode & ~MODE) | LOWREG; | |
664 | break; | |
665 | case 'w': case 'W': | |
666 | if (size != L_32 && size != L_16) | |
667 | as_warn (_("mismatch between register and suffix")); | |
668 | op->mode = (op->mode & ~MODE) | LOWREG; | |
669 | op->mode = (op->mode & ~SIZE) | L_16; | |
670 | break; | |
671 | case 'b': case 'B': | |
672 | op->mode = (op->mode & ~MODE) | LOWREG; | |
673 | if (size != L_32 && size != L_8) | |
674 | as_warn (_("mismatch between register and suffix")); | |
675 | op->mode = (op->mode & ~MODE) | LOWREG; | |
676 | op->mode = (op->mode & ~SIZE) | L_8; | |
677 | break; | |
678 | default: | |
20203fb9 | 679 | as_warn (_("invalid suffix after register.")); |
7ee7b84d MS |
680 | break; |
681 | } | |
682 | src += 2; | |
683 | } | |
684 | *ptr = src; | |
252b5132 RH |
685 | return; |
686 | } | |
687 | ||
688 | if (*src == '@') | |
689 | { | |
690 | src++; | |
691 | if (*src == '@') | |
692 | { | |
1b680e4f | 693 | *ptr = parse_exp (src + 1, op); |
7ee7b84d MS |
694 | if (op->exp.X_add_number >= 0x100) |
695 | { | |
d4e2de6b | 696 | int divisor = 1; |
7ee7b84d MS |
697 | |
698 | op->mode = VECIND; | |
699 | /* FIXME : 2? or 4? */ | |
700 | if (op->exp.X_add_number >= 0x400) | |
701 | as_bad (_("address too high for vector table jmp/jsr")); | |
702 | else if (op->exp.X_add_number >= 0x200) | |
703 | divisor = 4; | |
704 | else | |
705 | divisor = 2; | |
706 | ||
707 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; | |
708 | } | |
709 | else | |
710 | op->mode = MEMIND; | |
252b5132 | 711 | return; |
252b5132 RH |
712 | } |
713 | ||
7ee7b84d | 714 | if (*src == '-' || *src == '+') |
252b5132 | 715 | { |
1b680e4f | 716 | len = parse_reg (src + 1, &mode, &num, direction); |
252b5132 RH |
717 | if (len == 0) |
718 | { | |
70d6ecf3 | 719 | /* Oops, not a reg after all, must be ordinary exp. */ |
1b680e4f RS |
720 | op->mode = ABS | direction; |
721 | *ptr = parse_exp (src, op); | |
252b5132 | 722 | return; |
252b5132 RH |
723 | } |
724 | ||
d4e2de6b NC |
725 | if (((mode & SIZE) != PSIZE) |
726 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
727 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 728 | as_bad (_("Wrong size pointer register for architecture.")); |
1b680e4f RS |
729 | |
730 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; | |
252b5132 | 731 | op->reg = num; |
1b680e4f | 732 | *ptr = src + 1 + len; |
252b5132 RH |
733 | return; |
734 | } | |
735 | if (*src == '(') | |
736 | { | |
252b5132 RH |
737 | src++; |
738 | ||
7ee7b84d MS |
739 | /* See if this is @(ERn.x, PC). */ |
740 | len = parse_reg (src, &mode, &op->reg, direction); | |
741 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') | |
742 | { | |
743 | switch (TOLOWER (src[len + 1])) | |
744 | { | |
745 | case 'b': | |
746 | mode = PCIDXB | direction; | |
747 | break; | |
748 | case 'w': | |
749 | mode = PCIDXW | direction; | |
750 | break; | |
751 | case 'l': | |
752 | mode = PCIDXL | direction; | |
753 | break; | |
754 | default: | |
755 | mode = 0; | |
756 | break; | |
757 | } | |
758 | if (mode | |
759 | && src[len + 2] == ',' | |
3739860c | 760 | && TOLOWER (src[len + 3]) != 'p' |
7ee7b84d MS |
761 | && TOLOWER (src[len + 4]) != 'c' |
762 | && src[len + 5] != ')') | |
763 | { | |
764 | *ptr = src + len + 6; | |
765 | op->mode |= mode; | |
766 | return; | |
767 | } | |
768 | /* Fall through into disp case - the grammar is somewhat | |
769 | ambiguous, so we should try whether it's a DISP operand | |
770 | after all ("ER3.L" might be a poorly named label...). */ | |
771 | } | |
772 | ||
773 | /* Disp. */ | |
774 | ||
70d6ecf3 | 775 | /* Start off assuming a 16 bit offset. */ |
252b5132 | 776 | |
1b680e4f | 777 | src = parse_exp (src, op); |
252b5132 RH |
778 | if (*src == ')') |
779 | { | |
252b5132 | 780 | op->mode |= ABS | direction; |
1b680e4f | 781 | *ptr = src + 1; |
252b5132 RH |
782 | return; |
783 | } | |
784 | ||
785 | if (*src != ',') | |
786 | { | |
787 | as_bad (_("expected @(exp, reg16)")); | |
788 | return; | |
252b5132 RH |
789 | } |
790 | src++; | |
791 | ||
792 | len = parse_reg (src, &mode, &op->reg, direction); | |
7ee7b84d | 793 | if (len == 0 || (mode & MODE) != REG) |
252b5132 RH |
794 | { |
795 | as_bad (_("expected @(exp, reg16)")); | |
796 | return; | |
797 | } | |
252b5132 | 798 | src += len; |
7ee7b84d MS |
799 | if (src[0] == '.') |
800 | { | |
801 | switch (TOLOWER (src[1])) | |
802 | { | |
803 | case 'b': | |
804 | op->mode |= INDEXB | direction; | |
805 | break; | |
806 | case 'w': | |
807 | op->mode |= INDEXW | direction; | |
808 | break; | |
809 | case 'l': | |
810 | op->mode |= INDEXL | direction; | |
811 | break; | |
812 | default: | |
813 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); | |
814 | } | |
815 | src += 2; | |
816 | op->reg &= 7; | |
817 | } | |
818 | else | |
819 | op->mode |= DISP | direction; | |
1b680e4f | 820 | src = skip_colonthing (src, &op->mode); |
252b5132 | 821 | |
8a4c2869 | 822 | if (*src != ')') |
252b5132 RH |
823 | { |
824 | as_bad (_("expected @(exp, reg16)")); | |
825 | return; | |
826 | } | |
827 | *ptr = src + 1; | |
252b5132 RH |
828 | return; |
829 | } | |
830 | len = parse_reg (src, &mode, &num, direction); | |
831 | ||
832 | if (len) | |
833 | { | |
834 | src += len; | |
7ee7b84d | 835 | if (*src == '+' || *src == '-') |
252b5132 | 836 | { |
d4e2de6b NC |
837 | if (((mode & SIZE) != PSIZE) |
838 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
839 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 | 840 | as_bad (_("Wrong size pointer register for architecture.")); |
7ee7b84d | 841 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
252b5132 | 842 | op->reg = num; |
7ee7b84d | 843 | src++; |
252b5132 RH |
844 | *ptr = src; |
845 | return; | |
846 | } | |
d4e2de6b NC |
847 | if (((mode & SIZE) != PSIZE) |
848 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ | |
849 | && (!Nmode || ((mode & SIZE) != L_32))) | |
252b5132 RH |
850 | as_bad (_("Wrong size pointer register for architecture.")); |
851 | ||
852 | op->mode = direction | IND | PSIZE; | |
853 | op->reg = num; | |
854 | *ptr = src; | |
855 | ||
856 | return; | |
857 | } | |
858 | else | |
859 | { | |
860 | /* must be a symbol */ | |
861 | ||
862 | op->mode = ABS | direction; | |
1b680e4f | 863 | *ptr = parse_exp (src, op); |
252b5132 RH |
864 | return; |
865 | } | |
866 | } | |
867 | ||
252b5132 RH |
868 | if (*src == '#') |
869 | { | |
252b5132 | 870 | op->mode = IMM; |
1b680e4f | 871 | *ptr = parse_exp (src + 1, op); |
252b5132 RH |
872 | return; |
873 | } | |
d34049e8 ML |
874 | else if (startswith (src, "mach") || |
875 | startswith (src, "macl") || | |
876 | startswith (src, "MACH") || | |
877 | startswith (src, "MACL")) | |
252b5132 | 878 | { |
7ee7b84d | 879 | op->reg = TOLOWER (src[3]) == 'l'; |
252b5132 RH |
880 | op->mode = MACREG; |
881 | *ptr = src + 4; | |
882 | return; | |
883 | } | |
884 | else | |
885 | { | |
1b680e4f RS |
886 | op->mode = PCREL; |
887 | *ptr = parse_exp (src, op); | |
252b5132 RH |
888 | } |
889 | } | |
890 | ||
70d6ecf3 | 891 | static char * |
b54a3392 | 892 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
252b5132 RH |
893 | { |
894 | char *ptr = op_end; | |
895 | ||
896 | switch (noperands) | |
897 | { | |
898 | case 0: | |
252b5132 RH |
899 | break; |
900 | ||
901 | case 1: | |
902 | ptr++; | |
7ee7b84d | 903 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
904 | if (*ptr == ',') |
905 | { | |
906 | ptr++; | |
7ee7b84d | 907 | get_operand (&ptr, operand + 1, DST); |
252b5132 | 908 | } |
252b5132 | 909 | break; |
70d6ecf3 | 910 | |
252b5132 RH |
911 | case 2: |
912 | ptr++; | |
7ee7b84d | 913 | get_operand (&ptr, operand + 0, SRC); |
252b5132 RH |
914 | if (*ptr == ',') |
915 | ptr++; | |
7ee7b84d MS |
916 | get_operand (&ptr, operand + 1, DST); |
917 | break; | |
918 | ||
919 | case 3: | |
920 | ptr++; | |
921 | get_operand (&ptr, operand + 0, SRC); | |
922 | if (*ptr == ',') | |
923 | ptr++; | |
924 | get_operand (&ptr, operand + 1, DST); | |
925 | if (*ptr == ',') | |
926 | ptr++; | |
927 | get_operand (&ptr, operand + 2, OP3); | |
252b5132 RH |
928 | break; |
929 | ||
930 | default: | |
931 | abort (); | |
932 | } | |
933 | ||
252b5132 RH |
934 | return ptr; |
935 | } | |
936 | ||
7ee7b84d MS |
937 | /* MOVA has special requirements. Rather than adding twice the amount of |
938 | addressing modes, we simply special case it a bit. */ | |
939 | static void | |
940 | get_mova_operands (char *op_end, struct h8_op *operand) | |
941 | { | |
942 | char *ptr = op_end; | |
943 | ||
944 | if (ptr[1] != '@' || ptr[2] != '(') | |
945 | goto error; | |
946 | ptr += 3; | |
947 | operand[0].mode = 0; | |
1b680e4f | 948 | ptr = parse_exp (ptr, &operand[0]); |
7ee7b84d MS |
949 | |
950 | if (*ptr !=',') | |
951 | goto error; | |
952 | ptr++; | |
953 | get_operand (&ptr, operand + 1, DST); | |
954 | ||
955 | if (*ptr =='.') | |
956 | { | |
957 | ptr++; | |
958 | switch (*ptr++) | |
959 | { | |
960 | case 'b': case 'B': | |
961 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
962 | break; | |
963 | case 'w': case 'W': | |
964 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
965 | break; | |
966 | case 'l': case 'L': | |
967 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
968 | break; | |
969 | default: | |
970 | goto error; | |
971 | } | |
972 | } | |
973 | else if ((operand[1].mode & MODE) == LOWREG) | |
974 | { | |
3739860c | 975 | switch (operand[1].mode & SIZE) |
7ee7b84d MS |
976 | { |
977 | case L_8: | |
978 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; | |
979 | break; | |
980 | case L_16: | |
981 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; | |
982 | break; | |
983 | case L_32: | |
984 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; | |
985 | break; | |
986 | default: | |
987 | goto error; | |
988 | } | |
989 | } | |
990 | else | |
991 | goto error; | |
992 | ||
993 | if (*ptr++ != ')' || *ptr++ != ',') | |
994 | goto error; | |
995 | get_operand (&ptr, operand + 2, OP3); | |
996 | /* See if we can use the short form of MOVA. */ | |
997 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) | |
998 | && (operand[2].mode & MODE) == REG | |
999 | && (operand[1].reg & 7) == (operand[2].reg & 7)) | |
1000 | { | |
1001 | operand[1].mode = operand[2].mode = 0; | |
1002 | operand[0].reg = operand[2].reg & 7; | |
1003 | } | |
1004 | return; | |
1005 | ||
1006 | error: | |
1007 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); | |
7ee7b84d MS |
1008 | } |
1009 | ||
1010 | static void | |
1011 | get_rtsl_operands (char *ptr, struct h8_op *operand) | |
1012 | { | |
2132e3a3 AM |
1013 | int mode, len, type = 0; |
1014 | unsigned int num, num2; | |
7ee7b84d MS |
1015 | |
1016 | ptr++; | |
1017 | if (*ptr == '(') | |
1018 | { | |
1019 | ptr++; | |
1020 | type = 1; | |
1021 | } | |
1022 | len = parse_reg (ptr, &mode, &num, SRC); | |
1023 | if (len == 0 || (mode & MODE) != REG) | |
1024 | { | |
1025 | as_bad (_("expected register")); | |
1026 | return; | |
1027 | } | |
0613284f RS |
1028 | ptr += len; |
1029 | if (*ptr == '-') | |
7ee7b84d | 1030 | { |
0613284f | 1031 | len = parse_reg (++ptr, &mode, &num2, SRC); |
7ee7b84d MS |
1032 | if (len == 0 || (mode & MODE) != REG) |
1033 | { | |
1034 | as_bad (_("expected register")); | |
1035 | return; | |
1036 | } | |
1037 | ptr += len; | |
7ee7b84d MS |
1038 | /* CONST_xxx are used as placeholders in the opcode table. */ |
1039 | num = num2 - num; | |
2132e3a3 | 1040 | if (num > 3) |
7ee7b84d MS |
1041 | { |
1042 | as_bad (_("invalid register list")); | |
1043 | return; | |
1044 | } | |
1045 | } | |
1046 | else | |
1047 | num2 = num, num = 0; | |
0613284f RS |
1048 | if (type == 1 && *ptr++ != ')') |
1049 | { | |
1050 | as_bad (_("expected closing paren")); | |
1051 | return; | |
1052 | } | |
7ee7b84d MS |
1053 | operand[0].mode = RS32; |
1054 | operand[1].mode = RD32; | |
1055 | operand[0].reg = num; | |
1056 | operand[1].reg = num2; | |
1057 | } | |
1058 | ||
252b5132 RH |
1059 | /* Passed a pointer to a list of opcodes which use different |
1060 | addressing modes, return the opcode which matches the opcodes | |
70d6ecf3 | 1061 | provided. */ |
3048287a | 1062 | |
a720f7bc | 1063 | static const struct h8_instruction * |
b54a3392 KH |
1064 | get_specific (const struct h8_instruction *instruction, |
1065 | struct h8_op *operands, int size) | |
252b5132 | 1066 | { |
a720f7bc | 1067 | const struct h8_instruction *this_try = instruction; |
7ee7b84d | 1068 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
252b5132 | 1069 | int found = 0; |
a720f7bc | 1070 | int this_index = instruction->idx; |
7ee7b84d | 1071 | int noperands = 0; |
252b5132 RH |
1072 | |
1073 | /* There's only one ldm/stm and it's easier to just | |
1074 | get out quick for them. */ | |
7ee7b84d MS |
1075 | if (OP_KIND (instruction->opcode->how) == O_LDM |
1076 | || OP_KIND (instruction->opcode->how) == O_STM) | |
252b5132 RH |
1077 | return this_try; |
1078 | ||
7ee7b84d MS |
1079 | while (noperands < 3 && operands[noperands].mode != 0) |
1080 | noperands++; | |
1081 | ||
a720f7bc | 1082 | while (this_index == instruction->idx && !found) |
252b5132 | 1083 | { |
7ee7b84d | 1084 | int this_size; |
252b5132 | 1085 | |
7ee7b84d | 1086 | found = 1; |
a720f7bc | 1087 | this_try = instruction++; |
7ee7b84d | 1088 | this_size = this_try->opcode->how & SN; |
252b5132 | 1089 | |
7ee7b84d MS |
1090 | if (this_try->noperands != noperands) |
1091 | found = 0; | |
1092 | else if (this_try->noperands > 0) | |
252b5132 | 1093 | { |
3048287a | 1094 | int i; |
252b5132 RH |
1095 | |
1096 | for (i = 0; i < this_try->noperands && found; i++) | |
1097 | { | |
a720f7bc | 1098 | op_type op = this_try->opcode->args.nib[i]; |
7ee7b84d MS |
1099 | int op_mode = op & MODE; |
1100 | int op_size = op & SIZE; | |
252b5132 | 1101 | int x = operands[i].mode; |
7ee7b84d MS |
1102 | int x_mode = x & MODE; |
1103 | int x_size = x & SIZE; | |
252b5132 | 1104 | |
7ee7b84d | 1105 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
252b5132 | 1106 | { |
7ee7b84d MS |
1107 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
1108 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) | |
1109 | as_warn (_("can't use high part of register in operand %d"), i); | |
1110 | ||
1111 | if (x_size != op_size) | |
1112 | found = 0; | |
252b5132 | 1113 | } |
7ee7b84d | 1114 | else if (op_mode == REG) |
252b5132 | 1115 | { |
7ee7b84d MS |
1116 | if (x_mode == LOWREG) |
1117 | x_mode = REG; | |
1118 | if (x_mode != REG) | |
252b5132 RH |
1119 | found = 0; |
1120 | ||
7ee7b84d MS |
1121 | if (x_size == L_P) |
1122 | x_size = (Hmode ? L_32 : L_16); | |
1123 | if (op_size == L_P) | |
1124 | op_size = (Hmode ? L_32 : L_16); | |
252b5132 | 1125 | |
70d6ecf3 | 1126 | /* The size of the reg is v important. */ |
7ee7b84d | 1127 | if (op_size != x_size) |
252b5132 RH |
1128 | found = 0; |
1129 | } | |
7ee7b84d | 1130 | else if (op_mode & CTRL) /* control register */ |
252b5132 | 1131 | { |
7ee7b84d MS |
1132 | if (!(x_mode & CTRL)) |
1133 | found = 0; | |
1134 | ||
1135 | switch (x_mode) | |
1136 | { | |
1137 | case CCR: | |
1138 | if (op_mode != CCR && | |
1139 | op_mode != CCR_EXR && | |
1140 | op_mode != CC_EX_VB_SB) | |
1141 | found = 0; | |
1142 | break; | |
1143 | case EXR: | |
1144 | if (op_mode != EXR && | |
1145 | op_mode != CCR_EXR && | |
1146 | op_mode != CC_EX_VB_SB) | |
1147 | found = 0; | |
1148 | break; | |
1149 | case MACH: | |
1150 | if (op_mode != MACH && | |
1151 | op_mode != MACREG) | |
1152 | found = 0; | |
1153 | break; | |
1154 | case MACL: | |
1155 | if (op_mode != MACL && | |
1156 | op_mode != MACREG) | |
1157 | found = 0; | |
1158 | break; | |
1159 | case VBR: | |
1160 | if (op_mode != VBR && | |
1161 | op_mode != VBR_SBR && | |
1162 | op_mode != CC_EX_VB_SB) | |
1163 | found = 0; | |
1164 | break; | |
1165 | case SBR: | |
1166 | if (op_mode != SBR && | |
1167 | op_mode != VBR_SBR && | |
1168 | op_mode != CC_EX_VB_SB) | |
1169 | found = 0; | |
1170 | break; | |
1171 | } | |
1172 | } | |
1173 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) | |
1174 | { | |
1175 | operands[i].mode &= ~MODE; | |
252b5132 | 1176 | operands[i].mode |= ABSJMP; |
70d6ecf3 | 1177 | /* But it may not be 24 bits long. */ |
7ee7b84d | 1178 | if (x_mode == ABS && !Hmode) |
252b5132 RH |
1179 | { |
1180 | operands[i].mode &= ~SIZE; | |
1181 | operands[i].mode |= L_16; | |
1182 | } | |
7ee7b84d MS |
1183 | if ((operands[i].mode & SIZE) == L_32 |
1184 | && (op_mode & SIZE) != L_32) | |
1185 | found = 0; | |
252b5132 | 1186 | } |
7ee7b84d | 1187 | else if (x_mode == IMM && op_mode != IMM) |
252b5132 | 1188 | { |
35a35807 | 1189 | offsetT num = operands[i].exp.X_add_number & 0xffffffff; |
7ee7b84d MS |
1190 | if (op_mode == KBIT || op_mode == DBIT) |
1191 | /* This is ok if the immediate value is sensible. */; | |
1192 | else if (op_mode == CONST_2) | |
1193 | found = num == 2; | |
1194 | else if (op_mode == CONST_4) | |
1195 | found = num == 4; | |
1196 | else if (op_mode == CONST_8) | |
1197 | found = num == 8; | |
1198 | else if (op_mode == CONST_16) | |
1199 | found = num == 16; | |
1200 | else | |
1201 | found = 0; | |
252b5132 | 1202 | } |
7ee7b84d | 1203 | else if (op_mode == PCREL && op_mode == x_mode) |
252b5132 | 1204 | { |
ba18dd6f | 1205 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
7ee7b84d | 1206 | If x_size is L_8, promote it. */ |
ba18dd6f AO |
1207 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
1208 | || OP_KIND (this_try->opcode->how) == O_BSRBC | |
1209 | || OP_KIND (this_try->opcode->how) == O_BSRBS) | |
7ee7b84d MS |
1210 | if (x_size == L_8) |
1211 | x_size = L_16; | |
1212 | ||
70d6ecf3 | 1213 | /* The size of the displacement is important. */ |
7ee7b84d | 1214 | if (op_size != x_size) |
252b5132 RH |
1215 | found = 0; |
1216 | } | |
7ee7b84d MS |
1217 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
1218 | || op_mode == INDEXB || op_mode == INDEXW | |
1219 | || op_mode == INDEXL) | |
1220 | && op_mode == x_mode) | |
252b5132 RH |
1221 | { |
1222 | /* Promote a L_24 to L_32 if it makes us match. */ | |
7ee7b84d | 1223 | if (x_size == L_24 && op_size == L_32) |
252b5132 | 1224 | { |
7ee7b84d MS |
1225 | x &= ~SIZE; |
1226 | x |= x_size = L_32; | |
252b5132 | 1227 | } |
7ee7b84d | 1228 | |
7ee7b84d | 1229 | if (((x_size == L_16 && op_size == L_16U) |
2d0d09ca | 1230 | || (x_size == L_8 && op_size == L_8U) |
7ee7b84d MS |
1231 | || (x_size == L_3 && op_size == L_3NZ)) |
1232 | /* We're deliberately more permissive for ABS modes. */ | |
1233 | && (op_mode == ABS | |
1234 | || constant_fits_size_p (operands + i, op_size, | |
1235 | op & NO_SYMBOLS))) | |
1236 | x_size = op_size; | |
1237 | ||
1238 | if (x_size != 0 && op_size != x_size) | |
1239 | found = 0; | |
1240 | else if (x_size == 0 | |
1241 | && ! constant_fits_size_p (operands + i, op_size, | |
1242 | op & NO_SYMBOLS)) | |
252b5132 RH |
1243 | found = 0; |
1244 | } | |
7ee7b84d | 1245 | else if (op_mode != x_mode) |
252b5132 RH |
1246 | { |
1247 | found = 0; | |
70d6ecf3 | 1248 | } |
252b5132 RH |
1249 | } |
1250 | } | |
7ee7b84d MS |
1251 | if (found) |
1252 | { | |
1253 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) | |
d4ea8842 | 1254 | || (this_try->opcode->available == AV_H8S && ! Smode) |
7ee7b84d MS |
1255 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
1256 | found = 0, found_other = this_try; | |
1257 | else if (this_size != size && (this_size != SN && size != SN)) | |
1258 | found_mismatched = this_try, found = 0; | |
1259 | ||
1260 | } | |
252b5132 RH |
1261 | } |
1262 | if (found) | |
1263 | return this_try; | |
7ee7b84d MS |
1264 | if (found_other) |
1265 | { | |
1266 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), | |
1267 | found_other->opcode->name, | |
1268 | (! Hmode && ! Smode ? "H8/300" | |
1269 | : SXmode ? "H8sx" | |
1270 | : Smode ? "H8/300S" | |
1271 | : "H8/300H")); | |
1272 | } | |
1273 | else if (found_mismatched) | |
1274 | { | |
1275 | as_warn (_("mismatch between opcode size and operand size")); | |
1276 | return found_mismatched; | |
1277 | } | |
1278 | return 0; | |
252b5132 RH |
1279 | } |
1280 | ||
1281 | static void | |
e0471c16 | 1282 | check_operand (struct h8_op *operand, unsigned int width, const char *string) |
252b5132 RH |
1283 | { |
1284 | if (operand->exp.X_add_symbol == 0 | |
1285 | && operand->exp.X_op_symbol == 0) | |
1286 | { | |
70d6ecf3 AM |
1287 | /* No symbol involved, let's look at offset, it's dangerous if |
1288 | any of the high bits are not 0 or ff's, find out by oring or | |
1289 | anding with the width and seeing if the answer is 0 or all | |
1290 | fs. */ | |
252b5132 | 1291 | |
7ee7b84d | 1292 | if (! constant_fits_width_p (operand, width)) |
252b5132 | 1293 | { |
70d6ecf3 | 1294 | if (width == 255 |
252b5132 RH |
1295 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
1296 | { | |
1297 | /* Just ignore this one - which happens when trying to | |
1298 | fit a 16 bit address truncated into an 8 bit address | |
1299 | of something like bset. */ | |
1300 | } | |
166e23f9 KH |
1301 | else if (strcmp (string, "@") == 0 |
1302 | && width == 0xffff | |
1303 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) | |
1304 | { | |
1305 | /* Just ignore this one - which happens when trying to | |
1306 | fit a 24 bit address truncated into a 16 bit address | |
1307 | of something like mov.w. */ | |
1308 | } | |
70d6ecf3 | 1309 | else |
252b5132 RH |
1310 | { |
1311 | as_warn (_("operand %s0x%lx out of range."), string, | |
1312 | (unsigned long) operand->exp.X_add_number); | |
1313 | } | |
1314 | } | |
1315 | } | |
252b5132 RH |
1316 | } |
1317 | ||
1318 | /* RELAXMODE has one of 3 values: | |
1319 | ||
1320 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc | |
1321 | ||
1322 | 1 Output a relaxable 24bit absolute mov.w address relocation | |
1323 | (may relax into a 16bit absolute address). | |
1324 | ||
1325 | 2 Output a relaxable 16/24 absolute mov.b address relocation | |
1326 | (may relax into an 8bit absolute address). */ | |
1327 | ||
1328 | static void | |
bcb012d3 | 1329 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
252b5132 RH |
1330 | { |
1331 | int idx; | |
1332 | int size; | |
1333 | int where; | |
7ee7b84d | 1334 | char *bytes = frag_now->fr_literal + offset; |
252b5132 | 1335 | |
e0471c16 | 1336 | const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
252b5132 RH |
1337 | |
1338 | if (operand->exp.X_add_symbol == 0) | |
1339 | { | |
252b5132 RH |
1340 | switch (operand->mode & SIZE) |
1341 | { | |
1342 | case L_2: | |
1343 | check_operand (operand, 0x3, t); | |
7ee7b84d | 1344 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
252b5132 RH |
1345 | break; |
1346 | case L_3: | |
7ee7b84d | 1347 | case L_3NZ: |
252b5132 | 1348 | check_operand (operand, 0x7, t); |
7ee7b84d MS |
1349 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
1350 | break; | |
1351 | case L_4: | |
1352 | check_operand (operand, 0xF, t); | |
1353 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); | |
1354 | break; | |
1355 | case L_5: | |
1356 | check_operand (operand, 0x1F, t); | |
1357 | bytes[0] |= operand->exp.X_add_number & 31; | |
252b5132 RH |
1358 | break; |
1359 | case L_8: | |
7ee7b84d | 1360 | case L_8U: |
252b5132 | 1361 | check_operand (operand, 0xff, t); |
7ee7b84d | 1362 | bytes[0] |= operand->exp.X_add_number; |
252b5132 RH |
1363 | break; |
1364 | case L_16: | |
7ee7b84d | 1365 | case L_16U: |
252b5132 | 1366 | check_operand (operand, 0xffff, t); |
7ee7b84d MS |
1367 | bytes[0] |= operand->exp.X_add_number >> 8; |
1368 | bytes[1] |= operand->exp.X_add_number >> 0; | |
bcb012d3 DD |
1369 | /* MOVA needs both relocs to relax the second operand properly. */ |
1370 | if (relaxmode != 0 | |
1371 | && (OP_KIND(this_try->opcode->how) == O_MOVAB | |
1372 | || OP_KIND(this_try->opcode->how) == O_MOVAW | |
1373 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) | |
1374 | { | |
1375 | idx = BFD_RELOC_16; | |
1376 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); | |
1377 | } | |
252b5132 RH |
1378 | break; |
1379 | case L_24: | |
1380 | check_operand (operand, 0xffffff, t); | |
7ee7b84d MS |
1381 | bytes[0] |= operand->exp.X_add_number >> 16; |
1382 | bytes[1] |= operand->exp.X_add_number >> 8; | |
1383 | bytes[2] |= operand->exp.X_add_number >> 0; | |
252b5132 RH |
1384 | break; |
1385 | ||
1386 | case L_32: | |
70d6ecf3 | 1387 | /* This should be done with bfd. */ |
7ee7b84d MS |
1388 | bytes[0] |= operand->exp.X_add_number >> 24; |
1389 | bytes[1] |= operand->exp.X_add_number >> 16; | |
1390 | bytes[2] |= operand->exp.X_add_number >> 8; | |
1391 | bytes[3] |= operand->exp.X_add_number >> 0; | |
4132022d AM |
1392 | if (relaxmode != 0) |
1393 | { | |
81f5558e NC |
1394 | if ((operand->mode & MODE) == DISP && relaxmode == 1) |
1395 | idx = BFD_RELOC_H8_DISP32A16; | |
1396 | else | |
81f5558e | 1397 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; |
4132022d AM |
1398 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); |
1399 | } | |
252b5132 RH |
1400 | break; |
1401 | } | |
252b5132 RH |
1402 | } |
1403 | else | |
1404 | { | |
1405 | switch (operand->mode & SIZE) | |
1406 | { | |
252b5132 RH |
1407 | case L_24: |
1408 | case L_32: | |
1409 | size = 4; | |
1410 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; | |
81f5558e NC |
1411 | if ((operand->mode & MODE) == DISP && relaxmode == 1) |
1412 | idx = BFD_RELOC_H8_DISP32A16; | |
fe0bf0fd | 1413 | else if (relaxmode == 2) |
252b5132 RH |
1414 | idx = R_MOV24B1; |
1415 | else if (relaxmode == 1) | |
1416 | idx = R_MOVL1; | |
1417 | else | |
1418 | idx = R_RELLONG; | |
1419 | break; | |
1420 | default: | |
70d6ecf3 | 1421 | as_bad (_("Can't work out size of operand.\n")); |
1a0670f3 | 1422 | /* Fall through. */ |
252b5132 | 1423 | case L_16: |
7ee7b84d | 1424 | case L_16U: |
252b5132 RH |
1425 | size = 2; |
1426 | where = 0; | |
1427 | if (relaxmode == 2) | |
1428 | idx = R_MOV16B1; | |
1429 | else | |
1430 | idx = R_RELWORD; | |
4132022d AM |
1431 | operand->exp.X_add_number = |
1432 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
7ee7b84d | 1433 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
252b5132 RH |
1434 | break; |
1435 | case L_8: | |
1436 | size = 1; | |
1437 | where = 0; | |
1438 | idx = R_RELBYTE; | |
4132022d AM |
1439 | operand->exp.X_add_number = |
1440 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
7ee7b84d | 1441 | operand->exp.X_add_number |= bytes[0]; |
252b5132 RH |
1442 | } |
1443 | ||
1444 | fix_new_exp (frag_now, | |
1445 | offset + where, | |
1446 | size, | |
1447 | &operand->exp, | |
1448 | 0, | |
1449 | idx); | |
1450 | } | |
252b5132 RH |
1451 | } |
1452 | ||
70d6ecf3 | 1453 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
3048287a | 1454 | |
252b5132 | 1455 | static void |
b54a3392 | 1456 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
252b5132 | 1457 | { |
3048287a | 1458 | int i; |
252b5132 | 1459 | char *output = frag_more (this_try->length); |
d1e50f8a | 1460 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
252b5132 RH |
1461 | op_type c; |
1462 | unsigned int nibble_count = 0; | |
7ee7b84d | 1463 | int op_at[3]; |
3048287a | 1464 | int nib = 0; |
252b5132 | 1465 | int movb = 0; |
7ee7b84d | 1466 | char asnibbles[100]; |
252b5132 | 1467 | char *p = asnibbles; |
7ee7b84d | 1468 | int high, low; |
252b5132 | 1469 | |
d4ea8842 | 1470 | if (!Hmode && this_try->opcode->available != AV_H8) |
252b5132 | 1471 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
a720f7bc | 1472 | this_try->opcode->name); |
3739860c L |
1473 | else if (!Smode |
1474 | && this_try->opcode->available != AV_H8 | |
d4ea8842 MS |
1475 | && this_try->opcode->available != AV_H8H) |
1476 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), | |
1477 | this_try->opcode->name); | |
3739860c | 1478 | else if (!SXmode |
d4ea8842 MS |
1479 | && this_try->opcode->available != AV_H8 |
1480 | && this_try->opcode->available != AV_H8H | |
1481 | && this_try->opcode->available != AV_H8S) | |
1482 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), | |
1483 | this_try->opcode->name); | |
252b5132 | 1484 | |
7ee7b84d | 1485 | while (*nibble_ptr != (op_type) E) |
252b5132 RH |
1486 | { |
1487 | int d; | |
7ee7b84d MS |
1488 | |
1489 | nib = 0; | |
252b5132 RH |
1490 | c = *nibble_ptr++; |
1491 | ||
7ee7b84d | 1492 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
252b5132 RH |
1493 | |
1494 | if (c < 16) | |
3048287a | 1495 | nib = c; |
252b5132 RH |
1496 | else |
1497 | { | |
7ee7b84d MS |
1498 | int c2 = c & MODE; |
1499 | ||
1500 | if (c2 == REG || c2 == LOWREG | |
1501 | || c2 == IND || c2 == PREINC || c2 == PREDEC | |
1502 | || c2 == POSTINC || c2 == POSTDEC) | |
1503 | { | |
1504 | nib = operand[d].reg; | |
1505 | if (c2 == LOWREG) | |
1506 | nib &= 7; | |
1507 | } | |
1508 | ||
1509 | else if (c & CTRL) /* Control reg operand. */ | |
3048287a NC |
1510 | nib = operand[d].reg; |
1511 | ||
252b5132 | 1512 | else if ((c & DISPREG) == (DISPREG)) |
7ee7b84d MS |
1513 | { |
1514 | nib = operand[d].reg; | |
1515 | } | |
1516 | else if (c2 == ABS) | |
252b5132 RH |
1517 | { |
1518 | operand[d].mode = c; | |
7ee7b84d | 1519 | op_at[d] = nibble_count; |
252b5132 RH |
1520 | nib = 0; |
1521 | } | |
7ee7b84d MS |
1522 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
1523 | || (c & ABSJMP) || c2 == DISP) | |
252b5132 RH |
1524 | { |
1525 | operand[d].mode = c; | |
7ee7b84d | 1526 | op_at[d] = nibble_count; |
252b5132 RH |
1527 | nib = 0; |
1528 | } | |
7ee7b84d | 1529 | else if ((c & IGNORE) || (c & DATA)) |
3048287a NC |
1530 | nib = 0; |
1531 | ||
7ee7b84d | 1532 | else if (c2 == DBIT) |
252b5132 RH |
1533 | { |
1534 | switch (operand[0].exp.X_add_number) | |
1535 | { | |
1536 | case 1: | |
1537 | nib = c; | |
1538 | break; | |
1539 | case 2: | |
1540 | nib = 0x8 | c; | |
1541 | break; | |
1542 | default: | |
1543 | as_bad (_("Need #1 or #2 here")); | |
1544 | } | |
1545 | } | |
7ee7b84d | 1546 | else if (c2 == KBIT) |
252b5132 RH |
1547 | { |
1548 | switch (operand[0].exp.X_add_number) | |
1549 | { | |
1550 | case 1: | |
1551 | nib = 0; | |
1552 | break; | |
1553 | case 2: | |
1554 | nib = 8; | |
1555 | break; | |
1556 | case 4: | |
1557 | if (!Hmode) | |
1558 | as_warn (_("#4 not valid on H8/300.")); | |
1559 | nib = 9; | |
1560 | break; | |
1561 | ||
1562 | default: | |
1563 | as_bad (_("Need #1 or #2 here")); | |
1564 | break; | |
1565 | } | |
70d6ecf3 | 1566 | /* Stop it making a fix. */ |
252b5132 RH |
1567 | operand[0].mode = 0; |
1568 | } | |
1569 | ||
1570 | if (c & MEMRELAX) | |
3048287a | 1571 | operand[d].mode |= MEMRELAX; |
252b5132 RH |
1572 | |
1573 | if (c & B31) | |
3048287a | 1574 | nib |= 0x8; |
252b5132 | 1575 | |
7ee7b84d MS |
1576 | if (c & B21) |
1577 | nib |= 0x4; | |
1578 | ||
1579 | if (c & B11) | |
1580 | nib |= 0x2; | |
1581 | ||
1582 | if (c & B01) | |
1583 | nib |= 0x1; | |
1584 | ||
1585 | if (c2 == MACREG) | |
252b5132 | 1586 | { |
f0c56b90 NC |
1587 | if (operand[0].mode == MACREG) |
1588 | /* stmac has mac[hl] as the first operand. */ | |
1589 | nib = 2 + operand[0].reg; | |
1590 | else | |
1591 | /* ldmac has mac[hl] as the second operand. */ | |
1592 | nib = 2 + operand[1].reg; | |
252b5132 RH |
1593 | } |
1594 | } | |
1595 | nibble_count++; | |
1596 | ||
1597 | *p++ = nib; | |
1598 | } | |
1599 | ||
1600 | /* Disgusting. Why, oh why didn't someone ask us for advice | |
1601 | on the assembler format. */ | |
7ee7b84d | 1602 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
252b5132 | 1603 | { |
7ee7b84d MS |
1604 | high = (operand[1].reg >> 8) & 0xf; |
1605 | low = (operand[1].reg) & 0xf; | |
252b5132 | 1606 | asnibbles[2] = high - low; |
7ee7b84d MS |
1607 | asnibbles[7] = high; |
1608 | } | |
1609 | else if (OP_KIND (this_try->opcode->how) == O_STM) | |
1610 | { | |
1611 | high = (operand[0].reg >> 8) & 0xf; | |
1612 | low = (operand[0].reg) & 0xf; | |
1613 | asnibbles[2] = high - low; | |
1614 | asnibbles[7] = low; | |
252b5132 RH |
1615 | } |
1616 | ||
1617 | for (i = 0; i < this_try->length; i++) | |
3048287a | 1618 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
252b5132 | 1619 | |
81f5558e | 1620 | /* Note if this is a mov.b or a bit manipulation instruction |
ca9a79a1 NC |
1621 | there is a special relaxation which only applies. */ |
1622 | if ( this_try->opcode->how == O (O_MOV, SB) | |
1623 | || this_try->opcode->how == O (O_BCLR, SB) | |
1624 | || this_try->opcode->how == O (O_BAND, SB) | |
1625 | || this_try->opcode->how == O (O_BIAND, SB) | |
1626 | || this_try->opcode->how == O (O_BILD, SB) | |
1627 | || this_try->opcode->how == O (O_BIOR, SB) | |
1628 | || this_try->opcode->how == O (O_BIST, SB) | |
1629 | || this_try->opcode->how == O (O_BIXOR, SB) | |
1630 | || this_try->opcode->how == O (O_BLD, SB) | |
1631 | || this_try->opcode->how == O (O_BNOT, SB) | |
1632 | || this_try->opcode->how == O (O_BOR, SB) | |
1633 | || this_try->opcode->how == O (O_BSET, SB) | |
1634 | || this_try->opcode->how == O (O_BST, SB) | |
1635 | || this_try->opcode->how == O (O_BTST, SB) | |
1636 | || this_try->opcode->how == O (O_BXOR, SB)) | |
252b5132 RH |
1637 | movb = 1; |
1638 | ||
70d6ecf3 | 1639 | /* Output any fixes. */ |
7ee7b84d | 1640 | for (i = 0; i < this_try->noperands; i++) |
252b5132 RH |
1641 | { |
1642 | int x = operand[i].mode; | |
7ee7b84d | 1643 | int x_mode = x & MODE; |
252b5132 | 1644 | |
7ee7b84d | 1645 | if (x_mode == IMM || x_mode == DISP) |
fe0bf0fd AM |
1646 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, |
1647 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, | |
1648 | this_try); | |
7ee7b84d MS |
1649 | else if (x_mode == ABS) |
1650 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, | |
1651 | op_at[i] & 1, operand + i, | |
bcb012d3 DD |
1652 | (x & MEMRELAX) ? movb + 1 : 0, |
1653 | this_try); | |
3048287a | 1654 | |
7ee7b84d | 1655 | else if (x_mode == PCREL) |
252b5132 | 1656 | { |
7ee7b84d | 1657 | int size16 = (x & SIZE) == L_16; |
252b5132 RH |
1658 | int size = size16 ? 2 : 1; |
1659 | int type = size16 ? R_PCRWORD : R_PCRBYTE; | |
36ed2fff | 1660 | fixS *fixP; |
252b5132 RH |
1661 | |
1662 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); | |
1663 | ||
1664 | if (operand[i].exp.X_add_number & 1) | |
3048287a NC |
1665 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1666 | (unsigned long) operand->exp.X_add_number); | |
7ee7b84d MS |
1667 | if (size16) |
1668 | { | |
1669 | operand[i].exp.X_add_number = | |
1670 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; | |
1671 | } | |
1672 | else | |
1673 | { | |
1674 | operand[i].exp.X_add_number = | |
1675 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; | |
1676 | } | |
1677 | ||
1678 | /* For BRA/S. */ | |
1679 | if (! size16) | |
1680 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; | |
252b5132 | 1681 | |
36ed2fff | 1682 | fixP = fix_new_exp (frag_now, |
7ee7b84d | 1683 | output - frag_now->fr_literal + op_at[i] / 2, |
36ed2fff JL |
1684 | size, |
1685 | &operand[i].exp, | |
1686 | 1, | |
1687 | type); | |
1688 | fixP->fx_signed = 1; | |
252b5132 | 1689 | } |
7ee7b84d | 1690 | else if (x_mode == MEMIND) |
252b5132 | 1691 | { |
252b5132 RH |
1692 | check_operand (operand + i, 0xff, "@@"); |
1693 | fix_new_exp (frag_now, | |
1694 | output - frag_now->fr_literal + 1, | |
1695 | 1, | |
1696 | &operand[i].exp, | |
1697 | 0, | |
1698 | R_MEM_INDIRECT); | |
1699 | } | |
7ee7b84d MS |
1700 | else if (x_mode == VECIND) |
1701 | { | |
1702 | check_operand (operand + i, 0x7f, "@@"); | |
1703 | /* FIXME: approximating the effect of "B31" here... | |
1704 | This is very hackish, and ought to be done a better way. */ | |
1705 | operand[i].exp.X_add_number |= 0x80; | |
1706 | fix_new_exp (frag_now, | |
1707 | output - frag_now->fr_literal + 1, | |
1708 | 1, | |
1709 | &operand[i].exp, | |
1710 | 0, | |
1711 | R_MEM_INDIRECT); | |
1712 | } | |
252b5132 RH |
1713 | else if (x & ABSJMP) |
1714 | { | |
3c1ba8a3 | 1715 | int where = 0; |
7ee7b84d | 1716 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
3c1ba8a3 | 1717 | |
3c1ba8a3 JL |
1718 | /* To be compatible with the proposed H8 ELF format, we |
1719 | want the relocation's offset to point to the first byte | |
1720 | that will be modified, not to the start of the instruction. */ | |
3739860c | 1721 | |
7ee7b84d MS |
1722 | if ((operand->mode & SIZE) == L_32) |
1723 | { | |
1724 | where = 2; | |
1725 | reloc_type = R_RELLONG; | |
1726 | } | |
1727 | else | |
1728 | where = 1; | |
de342d07 | 1729 | |
70d6ecf3 | 1730 | /* This jmp may be a jump or a branch. */ |
252b5132 | 1731 | |
3739860c L |
1732 | check_operand (operand + i, |
1733 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, | |
7ee7b84d | 1734 | "@"); |
3048287a | 1735 | |
252b5132 | 1736 | if (operand[i].exp.X_add_number & 1) |
3048287a NC |
1737 | as_warn (_("branch operand has odd offset (%lx)\n"), |
1738 | (unsigned long) operand->exp.X_add_number); | |
1739 | ||
252b5132 | 1740 | if (!Hmode) |
70d6ecf3 | 1741 | operand[i].exp.X_add_number = |
4132022d | 1742 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
252b5132 | 1743 | fix_new_exp (frag_now, |
3c1ba8a3 | 1744 | output - frag_now->fr_literal + where, |
252b5132 RH |
1745 | 4, |
1746 | &operand[i].exp, | |
1747 | 0, | |
7ee7b84d | 1748 | reloc_type); |
252b5132 RH |
1749 | } |
1750 | } | |
252b5132 RH |
1751 | } |
1752 | ||
70d6ecf3 AM |
1753 | /* Try to give an intelligent error message for common and simple to |
1754 | detect errors. */ | |
3048287a | 1755 | |
252b5132 | 1756 | static void |
b54a3392 KH |
1757 | clever_message (const struct h8_instruction *instruction, |
1758 | struct h8_op *operand) | |
252b5132 | 1759 | { |
70d6ecf3 | 1760 | /* Find out if there was more than one possible opcode. */ |
252b5132 | 1761 | |
a720f7bc | 1762 | if ((instruction + 1)->idx != instruction->idx) |
252b5132 | 1763 | { |
3048287a | 1764 | int argn; |
252b5132 | 1765 | |
70d6ecf3 AM |
1766 | /* Only one opcode of this flavour, try to guess which operand |
1767 | didn't match. */ | |
a720f7bc | 1768 | for (argn = 0; argn < instruction->noperands; argn++) |
252b5132 | 1769 | { |
a720f7bc | 1770 | switch (instruction->opcode->args.nib[argn]) |
252b5132 RH |
1771 | { |
1772 | case RD16: | |
1773 | if (operand[argn].mode != RD16) | |
1774 | { | |
1775 | as_bad (_("destination operand must be 16 bit register")); | |
1776 | return; | |
1777 | ||
1778 | } | |
1779 | break; | |
1780 | ||
1781 | case RS8: | |
252b5132 RH |
1782 | if (operand[argn].mode != RS8) |
1783 | { | |
1784 | as_bad (_("source operand must be 8 bit register")); | |
1785 | return; | |
1786 | } | |
1787 | break; | |
1788 | ||
1789 | case ABS16DST: | |
1790 | if (operand[argn].mode != ABS16DST) | |
1791 | { | |
1792 | as_bad (_("destination operand must be 16bit absolute address")); | |
1793 | return; | |
1794 | } | |
1795 | break; | |
1796 | case RD8: | |
1797 | if (operand[argn].mode != RD8) | |
1798 | { | |
1799 | as_bad (_("destination operand must be 8 bit register")); | |
1800 | return; | |
1801 | } | |
1802 | break; | |
1803 | ||
252b5132 RH |
1804 | case ABS16SRC: |
1805 | if (operand[argn].mode != ABS16SRC) | |
1806 | { | |
1807 | as_bad (_("source operand must be 16bit absolute address")); | |
1808 | return; | |
1809 | } | |
1810 | break; | |
1811 | ||
1812 | } | |
1813 | } | |
1814 | } | |
1815 | as_bad (_("invalid operands")); | |
1816 | } | |
1817 | ||
d4ea8842 | 1818 | |
1b680e4f RS |
1819 | /* If OPERAND is part of an address, adjust its size and value given |
1820 | that it addresses SIZE bytes. | |
d4ea8842 | 1821 | |
1b680e4f RS |
1822 | This function decides how big non-immediate constants are when no |
1823 | size was explicitly given. It also scales down the assembly-level | |
d4ea8842 MS |
1824 | displacement in an @(d:2,ERn) operand. */ |
1825 | ||
1826 | static void | |
b54a3392 | 1827 | fix_operand_size (struct h8_op *operand, int size) |
d4ea8842 | 1828 | { |
1b680e4f | 1829 | if (SXmode && (operand->mode & MODE) == DISP) |
d4ea8842 MS |
1830 | { |
1831 | /* If the user didn't specify an operand width, see if we | |
1832 | can use @(d:2,ERn). */ | |
1b680e4f RS |
1833 | if ((operand->mode & SIZE) == 0 |
1834 | && operand->exp.X_add_symbol == 0 | |
1835 | && operand->exp.X_op_symbol == 0 | |
d4ea8842 MS |
1836 | && (operand->exp.X_add_number == size |
1837 | || operand->exp.X_add_number == size * 2 | |
1838 | || operand->exp.X_add_number == size * 3)) | |
1839 | operand->mode |= L_2; | |
1840 | ||
1841 | /* Scale down the displacement in an @(d:2,ERn) operand. | |
1842 | X_add_number then contains the desired field value. */ | |
1843 | if ((operand->mode & SIZE) == L_2) | |
1844 | { | |
1845 | if (operand->exp.X_add_number % size != 0) | |
1846 | as_warn (_("operand/size mis-match")); | |
1847 | operand->exp.X_add_number /= size; | |
1848 | } | |
1849 | } | |
1850 | ||
d4ea8842 MS |
1851 | if ((operand->mode & SIZE) == 0) |
1852 | switch (operand->mode & MODE) | |
1853 | { | |
1854 | case DISP: | |
1855 | case INDEXB: | |
1856 | case INDEXW: | |
1857 | case INDEXL: | |
1858 | case ABS: | |
1b680e4f RS |
1859 | /* Pick a 24-bit address unless we know that a 16-bit address |
1860 | is safe. get_specific() will relax L_24 into L_32 where | |
1861 | necessary. */ | |
1862 | if (Hmode | |
3739860c | 1863 | && !Nmode |
35a35807 AM |
1864 | && ((((addressT) operand->exp.X_add_number + 0x8000) |
1865 | & 0xffffffff) > 0xffff | |
1b680e4f RS |
1866 | || operand->exp.X_add_symbol != 0 |
1867 | || operand->exp.X_op_symbol != 0)) | |
1868 | operand->mode |= L_24; | |
1869 | else | |
1870 | operand->mode |= L_16; | |
1871 | break; | |
1872 | ||
1873 | case PCREL: | |
35a35807 AM |
1874 | if ((((addressT) operand->exp.X_add_number + 0x80) |
1875 | & 0xffffffff) <= 0xff) | |
cc189afc DD |
1876 | { |
1877 | if (operand->exp.X_add_symbol != NULL) | |
1878 | operand->mode |= bsize; | |
1879 | else | |
1880 | operand->mode |= L_8; | |
1881 | } | |
1b680e4f RS |
1882 | else |
1883 | operand->mode |= L_16; | |
d4ea8842 MS |
1884 | break; |
1885 | } | |
1886 | } | |
1887 | ||
1888 | ||
70d6ecf3 AM |
1889 | /* This is the guts of the machine-dependent assembler. STR points to |
1890 | a machine dependent instruction. This function is supposed to emit | |
1891 | the frags/bytes it assembles. */ | |
3048287a | 1892 | |
252b5132 | 1893 | void |
b54a3392 | 1894 | md_assemble (char *str) |
252b5132 RH |
1895 | { |
1896 | char *op_start; | |
1897 | char *op_end; | |
7ee7b84d | 1898 | struct h8_op operand[3]; |
a720f7bc KD |
1899 | const struct h8_instruction *instruction; |
1900 | const struct h8_instruction *prev_instruction; | |
252b5132 RH |
1901 | |
1902 | char *dot = 0; | |
0c0b9be0 | 1903 | char *slash = 0; |
252b5132 | 1904 | char c; |
7ee7b84d | 1905 | int size, i; |
252b5132 | 1906 | |
70d6ecf3 | 1907 | /* Drop leading whitespace. */ |
252b5132 RH |
1908 | while (*str == ' ') |
1909 | str++; | |
1910 | ||
70d6ecf3 | 1911 | /* Find the op code end. */ |
252b5132 RH |
1912 | for (op_start = op_end = str; |
1913 | *op_end != 0 && *op_end != ' '; | |
1914 | op_end++) | |
1915 | { | |
1916 | if (*op_end == '.') | |
1917 | { | |
1918 | dot = op_end + 1; | |
1919 | *op_end = 0; | |
1920 | op_end += 2; | |
1921 | break; | |
1922 | } | |
0c0b9be0 AO |
1923 | else if (*op_end == '/' && ! slash) |
1924 | slash = op_end; | |
252b5132 RH |
1925 | } |
1926 | ||
252b5132 RH |
1927 | if (op_end == op_start) |
1928 | { | |
1929 | as_bad (_("can't find opcode ")); | |
1930 | } | |
1931 | c = *op_end; | |
1932 | ||
1933 | *op_end = 0; | |
1934 | ||
0c0b9be0 AO |
1935 | /* The assembler stops scanning the opcode at slashes, so it fails |
1936 | to make characters following them lower case. Fix them. */ | |
1937 | if (slash) | |
1938 | while (*++slash) | |
1939 | *slash = TOLOWER (*slash); | |
1940 | ||
a720f7bc | 1941 | instruction = (const struct h8_instruction *) |
629310ab | 1942 | str_hash_find (opcode_hash_control, op_start); |
252b5132 | 1943 | |
a720f7bc | 1944 | if (instruction == NULL) |
252b5132 RH |
1945 | { |
1946 | as_bad (_("unknown opcode")); | |
1947 | return; | |
1948 | } | |
1949 | ||
70d6ecf3 | 1950 | /* We used to set input_line_pointer to the result of get_operands, |
252b5132 RH |
1951 | but that is wrong. Our caller assumes we don't change it. */ |
1952 | ||
7ee7b84d MS |
1953 | operand[0].mode = 0; |
1954 | operand[1].mode = 0; | |
1955 | operand[2].mode = 0; | |
1956 | ||
1957 | if (OP_KIND (instruction->opcode->how) == O_MOVAB | |
1958 | || OP_KIND (instruction->opcode->how) == O_MOVAW | |
1959 | || OP_KIND (instruction->opcode->how) == O_MOVAL) | |
1960 | get_mova_operands (op_end, operand); | |
1961 | else if (OP_KIND (instruction->opcode->how) == O_RTEL | |
1962 | || OP_KIND (instruction->opcode->how) == O_RTSL) | |
1963 | get_rtsl_operands (op_end, operand); | |
1964 | else | |
1965 | get_operands (instruction->noperands, op_end, operand); | |
1966 | ||
252b5132 | 1967 | *op_end = c; |
a720f7bc | 1968 | prev_instruction = instruction; |
252b5132 | 1969 | |
4892e510 NC |
1970 | /* Now we have operands from instruction. |
1971 | Let's check them out for ldm and stm. */ | |
1972 | if (OP_KIND (instruction->opcode->how) == O_LDM) | |
1973 | { | |
1974 | /* The first operand must be @er7+, and the | |
1975 | second operand must be a register pair. */ | |
1976 | if ((operand[0].mode != RSINC) | |
1977 | || (operand[0].reg != 7) | |
1978 | || ((operand[1].reg & 0x80000000) == 0)) | |
1979 | as_bad (_("invalid operand in ldm")); | |
1980 | } | |
1981 | else if (OP_KIND (instruction->opcode->how) == O_STM) | |
1982 | { | |
1983 | /* The first operand must be a register pair, | |
1984 | and the second operand must be @-er7. */ | |
1985 | if (((operand[0].reg & 0x80000000) == 0) | |
1986 | || (operand[1].mode != RDDEC) | |
1987 | || (operand[1].reg != 7)) | |
1988 | as_bad (_("invalid operand in stm")); | |
1989 | } | |
1990 | ||
252b5132 RH |
1991 | size = SN; |
1992 | if (dot) | |
1993 | { | |
0c0b9be0 | 1994 | switch (TOLOWER (*dot)) |
252b5132 RH |
1995 | { |
1996 | case 'b': | |
1997 | size = SB; | |
1998 | break; | |
1999 | ||
2000 | case 'w': | |
2001 | size = SW; | |
2002 | break; | |
2003 | ||
2004 | case 'l': | |
2005 | size = SL; | |
2006 | break; | |
2007 | } | |
2008 | } | |
7ee7b84d MS |
2009 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
2010 | OP_KIND (instruction->opcode->how) == O_MOVAW || | |
2011 | OP_KIND (instruction->opcode->how) == O_MOVAL) | |
252b5132 | 2012 | { |
d4ea8842 MS |
2013 | switch (operand[0].mode & MODE) |
2014 | { | |
7ee7b84d MS |
2015 | case INDEXB: |
2016 | default: | |
d4ea8842 | 2017 | fix_operand_size (&operand[1], 1); |
7ee7b84d MS |
2018 | break; |
2019 | case INDEXW: | |
d4ea8842 | 2020 | fix_operand_size (&operand[1], 2); |
7ee7b84d MS |
2021 | break; |
2022 | case INDEXL: | |
d4ea8842 | 2023 | fix_operand_size (&operand[1], 4); |
7ee7b84d | 2024 | break; |
252b5132 RH |
2025 | } |
2026 | } | |
7ee7b84d MS |
2027 | else |
2028 | { | |
d4ea8842 MS |
2029 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
2030 | switch (size) | |
2031 | { | |
7ee7b84d MS |
2032 | case SN: |
2033 | case SB: | |
2034 | default: | |
d4ea8842 | 2035 | fix_operand_size (&operand[i], 1); |
7ee7b84d MS |
2036 | break; |
2037 | case SW: | |
d4ea8842 | 2038 | fix_operand_size (&operand[i], 2); |
7ee7b84d MS |
2039 | break; |
2040 | case SL: | |
d4ea8842 | 2041 | fix_operand_size (&operand[i], 4); |
7ee7b84d MS |
2042 | break; |
2043 | } | |
2044 | } | |
252b5132 | 2045 | |
d4ea8842 MS |
2046 | instruction = get_specific (instruction, operand, size); |
2047 | ||
2048 | if (instruction == 0) | |
2049 | { | |
2050 | /* Couldn't find an opcode which matched the operands. */ | |
2051 | char *where = frag_more (2); | |
2052 | ||
2053 | where[0] = 0x0; | |
2054 | where[1] = 0x0; | |
2055 | clever_message (prev_instruction, operand); | |
2056 | ||
2057 | return; | |
2058 | } | |
2059 | ||
a720f7bc | 2060 | build_bytes (instruction, operand); |
2c8714f2 | 2061 | |
2c8714f2 | 2062 | dwarf2_emit_insn (instruction->length); |
252b5132 RH |
2063 | } |
2064 | ||
2065 | symbolS * | |
b54a3392 | 2066 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
2067 | { |
2068 | return 0; | |
2069 | } | |
2070 | ||
499ac353 | 2071 | /* Various routines to kill one day. */ |
bc0d738a | 2072 | |
6d4af3c2 | 2073 | const char * |
b54a3392 | 2074 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 2075 | { |
5b7c81bd | 2076 | return ieee_md_atof (type, litP, sizeP, true); |
252b5132 RH |
2077 | } |
2078 | \f | |
6fd4f6cc | 2079 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
5518c738 | 2080 | #define OPTION_MACH (OPTION_MD_BASE+1) |
6fd4f6cc | 2081 | |
5a38dc70 | 2082 | const char *md_shortopts = ""; |
5518c738 YS |
2083 | struct option md_longopts[] = |
2084 | { | |
6fd4f6cc | 2085 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
5518c738 | 2086 | { "mach", required_argument, NULL, OPTION_MACH }, |
252b5132 RH |
2087 | {NULL, no_argument, NULL, 0} |
2088 | }; | |
70d6ecf3 AM |
2089 | |
2090 | size_t md_longopts_size = sizeof (md_longopts); | |
252b5132 | 2091 | |
5518c738 YS |
2092 | struct mach_func |
2093 | { | |
2094 | const char *name; | |
2095 | void (*func) (void); | |
2096 | }; | |
2097 | ||
2098 | static void | |
2099 | mach_h8300h (void) | |
2100 | { | |
2101 | Hmode = 1; | |
2102 | Smode = 0; | |
2103 | Nmode = 0; | |
2104 | SXmode = 0; | |
2105 | default_mach = bfd_mach_h8300h; | |
2106 | } | |
2107 | ||
2108 | static void | |
2109 | mach_h8300hn (void) | |
2110 | { | |
2111 | Hmode = 1; | |
2112 | Smode = 0; | |
2113 | Nmode = 1; | |
2114 | SXmode = 0; | |
2115 | default_mach = bfd_mach_h8300hn; | |
2116 | } | |
2117 | ||
2118 | static void | |
2119 | mach_h8300s (void) | |
2120 | { | |
2121 | Hmode = 1; | |
2122 | Smode = 1; | |
2123 | Nmode = 0; | |
2124 | SXmode = 0; | |
2125 | default_mach = bfd_mach_h8300s; | |
2126 | } | |
2127 | ||
2128 | static void | |
2129 | mach_h8300sn (void) | |
2130 | { | |
2131 | Hmode = 1; | |
2132 | Smode = 1; | |
2133 | Nmode = 1; | |
2134 | SXmode = 0; | |
2135 | default_mach = bfd_mach_h8300sn; | |
2136 | } | |
2137 | ||
2138 | static void | |
2139 | mach_h8300sx (void) | |
2140 | { | |
2141 | Hmode = 1; | |
2142 | Smode = 1; | |
2143 | Nmode = 0; | |
2144 | SXmode = 1; | |
2145 | default_mach = bfd_mach_h8300sx; | |
2146 | } | |
2147 | ||
2148 | static void | |
2149 | mach_h8300sxn (void) | |
2150 | { | |
2151 | Hmode = 1; | |
2152 | Smode = 1; | |
2153 | Nmode = 1; | |
2154 | SXmode = 1; | |
2155 | default_mach = bfd_mach_h8300sxn; | |
2156 | } | |
2157 | ||
2158 | const struct mach_func mach_table[] = | |
2159 | { | |
2160 | {"h8300h", mach_h8300h}, | |
2161 | {"h8300hn", mach_h8300hn}, | |
2162 | {"h8300s", mach_h8300s}, | |
2163 | {"h8300sn", mach_h8300sn}, | |
2164 | {"h8300sx", mach_h8300sx}, | |
2165 | {"h8300sxn", mach_h8300sxn} | |
2166 | }; | |
2167 | ||
252b5132 | 2168 | int |
17b9d67d | 2169 | md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) |
252b5132 | 2170 | { |
5518c738 | 2171 | unsigned int i; |
6fd4f6cc DD |
2172 | switch (c) |
2173 | { | |
2174 | case OPTION_H_TICK_HEX: | |
2175 | enable_h_tick_hex = 1; | |
2176 | break; | |
5518c738 YS |
2177 | case OPTION_MACH: |
2178 | for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) | |
2179 | { | |
2180 | if (strcasecmp (arg, mach_table[i].name) == 0) | |
2181 | { | |
2182 | mach_table[i].func(); | |
2183 | break; | |
2184 | } | |
2185 | } | |
2186 | if (i >= sizeof(mach_table) / sizeof(struct mach_func)) | |
2187 | as_bad (_("Invalid argument to --mach option: %s"), arg); | |
2188 | break; | |
6fd4f6cc DD |
2189 | default: |
2190 | return 0; | |
2191 | } | |
2192 | return 1; | |
252b5132 RH |
2193 | } |
2194 | ||
2195 | void | |
5518c738 | 2196 | md_show_usage (FILE *stream) |
252b5132 | 2197 | { |
5518c738 YS |
2198 | fprintf (stream, _(" H8300-specific assembler options:\n")); |
2199 | fprintf (stream, _("\ | |
2200 | -mach=<name> Set the H8300 machine type to one of:\n\ | |
2201 | h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); | |
2202 | fprintf (stream, _("\ | |
2203 | -h-tick-hex Support H'00 style hex constants\n")); | |
252b5132 RH |
2204 | } |
2205 | \f | |
b54a3392 | 2206 | void tc_aout_fix_to_chars (void); |
3048287a | 2207 | |
252b5132 | 2208 | void |
b54a3392 | 2209 | tc_aout_fix_to_chars (void) |
252b5132 RH |
2210 | { |
2211 | printf (_("call to tc_aout_fix_to_chars \n")); | |
2212 | abort (); | |
2213 | } | |
2214 | ||
2215 | void | |
7be1c489 | 2216 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
b54a3392 KH |
2217 | segT seg ATTRIBUTE_UNUSED, |
2218 | fragS *fragP ATTRIBUTE_UNUSED) | |
252b5132 RH |
2219 | { |
2220 | printf (_("call to md_convert_frag \n")); | |
2221 | abort (); | |
2222 | } | |
2223 | ||
3c1ba8a3 | 2224 | valueT |
b54a3392 | 2225 | md_section_align (segT segment, valueT size) |
3c1ba8a3 | 2226 | { |
fd361982 | 2227 | int align = bfd_section_alignment (segment); |
239c0f4c | 2228 | return ((size + (1 << align) - 1) & (-1U << align)); |
3c1ba8a3 | 2229 | } |
252b5132 RH |
2230 | |
2231 | void | |
55cf6793 | 2232 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 RH |
2233 | { |
2234 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; | |
a161fe53 | 2235 | long val = *valP; |
252b5132 RH |
2236 | |
2237 | switch (fixP->fx_size) | |
2238 | { | |
2239 | case 1: | |
2240 | *buf++ = val; | |
2241 | break; | |
2242 | case 2: | |
2243 | *buf++ = (val >> 8); | |
2244 | *buf++ = val; | |
2245 | break; | |
2246 | case 4: | |
2247 | *buf++ = (val >> 24); | |
2248 | *buf++ = (val >> 16); | |
2249 | *buf++ = (val >> 8); | |
2250 | *buf++ = val; | |
2251 | break; | |
550c1888 NC |
2252 | case 8: |
2253 | /* This can arise when the .quad or .8byte pseudo-ops are used. | |
2254 | Returning here (without setting fx_done) will cause the code | |
2255 | to attempt to generate a reloc which will then fail with the | |
2256 | slightly more helpful error message: "Cannot represent | |
2257 | relocation type BFD_RELOC_64". */ | |
2258 | return; | |
252b5132 RH |
2259 | default: |
2260 | abort (); | |
2261 | } | |
94f592af NC |
2262 | |
2263 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) | |
2264 | fixP->fx_done = 1; | |
252b5132 RH |
2265 | } |
2266 | ||
2267 | int | |
c85dd50d NC |
2268 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
2269 | segT segment_type ATTRIBUTE_UNUSED) | |
252b5132 | 2270 | { |
c85dd50d | 2271 | printf (_("call to md_estimate_size_before_relax \n")); |
252b5132 RH |
2272 | abort (); |
2273 | } | |
2274 | ||
70d6ecf3 | 2275 | /* Put number into target byte order. */ |
252b5132 | 2276 | void |
b54a3392 | 2277 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
252b5132 RH |
2278 | { |
2279 | number_to_chars_bigendian (ptr, use, nbytes); | |
2280 | } | |
70d6ecf3 | 2281 | |
252b5132 | 2282 | long |
52b010e4 | 2283 | md_pcrel_from (fixS *fixp) |
252b5132 | 2284 | { |
52b010e4 NC |
2285 | as_bad_where (fixp->fx_file, fixp->fx_line, |
2286 | _("Unexpected reference to a symbol in a non-code section")); | |
2287 | return 0; | |
252b5132 RH |
2288 | } |
2289 | ||
f333765f | 2290 | arelent * |
b54a3392 | 2291 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
f333765f JL |
2292 | { |
2293 | arelent *rel; | |
2294 | bfd_reloc_code_real_type r_type; | |
2295 | ||
de342d07 JL |
2296 | if (fixp->fx_addsy && fixp->fx_subsy) |
2297 | { | |
2298 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) | |
2299 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) | |
2300 | { | |
4bf09429 | 2301 | as_bad_subtract (fixp); |
de342d07 JL |
2302 | return NULL; |
2303 | } | |
2304 | } | |
2305 | ||
325801bd TS |
2306 | rel = XNEW (arelent); |
2307 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
f333765f JL |
2308 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
2309 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
2310 | rel->addend = fixp->fx_offset; | |
2311 | ||
2312 | r_type = fixp->fx_r_type; | |
2313 | ||
2314 | #define DEBUG 0 | |
2315 | #if DEBUG | |
2316 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); | |
c85dd50d | 2317 | fflush (stderr); |
f333765f JL |
2318 | #endif |
2319 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); | |
2320 | if (rel->howto == NULL) | |
2321 | { | |
2322 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
2323 | _("Cannot represent relocation type %s"), | |
2324 | bfd_get_reloc_code_name (r_type)); | |
2325 | return NULL; | |
2326 | } | |
2327 | ||
2328 | return rel; | |
2329 | } |